A Coupled Chaotic Circuit Based on Van der pol-Duffing Memristor Chaotic Oscillator

Abstract

The application provides a coupling chaotic circuit based on a Vanderpol-Duffing memristor chaotic oscillator, which comprises an adder one, an adder two, an integrator one, an integrator two, an integrator three, an integrator four, an integrator five, an integrator six, a multiplier X1, a multiplier X2, a multiplier X3, a multiplier X4, a multiplier X5, a multiplier X6, a multiplier X7, a multiplier X8, an inverter one, an inverter two, an inverter three, an inverter four, an inverter five, an inverter six and a sine signal source V; the application has the beneficial effect that: by adding a linear coupling term to the coupling chaotic circuit based on the Vanderpol-Duffing memristor chaotic oscillator, a coupling chaotic system with a more complex nonlinear structure and more stable chaotic performance is obtained.

Description

Technical Field

[0001] This invention relates to the field of chaotic circuits, and more particularly to a coupled chaotic circuit based on a Van der pol-Duffing memristor chaotic oscillator. Background Technology

[0002] The resistance of a memristor can be changed by a tiny electrical signal, and it also has advantages such as low noise, high stability, fast response, and low power consumption. Introducing a memristor into a chaotic system can increase the system's stability, making the chaotic system easier to control and reducing instability caused by factors such as parameter changes. Furthermore, the introduction of a memristor makes the dynamic behavior of the chaotic system more complex, generating richer chaotic sequences and more nonlinear dynamic behaviors, thereby improving the performance of the chaotic system.

[0003] The coupled chaotic system based on the Van der Pohl-Duffing chaotic oscillator using a memristor is obtained by linearly coupling two subsystems. Due to its more complex dynamic behavior and more stable chaotic performance, it can be less affected by noise and interference, and has broad application prospects in communication encryption, weak signal detection, image processing, and other fields. Currently, there is no research on incorporating memristors into coupled chaotic systems. This invention incorporates memristors into the coupled chaotic system, improving the nonlinear characteristics of the entire coupled chaotic system, giving the system better stability and noise immunity. Research on coupled memristor chaotic systems has important practical significance for enriching chaotic circuits. Summary of the Invention

[0004] To address the aforementioned problems, this invention designs a coupled chaotic circuit based on a Van der pol-Duffing memristor chaotic oscillator. This coupled chaotic circuit includes adder 1, adder 2, integrator 1, integrator 2, integrator 3, integrator 4, integrator 5, integrator 6, multiplier X1, multiplier X2, multiplier X3, multiplier X4, multiplier X5, multiplier X6, multiplier X7, multiplier X8, inverter 1, inverter 2, inverter 3, inverter 4, inverter 5, inverter 6, and a sine wave signal source V.

[0005] Specifically, pins IO1, IO2, IO3, IO4, IO5, IO6, and IO7 of adder one are connected to the output of multiplier X2, pin IO2 of integrator one, pin IO1 of inverter two, the output of multiplier X3, the positive terminal of sine wave source V, pin IO1 of inverter six, and pin IO2 of inverter three, respectively. Pin IO8 of adder one is connected to pin IO1 of integrator one, and pin IO2 of integrator one is connected to pin IO1 of inverter one. Pin IO1 of integrator two is connected to pin IO2 of inverter one, and pin IO2 of integrator two is connected to pin IO1 of inverter two. Pin IO1 of integrator three is connected to pin IO2 of inverter two, and pin IO2 of integrator three is connected to pin IO1 of inverter three.

[0006] The Y and X ports of multiplier X1 are both connected to IO2 of inverter 2. The output port of multiplier X1 is connected to the Y port of multiplier X2. The X port of multiplier X2 is connected to pin IO2 of inverter 1. The Y port of multiplier X3 is connected to pin IO2 of inverter 2. The X port of multiplier X3 is connected to the output port of multiplier X4. The X and Y ports of multiplier X4 are both connected to pin IO2 of integrator 3.

[0007] Pins IO1, IO2, IO3, IO4, IO5, IO6, and IO7 of adder 2 are connected to the output of multiplier X6, pin IO2 of integrator 4, pin IO1 of inverter 5, the output of multiplier X7, the positive terminal of sine wave source V, pin IO1 of inverter 3, and pin IO2 of inverter 6, respectively. Pin IO8 of adder 2 is connected to pin IO1 of integrator 4, and pin IO2 of integrator 4 is connected to pin IO1 of inverter 4. Pin IO1 of integrator 5 is connected to pin IO2 of inverter 4, and pin IO2 of integrator 5 is connected to pin IO1 of inverter 5. Pin IO1 of integrator 6 is connected to pin IO2 of inverter 5, and pin IO2 of integrator 6 is connected to pin IO1 of inverter 6.

[0008] The Y and X ports of multiplier X5 are both connected to the IO2 pin of inverter 5, and the output port of multiplier X5 is connected to the Y port of multiplier X6; the X port of multiplier X6 is connected to the IO2 pin of inverter 4; the Y port of multiplier X7 is connected to the IO2 pin of inverter 5, and the X port of multiplier X7 is connected to the output port of multiplier X8; the X and Y ports of multiplier X8 are both connected to the IO2 pin of integrator 6.

[0009] Furthermore, integrator 1, integrator 2, integrator 3, integrator 4, integrator 5, and integrator 6 are all composed of the same resistors, capacitors, and operational amplifiers; adder 1 and adder 2 are both composed of the same resistors and operational amplifiers; inverter 1, inverter 2, inverter 3, inverter 4, inverter 5, and inverter 6 are all composed of the same resistors and operational amplifiers.

[0010] Each integrator includes resistors R1, R2, and R3, an operational amplifier U1, and a capacitor C1. One end of resistor R1 is connected to pin IO1 of the integrator itself, and the other end is connected to the inverting input of operational amplifier U1. One end of resistor R2 is grounded, and the other end is connected to the non-inverting input of operational amplifier U1. Resistor R3 and capacitor C1 are connected in parallel to form a parallel network, one end of which is connected to the inverting input of operational amplifier U1, and the other end is connected to the output of operational amplifier U1. The output of operational amplifier U1 is connected to pin IO2 of the integrator itself.

[0011] Each adder includes resistors R4, R5, R6, R7, R8, R9, R10, and R11, and operational amplifier U2. One end of resistor R4 is connected to pin IO1 of the adder itself, and the other end is connected to the inverting input of operational amplifier U2. One end of resistor R5 is connected to pin IO2 of the adder itself, and the other end is connected to the inverting input of operational amplifier U2. One end of resistor R6 is connected to pin IO3 of the adder itself, and the other end is connected to the inverting input of operational amplifier U2. One end of resistor R7 is connected to pin IO4 of the adder itself, and the other end is connected to the inverting input of operational amplifier U2. The inverting input is connected; one end of resistor R8 is connected to pin IO5 of the adder itself, and the other end is connected to the inverting input of operational amplifier U2; one end of resistor R11 is connected to pin IO6 of the adder itself, and the other end is connected to the inverting input of operational amplifier U2; one end of resistor R10 is connected to pin IO7 of the adder itself, and the other end is connected to the inverting input of operational amplifier U2; one end of resistor R9 is connected to the output of operational amplifier U2, and the other end is connected to the inverting input of operational amplifier U2; the non-inverting input of operational amplifier U2 is grounded, and the output of operational amplifier U2 is connected to pin IO8 of the adder itself.

[0012] Each inverter includes resistors R12 and R13 and operational amplifier U3. One end of resistor R12 is connected to pin IO1 of the inverter itself, and the other end is connected to the inverting input of operational amplifier U3. One end of resistor R13 is connected to the output of operational amplifier U3, and the other end is connected to the inverting input of operational amplifier U3. The non-inverting input of operational amplifier U3 is grounded, and the output of operational amplifier U3 is connected to pin IO2 of the inverter itself.

[0013] Furthermore, a voltage signal is generated by a sinusoidal signal source to drive the operation of the entire coupled chaotic circuit. After the voltage signal flows through the coupled chaotic system, it reaches a stable state. The state of the coupled chaotic system at this time is determined by reading the output voltages of integrators one, two, and three.

[0014] Furthermore, the capacitor C1 = 100uF; resistors R1 = 10KΩ, R2 = 9.5KΩ, R3 = 220KΩ, R4 = 20KΩ, R5 = 20KΩ, R6 = 10KΩ, R7 = 10KΩ, R8 = 10KΩ, R9 = 10KΩ, R10 = 10KΩ, R11 = 10KΩ, R12 = 10KΩ, and R13 = 10KΩ; operational amplifiers U1, U2, and U3 all use operational amplifier TL082; multipliers X1, X2, X3, X4, X5, X6, X7, and X8 all use multiplier AD633.

[0015] Furthermore, the coupled chaotic circuit includes a first memristor based on a Van der pol-Duffing memristor-coupled chaotic oscillator and a second memristor based on a Van der pol-Duffing memristor-coupled chaotic oscillator. The first memristor includes an integrator X3, a multiplier X3, and a multiplier X4, and the second memristor includes an integrator X6, a multiplier X7, and a multiplier X8.

[0016] Furthermore, the mathematical model of the Van der pol-Duffing memristor-coupled chaotic oscillator is shown in equation (1):

[0017]

[0018] Where x and y represent voltages, and μ represents the nonlinear damping coefficient. Let f(x) represent a memristor, k(xy) and k(yx) represent linear coupling terms, k represents the coupling coefficient, F represents the amplitude of the sinusoidal signal, ω represents the angular frequency of the sinusoidal signal, and t represents time.

[0019] Equation (1) can be expressed as the following differential equation:

[0020]

[0021] Where x1, x2, x3, y1, y2, and y3 are the six state variables of the coupled system, x1 represents the output voltage of integrator 3, x2 represents the output voltage of integrator 2, x3 represents the output voltage of integrator 1, y1 represents the output voltage of integrator 6, y2 represents the output voltage of integrator 5, and y3 represents the output voltage of integrator 4. The memristor value represents the magnetic flux density. It means, that is a and b are both constants, and the magnetic flux is... It is equal to the integral of the voltage across the memristor with respect to time t;

[0022] The coupled chaotic circuit designed by the Van der pol-Duffing memristor chaotic oscillator above has two nonlinear systems. The two systems are coupled together by a linear coupling term, which improves the nonlinearity and noise immunity of the entire chaotic system.

[0023] The beneficial effect of this invention is that by adding linear coupling terms to the Van der pol-Duffing memristor chaotic oscillator circuit, a coupled chaotic system with a more complex nonlinear structure and more stable chaotic performance is obtained. Attached Figure Description

[0024] The present invention will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings:

[0025] Figure 1 The coupled chaotic circuit diagram based on the Van der pol-Duffing memristor chaotic oscillator proposed in this invention is shown.

[0026] Figure 2 This is a circuit diagram of the integrator in the circuit proposed in this invention;

[0027] Figure 3 This is a circuit diagram of the adder in the circuit proposed in this invention;

[0028] Figure 4 This is a schematic diagram of the inverter circuit structure in the circuit proposed in this invention;

[0029] Figure 5 The x2-x3 simulation phase diagram of the coupled chaotic circuit proposed in this invention in Multisim;

[0030] Figure 6 The simulation timing diagrams for x1, x2, and x3 of the coupled chaotic circuit proposed in this invention in Multisim are shown. Detailed Implementation

[0031] To provide a clearer understanding of the technical features, objectives, and effects of the present invention, specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0032] Please refer to Figure 1 This invention designs a coupled chaotic circuit based on a Van der Pohl-Duffing memristor chaotic oscillator, comprising: adder 1, adder 2, integrator 1, integrator 2, integrator 3, integrator 4, integrator 5, integrator 6, multiplier X1, multiplier X2, multiplier X3, multiplier X4, multiplier X5, multiplier X6, multiplier X7, multiplier X8, inverter 1, inverter 2, inverter 3, inverter 4, inverter 5, inverter 6, and a sinusoidal signal source V; a voltage signal is generated by the sinusoidal signal source to drive the operation of the entire coupled chaotic circuit. After the voltage signal flows through the system, it reaches a stable state. The state of the system at this time is determined by reading the output voltages of integrators 1, 2, and 3.

[0033] Specifically, pin IO1 of adder-1 is connected to the output port of multiplier X2; pin IO2 of adder-1 is connected to pin IO2 of integrator-1; pin IO3 of adder-1 is connected to pin IO2 of integrator-2; pin IO4 of adder-1 is connected to the output port of multiplier X3; pin IO5 of adder-1 is connected to the positive terminal of sine wave source V; pin IO6 of adder-1 is connected to pin IO2 of integrator-6; pin IO7 of adder-1 is connected to pin IO2 of inverter-3; pin IO1 of integrator-1 is connected to pin IO8 of adder-1; pin IO2 of integrator-1 is connected to pin IO1 of inverter-1; pin IO1 of integrator-2 is connected to pin IO8 of multiplier-1; pin IO2 of integrator-1 is connected to pin IO1 of inverter-1; pin IO1 of integrator-2 is connected to pin IO2 of multiplier X2; pin IO3 of adder-1 is connected to pin IO2 of multiplier X3; pin IO4 of adder-1 is connected to the output port of multiplier X3; pin IO5 of adder-1 is connected to the positive terminal of sine wave source V; pin IO6 of adder-1 is connected to pin IO2 of integrator-6; pin IO7 of adder-1 is connected to pin IO2 of inverter-3; pin IO1 of integrator-1 is connected to pin IO2 of multiplier X2; pin IO2 of integrator-1 is connected to pin IO2 of multiplier X3; pin IO4 of adder-1 is connected to the output port of multiplier X3; pin IO5 of adder-1 is connected to the positive terminal of sine wave source V; pin IO6 of adder-1 is connected to pin IO2 of integrator-1; pin IO7 of adder-1 The pin IO2 of Integrator 1 is connected to the pin IO2 of Integrator 2, and the pin IO2 of Integrator 2 is connected to the pin IO1 of Inverter 2; the pin IO1 of Integrator 3 is connected to the pin IO2 of Inverter 2, and the pin IO2 of Integrator 3 is connected to the pin IO1 of Inverter 3; the pin IO1 of Integrator 4 is connected to the pin IO8 of Adder 2, and the pin IO2 of Integrator 4 is connected to the pin IO1 of Inverter 4; the pin IO1 of Integrator 5 is connected to the pin IO2 of Inverter 4, and the pin IO2 of Integrator 5 is connected to the pin IO1 of Inverter 5; the pin IO1 of Integrator 6 is connected to the pin IO2 of Inverter 5, and the pin IO2 of Integrator 6 is connected to the pin IO1 of Inverter 6.

[0034] The Y port of multiplier X1 is connected to pin IO2 of inverter 2, the X port of multiplier X1 is connected to pin IO2 of inverter 2, and the output port of multiplier X1 is connected to the Y port of multiplier X2; the X port of multiplier X2 is connected to pin IO2 of inverter 1; the Y port of multiplier X3 is connected to pin IO2 of inverter 2, and the X port of multiplier X3 is connected to the output port of multiplier X4; the X port of multiplier X4 is connected to pin IO2 of integrator 3, and the Y port of multiplier X4 is connected to pin IO2 of integrator 3.

[0035] Adder 2's pin IO1 is connected to the output port of multiplier X6; adder 2's pin IO2 is connected to integrator 4's pin IO2; adder 2's pin IO3 is connected to integrator 5's pin IO2; adder 2's pin IO4 is connected to the output port of multiplier X7; adder 2's pin IO5 is connected to the positive terminal of the sine wave source V; adder 2's pin IO6 is connected to integrator 3's pin IO2; and adder 2's pin IO7 is connected to the inverter. Pin IO2 of Integrator 6 is connected to Integrator 4; Pin IO1 of Integrator 4 is connected to Pin IO8 of Adder 2; Pin IO2 of Integrator 4 is connected to Pin IO1 of Inverter 4; Pin IO1 of Integrator 5 is connected to Pin IO2 of Inverter 4; Pin IO2 of Integrator 5 is connected to Pin IO1 of Inverter 5; Pin IO1 of Integrator 6 is connected to Pin IO2 of Inverter 5; Pin IO2 of Integrator 6 is connected to Pin IO1 of Inverter 6.

[0036] The Y port of multiplier X5 is connected to pin IO2 of inverter 5, the X port of multiplier X5 is connected to pin IO2 of inverter 5, and the output port of multiplier X5 is connected to the Y port of multiplier X6; the X port of multiplier X6 is connected to pin IO2 of inverter 4; the Y port of multiplier X7 is connected to pin IO2 of inverter 5, and the X port of multiplier X7 is connected to the output port of multiplier X8; the X port of multiplier X8 is connected to pin IO2 of integrator 6, and the Y port of multiplier X8 is connected to pin IO2 of integrator 6.

[0037] The integrators 1, 2, 3, 4, 5, and 6 mentioned above are all composed of the same resistors, capacitors, and operational amplifiers; adders 1 and 2 are both composed of the same resistors and operational amplifiers; inverters 1, 2, 3, 4, 5, and 6 are all composed of the same resistors and operational amplifiers.

[0038] Each integrator circuit structure is as follows: Figure 2As shown, one end of resistor R1 is connected to pin IO1 of the integrator itself, and the other end of resistor R1 is connected to the inverting input of operational amplifier U1; one end of resistor R2 is grounded, and the other end of resistor R2 is connected to the non-inverting input of operational amplifier U1; resistor R3 and capacitor C1 are connected in parallel to form a parallel network, one end of which is connected to the inverting input of operational amplifier U1, and the other end of which is connected to the output of operational amplifier U1; the output of operational amplifier U1 is connected to pin IO2 of the integrator itself.

[0039] The circuit structure of each adder is as follows: Figure 3 As shown, one end of resistor R4 is connected to pin IO1 of the adder itself, and the other end of resistor R4 is connected to the inverting input of operational amplifier U2; one end of resistor R5 is connected to pin IO2 of the adder itself, and the other end of resistor R5 is connected to the inverting input of operational amplifier U2; one end of resistor R6 is connected to pin IO3 of the adder itself, and the other end of resistor R6 is connected to the inverting input of operational amplifier U2; one end of resistor R7 is connected to pin IO4 of the adder itself, and the other end of resistor R7 is connected to the inverting input of operational amplifier U2; one end of resistor R8 is connected to pin IO5 of the adder itself. The other end of resistor R8 is connected to the inverting input of operational amplifier U2; one end of resistor R11 is connected to pin IO6 of the adder itself, and the other end of resistor R11 is connected to the inverting input of operational amplifier U2; one end of resistor R10 is connected to pin IO7 of the adder itself, and the other end of resistor R10 is connected to the inverting input of operational amplifier U2; one end of resistor R9 is connected to the output of operational amplifier U2, and the other end of resistor R9 is connected to the inverting input of operational amplifier U2; the non-inverting input of operational amplifier U2 is grounded, and the output of operational amplifier U2 is connected to pin IO8 of the adder itself.

[0040] The circuit structure of each inverter is as follows: Figure 4 As shown, one end of resistor R12 is connected to pin IO1 of the inverter itself, and the other end of resistor R12 is connected to the inverting input of operational amplifier U3; one end of resistor R13 is connected to the output of operational amplifier U3, and the other end of resistor R13 is connected to the inverting input of operational amplifier U3; the non-inverting input of operational amplifier U3 is grounded, and the output of operational amplifier U3 is connected to pin IO2 of the inverter itself.

[0041] The first memristor of the Van der pol-Duffing memristor-coupled chaotic oscillator consists of integrator X3, multiplier X3, and multiplier X4, while the second memristor of the Van der pol-Duffing memristor-coupled chaotic oscillator consists of integrator X6, multiplier X7, and multiplier X8.

[0042] The Van der pol-Duffing memristor-coupled chaotic oscillator designed in this embodiment can be expressed mathematically as shown in formula (1):

[0043]

[0044] Where x and y represent voltages, and μ represents the nonlinear damping coefficient. Let f(x) represent a memristor, k(xy) and k(yx) represent linear coupling terms, k represents the coupling coefficient, F represents the amplitude of the sinusoidal signal, and ω represents the angular frequency of the sinusoidal signal.

[0045] Equation (1) can be expressed as a differential equation as shown in equation (2):

[0046]

[0047] Where x1, x2, x3, y1, y2, and y3 are the six state variables of the coupled system, x1 represents the output voltage of integrator 3, x2 represents the output voltage of integrator 2, x3 represents the output voltage of integrator 1, y1 represents the output voltage of integrator 6, y2 represents the output voltage of integrator 5, and y3 represents the output voltage of integrator 4. The memristor value represents the magnetic flux density. It means, that is a and b are both constants, and the magnetic flux is... It equals the integral of the voltage across the memristor over time.

[0048] Figure 5 This is a simulation phase diagram of v2-x3 in Multisim, where operational amplifiers U1, U2, and U3 all use operational amplifier TL082; multipliers X1, X2, X3, X4, X5, X6, X7, and X8 all use multiplier AD633; capacitor C1 = 100uF; resistor R1 = 10KΩ; and so on. Resistors R2 = 9.5KΩ, R3 = 220KΩ, R4 = 20KΩ, R5 = 20KΩ, R6 = 10KΩ, R7 = 10KΩ, R8 = 10KΩ, R9 = 10KΩ, R10 = 10KΩ, R11 = 10KΩ, R12 = 10KΩ, R13 = 10KΩ; other parameters are F = 0.5V, ω = 1rad / s. a = 1, k = 0.5, Figure 6 The following are the simulation timing diagrams (x1, x2, x3) of the coupled chaotic circuit proposed in this invention in Multisim; Figure 5 , Figure 6 It can be seen that the coupled chaotic circuit based on the Van der pol-Duffing memristor chaotic oscillator of the present invention can generate complex chaotic signals and realize complex dynamic behavior.

[0049] The beneficial effect of this invention is that by adding linear coupling terms to the Van der pol-Duffing memristor chaotic oscillator circuit, a coupled chaotic system with a more complex nonlinear structure and more stable chaotic performance is obtained.

Claims

1. A coupled chaotic circuit based on a Van der Pohl-Duffing memristor chaotic oscillator, characterized in that: The coupled chaotic circuit includes adder 1, adder 2, integrator 1, integrator 2, integrator 3, integrator 4, integrator 5, integrator 6, multiplier X1, multiplier X2, multiplier X3, multiplier X4, multiplier X5, multiplier X6, multiplier X7, multiplier X8, inverter 1, inverter 2, inverter 3, inverter 4, inverter 5, inverter 6, and a sine wave signal source V; Specifically, pins IO1, IO2, IO3, IO4, IO5, IO6, and IO7 of adder one are connected to the output of multiplier X2, pin IO2 of integrator one, pin IO1 of inverter two, the output of multiplier X3, the positive terminal of sine wave source V, pin IO1 of inverter six, and pin IO2 of inverter three, respectively. Pin IO8 of adder one is connected to pin IO1 of integrator one, and pin IO2 of integrator one is connected to pin IO1 of inverter one. Pin IO1 of integrator two is connected to pin IO2 of inverter one, and pin IO2 of integrator two is connected to pin IO1 of inverter two. Pin IO1 of integrator three is connected to pin IO2 of inverter two, and pin IO2 of integrator three is connected to pin IO1 of inverter three. The Y and X ports of multiplier X1 are both connected to IO2 of inverter 2. The output port of multiplier X1 is connected to the Y port of multiplier X2. The X port of multiplier X2 is connected to pin IO2 of inverter 1. The Y port of multiplier X3 is connected to pin IO2 of inverter 2. The X port of multiplier X3 is connected to the output port of multiplier X4. The X and Y ports of multiplier X4 are both connected to pin IO2 of integrator 3. Pins IO1, IO2, IO3, IO4, IO5, IO6, and IO7 of adder 2 are connected to the output of multiplier X6, pin IO2 of integrator 4, pin IO1 of inverter 5, the output of multiplier X7, the positive terminal of sine wave source V, pin IO1 of inverter 3, and pin IO2 of inverter 6, respectively. Pin IO8 of adder 2 is connected to pin IO1 of integrator 4, and pin IO2 of integrator 4 is connected to pin IO1 of inverter 4. Pin IO1 of integrator 5 is connected to pin IO2 of inverter 4, and pin IO2 of integrator 5 is connected to pin IO1 of inverter 5. Pin IO1 of integrator 6 is connected to pin IO2 of inverter 5, and pin IO2 of integrator 6 is connected to pin IO1 of inverter 6. The Y and X ports of multiplier X5 are both connected to the IO2 pin of inverter 5, and the output port of multiplier X5 is connected to the Y port of multiplier X6; the X port of multiplier X6 is connected to the IO2 pin of inverter 4; the Y port of multiplier X7 is connected to the IO2 pin of inverter 5, and the X port of multiplier X7 is connected to the output port of multiplier X8; the X and Y ports of multiplier X8 are both connected to the IO2 pin of integrator 6. Integrator 1, Integrator 2, Integrator 3, Integrator 4, Integrator 5, and Integrator 6 are all composed of the same resistors, capacitors, and operational amplifiers; Adder 1 and Adder 2 are both composed of the same resistors and operational amplifiers; Inverter 1, Inverter 2, Inverter 3, Inverter 4, Inverter 5, and Inverter 6 are all composed of the same resistors and operational amplifiers. Each integrator includes resistors R1, R2, and R3, an operational amplifier U1, and a capacitor C1. One end of resistor R1 is connected to pin IO1 of the integrator itself, and the other end is connected to the inverting input of operational amplifier U1. One end of resistor R2 is grounded, and the other end is connected to the non-inverting input of operational amplifier U1. Resistor R3 and capacitor C1 are connected in parallel to form a parallel network, one end of which is connected to the inverting input of operational amplifier U1, and the other end is connected to the output of operational amplifier U1. The output of operational amplifier U1 is connected to pin IO2 of the integrator itself. Each adder includes resistors R4, R5, R6, R7, R8, R9, R10, and R11, and operational amplifier U2. One end of resistor R4 is connected to pin IO1 of the adder itself, and the other end is connected to the inverting input of operational amplifier U2. One end of resistor R5 is connected to pin IO2 of the adder itself, and the other end is connected to the inverting input of operational amplifier U2. One end of resistor R6 is connected to pin IO3 of the adder itself, and the other end is connected to the inverting input of operational amplifier U2. One end of resistor R7 is connected to pin IO4 of the adder itself, and the other end is connected to the inverting input of operational amplifier U2. The inverting input is connected; one end of resistor R8 is connected to pin IO5 of the adder itself, and the other end is connected to the inverting input of operational amplifier U2; one end of resistor R11 is connected to pin IO6 of the adder itself, and the other end is connected to the inverting input of operational amplifier U2; one end of resistor R10 is connected to pin IO7 of the adder itself, and the other end is connected to the inverting input of operational amplifier U2; one end of resistor R9 is connected to the output of operational amplifier U2, and the other end is connected to the inverting input of operational amplifier U2; the non-inverting input of operational amplifier U2 is grounded, and the output of operational amplifier U2 is connected to pin IO8 of the adder itself. Each inverter includes resistors R12 and R13 and operational amplifier U3. One end of resistor R12 is connected to pin IO1 of the inverter itself, and the other end is connected to the inverting input of operational amplifier U3. One end of resistor R13 is connected to the output of operational amplifier U3, and the other end is connected to the inverting input of operational amplifier U3. The non-inverting input of operational amplifier U3 is grounded, and the output of operational amplifier U3 is connected to pin IO2 of the inverter itself.

2. The coupled chaotic circuit based on the Van der Pohl-Duffing memristor chaotic oscillator according to claim 1, characterized in that: A voltage signal is generated by a sinusoidal signal source to drive the operation of the entire coupled chaotic circuit. After the voltage signal flows through the coupled chaotic system, it reaches a stable state. The state of the coupled chaotic system at this time is determined by reading the output voltages of integrators one, two, and three.

3. The coupled chaotic circuit based on the Van der Pohl-Duffing memristor chaotic oscillator according to claim 1, characterized in that: Capacitor C1 = 100uF; Resistors R1 = 10 KΩ, R2 = 9.5KΩ, R3 = 220 KΩ, R4 = 20 KΩ, R5 = 20 KΩ, R6 = 10KΩ, R7 = 10 KΩ, R8 = 10 KΩ, R9 = 10 KΩ, R10 = 10 KΩ, R11 = 10 KΩ, R12 = 10 KΩ, R13 = 10 KΩ; Operational amplifiers U1, U2, and U3 all use operational amplifier TL082; Multipliers X1, X2, X3, X4, X5, X6, X7, and X8 all use multiplier AD633.

4. The coupled chaotic circuit based on the Van der Pohl-Duffing memristor chaotic oscillator according to claim 1, characterized in that: The coupled chaotic circuit includes a first memristor based on a Van der pol-Duffing memristor-coupled chaotic oscillator and a second memristor based on a Van der pol-Duffing memristor-coupled chaotic oscillator. The first memristor includes an integrator X3, a multiplier X3, and a multiplier X4. The second memristor includes an integrator X6, a multiplier X7, and a multiplier X8.

5. The coupled chaotic circuit based on the Van der Pohl-Duffing memristor chaotic oscillator according to claim 4, characterized in that: The mathematical model of the Van der pol-Duffing memristor-coupled chaotic oscillator is shown in equation (1): （1） in, x, y Indicates voltage. Represents the nonlinear damping coefficient. Indicates memristor, Represents a linearly coupled term. Represents the coupling coefficient. This represents the amplitude of a sinusoidal signal. ω Represents the angular frequency of a sinusoidal signal. t Indicates time; Equation (1) can be expressed as the differential equation shown below: （2） in, , , , , , These are the six state variables of a coupled system. This represents the output voltage of integrator 3. This represents the output voltage of integrator 2. This represents the output voltage of integrator one. This indicates the output voltage of integrator six. This represents the output voltage of integrator 5. This indicates the output voltage of integrator four; The memristor value represents the magnetic flux density. It means, that is , Both are constants, magnetic flux The voltage across the memristor is equal to the voltage across time. t The integral; The coupled chaotic circuit designed by the Van der pol-Duffing memristor chaotic oscillator above has two nonlinear systems. The two systems are coupled together by a linear coupling term, which improves the nonlinearity and stability of the entire coupled chaotic circuit.

Images