camera device

Abstract

An imaging device includes a photoelectric conversion section that generates electric charges through photoelectric conversion, a charge accumulation section that accumulates the electric charges, and a metal-oxide-semiconductor capacitor that includes a first terminal, a second terminal, a gate, an oxide layer, and at least one semiconductor region. In exposure, the first terminal is electrically connected to the charge accumulation section, the gate is electrically connected to the first terminal, the at least one semiconductor region is electrically connected to the second terminal, and the oxide layer is located between the gate and the at least one semiconductor region.

Description

Technical Field

[0001] This disclosure relates to camera devices. Background Technology

[0002] Image sensors are used in digital cameras and other applications. Examples of image sensors include CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors.

[0003] In one example of the image sensor involved, a photodiode is disposed on a semiconductor substrate.

[0004] In other examples of image sensors, a photoelectric conversion layer is disposed above a semiconductor substrate. Imaging devices with this structure are sometimes referred to as stacked imaging devices. Stacked imaging devices are described in Patent Documents 1 and 2.

[0005] In a specific example of a stacked imaging device, signal charge is generated through photoelectric conversion. The generated charge is stored in a charge storage unit. The signal corresponding to the amount of charge stored in the charge storage unit is read out via a CCD circuit or a CMOS circuit formed on a semiconductor substrate.

[0006] Prior art literature

[0007] Patent documents

[0008] Patent Document 1: Japanese Patent Application Publication No. 2010-171439

[0009] Patent Document 2: Japanese Patent Application Publication No. 2018-117347 Summary of the Invention

[0010] The problem to be solved by the present invention

[0011] This disclosure provides techniques suitable for ensuring a signal-to-noise (S / N) ratio under intermediate illumination and achieving a wide dynamic range.

[0012] Methods for solving problems

[0013] This disclosure provides a camera device comprising:

[0014] The photoelectric conversion unit generates electric charge through photoelectric conversion;

[0015] Charge storage section, which stores the charge; and

[0016] A metal-oxide-semiconductor capacitor, comprising a first terminal, a second terminal, a gate, an oxide layer, and at least one semiconductor region.

[0017] During exposure, the first terminal is electrically connected to the charge storage unit.

[0018] The gate is electrically connected to the first terminal.

[0019] The at least one semiconductor region is electrically connected to the second terminal.

[0020] The oxide layer is located between the gate and the at least one semiconductor region.

[0021] Invention Effects

[0022] The techniques disclosed herein are suitable for ensuring the S / N ratio at intermediate illuminance and achieving a wide dynamic range. Attached Figure Description

[0023] Figure 1 This is a schematic diagram showing the circuit structure of the camera device according to the first embodiment.

[0024] Figure 2 This is a circuit diagram of the pixel according to the first embodiment.

[0025] Figure 3 This is a structural diagram of the photoelectric conversion unit according to the first embodiment.

[0026] Figure 4 It is a graph showing the relationship between the capacitance value of the MOS capacitor according to the first embodiment and the voltage between terminals.

[0027] Figure 5 It is a graph showing the relationship between the S / N ratio and illuminance.

[0028] Figure 6 This is a graph showing the relationship between the capacitance value of the MOS capacitor according to the second embodiment and the voltage between terminals.

[0029] Figure 7 This is a circuit diagram of the pixel involved in the third embodiment. Detailed Implementation

[0030] (A summary of one approach covered in this disclosure)

[0031] The camera device involved in the first aspect of this disclosure includes:

[0032] The photoelectric conversion unit generates electric charge through photoelectric conversion;

[0033] Charge storage section, which stores the charge; and

[0034] A metal-oxide-semiconductor capacitor includes a first terminal, a second terminal, a gate, an oxide layer, and at least one semiconductor region. During exposure, the first terminal is electrically connected to the charge storage section.

[0035] The gate is electrically connected to the first terminal.

[0036] The at least one semiconductor region is electrically connected to the second terminal.

[0037] The oxide layer is located between the gate and the at least one semiconductor region.

[0038] The technology involved in the first method is suitable for ensuring the S / N ratio under intermediate illuminance and achieving a wide dynamic range.

[0039] In the second aspect of this disclosure, for example, in the camera device involved in the first aspect,

[0040] The capacitance value of the MOS capacitor can also change continuously in accordance with the potential of the charge storage section.

[0041] The technology involved in the second method is suitable for ensuring the S / N ratio under intermediate illumination and achieving a wide dynamic range.

[0042] In the third aspect of this disclosure, for example, in the camera device involved in the first or second aspect,

[0043] The CV characteristic, defined as the relationship between the capacitance value of the MOS capacitor and the inter-terminal voltage, which is the voltage between the first terminal and the second terminal, may also have an inflection point.

[0044] If the potential of the charge storage section changes continuously, the voltage between the terminals and the capacitance value can also change continuously across the inflection point.

[0045] According to the third method, the capacitance value of the MOS capacitor can be greatly changed in response to the change in the potential of the charge accumulation section.

[0046] In the fourth aspect of this disclosure, for example, the imaging device according to the third aspect may also include: a setting device that sets the range of potential change of the charge accumulation section to a range from a first potential to a second potential.

[0047] The CV characteristic may also include a first band region having the inflection point.

[0048] If the potential of the charge storage section changes from the first potential to the second potential, the inter-terminal voltage and the capacitance value can also change from the inter-terminal voltage and the capacitance value at one end of the first band to the inter-terminal voltage and the capacitance value at the other end of the first band.

[0049] The fourth method is an example of the configuration of a camera device.

[0050] In the fifth aspect of this disclosure, for example, in any one of the camera devices involved in aspects 1 to 4,

[0051] The second terminal can also be applied with a first DC potential so that the capacitance value of the MOS capacitor changes continuously in accordance with the inter-terminal voltage, which is the voltage between the first terminal and the second terminal.

[0052] According to method 5, the construction of the camera device can be simplified.

[0053] In the sixth aspect of this disclosure, for example, in any one of the camera devices involved in aspects 1 to 5,

[0054] The CV characteristic, defined as the relationship between the capacitance value of the MOS capacitor and the inter-terminal voltage, which is the voltage between the first terminal and the second terminal, may also include a first band and a second band.

[0055] The capacitance value in the second band is smaller than the capacitance value in the first band.

[0056] The absolute value of the ratio of the change in capacitance value in the second band to the change in inter-terminal voltage may also be smaller than the absolute value of the ratio of the change in capacitance value in the first band to the change in inter-terminal voltage.

[0057] The camera device may also include a first mode and a second mode in its photography modes.

[0058] In the first mode, the second terminal can also be applied a potential, so that the voltage between the terminals varies within the first band in response to a change in the potential of the charge accumulation section.

[0059] In the second mode, the second terminal can also be applied a potential so that the voltage between the terminals changes in the second band when the potential of the charge accumulation section changes.

[0060] In the second mode of the sixth method, it is easy to suppress at least one of the deviations from noise and signal.

[0061] The charge can also be a positive charge, and the potential of the second terminal in the second mode can be higher than the potential of the second terminal in the first mode. Alternatively, the charge can also be a negative charge, and the potential of the second terminal in the second mode can be lower than the potential of the second terminal in the first mode.

[0062] In the seventh aspect of this disclosure, for example, in any one of the camera devices involved in aspects 1 to 6,

[0063] The CV characteristic, defined as the relationship between the capacitance value of the MOS capacitor and the inter-terminal voltage, which is the voltage between the first terminal and the second terminal, may also have a first band and a third band.

[0064] The capacitance value in the third band is greater than the capacitance value in the first band.

[0065] The absolute value of the ratio of the change in capacitance value in the third band to the change in the inter-terminal voltage may also be smaller than the absolute value of the ratio of the change in capacitance value in the first band to the change in the inter-terminal voltage.

[0066] The camera device may also include a first mode and a third mode in its photography modes.

[0067] In the first mode, the second terminal can also be applied a potential, so that the voltage between the terminals varies within the first band in response to a change in the potential of the charge accumulation section.

[0068] In the third mode, the second terminal can also be applied a potential so that the voltage between the terminals changes in the third band when the potential of the charge accumulation section changes.

[0069] In the third mode of the seventh method, it is easy to suppress at least one of the deviations from noise and signal.

[0070] The charge can also be a positive charge, and the potential of the second terminal in the third mode can be lower than the potential of the second terminal in the first mode. Alternatively, the charge can also be a negative charge, and the potential of the second terminal in the third mode can be higher than the potential of the second terminal in the first mode.

[0071] In the eighth aspect of this disclosure, for example, the camera device involved in any one of the first to seventh aspects may also further include:

[0072] The amplifying transistor outputs a signal corresponding to the potential of the charge accumulation section.

[0073] The camera device can also switch the potential applied to the second terminal in accordance with the output signal.

[0074] According to method 8, it is possible to switch photography modes.

[0075] In the ninth aspect of this disclosure, for example, any of the camera devices involved in any of the first to eighth aspects may also include: a voltage source that applies a potential to the second terminal.

[0076] The ninth method is an example of the configuration of a camera device.

[0077] In the tenth aspect of this disclosure, for example, the imaging device involved in any one of the first to ninth aspects may further include: a semiconductor substrate, including the at least one semiconductor region.

[0078] The photoelectric conversion unit can also be located at a position separate from the semiconductor substrate.

[0079] According to the configuration of the 10th method, compared with the configuration of a photodiode in which the photoelectric conversion unit is disposed on a semiconductor substrate, the photoelectric conversion unit is less likely to affect the capacitance value of the MOS capacitor.

[0080] The camera device involved in the 11th aspect of this disclosure includes:

[0081] A charge storage section that stores the charge generated through photoelectric conversion; and

[0082] The transistor has a source region and a drain region that are electrically connected to each other. The transistor functions as a MOS capacitor, which includes a first terminal that is electrically connected to the charge accumulation section during exposure.

[0083] The technology involved in Method 11 is suitable for ensuring the S / N ratio at intermediate illuminance and achieving a wide dynamic range.

[0084] The camera device involved in the 12th aspect of this disclosure includes:

[0085] A charge storage section that stores the charge generated through photoelectric conversion; and

[0086] A metal-oxide-semiconductor capacitor includes a first terminal electrically connected to the charge accumulation section during exposure, an oxide layer, and a source / drain region.

[0087] In the implementation, terms such as "upper" and "lower" are used only to specify the mutual configuration between components, and are not intended to limit the posture of the camera device when it is used.

[0088] In the implementation, the conductivity type of the impurity region and other elements that accompany the positive and negative changes of the signal charge can be appropriately adjusted. Furthermore, the terminology related to the positive and negative changes of the signal charge can be appropriately replaced.

[0089] In the following embodiments, the expression "charge storage section is electrically connected to element X" can be used. Specifically, in the following embodiments, the above expression can be used even when the charge storage section is composed of part or all of element X. Therefore, the above expression should be interpreted as including the case where the charge storage section is composed of part or all of element X. Furthermore, in the following embodiments, the charge storage section and other elements can be listed as "having / possessing a charge storage section and element X". Specifically, in the following embodiments, the above listing is possible even when the charge storage section is composed of part or all of element X. In the above-listed cases, it should be permissible for the charge storage section to be composed of part or all of element X. For example, in the following embodiments, one of the source and drain of an overflow transistor can constitute a charge storage section. One of the source and drain of a reset transistor can constitute a charge storage section. A photoelectric conversion section can constitute a charge storage section.

[0090] In the following implementation, the expression "having / possessing a MOS capacitor and a specific transistor" may be used. This expression should be interpreted as including a case where the MOS capacitor is constructed using a specific transistor. That is, this expression should be interpreted as including a case where the MOS capacitor and the specific transistor are partially or entirely repeated.

[0091] In implementations, ordinal numbers such as 1st, 2nd, 3rd, etc., are sometimes used. When an ordinal number is added to an element, it is not necessary for a lower-order element of the same kind to exist. For example, using the term "3rd pattern" does not mean that a 2nd pattern must exist alongside the 3rd pattern. Furthermore, the ordinal number can be changed, deleted, or added as needed.

[0092] A general or specific approach can be implemented by components, devices, modules, systems, or methods. Furthermore, a general or specific approach can also be implemented through any combination of components, devices, modules, systems, and methods.

[0093] The additional effects and advantages of the disclosed embodiments are clear from the specification and drawings. Effects and / or advantages are provided by the various embodiments or features disclosed in the specification and drawings, and it is not necessary to obtain more than one of them, but all of them.

[0094] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Furthermore, the embodiments described below are general or specific examples. The numerical values, shapes, materials, constituent elements, arrangements and connections of constituent elements, steps, and sequences of steps shown in the following embodiments are examples and are not intended to limit the present disclosure. Various methods described in this specification can be combined with each other as long as they do not create contradictions. Additionally, among the constituent elements in the following embodiments, constituent elements not described in the independent claims representing the highest-level concept are described as arbitrary constituent elements. In the following description, constituent elements having substantially the same function are indicated by common reference numerals, and sometimes descriptions are omitted.

[0095] (First Embodiment)

[0096] Figure 1 This is a schematic diagram showing the circuit structure of the camera device 1 according to the first embodiment.

[0097] In this embodiment, the imaging device 1 is a stacked solid-state imaging device. The imaging device 1 includes multiple pixels 14, a driving circuit section, a photoelectric conversion control line 16, multiple vertical signal lines 17, multiple power supply lines 62, power supply lines 21, voltage lines 75, and multiple feedback lines 23.

[0098] Multiple pixels 14 are arranged in two dimensions on the semiconductor substrate 9. Specifically, the multiple pixels 14 are arranged in both row and column directions. The multiple pixels 14 constitute a photosensitive area. The photosensitive area is also referred to as a pixel area. The imaging device 1 can also be a line sensor. In this case, the multiple pixels 14 can be arranged in one dimension.

[0099] The driving circuitry sequentially drives multiple pixels 14 and reads out the signals obtained through photoelectric conversion. The driving circuitry includes a vertical scanning unit 15, a horizontal signal readout unit 20, multiple column signal processing units 19, multiple load units 18, and multiple differential amplifiers 22. The vertical scanning unit 15 is also referred to as a row scanning circuit. The horizontal signal readout unit 20 is also referred to as a column scanning circuit. The column signal processing unit 19 is also referred to as a row signal accumulation unit. The differential amplifiers 22 are also referred to as feedback amplifiers.

[0100] Each pixel 14 has a photoelectric conversion unit 10, an amplification transistor 11, a reset transistor 12, an address transistor 13, an overflow transistor 60, and a MOS (Metal Oxide Semiconductor) capacitor 70. The address transistor 13 is also called a row selection transistor. The overflow transistor 60 is also called a burn-in protection transistor.

[0101] In this embodiment, transistors 11, 12, 13, and 60 are MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). Specifically, in this embodiment, transistors 11, 12, 13, and 60 are N-type MOSFETs. However, transistors 11, 12, 13, and 60 could also be P-type MOSFETs. Transistors 11, 12, 13, and 60 could also be bipolar transistors or other types of transistors different from MOSFETs. The same applies to the band control transistor 56 in the third embodiment.

[0102] Power supply wiring 21 is the wiring used for the source follower power supply. Power supply wiring 21 supplies the specified power supply voltage to each pixel 14.

[0103] Each row of pixels 14 is provided with a signal line. Each row of pixels 14 is electrically connected to the vertical scanning unit 15 via the corresponding signal line.

[0104] A vertical signal line 17 is provided for each column of pixels 14. Each column of pixels 14 is electrically connected to the corresponding vertical signal line 17.

[0105] A load section 18 is provided for each vertical signal line 17. Each load section 18 is electrically connected to the corresponding vertical signal line 17. The load section 18 and the amplifying transistor 11 work together to form a source follower circuit.

[0106] Each vertical signal line 17 is provided with a column signal processing unit 19. Each column signal processing unit 19 is electrically connected to the corresponding vertical signal line 17. These column signal processing units 19 are electrically connected to the horizontal signal readout unit 20. These column signal processing units 19 are arranged in the horizontal direction, i.e., the row direction.

[0107] A differential amplifier 22 is provided for each vertical signal line 17. The negative input terminal of the differential amplifier 22 is electrically connected to the corresponding vertical signal line 17. A predetermined potential is applied to the positive input terminal of the differential amplifier 22. The output terminal of the differential amplifier 22 is electrically connected to the pixel 14 via the feedback line 23 corresponding to each column.

[0108] Figure 2 This is a circuit diagram of pixel 14 according to the first embodiment.

[0109] The photoelectric conversion unit 10 is electrically connected to one of the source and drain of the reset transistor 12, one of the source and drain of the overflow transistor 60, the first terminal Cv of the MOS (Metal Oxide Semiconductor) capacitor 70, and the gate electrode of the amplifying transistor 11. One of the source and drain of the amplifying transistor 11 is electrically connected to the power supply wiring 21. The other of the source and drain of the amplifying transistor 11 is electrically connected to one of the source and drain of the address transistor 13. The other of the source and drain of the address transistor 13 is electrically connected to the vertical signal line 17. The other of the source and drain of the reset transistor 12 is electrically connected to the feedback line 23.

[0110] The photoelectric conversion unit 10 converts light into electrical charge. In this way, the photoelectric conversion unit 10 generates a charge corresponding to the illuminance of the incident light. The charge generated through photoelectric conversion in the photoelectric conversion unit 10 is called a signal charge.

[0111] In this embodiment, the signal charge is a positive charge. However, the signal charge can also be a negative charge.

[0112] Figure 3 This is a configuration diagram of the photoelectric conversion unit 10 according to the first embodiment. The photoelectric conversion unit 10 is disposed above the semiconductor substrate 9. The photoelectric conversion unit 10 has a photoelectric conversion layer 10a, a pixel electrode 10b, and a counter electrode 10c. The photoelectric conversion layer 10a is disposed between the pixel electrode 10b and the counter electrode 10c. The photoelectric conversion layer 10a generates charge through photoelectric conversion. The pixel electrode 10b collects this charge.

[0113] The charge generated by photoelectric conversion is stored in the charge storage section 24. Specifically, the charge generated in the photoelectric conversion section 10 is stored in the charge storage section 24. The potential of the charge storage section 24 changes accordingly with the amount of charge stored in the charge storage section 24. In this embodiment, the charge storage section 24 is provided in the diffusion region of the semiconductor substrate 9.

[0114] In this embodiment, the opposing electrodes 10c in the plurality of pixels 14 form electrodes connected together. In addition, the photoelectric conversion layers 10a in the plurality of pixels 14 form films connected together.

[0115] The MOS capacitor 70 has a first terminal Cv and a second terminal TT. The first terminal Cv is electrically connected to the charge storage unit 24. Because the MOS capacitor 70 and the charge storage unit 24 are electrically connected, the charge accumulation can be smoothly distributed among the MOS capacitor 70 and the charge storage unit 24 for each pixel without interference. Specifically, the first terminal Cv and the charge storage unit 24 are interconnected without being switched by a switching element or the like.

[0116] MOS capacitor 70 is a variable capacitor. Specifically, the capacitance value of MOS capacitor 70 changes accordingly with the potential difference between terminal 1 Cv and terminal 2 TT.

[0117] The camera device 1 includes a voltage source 77. The voltage source 77 applies a potential to the second terminal TT. Specifically, the voltage source 77 applies a potential to the second terminal TT via a voltage line 75. The voltage source 77 may be included in the drive circuit section.

[0118] During exposure, the photoelectric conversion unit 10, the charge storage unit 24, and the first terminal Cv are electrically connected. In this configuration, no transistor is required between them. This is advantageous from the viewpoint of suppressing deviations in the output characteristics of each pixel 14. Furthermore, when the photoelectric conversion unit 10 has a photoelectric conversion layer 10a, a pixel electrode 10b, and a counter electrode 10c, "exposure" can be achieved by applying a voltage to the counter electrode 10c.

[0119] A MOS capacitor 70 is disposed on a semiconductor substrate 9. A photoelectric conversion unit 10 is located at a position separate from the semiconductor substrate 9. According to this configuration, compared to a configuration where the photoelectric conversion unit 10 is a photodiode disposed on the semiconductor substrate 9, the photoelectric conversion unit 10 is less likely to affect the capacitance value of the MOS capacitor 70.

[0120] The amplifying transistor 11 outputs an output signal corresponding to the potential of the charge storage section 24. Specifically, the output signal is a signal voltage.

[0121] Address transistor 13 selectively outputs the output signal from amplifying transistor 11. In this way, the output signal is read from vertical signal line 17 via amplifying transistor 11 and address transistor 13.

[0122] The reset transistor 12 resets the potential of the charge storage section 24. The reset transistor 12 can also be described as resetting the signal charge stored in the charge storage section 24.

[0123] The overflow transistor 60 turns on when the potential of the charge storage section 24 reaches the threshold potential. By turning on the overflow transistor 60, excess charge accumulated in the charge storage section 24 is discharged to the power supply wiring 62. This prevents screen burn-in and other malfunctions. The threshold potential is, for example, the power supply potential VDD.

[0124] As can be understood from the above description, in this embodiment, a setting device 65 is configured. The setting device 65 sets the range of potential change of the charge accumulation section 24 to a range from the first potential to the second potential.

[0125] The setter 65 may include a reset transistor 12. In this case, the reset transistor 12 can reset the potential of the charge storage section 24 to the first potential.

[0126] The setter 65 may include an overflow transistor 60. In this case, the overflow transistor 60 can discharge the charge accumulated in the charge storage section 24 when the potential of the charge storage section 24 reaches the second potential.

[0127] The setting device 65 may include a photoelectric conversion unit 10. In this case, a second potential may be applied to the counter electrode 10c.

[0128] The difference between the first and second potentials is, for example, 0V or higher and 6V or lower, and in a specific example, 0.5V or higher and 4V or lower. Typically, the absolute value of the first potential is smaller than the absolute value of the second potential. When the signal charge is positive, the second potential can be higher than the first potential. In this case, for example, the first potential is 0V or higher and 1V or lower, and the second potential is 3V or higher and 6V or lower. When the signal charge is negative, the overflow transistor 60 can be omitted.

[0129] In this embodiment, the charge storage section 24 is one of the source and drain of the reset transistor 12. Additionally, the charge storage section 24 is one of the source and drain of the overflow transistor 60. That is, the charge storage section 24 simultaneously functions as a signal charge storage section, as one of the source and drain of the reset transistor 12, and as one of the source and drain of the overflow transistor 60.

[0130] The operation of camera device 1 will be explained below.

[0131] The vertical scan unit 15 applies a row selection signal to the gate electrode of the address transistor 13. The row selection signal controls the on and off states of the address transistor 13. Using the row selection signal, the row to be read is scanned in the vertical direction (column direction) to select the row to be read. An output signal is read from the pixel 14 of the selected row onto the vertical signal line 17.

[0132] The vertical scanning unit 15 applies a reset signal to the gate electrode of the reset transistor 12. The reset signal controls the on and off states of the reset transistor 12. The reset signal selects the row of pixels 14 that will be reset.

[0133] The photoelectric conversion control line 16 is electrically connected to all pixels 14. A constant voltage is applied to all photoelectric conversion units 10 within the imaging device 1 via the photoelectric conversion control line 16. As described above, in this embodiment, the opposing electrodes 10c in the plurality of pixels form an electrode connected together. A constant voltage is applied to this connected electrode via the photoelectric conversion control line 16. In this embodiment, this constant voltage is a positive constant voltage.

[0134] As described above, the vertical signal line 17 is electrically connected to the other of the source and drain of the address transistor 13 in the corresponding column of pixel 14. The vertical signal line 17 transmits the output signal read from pixel 14 in the column direction, i.e., the vertical direction.

[0135] The signal processing unit 19 performs noise suppression signal processing and analog-to-digital conversion (AD conversion), etc. Noise suppression signal processing, for example, is correlated double sampling.

[0136] The horizontal signal readout unit 20 reads signals sequentially from multiple column signal processing units 19 to a horizontal common signal line (not shown).

[0137] Furthermore, power supply wiring 21 is routed in the vertical direction of pixel 14 in the photosensitive area. The vertical direction is... Figure 1 The vertical direction on the paper. The reason for routing in the vertical direction is as follows: Pixels 14 are selected row by row. Therefore, if the power supply wiring 21 is routed in the row direction, the pixel drive current of a row flows entirely in one wiring, resulting in a large voltage drop. By routing in the vertical direction, this situation can be avoided. Through the power supply wiring 21, a common source follower power supply voltage is applied to the amplification transistors 11 of all pixels 14.

[0138] When address transistor 13 and reset transistor 12 are in the ON state, the negative input terminal of differential amplifier 22 is supplied with the output signal of address transistor 13. Differential amplifier 22 performs feedback operation to make the gate potential of amplifying transistor 11 a predetermined feedback voltage. The feedback voltage is the output voltage of differential amplifier 22. In this embodiment, the output voltage of differential amplifier 22 is a positive voltage.

[0139] In the imaging device 1, pixels 14 in one row selected by the vertical scanning unit 15 are selected. The signal charge obtained by photoelectric conversion in the photoelectric conversion unit 10 within the selected pixel 14 is amplified by the amplifying transistor 11. The output signal corresponding to the signal charge is output from the amplifying transistor 11 to the vertical signal line 17 via the address transistor 13. Thereafter, the output signal is input to the horizontal signal readout unit 20 via the column signal processing unit 19, and is selected and output by the horizontal signal readout unit 20.

[0140] By turning on the reset transistor 12, the signal charge within the pixel 14 is discharged. At this time, thermal noise, known as kTC noise, is generated from the reset transistor 12. This thermal noise also remains when the reset transistor 12 is turned off and the accumulation of signal charge in the charge accumulation section 24 begins.

[0141] The thermal noise is suppressed as follows: Vertical signal line 17 is electrically connected to the negative input terminal of differential amplifier 22. The voltage on vertical signal line 17, i.e., the input voltage to the negative input terminal, is inverted and amplified by differential amplifier 22. The inverted and amplified voltage is fed back to the other of the source and drain of reset transistor 12 via feedback line 23. Thus, thermal noise generated in reset transistor 12 can be suppressed through negative feedback control. Specifically, the AC component of the thermal noise can be fed back to the other of the source and drain of reset transistor 12. In this embodiment, the DC component is above 0V and below 1V, as described above.

[0142] The following explains the MOS capacitor 70. Figure 4 It is a graph showing the relationship between the capacitance value of the MOS capacitor 70 according to the first embodiment and the voltage between terminals.

[0143] exist Figure 4 In the diagram, the horizontal axis represents the voltage between the terminals of MOS capacitor 70. Specifically, the voltage between the terminals is the difference between the potential of terminal 1 (Cv) and the potential of terminal 2 (TT). The unit of the horizontal axis is volts (V). The vertical axis represents the capacitance value of MOS capacitor 70. The unit of the vertical axis is arbitrary units (au). These will be discussed later. Figure 6 The same applies to China.

[0144] Hereinafter, the voltage between the terminals of MOS capacitor 70 is sometimes referred to as the Cv-TT voltage. The capacitance value of MOS capacitor 70 is sometimes referred to as the capacitance C. The relationship between the capacitance C and the Cv-TT voltage is sometimes referred to as the CV characteristic. According to... Figure 4 It is understood that the capacitance value C can vary depending on the voltage between Cv and TT. In this embodiment, through this CV characteristic, the MOS capacitor 70 becomes a variable capacitor.

[0145] In this embodiment, the capacitance value C and the voltage between Cv-TT change continuously. Specifically, if the voltage between Cv-TT changes continuously, the capacitance value C changes continuously. These characteristics are suitable for ensuring the S / N ratio at intermediate illumination and achieving a wide dynamic range. In this context, intermediate illumination means an illumination that is greater than the lowest illumination at which the imaging device 1 exhibits sensitivity and lower than the highest illumination at which the imaging device 1 exhibits sensitivity. The reasons for obtaining such advantages will be explained below.

[0146] Figure 5This is a graph showing the relationship between the S / N ratio and illuminance. In Figure 5 In the diagram, the horizontal axis represents illuminance, measured in lux. The vertical axis represents the S / N ratio. The solid line indicates the relationship between the S / N ratio and illuminance in the imaging device 1 of this embodiment. The dashed line indicates the relationship between the S / N ratio and illuminance in conventional 1-pixel 2-unit imaging devices. A 1-pixel 2-unit imaging device is, for example, the device described in Patent Document 2.

[0147] In the 1-pixel 2-unit method, a first camera unit and a second camera unit are configured within a single pixel. The first camera unit is used in low-illuminance conditions, exhibiting high sensitivity and low saturation. The second camera unit is used in high-illuminance conditions, exhibiting low sensitivity and high saturation. In the 1-pixel 2-unit method, a wide dynamic range is achieved using the first and second camera units. However, in the 1-pixel 2-unit method, there is a problem of low signal-to-noise ratio (S / N ratio) and image quality degradation at intermediate illumination levels. Specifically, in the 1-pixel 2-unit method, data based on signals from the first camera unit used in low-illuminance conditions and data based on signals from the second camera unit used in high-illuminance conditions are software-linked at an illumination level equivalent to intermediate illumination. At intermediate illumination levels where this link is formed, the S / N ratio related to the signal from the first camera unit is high, while the S / N ratio related to the signal from the second camera unit is low. Figure 5 It's understandable that the S / N ratio decreases sharply under intermediate illuminance.

[0148] In contrast, in this embodiment, the capacitance value C can be continuously increased relative to the increase in illuminance. This enables a "seamless" S / N ratio that does not decrease sharply at intermediate illuminance levels, and achieves a wide dynamic range.

[0149] The advantages of this implementation method can also be explained from other perspectives.

[0150] In typical stacked camera devices, it is impossible to completely transfer the charge accumulated in the charge storage section. Therefore, a configuration using a feedback loop to eliminate noise is sometimes employed. Reducing the capacitance of the charge storage section makes it easier to ensure efficient noise cancellation. Furthermore, reducing the capacitance of the charge storage section also makes it easier to ensure conversion gain. A smaller capacitance in the charge storage section is advantageous for imaging in dark scenes. On the other hand, increasing the capacitance of the charge storage section allows for a smoother change in the potential of the charge storage section relative to the change in the amount of signal charge accumulated in it. This implies high saturation in the camera device. A larger capacitance in the charge storage section is advantageous for imaging in bright scenes. A larger capacitance in the charge storage section can also be said to achieve a wide dynamic range. Thus, both small and large capacitance configurations of the charge storage section have their advantages and disadvantages.

[0151] In contrast, in this embodiment, the capacitance value C of the MOS capacitor 70 can be reduced during feedback operation. When recording in a dark scene, reducing the capacitance value C ensures conversion gain. On the other hand, when recording in a bright scene, increasing the capacitance value C improves the saturation level of the imaging device 1. According to this embodiment, an imaging device 1 that combines these advantages can be realized. Specifically, by continuously changing the capacitance value C of the MOS capacitor 70, the effects of noise can be suppressed and a wide dynamic range can be achieved.

[0152] In this embodiment, the capacitance value C changes continuously in response to the potential of the charge storage unit 24. Specifically, if the potential of the charge storage unit 24 changes continuously, the capacitance value C changes continuously. These features are suitable for ensuring the S / N ratio under intermediate illuminance and achieving a wide dynamic range.

[0153] Specifically, a potential is applied to the second terminal TT so that the capacitance value C changes continuously in accordance with the potential of the charge storage unit 24. Furthermore, specifically, a potential is applied to the second terminal TT so that the capacitance value C changes continuously as the potential of the charge storage unit 24 changes continuously.

[0154] In this embodiment, the CV characteristic of the MOS capacitor 70 has an inflection point IP. If the potential of the charge storage section 24 changes continuously, the voltage between Cv and TT and the capacitance value C change continuously across the inflection point IP. According to this configuration, it is easy to make the capacitance value C of the MOS capacitor 70 change significantly in response to the change in the potential of the charge storage section 24. Specifically, a potential is applied to the second terminal TT so that the voltage between Cv and TT and the capacitance value C change continuously across the inflection point IP when the potential of the charge storage section 24 changes continuously. In this context, the inflection point IP is the point where the sign of the value obtained by differentiating the capacitance value C by the second-order derivative of the voltage between Cv and TT changes.

[0155] In this embodiment, the CV characteristic of the MOS capacitor 70 includes a first band B1. The first band B1 has an inflection point IP. If the potential of the charge storage section 24 changes from the first potential to the second potential, the voltage and capacitance C between Cv and TT change from the values ​​at one end of the first band B1 to the values ​​at the other end. Specifically, a potential is applied to the second terminal TT so that when the potential of the charge storage section 24 changes from the first potential to the second potential, the voltage and capacitance C between Cv and TT change from the values ​​at one end of the first band B1 to the values ​​at the other end.

[0156] In this embodiment, a first DC potential is applied to the second terminal TT so that the voltage between the capacitance value C and Cv-TT changes continuously. This structure is simple. The first DC potential is, for example, 0V or higher and 2V or lower. Specifically, the first DC potential is applied to the second terminal TT so that the capacitance value C changes continuously as the potential of the charge accumulation section 24 changes continuously.

[0157] exist Figure 4 In the example shown, within the first band B1, if the voltage between Cv and TT increases, the capacitance value C changes monotonically and continuously. Here, monotonically changing means either always increasing or always decreasing. The first band B1 can be referred to as the variable capacitance band. Specifically, in the first band B1 of this embodiment, if the voltage between Cv and TT increases, the capacitance value C increases monotonically and continuously.

[0158] exist Figure 4 In the specific example shown, the first potential is 1V. The second potential is 3V. The potential applied to the second terminal TT is 0V. The variable capacitor band is the band where the voltage between Cv and TT is greater than 1V and less than 3V.

[0159] In this embodiment, the imaging device 1 includes a specific transistor 80. The specific transistor 80 is typically a MOSFET including a gate, an oxide layer, and at least one semiconductor region. The MOSFET capacitor 70 is constructed using the specific transistor 80. The source and drain regions of the specific transistor 80 are electrically connected to each other. Electrically connecting the source and drain regions of the specific transistor 80 is suitable for achieving… Figure 4 The CV characteristics of the MOS capacitor 70 are shown. The source and drain regions of a specific transistor 80 can be electrically connected by wiring. Alternatively, the specific transistor 80 can have a single semiconductor region, i.e., a source / drain region, in place of the source and drain regions, where the source and drain regions are integrated.

[0160] In this embodiment, one of the first terminal Cv and the second terminal TT is electrically connected to the source and drain of a specific transistor 80. The other of the first terminal Cv and the second terminal TT is electrically connected to the gate electrode of the specific transistor 80. Figure 1 and Figure 2 In this example, terminal TT is electrically connected to the source and drain of transistor 80. Terminal Cv is electrically connected to the gate electrode of transistor 80. Transistor 80 may be disposed on semiconductor substrate 9.

[0161] In this embodiment, the imaging mode of the camera device 1 includes a first mode. In the first mode, if the potential of the charge storage unit 24 changes continuously, the capacitance value C of the MOS capacitor 70 changes continuously. Specifically, in the first mode, a potential is applied to the second terminal TT so that the capacitance value C of the MOS capacitor 70 changes continuously when the potential of the charge storage unit 24 changes continuously.

[0162] The following describes several other embodiments. Hereinafter, the same reference numerals will be used for elements common to the embodiments already described and those described subsequently, and their descriptions may sometimes be omitted. Descriptions related to each embodiment are applicable to each other as long as they do not contradict each other technically. Embodiments can also be combined with each other as long as they do not contradict each other technically.

[0163] (Second Implementation)

[0164] In the second embodiment, it can be used in the same way as in the first embodiment. Figure 1 and Figure 2 The circuit structure is shown. In the second embodiment, the camera device 1 has a second mode and a third mode in addition to the first mode.

[0165] Figure 6 This is a graph showing the relationship between the capacitance value of the MOS capacitor 70 according to the second embodiment and the voltage between terminals. In addition to the first band B1, the CV characteristics also include a second band B2 and a third band B3.

[0166] exist Figure 6 In the example, the second band B2 is the band where the voltage between Cv and TT is lower than that of the first band B1. The third band B3 is the band where the voltage between Cv and TT is higher than that of the first band B1.

[0167] exist Figure 6 In the example, the second band field B2 is connected to the first band field B1. The third band field B3 is connected to the first band field B1. However, the second band field B2 can also be disconnected from the first band field B1. The third band field B3 can also be disconnected from the first band field B1.

[0168] In Mode 1, a potential is applied to the second terminal TT, causing the voltage between Cv and TT to vary within the first band B1 in response to a change in the potential of the charge accumulation section 24. In Mode 2, a potential is applied to the second terminal TT, causing the voltage between Cv and TT to vary within the second band B2 in response to a change in the potential of the charge accumulation section 24. In Mode 3, a potential is applied to the second terminal TT, causing the voltage between Cv and TT to vary within the third band B3 in response to a change in the potential of the charge accumulation section 24.

[0169] In the second band region B2, the capacitance value C is smaller compared to the first band region B1. Furthermore, in the second band region B2, the absolute value of the ratio of the change in capacitance value C to the change in voltage between Cv and TT is smaller compared to the first band region B1. Therefore, in the second mode, it is easier to suppress at least one of the deviations from noise and signal, and to perform high-sensitivity and low-saturation imaging. In detail, the ratio of the change in capacitance value C to the change in voltage between Cv and TT is obtained by differentiating the capacitance value C by the voltage between Cv and TT.

[0170] In the third band domain B3, the capacitance value C is larger compared to the first band domain B1. Furthermore, in the third band domain B3, the absolute value of the ratio of the change in capacitance value C to the change in voltage between Cv and TT is smaller compared to the first band domain B1. Therefore, according to the third mode, it is easy to suppress at least one of the deviations from noise and signal, and to perform low-sensitivity and high-saturation imaging.

[0171] In this embodiment, the charge stored in the charge storage section 24 is a positive charge. The potential of the second terminal TT in the second mode is higher than the potential of the second terminal TT in the first mode. The potential of the second terminal TT in the third mode is lower than the potential of the second terminal TT in the first mode.

[0172] In the modified example, the charge stored in the charge storage section 24 is a negative charge. The potential of the second terminal TT in the second mode is lower than the potential of the second terminal TT in the first mode. The potential of the second terminal TT in the third mode is higher than the potential of the second terminal TT in the first mode.

[0173] In the first mode, a first DC potential is applied to the second terminal TT, causing the voltage between Cv and TT to vary within the first band B1 in response to changes in the potential of the charge accumulation section 24. In the second mode, a second DC potential is applied to the second terminal TT, causing the voltage between Cv and TT to vary within the second band B2 in response to changes in the potential of the charge accumulation section 24. In the third mode, a third DC potential is applied to the second terminal TT, causing the voltage between Cv and TT to vary within the third band B3 in response to changes in the potential of the charge accumulation section 24. This structure is simple.

[0174] exist Figure 6 In the example shown, in the first band region B1, if the voltage between Cv and TT increases, the capacitance value C changes continuously and monotonically. The first band region B1 can be referred to as the variable capacitance band region. Specifically, in the first band region B1 of this embodiment, if the voltage between Cv and TT increases, the capacitance value C increases continuously and monotonically. On the other hand, the second band region B2 can be referred to as the low capacitance stability band region. The third band region B3 can be referred to as the high capacitance stability band region.

[0175] The Cv-TT voltage corresponding to the first band region B1 in the second embodiment differs from the Cv-TT voltage corresponding to the first band region B1 in the first embodiment. The Cv-TT voltage corresponding to the first band region B1 can be adjusted by adjusting the amount of impurity injected into the MOS capacitor 70, etc. The same applies to the Cv-TT voltage corresponding to the second band region B2 and the third band region B3. However, the Cv-TT voltage corresponding to the first band region B1 in the second embodiment can also be the same as the Cv-TT voltage corresponding to the first band region B1 in the first embodiment.

[0176] In the second embodiment, the first DC potential is, for example, 1V or more and 3V or less. The second DC potential is, for example, 3V or more and 5V or less. The third DC potential is, for example, 0V or more and 1V or less.

[0177] exist Figure 6 In the specific example shown, the first potential is 1V. The second potential is 3V. In mode 1, the potential applied to terminal TT is 2V. In mode 2, the potential applied to terminal TT is 4V. In mode 3, the potential applied to terminal TT is 0V. The variable capacitance band is the band where the voltage between Cv and TT is above -1V and below 1V. The low capacitance stability band is the band where the voltage between Cv and TT is above -3V and below -1V. The high capacitance stability band is the band where the voltage between Cv and TT is above 1V and below 3V.

[0178] In this embodiment, the camera device 1 switches the voltage applied to the second terminal TT in accordance with the output signal output from the amplifying transistor 11. In this way, the camera device 1 switches the imaging mode.

[0179] For reference Figure 6 As explained, various potentials can be applied to the second terminal TT of the MOS capacitor 70. More precisely, the CV characteristic changes due to the reverse bias effect of the MOS capacitor 70, corresponding to the potential applied to the second terminal TT. In a typical example, if the potential applied to the second terminal TT is increased, then... Figure 6 The CV characteristic curve is shifted to the right overall. By taking this shift into account when setting the applied potential to the second terminal TT, the capacitance value C of the MOS capacitor 70 can be adjusted to the desired value.

[0180] In one example, the photosensitive area is divided into multiple regions. The common potential applied to the second terminal TT of the MOS capacitors 70 of the multiple pixels 14 belonging to a certain region, and the common potential applied to the second terminal TT of the MOS capacitors 70 of the multiple pixels 14 belonging to other regions, can be set independently. For example, a first common potential is applied to the second terminal TT of the MOS capacitors 70 of the multiple pixels 14 belonging to the first region. A second common potential is applied to the second terminal TT of the MOS capacitors 70 of the multiple pixels 14 belonging to the second region. A third common potential is applied to the second terminal TT of the MOS capacitors 70 of the multiple pixels 14 belonging to the third region. The first, second, and third common potentials can be set independently. According to this configuration, it is possible to set which band of the CV characteristics of the MOS capacitor 70 to utilize for each region. For example, the imaging device 1 can be operated by utilizing the first band B1 in the first region, the second band B2 in the second region, and the third band B3 in the third region.

[0181] In the example above, after dividing the photosensitive area into multiple regions, a common potential is applied to the second terminal TT of the MOS capacitor 70 of the multiple pixels 14 belonging to each region. This avoids overly complex control and allows for adjustment of sensitivity and saturation level for each region. However, it is also possible to apply independent potentials to the second terminal TT of the MOS capacitor 70 in each pixel 14.

[0182] (Third Implementation)

[0183] Figure 7 This is a circuit diagram of pixel 94 according to the third embodiment. Pixel 94 not only has an amplification transistor 11, an address transistor 13, a reset transistor 12 and an overflow transistor 60, but also a band control transistor 56, a first capacitor element 51 and a second capacitor element 52.

[0184] The gate electrode of the amplifying transistor 11, the charge storage section 24, the first terminal Cv of the MOS capacitor 70, the photoelectric conversion section 10, and one end of the first capacitor element 51 are electrically connected. One of the source and drain of the amplifying transistor 11 is electrically connected to the power supply wiring 21. In this embodiment, the charge storage section 24 is also one of the source and drain of the reset transistor 12, and one of the source and drain of the overflow transistor 60. The other of the source and drain of the reset transistor 12, one of the source and drain of the band control transistor 56, the other end of the first capacitor element 51, and one end of the second capacitor element 52 are electrically connected. A DC potential is applied to the other end of the second capacitor element 52. The other of the source and drain of the amplifying transistor 11, one of the source and drain of the address transistor 13, and the other of the source and drain of the band control transistor 56 are electrically connected. The other of the source and drain of the address transistor 13 is electrically connected to the vertical signal line 17.

[0185] To suppress kTC noise generated when the reset transistor 12 is turned off, a band-domain control transistor 56, a first capacitor element 51, and a second capacitor element 52 are used. For detailed techniques for suppressing kTC noise, please refer to Patent Document 2, etc.

[0186] The CV characteristics of the MOS capacitor 70 in the third embodiment are compared with those of the reference. Figure 6 The CV characteristic of the MOS capacitor 70 in the second embodiment described herein is the same. In the third embodiment, a potential can be applied to the second terminal TT in the same manner as in the second embodiment. Wherein, in Figure 7 In the circuit structure of the third embodiment shown, the MOS capacitor 70 can also be used according to the first embodiment.

[0187] Various modifications can be applied to the technology described in the first to third embodiments.

[0188] Some elements in the diagram may be omitted. For example, overflow transistor 60 may be omitted.

[0189] The photoelectric conversion unit 10 may also be a photodiode disposed on the semiconductor substrate 9. The imaging device 1 may also have a transfer transistor.

[0190] Here, we will explain the phenomenon of a "charge accumulation section that accumulates the charge generated through photoelectric conversion." (Refer to...) Figure 1 , Figure 2 and Figure 7The charge storage section 24 described herein can correspond to the charge storage section involved in this manifestation. Furthermore, in the case where the photoelectric conversion section 10 is a photodiode, the photodiode can store the charge generated through photoelectric conversion. Therefore, in this case, the photodiode serving as the photoelectric conversion section 10 can correspond to the charge storage section involved in the aforementioned manifestation. The first terminal Cv of the MOS capacitor 70 can be electrically connected to this photodiode.

[0191] The relationship between the capacitance C of the MOS capacitor 70 and the potential of the charge storage section 24 is defined as the CE characteristic. This describes the behavior as "the capacitance C changes continuously in response to the potential of the charge storage section 24." This behavior means that, in the aforementioned CE characteristic, the capacitance C of the MOS capacitor 70 changes continuously in response to the potential of the charge storage section 24. This behavior does not mean that the potential of the photoelectric conversion section 10 must change continuously over time as photoelectric conversion occurs in the photoelectric conversion section 10. For example, consider the following configuration: the photoelectric conversion section 10 and the charge storage section 24 are connected via a transfer transistor. When the transfer transistor is turned on, the charge of the photoelectric conversion section 10 is transferred to the charge storage section 24, and the potential of the charge storage section 24 changes in stages. In this configuration, the characteristic of "the capacitance C of the MOS capacitor 70 changing continuously in response to the potential of the charge storage section 24" can also be achieved. The same applies to the characteristic of "the capacitance C of the MOS capacitor 70 changing continuously while the potential of the charge storage section 24 changes continuously."

[0192] To further explain the phenomenon that "the capacitance value C changes continuously in response to the potential of the charge storage section 24," this means that, in at least a portion of the aforementioned CE characteristics, the capacitance value C changes continuously in response to the potential of the charge storage section 24. The same applies to the phenomenon that "the capacitance value C changes continuously when the potential of the charge storage section 24 changes continuously."

[0193] This describes the behavior of "the voltage between capacitance C and Cv-TT changes continuously." This behavior means that, in at least a portion of the CV characteristic of the MOS capacitor 70, the voltage between capacitance C and Cv-TT changes continuously. The same applies to the behavior of "the capacitance C changes continuously when the voltage between Cv-TT changes continuously."

[0194] Industrial applicability

[0195] The camera device disclosed herein is useful for, for example, image sensors and digital cameras. The camera device disclosed herein can be used in medical cameras, robotic cameras, security cameras, cameras mounted on vehicles, etc.

[0196] Explanation of reference numerals in the attached figures:

[0197] 1 camera device

[0198] 9 Semiconductor substrates

[0199] 10 Photoelectric Conversion Unit

[0200] 10a Photoelectric conversion layer

[0201] 10-bit pixel electrode

[0202] 10c Counter electrode

[0203] 11 Amplifying Transistors

[0204] 12 reset transistors

[0205] 13-address transistor

[0206] 14, 94 pixels

[0207] 15 Vertical Scanning Units

[0208] 16 photoelectric conversion control lines

[0209] 17 Vertical Signal Lines

[0210] 18 load section

[0211] 19 signal processing units

[0212] 20-level signal readout unit

[0213] 21 Power Wiring

[0214] 22 Differential Amplifier

[0215] 23 Feedback Line

[0216] 24 Charge Accumulation Section

[0217] 51. First capacitor element

[0218] 52. Second capacitor element

[0219] 56-band control transistor

[0220] 60 overflow transistors

[0221] 62 Power Wiring

[0222] 65 Setting Tool

[0223] 70MOS capacitor

[0224] Cv terminal 1

[0225] TT 2nd terminal

[0226] 75 voltage line

[0227] 77 voltage source

[0228] 80 specific transistors

[0229] B1 First Zone

[0230] B2 Second Zone

[0231] B3 3rd zone

[0232] IP Turning Point

Claims

1. A camera device, comprising: The photoelectric conversion unit generates electric charge through photoelectric conversion; Charge storage section, which stores the charge; and A metal-oxide-semiconductor capacitor, comprising a first terminal, a second terminal, a gate, an oxide layer, and at least one semiconductor region. During exposure, the first terminal is electrically connected to the charge storage unit. The gate is electrically connected to the first terminal. The at least one semiconductor region is electrically connected to the second terminal. The oxide layer is located between the gate and the at least one semiconductor region. The CV characteristic, defined as the relationship between the capacitance value of the metal-oxide-semiconductor capacitor and the inter-terminal voltage, which is the voltage between the first terminal and the second terminal, includes a first band and a second band. The capacitance value in the second band is smaller than the capacitance value in the first band. The absolute value of the ratio of the change in capacitance value in the second band to the change in inter-terminal voltage is smaller than the absolute value of the ratio of the change in capacitance value in the first band to the change in inter-terminal voltage. The camera device has two shooting modes: a first mode and a second mode. In the first mode, a potential is applied to the second terminal so that the inter-terminal voltage varies within the first band in response to a change in the potential of the charge accumulation section. In the second mode, a potential is applied to the second terminal so that the voltage between the terminals varies within the second band when the potential of the charge accumulation section changes.

2. The camera device as described in claim 1, The capacitance value of the metal-oxide-semiconductor capacitor changes continuously in accordance with the potential of the charge storage section.

3. The camera device as described in claim 1 or 2, The CV characteristic has an inflection point. If the potential of the charge accumulation section changes continuously, the voltage between the terminals and the capacitance value change continuously across the inflection point.

4. The camera device as described in claim 3, further comprising: The setting device sets the range of potential change of the charge accumulation section to a range from the first potential to the second potential. The CV characteristic includes the first band region having the inflection point. If the potential of the charge storage section changes from the first potential to the second potential, the inter-terminal voltage and the capacitance value change from the inter-terminal voltage and the capacitance value at one end of the first band to the inter-terminal voltage and the capacitance value at the other end of the first band.

5. The camera device as described in claim 1 or 2, The second terminal is given a first DC potential so that the capacitance value of the metal-oxide-semiconductor capacitor changes continuously in accordance with the voltage between the terminals.

6. The camera device as described in claim 1 or 2, further comprising: The amplifying transistor outputs a signal corresponding to the potential of the charge accumulation section. The camera device switches the applied potential to the second terminal in accordance with the output signal.

7. The camera device as described in claim 1 or 2, further comprising: A voltage source applies a potential to the second terminal.

8. The camera device as described in claim 1 or 2, further comprising: A semiconductor substrate, including the at least one semiconductor region, The photoelectric conversion unit is separate from the semiconductor substrate.

9. A camera device, comprising: The photoelectric conversion unit generates electric charge through photoelectric conversion; Charge storage section, which stores the charge; and A metal-oxide-semiconductor capacitor, comprising a first terminal, a second terminal, a gate, an oxide layer, and at least one semiconductor region. During exposure, the first terminal is electrically connected to the charge storage unit. The gate is electrically connected to the first terminal. The at least one semiconductor region is electrically connected to the second terminal. The oxide layer is located between the gate and the at least one semiconductor region. The CV characteristic, defined as the relationship between the capacitance value of the metal-oxide-semiconductor capacitor and the inter-terminal voltage, which is the voltage between the first terminal and the second terminal, includes a first band and a third band. The capacitance value in the third band is greater than the capacitance value in the first band. The absolute value of the ratio of the change in capacitance value in the third band to the change in inter-terminal voltage is smaller than the absolute value of the ratio of the change in capacitance value in the first band to the change in inter-terminal voltage. The camera device has two shooting modes: mode 1 and mode 3. In the first mode, a potential is applied to the second terminal so that the inter-terminal voltage varies within the first band in response to a change in the potential of the charge accumulation section. In the third mode, a potential is applied to the second terminal so that the voltage between the terminals varies in the third band when the potential of the charge accumulation section changes.

10. The camera device as claimed in claim 9, The capacitance value of the metal-oxide-semiconductor capacitor changes continuously in accordance with the potential of the charge storage section.

11. The camera device as described in claim 9 or 10, The CV characteristic has an inflection point. If the potential of the charge accumulation section changes continuously, the voltage between the terminals and the capacitance value change continuously across the inflection point.

12. The camera device as claimed in claim 11, further comprising: The setting device sets the range of potential change of the charge accumulation section to a range from the first potential to the second potential. The CV characteristic includes the first band region having the inflection point. If the potential of the charge storage section changes from the first potential to the second potential, the inter-terminal voltage and the capacitance value change from the inter-terminal voltage and the capacitance value at one end of the first band to the inter-terminal voltage and the capacitance value at the other end of the first band.

13. The camera device as described in claim 9 or 10, The second terminal is given a first DC potential so that the capacitance value of the metal-oxide-semiconductor capacitor changes continuously in accordance with the voltage between the terminals.

14. The camera device as described in claim 9 or 10, further comprising: The amplifying transistor outputs a signal corresponding to the potential of the charge accumulation section. The camera device switches the applied potential to the second terminal in accordance with the output signal.

15. The camera device as described in claim 9 or 10, further comprising: A voltage source applies a potential to the second terminal.

16. The camera device as described in claim 9 or 10, further comprising: A semiconductor substrate, including the at least one semiconductor region, The photoelectric conversion unit is separate from the semiconductor substrate.

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