Circuit interface testing method

Abstract

The application relates to a circuit interface test method, which comprises the following steps: (1) a circuit structure enters a power-on reset state, and a preset number of window periods are set; (2) the circuit structure enters a first window period, and a chip waits to receive a function timing signal matching the characteristics of a preset interface; (3) the chip further judges whether the function timing signal with the related characteristics is received, if yes, the chip directly enters a function mode of the current preset interface; otherwise, the step (4) is entered; (4) if the function timing signal with the related characteristics is not received by each chip pin in the current window period, the circuit structure returns to the step (2) and enters a next window period for test processing, until the traversal of all the preset number of window periods is completed, and the step (5) is entered; (5) the chip enters a normal working state. The circuit interface test method adopts the application, can adapt to application requirements in different scenes, reduces packaging cost, and improves the packaging success rate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit test, in particular to the technical field of circuit interface test, and specifically to a circuit interface test method. BACKGROUND

[0002] When designing integrated circuits, test, programming and debugging interfaces are generally reserved. The test interface refers to the circuit structure between the integrated circuit and the test system, which is used to determine whether the function and performance of the circuit can meet the shipment standard. The programming interface refers to the circuit structure between the integrated circuit and the programming system, which is used to download program files to the ROM (common ROMs include OTP, MTP, Flash, etc.) of the MCU circuit through ISP (In System Programing) or ICP (In Circuit Programing) programming methods. The debugging interface refers to the circuit structure between the integrated circuit and the debugging system, which is used to debug the mode parameters or programs of the chip. Common debugging interfaces include JTAG and SWD.

[0003] The prior art generally allocates different chip pins to the three types of interfaces, or allocates the same chip pin to two or three types of interfaces to achieve pin function multiplexing, but each type of interface is only allocated to a fixed chip pin.

[0004] For the test interface, since it itself occupies several chip pins (the specific number is determined by the test module of the chip), the IO port characteristics (input and output functions, pull-up and pull-down functions, output high voltage driving capability, output low voltage driving capability, etc.) of the pin cannot be tested, which reduces the test coverage. In actual application scenarios, if these pins are used, the circuit may fail, which reduces the reliability of the whole machine and causes irreparable consequences.

[0005] For the programming interface, in the ISP mode, i.e., programming and writing on the board, the chip is not removed and placed in the programmer. The chip pin corresponding to the programming interface needs to be reserved on the board. If the chip pin is fixed, it will limit the peripheral schematic design and PCB layout design in actual application, which is poor in flexibility and low in efficiency.

[0006] For the debugging interface, since it itself occupies several chip pins (the specific number is determined by the debugging module of the chip), the pin cannot be used as a normal IO port or other analog functions given by the chip in the debugging mode, which affects the scheme development or whole machine debugging, is poor in flexibility and low in efficiency.

[0007] Because the same chip is often packaged into different pin numbers in practical application, such as 20 PAD chip, in addition to the circuit packaged into 20 pin, it is also possible to package into 8 pin circuit, in the case of small pin number application, the test interface, burning interface and debugging interface pin defined by the chip must be sealed out, otherwise the corresponding function cannot be realized, at this time, higher requirements are put forward to the package, resulting in poor flexibility, poor degree of freedom, and significantly reduced adaptability in practical application. SUMMARY

[0008] The purpose of the present application is to overcome the above-mentioned shortcomings of the prior art, and to provide a circuit interface test method with high flexibility and good degree of freedom.

[0009] In order to achieve the above-mentioned purpose, the circuit interface test method of the present application is as follows:

[0010] The circuit interface test method, which mainly comprises the following steps:

[0011] (1) The circuit structure enters the power-on reset state, and sets the preset number of window periods according to the number of chip pins and the number of pins required by each preset interface;

[0012] (2) The circuit structure enters the first window period, and the chip automatically allocates each preset interface to different chip pins, and waits to receive a function timing signal matching the characteristics of the preset interface respectively;

[0013] (3) The chip further judges whether each chip pin receives the function timing signal of the related characteristics, if yes, the chip directly enters the function mode of the current preset interface, and completes the corresponding function; otherwise, step (4) is entered;

[0014] (4) If each chip pin does not receive the function timing signal of the related characteristics in the current window period, the circuit structure returns to step (2) and enters the next window period for test processing, until the traversal of all preset number of window periods is completed, and step (5) is entered;

[0015] (5) The chip enters the normal working state.

[0016] Preferably, each preset interface comprises:

[0017] Test interface, burning interface and debugging interface.

[0018] Preferably, the circuit structure sets the preset number of window periods according to the following rules:

[0019]

[0020] Wherein, A is the pin number of the current chip, B is the fixed pin, the fixed pin includes power pin, ground pin and analog pin, C is the pin number required by the current interface.

[0021] Preferably, the step (2) comprises:

[0022] (2.1) the circuit structure enters the first window period, and the test interface, the burning interface and the debugging interface are assigned with corresponding test pins according to the preset test rule;

[0023] (2.2) after the test pin assignment is completed, the chip automatically assigns the test interface, the burning interface and the debugging interface to different chip pins;

[0024] (2.3) the test interface, the burning interface and the debugging interface enter the waiting state, respectively waiting for the functional timing signal matching the feature of the preset test pin.

[0025] Preferably, the step (3) comprises:

[0026] (3.1) the chip judges whether each preset interface receives the functional timing signal matching the feature of the preset test pin, if yes, it enters step (3.2); otherwise, it directly enters step (4);

[0027] (3.2) the chip further judges the signal receiving interface receiving the corresponding functional timing signal, after confirming the functional characteristics of the signal receiving interface, it directly enters the functional test mode of the current interface to complete the corresponding test function.

[0028] Preferably, the step (3.2) further comprises:

[0029] the chip only sets the interface corresponding to the first received functional timing signal as the signal receiving interface, after the signal receiving interface is set, other interfaces will automatically close the test mode, the circuit structure will enter the test mode of the current signal receiving interface to complete the corresponding test function.

[0030] Preferably, when the signal receiving interface is the test interface, the circuit structure makes the current chip enter the test mode through the peripheral test system;

[0031] when the signal receiving interface is the burning interface, the circuit structure makes the current chip enter the burning mode through the peripheral burning system;

[0032] When the signal receiving interface is the debugging interface, the circuit structure makes the current chip enter the debugging mode through the peripheral debugging system.

[0033] Preferably, the circuit structure further comprises:

[0034] If all the function pins of the chip do not receive the function timing signal in the current window period, the chip will automatically enter the next window period and reassign new function pins to each preset interface to wait for receiving new function timing signals.

[0035] Preferably, if the circuit structure still does not receive the function timing signal in the last window period of the preset number of window periods, the current circuit structure is reset and the chip enters the normal working state.

[0036] Compared with the prior art, the circuit interface test method of the application can automatically assign the test interface, the burning interface and the debugging interface pins to any pin of the chip, greatly increasing the flexibility; the test coverage is increased, the problem that the direct test pin cannot be tested is solved; the degree of freedom in designing the application scheme and the burning interface scheme is greatly increased, which is conducive to the optimal PCB wiring and better application effect, and can better adapt to the application requirements of different customers in different scenarios; the debugging interface is assigned according to the application requirements, which solves the problem that the debugging interface cannot participate in the simulation debugging; when considering small pin packaging, it is more flexible, without abandoning some functions or making complex wiring to meet the interface, which increases the application scenarios, reduces the packaging cost, and effectively improves the packaging success rate. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 The flowchart of the circuit interface test method of the application.

[0038] Figure 2 The timing change state diagram of a specific embodiment of the circuit interface test method of the application. DETAILED DESCRIPTION

[0039] In order to more clearly describe the technical content of the application, the following further describes in combination with specific embodiments.

[0040] Before embodiments of the present application are described in detail, it is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. It is also to be understood that where the description uses terms such as first, second, third, etc. and other colloquial terms, it is not to be construed as implying any actual relationships between the entities so described. The terms "including", "containing", "comprising", or any other similar terms are intended to be broad and encompass the terms "consisting" and "consisting essentially of". It is intended that all embodiments disclosing business methods, kits, and / or compositions are intended to be covered by the scope of the present application. It is also intended that the scope of the present application encompasses all such business methods, kits, and / or compositions.

[0041] Referring to Figure 1 The circuit interface test method, wherein the method comprises the following steps:

[0042] (1) The circuit structure enters a power-on reset state, and a preset number of window periods is set according to the number of chip pins and the number of pins required by each preset interface;

[0043] (2) The circuit structure enters the first window period, and the chip automatically allocates each preset interface to different chip pins and waits to receive a functional timing signal matching the characteristics of the preset interface;

[0044] (3) The chip further determines whether each chip pin receives the functional timing signal of the related characteristics, if yes, the chip directly enters the functional mode of the current preset interface and completes the corresponding function; otherwise, step (4) is entered;

[0045] (4) If each chip pin does not receive the functional timing signal of the related characteristics in the current window period, the circuit structure returns to step (2) and enters the next window period for test processing, until the traversal of all the preset number of window periods is completed and step (5) is entered;

[0046] (5) The chip enters a normal working state.

[0047] As a preferred embodiment of the present application, each preset interface comprises:

[0048] a test interface, a burning interface, and a debugging interface.

[0049] It can be understood that in actual application, each preset interface involved in the present technical solution is not limited to the test interface, the burning interface, and the debugging interface mentioned above, and the setting of the preset interface can be specifically set according to actual conditions. The above is only a schematic enumeration.

[0050] As a preferred embodiment of the present application, the circuit structure sets the preset number of window periods according to the following rules:

[0051]

[0052] Wherein, A is the pin number of the current chip, B is the fixed pin, the fixed pin includes the power pin, the ground pin and the analog pin, and C is the pin number required by the current interface.

[0053] Suppose that a chip has A pins, after removing the power, ground, analog pins, a total of B pins, the general IO port that can be used for distribution still has A-B, if the pin number required by an interface is C, theoretically, there can be (A-B)! /

C!(A-B-C)!

[0054] In actual application, the technical solution distributes a plurality of window periods, in each different window period, the chip automatically distributes the test interface, the burning interface and the debugging interface to different chip pins. If the chip receives a characteristic timing signal from the pin of the corresponding interface in a certain window period, the chip enters the corresponding test, burning or debugging mode, and interacts with the test system, the burning system or the debugging system to complete the corresponding function; otherwise, the next window period is entered. If all window periods are traversed and no timing signal (test, burning, debugging signal) matching is found, the chip works in the normal mode.

[0055] As a preferred embodiment of the present application, the step (2) comprises:

[0056] (2.1) the circuit structure enters the first window period, and distributes the corresponding test pins to the test interface, the burning interface and the debugging interface according to the preset test rule;

[0057] (2.2) after the test pin distribution is completed, the chip automatically distributes the test interface, the burning interface and the debugging interface to different chip pins;

[0058] (2.3) the test interface, the burning interface and the debugging interface enter the waiting state, and respectively wait for the functional timing signal matching the characteristics of the preset test pin.

[0059] As a preferred embodiment of the present application, the step (3) comprises:

[0060] (3.1) the chip judges whether the functional timing signal matching the characteristics of the preset test pin is received by each preset interface, if yes, step (3.2) is entered; otherwise, step (4) is directly entered;

[0061] (3.2) The chip further judges the signal receiving interface receiving the corresponding function timing signal, and after confirming the function characteristics of the signal receiving interface, directly enters the function test mode of the current interface to complete the corresponding test function.

[0062] As a preferred embodiment of the present application, the step (3.2) further comprises:

[0063] The chip only sets the interface corresponding to the first received function timing signal as the signal receiving interface, and when the signal receiving interface is set, other interfaces will automatically close the test mode, and the circuit structure enters the test mode of the current signal receiving interface to complete the corresponding test function.

[0064] As a preferred embodiment of the present application, when the signal receiving interface is the test interface, the circuit structure makes the current chip enter the test mode through the peripheral test system;

[0065] When the signal receiving interface is the burning interface, the circuit structure makes the current chip enter the burning mode through the peripheral burning system;

[0066] When the signal receiving interface is the debugging interface, the circuit structure makes the current chip enter the debugging mode through the peripheral debugging system.

[0067] As a preferred embodiment of the present application, the circuit structure further comprises:

[0068] If all function pins of the chip do not receive function timing signals in the current window period, the chip will automatically enter the next window period and reassign new function pins to each preset interface to wait for receiving new function timing signals.

[0069] As a preferred embodiment of the present application, if the circuit structure still does not receive function timing signals in the last window period of the preset number of window periods, the current circuit structure is reset and ends, and the chip enters the normal working state.

[0070] Please refer to Figure 2As shown, in a specific embodiment of the present application, after power-on reset, the chip enters window period 1, at which time the chip assigns the pins of the test interface as 1 & 2, assigns the pin of the burning interface as 1, and assigns the pins of the debugging interface as 1 & 2 & 3. (Note: the number of pins assigned by different interfaces each time is determined by different circuits and different structures) During the window period, if a test signal sent by a test system is received at the 1 & 2 pins, the chip enters the test mode; if a burning signal sent by a burning system is received at the 1 pin, the chip enters the burning mode; and if a debugging signal sent by a debugging system is received at the 1 & 2 & 3 pins, the chip enters the debugging mode. Once one of the three interfaces receives the corresponding signal, the other two interfaces are automatically closed, i.e., if a test signal sent by a test system is received at the 1 & 2 pins, the chip enters the test mode, and the burning interface and the debugging interface are closed at the same time, and if a burning signal is received at the 1 pin or a debugging signal is received at the 1 & 2 & 3 pins, the burning interface and the debugging interface do not respond, and the chip does not enter the burning mode or the debugging mode. In actual application, the test signal, the burning signal, and the debugging signal are sent by peripheral test systems, burning systems, and debugging systems, and each time the purpose is clear, and the three situations do not occur at the same time.

[0071] If during the window period 1, the relevant pins all receive the test signal, the burning signal, or the debugging signal, the chip enters window period 2, and newly assigns the pins of the test interface, the burning interface, and the debugging interface, and waits to receive the signal. If during the last window period n, the test signal, the burning signal, or the debugging signal is not received, the system reset ends, and the chip enters the normal working state.

[0072] In actual application, the window period is designed according to the number of pins of the chip and the number of pins required by the test interface, the burning interface, and the debugging interface, and in theory, all pin arrangement combinations can be covered, and the window period can also be reduced according to the actual situation.

[0073] Each window period is automatically assigned the pins of the test interface, the burning interface, and the debugging interface by the chip, and waits to receive the test signal, the burning signal, and the debugging signal, and this process does not need to be configured through other software or hardware.

[0074] When the circuit structure receives a certain functional timing signal, the other two interface signals are automatically closed, i.e., the test mode, the burning mode, and the debugging mode only enter a certain mode, and the three modes do not compete with each other.

[0075] If the test signal, the burning signal, or the debugging signal is not received during the current window period, the circuit structure automatically enters the next window period, and newly assigns the pins of the test interface, the burning interface, and the debugging interface;

[0076] If no test, burn, or debug signal is received after traversing all the window periods, the system reset is completed and the chip enters a normal working state.

[0077] Any procedural or methodological descriptions in the flow charts or otherwise described herein can be understood to represent modules, segments, or portions of code that include executable instructions for implementing the steps of a particular logic function or process, and the scope of the preferred embodiments of the present application includes additional implementations in which the functions are performed in an order different from that shown or discussed, including substantially simultaneously or in reverse order, as appropriate, in accordance with the functions involved, as will be understood by those skilled in the art of the embodiments to which the present application pertains.

[0078] It should be understood that portions of the present application can be realized with hardware, software, firmware or a combination thereof. In the above embodiments, a plurality of steps or methods can be realized with software or firmware stored in a memory and executed by a suitable instruction execution device.

[0079] It can be understood by those skilled in the art of the present application that all or part of the steps carried out by the above-mentioned embodiments can be instructed by a program to complete the relevant hardware, and the program can be stored in a computer readable storage medium, and the program includes one of the steps of the method embodiments or a combination thereof when executed.

[0080] In the description of the present specification, the description of the terms "an embodiment", "some embodiments", "an example", "a specific example", or "embodiments" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily mean the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0081] Although the embodiments of the present application have been shown and described above, it can be understood that the above-mentioned embodiments are exemplary and cannot be understood as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above-mentioned embodiments within the scope of the present application.

[0082] Compared with the prior art, the circuit interface test method has the following advantages: the test interface, the burning interface and the debugging interface pin distribution can be automatically distributed to any pin of the chip, the flexibility is greatly increased; the test coverage is increased, the problem that the direct test pin cannot be tested is solved; the freedom degree is greatly increased when designing the application scheme and the burning interface scheme, which is beneficial to the PCB wiring of the more optimal solution, better application effect is achieved, and the application requirements of different customers and different scenes can be better adapted; the debugging interface is distributed according to the application requirements, the problem that the debugging interface cannot participate in the simulation debugging is solved; when the small pin package is considered, the flexibility is further improved, some functions do not need to be abandoned or complex wiring is not needed in order to match the interface, the application scene is increased, the packaging cost is reduced, and the packaging success rate is effectively improved.

[0083] In this specification, the application has been described with reference to its particular embodiments. It is clear, however, that various modifications and changes can be made without departing from the spirit and scope of the application. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

Claims

1. A method of testing a circuit interface, characterized by, The method comprises the following steps: (1) the circuit structure enters a power-on reset state, and a preset number of window periods is set according to the number of chip pins and the number of pins required by each preset interface; (2) the circuit structure enters the first window period, and the chip automatically allocates each preset interface to different chip pins and waits to receive a functional timing signal matching the characteristics of the preset interface; (3) the chip determines whether each chip pin receives a functional timing signal with relevant characteristics, if yes, the chip directly enters the functional mode of the current preset interface to complete the corresponding function; otherwise, step (4) is entered; (4) if each chip pin does not receive a functional timing signal with relevant characteristics in the current window period, the circuit structure returns to step (2) and enters the next window period for testing, until all the preset number of window periods are traversed, and step (5) is entered; (5) the chip enters a normal working state; Each preset interface comprises: a test interface, a burning interface and a debugging interface; The circuit structure sets the preset number of window periods according to the following rules: Wherein, A is the number of pins of the current chip, B is a fixed pin, the fixed pin includes a power pin, a ground pin and an analog pin, and C is the number of pins required by the current interface.

2. The circuit interface test method of claim 1, wherein, Step (2) comprises: (2.1) the circuit structure enters the first window period, and according to the preset test rule, the test interface, the burning interface and the debugging interface are allocated corresponding test pins; (2.2) after the test pin allocation is completed, the chip automatically allocates the test interface, the burning interface and the debugging interface to different chip pins; (2.3) the test interface, the burning interface and the debugging interface enter a waiting state, and respectively wait for a functional timing signal matching the characteristics of the preset test pin.

3. The circuit interface test method of claim 1, wherein, Step (3) comprises: (3.1) the chip determines whether each preset interface receives a functional timing signal matching the characteristics of the preset test pin, if yes, step (3.2) is entered; otherwise, step (4) is directly entered; (3.2) the chip determines the signal receiving interface receiving the corresponding functional timing signal, and after confirming the functional characteristics of the signal receiving interface, directly enters the functional test mode of the current interface to complete the corresponding test function.

4. The circuit interface test method of claim 3, wherein, Step (3.2) further comprises: The chip only sets the interface receiving the first functional timing signal as the signal receiving interface, and when the signal receiving interface is set, other interfaces will automatically close the test mode, the circuit structure will enter the test mode of the current signal receiving interface to complete the corresponding test function.

5. The circuit interface test method of claim 3, wherein when the signal receiving interface is the test interface, the circuit structure makes the current chip enter a test mode through a peripheral test system; When the signal receiving interface is the burning interface, the circuit structure makes the current chip enter a burning mode through a peripheral burning system; When the signal receiving interface is the debugging interface, the circuit structure makes the current chip enter a debugging mode through a peripheral debugging system.

6. The circuit interface test method according to any one of claims 1 to 5, characterized by, The circuit structure further comprises: If all the function pins of the chip do not receive function timing signals in the current window period, the chip will automatically enter the next window period and reassign new function pins to each preset interface to wait for receiving new function timing signals.

7. The circuit interface test method according to any one of claims 1 to 5, characterized by, If the circuit structure still does not receive function timing signals in the last window period of the preset number of window periods, the current circuit structure is reset and ends, and the chip enters a normal working state.

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