Static computation partitioning method for improving performance of storage-computing integrated system

Abstract

The application discloses a static calculation division method for improving the performance of a memory-computing integrated system, and comprises the following steps: S1, dividing a program into a plurality of basic blocks, and converting the program into an annotated call graph of the program, wherein a node in the annotated call graph corresponds to a basic block in the program; S2, dividing each node in the annotated call graph into an in-memory computing unit or a processor on a chip, forming a plurality of division schemes of the program, and outputting a program division scheme with the shortest execution time. v Based on offline analysis of the program, a calculation division algorithm between the processor on the chip and the in-memory computing unit is proposed, and finally, the calculation division problem of the memory-computing integrated system is converted into a minimum cut problem of the annotated call graph. The calculation division obtained by using the method can effectively improve the system performance and reduce the energy consumption caused by unnecessary data movement.

Description

Technical Field

[0001] This invention belongs to the field of computer technology, and more specifically, this invention relates to a static computation partitioning method for improving the performance of an in-memory computing system. Background Technology

[0002] With the booming development of emerging fields such as big data, deep learning, and artificial intelligence, the datasets used in applications are constantly increasing, and information processing is gradually shifting from traditional "computation-intensive" to "memory-intensive." In the past decade, as silicon-based electronic devices have approached their physical limits and Moore's Law is nearing its end, the performance of central processing units (CPUs) has struggled to improve rapidly and continuously. Simultaneously, traditional storage devices cannot simultaneously possess both "high speed" and "high density," leading to the current von Neumann architecture, centered on computation, heavily relying on hierarchical storage structures to achieve a trade-off between system performance and storage capacity. However, in the era of big data, the discretized and randomized data access causes a precipitous drop in the efficiency of hierarchical storage, even pushing it to the brink of failure. Frequent data movement between the processor and multiple levels of storage results in a series of problems, including bandwidth limitations, decreased computational efficiency, and low energy efficiency. Traditional von Neumann architecture computers are facing severe challenges and are struggling to meet the computational demands of an intelligent society.

[0003] To alleviate or even break down the memory wall, the main technological approach currently is to completely abandon the inherent concept of "separation of memory and computation" in the von Neumann architecture, making breakthroughs at the underlying architecture level and redesigning the computer architecture. This approach is called processing-in-memory (PIM) architecture. The main idea of ​​PIM architecture is to integrate computing units within memory, utilizing the ultra-high bandwidth and low access latency of memory to achieve near-data computation. In recent years, manufacturing enabling technologies such as 3D stacked memory and through-silicon vias (TSVs) and the emergence of "killer applications" such as big data and neural networks have brought new opportunities for the development of PIM architecture. By integrating high-concurrency, high-performance computing units within memory to perform near-data or even on-site computation, PIM architecture can achieve performance acceleration of one to two orders of magnitude for some applications and reduce data handling energy consumption by about 80%. Some new non-volatile memory (NVM) devices can even achieve complete integration of computation and storage. Since data does not need to be frequently moved between memory and CPU through interfaces, in-memory computing architecture has become one of the feasible means to alleviate or even break down the storage wall.

[0004] Currently, there have been some studies on the computation partitioning problem in in-memory computing systems, but the main focus is on solving the computation partitioning between multiple computing units in memory. For example, Prometheus proposed a computation partitioning algorithm based on community detection to minimize the data transfer between different computing units within the HMC. Such methods usually assume that all computation tasks are executed in memory, and the on-chip processor is almost completely idle, wasting valuable computing resources. Summary of the Invention

[0005] This invention provides a static computation partitioning method to improve the performance of in-memory computing systems, aiming to address the aforementioned problems.

[0006] This invention is implemented as follows: a static computation partitioning method for improving the performance of an in-memory computing system, the method comprising the following steps:

[0007] S1. Divide the program into several basic blocks and transform the program into a comment call graph. The nodes in the comment call graph correspond to the basic blocks in the program.

[0008] S2. Divide each node v in the annotation call diagram into internal computing units or on-chip processors to form multiple program partitioning schemes, and output the program partitioning scheme with the shortest execution time.

[0009] Furthermore, the method for generating the annotation-call graph is as follows:

[0010] S11. Use the LLVM intermediate layer to abstract high-level programming languages ​​into assembly language, and then instrument the assembly language to form the program's execution flowchart.

[0011] S12. Generate the post-order dominance tree of the execution flowchart based on the Lengauer-Tarjan algorithm;

[0012] S13. Based on the dominance relationship between basic blocks in the post-order dominance tree, control dependency edges are formed in the annotation call graph. After adding data dependency edges, adding the attributes of edges and nodes, the annotation call graph is formed.

[0013] Furthermore, the process of generating control dependency edges is as follows:

[0014] S131. Check if there is a loop in the execution flowchart of the detection program. If there is, execute step S132 and then step S133. If there is no loop, execute step S133 directly.

[0015] S132. Traverse all edges e in the post-order dominator tree edge set E2. 2 In the execution process, edge set E1 is deleted along with edge e. 2 Identical edges form control dependency edges in the annotation call graph;

[0016] S133. All nodes in the ring depend on the head node, thereby extracting control dependencies.

[0017] Furthermore, the specific formula for calculating the execution time of the program partitioning scheme is as follows:

[0018] T all =T CPU +T PIM +T M

[0019] Among them, T CPU T represents the total execution time on the on-chip processor. PIM T is the total execution time of the in-memory computing unit. M This represents the total data transfer time between the on-chip processor and the in-memory computing unit.

[0020] Furthermore, T CPU T PIM T M The specific calculation formula is as follows:

[0021]

[0022]

[0023]

[0024]

[0025] in, This represents the total execution time of all basic blocks in the point set S on the on-chip processor. This represents the total time taken to execute all basic blocks in the point set T on in-memory computational units. S represents the total time for data transfer between the on-chip processor and the in-memory computing unit. u,v BW represents the amount of data transferred between basic block u and basic block v, and BW represents the memory read / write bandwidth.

[0026] When the instruction corresponding to basic block v is executed on the in-memory computation unit, I v =1, when the instruction corresponding to basic block v is executed in the on-chip processor, I v =0.

[0027] Furthermore, the specific method for obtaining the program partitioning scheme with the shortest execution time is as follows:

[0028] The basic block u with the highest number of executions is distributed to the in-memory computing unit for execution, and the remaining basic blocks are distributed to the on-chip processor for execution. The partitioning scheme of the program is used as the initial solution, and the total execution time of the partitioning scheme is calculated.

[0029] In each iteration, select those whose execution frequency exceeds a threshold T. H The basic blocks are distributed to the set of basic blocks {U} that are executed by the in-memory computing units, in the current optimal solution {I}. opt Based on the inverted number of the basic block j variable I j This forms the i-th feasible solution {I}. i ;

[0030] Calculate partitioning scheme {I} i The corresponding execution time T i Calculate the execution time T i The execution time T of the current optimal solution opt The difference ΔT, if ΔT is negative, then a feasible solution {I} is possible. i That is, find the current optimal solution and update the current optimal time to the execution time T. i If ΔT is positive, then the solution {I} is feasible. i If the execution time is longer than the current optimal solution, accept the feasible solution {I} with probability r. i A feasible solution {I} is about to be found. i As the current optimal solution, update the current optimal execution time T. i .

[0031] Furthermore, if ΔT = 0, compare the feasible solutions {I} i and the current optimal solution {I} opt The data transfer power consumption ΔE corresponding to the partitioning scheme is determined, and the partitioning scheme with the lower data transfer power consumption is selected as the current optimal solution.

[0032] Furthermore, the specific formula for calculating probability r is as follows:

[0033]

[0034] Where k is the correction coefficient, representing the current inversion of I. j The percentage of executions of the basic block relative to the maximum number of executions, where ΔT is the number of executions of the i-th feasible solution {I}. i The corresponding execution time T i The execution time T of the current optimal solution opt The difference.

[0035] The static computation partitioning method for improving the performance of in-memory computing systems provided by this invention has the following beneficial technical effects: Addressing the problem that existing computation partitioning algorithms do not consider the coexistence of on-chip processors and in-memory computing units, this invention proposes a computation partitioning method between on-chip processors and in-memory computing units based on offline program analysis. Through offline program analysis, an annotated call graph of the in-memory computing program is generated, ultimately transforming the computation partitioning problem in the in-memory computing system into a minimum cut problem in the annotated call graph. Combined with the method proposed in this invention to accelerate the solution and convergence speed of the partitioning problem, the combined performance of on-chip processors and in-memory computing units can be fully utilized, while reducing unnecessary data transfer overhead. Attached Figure Description

[0036] Figure 1 A flowchart illustrating a static computation partitioning method for improving the performance of an in-memory computing system provided in an embodiment of the present invention;

[0037] Figure 2 This is a flowchart illustrating the generation of a comment call graph from source code, provided in an embodiment of the present invention. In the flowchart, (a) is the source code of the program, (b) is the intermediate representation of the program, (c) is the execution flowchart of the program, and (d) is the comment call graph of the program.

[0038] Figure 3 The diagram shows the process of dividing a basic block according to an embodiment of the present invention, where (a) is a schematic diagram of the division and (b) is a schematic diagram of the corresponding division result. Detailed Implementation

[0039] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, so as to help those skilled in the art to have a more complete, accurate and in-depth understanding of the inventive concept and technical solution of the present invention.

[0040] This invention proposes a computation partitioning method to maximize system performance in an in-memory computing architecture. It abstracts the execution process of an in-memory computing program as an annotated call graph (ACG) and transforms computation partitioning into a minimum cut problem within the ACG, thereby achieving quantifiable computation partitioning. This invention treats the in-memory computing unit as a whole, comprehensively considering the computation partitioning between the on-chip processor (i.e., CPU) and the in-memory computing unit, fully leveraging the respective advantages of both to maximize the overall performance of the in-memory computing system.

[0041] Figure 1 A flowchart of a static computation partitioning method for improving the performance of an in-memory computing system provided in an embodiment of the present invention is shown. The method specifically includes the following steps:

[0042] S1. Divide the program into several basic blocks and transform the program into a comment call graph. The nodes in the comment call graph correspond to the basic blocks in the program.

[0043] An annotation call graph is a directed acyclic graph (DAG) that represents the execution and dependency relationships between different sub-procedures (i.e., basic blocks) during program execution. The annotation call graph G = {V, E, P} is essentially a program dependency graph, consisting of three parts: a node set V, an edge set E, and an attribute set P. Each node v ∈ V represents a sub-procedure or sub-function of the program. Each edge e = (u, v) ∈ E in the annotation call graph represents the dependency relationship between node u and node v, including control dependencies and data dependencies. Nodes and edges in the annotation call graph also possess additional attributes p ∈ P, which mainly include: the number of times the node or edge is executed, the execution time, and the storage space. This invention provides a detailed description of the generation process of the annotation call graph, as follows:

[0044] S11. Use the LLVM intermediate layer to abstract high-level programming languages ​​into assembly language, and then instrument the assembly language to form the program's execution flowchart.

[0045] S12. Generate the post-order dominance tree of the execution flowchart based on the Lengauer-Tarjan algorithm;

[0046] S13. Based on the dominance relationships between basic blocks in the post-order dominance tree, control dependency edges are formed in the annotation call graph. After adding data dependency edges, adding edge and node attributes, the annotation call graph is formed. The specific process of generating control dependency edges is as follows:

[0047] S131. Check if there is a loop in the execution flowchart of the detection program. If there is, execute step S132 and then step S133. If there is no loop, execute step S133 directly.

[0048] S132. Traverse all edges e in the post-order dominator tree edge set E2. 2 In the execution process, edge set E1 is deleted along with edge e. 2 Identical edges form control dependency edges in the annotation call graph;

[0049] S133. Since all nodes in the ring depend on the head node, reconstruct the edges in the ring.

[0050] Reconstructing a ring structure refers to determining the dependencies between nodes in the ring structure, such as the edges (1,2), (2,4), (4,5), (5,6), and (6,2) in the edge set E2 of the program flowchart. Here, (6,2) indicates that node 6 points to node 2, so node 6 depends on node 2.

[0051] To obtain the commented call graph of a program, dynamic analysis of the program is required first. Because high-level programming languages ​​encapsulate data to a high degree, they struggle to accurately represent memory access behavior. Therefore, the source code needs to be converted into assembly language, which is closer to the underlying hardware. Based on this consideration, this invention uses LLVM intermediate representation (IR) as an intermediate language to represent the program's memory access behavior. During the compilation of IR, LLVM divides the entire program into several basic blocks, which can serve as nodes in the commented call graph. The calls and dependencies between basic blocks can construct directed edges in the commented call graph, and the execution information of the basic blocks themselves can serve as attributes in the commented call graph. Figure 2 Taking the shaded area marked in PageRank algorithm (a) as an example, the intermediate representation of the source code compiled using the LLVM intermediate layer can be used to obtain the program address, such as... Figure 2 As shown in (b), timestamps are added before and after the intermediate representation to obtain the execution time and number of executions for each basic block, and an execution flowchart of the program is generated, as follows. Figure 2 As shown in (c). Comment call diagram (e.g.) Figure 2The generation process (as shown in (d)) is as described in Algorithm 1. First, start and end nodes are added to the execution flowchart (line 1 of Algorithm). Then, all edges in the execution flowchart are reversed, and the Lengauer-Tarjan algorithm is used to generate the post-dominant tree (PDT) of the execution flowchart. The PDT reflects the dominance relationship between the basic blocks in the execution flowchart (lines 2-3 of Algorithm), thereby constructing the control-related edges in the annotation call graph. Specifically, for each basic block v in the program execution flowchart that is not an ancestor of basic block u in the PDT (lines 4-6 of Algorithm), the minimum common ancestor L of basic blocks u and v in the PDT is found, and the set of all nodes {p} in the path from basic block L to basic block v in the PDT is obtained (lines 7-8 of Algorithm). Next, the algorithm eliminates the cycles in the execution flowchart. If a cycle exists in the execution flowchart, the least common ancestor L of basic blocks u and v in the post-order dominance tree is basic block u. In this case, it is only necessary to remove basic block v from the point set {p} (Algorithm lines 9-11). After the cycle removal process, any point n ∈ {p} in the point set {p} has a control dependency on node L. Therefore, directed edges from node L to node n can be constructed in the annotation call graph (Algorithm lines 12-14), thus completing the construction of control dependency edges in the annotation call graph. Subsequently, based on the variable dependencies in the source code, data dependency edges are added to the annotation call graph (Algorithm line 17). Finally, the information collected during the process of forming the program's execution flowchart using LLVM is appended to the nodes and edges in the annotation call graph, completing the generation process of the program's annotation call graph.

[0052] Algorithm 1. Comment Call Graph Generation Algorithm

[0053] Input: Program execution flowchart g = {V, E'}, attribute set P

[0054] Output: The program's comment call graph G = (V, E, P)

[0055]

[0056] S2. Divide each node v in the annotation call diagram into internal computing units or on-chip processors to form multiple program partitioning schemes, and output the program partitioning scheme with the shortest execution time.

[0057] Based on the annotation call graph, this invention proposes a computational partitioning method based on minimum cut, such as... Figure 3 As shown in (b). Figure 3 (b) is a graph structure consisting of 8 nodes (6-13 in horizontal direction, totaling 8 nodes) and directed edges. Figure 2(b) The comment call diagram corresponding to the program will be used as an example to propose the in-memory computing partitioning method.

[0058] To intuitively demonstrate the principle of the proposed computational partitioning method, this invention first introduces two pseudo-nodes, CPU and PIM. Starting from these two pseudo-nodes, a series of connections are drawn to each node in the annotation call graph. Thus, the problem of partitioning the execution of basic blocks can be transformed into... Figure 3 (b) shows the graph partitioning problem of the comment call graph—that is, partitioning the comment call graph G after adding two pseudo-nodes, CPU and PIM, into two parts (S,T), such that CPU∈S and PIM∈T. Basic block b∈T indicates that basic block b is operated on in-memory computing units, and basic block b∈S indicates that basic block b is executed on the on-chip processor. Figure 3 (b) provides three different examples of computation partitioning in an in-memory computing architecture. Computation partition 2 only includes pseudo-nodes (PIM), which means that all programs are executed on the on-chip processor. Computation partition 3 includes all eight basic blocks except for pseudo-nodes (PIM), which means that all programs are executed on the in-memory computing unit.

[0059] Computational partitioning 2 and 3 typically occur only in extreme cases. In most cases, the result of computational partitioning should be that some basic blocks are executed in memory and some are executed on the on-chip processor. Figure 3 The calculation partition 1 in (b) is similar. Besides the pseudo-node PIM, calculation partition 1 includes three basic blocks: node 9, node 10, and node 11. These three basic blocks are calculated in memory, while the remaining basic blocks are executed on the on-chip processor. The corresponding calculation partition results are as follows: Figure 3 As shown in (a).

[0060] Therefore, once the partition G=(S,T) of the annotation call graph G=(V,E,P) is determined, the total execution time T of the basic block is... all It can be expressed using formula (1):

[0061] T all =T CPU +T PIM +T M (1)

[0062] Total execution time T all It consists of three parts: the total execution time T of the on-chip processor. CPU Total execution time T in memory computing units PIM The total data transfer time T between the on-chip processor and the in-memory computing unit M Among them, T CPU The total execution time of all basic blocks u∈S in the point set S on the on-chip processor can be determined by... Indicates; T PIM The total time taken to execute all basic blocks v∈T in a point set T on in-memory computation units can be determined by this. It means that S u,v BW represents the amount of data transferred between basic block u and basic block v, and BW represents the memory read / write bandwidth. This can be viewed as the total time T for data transfer between the on-chip processor and the in-memory computing unit. M In summary, the total execution time T of the program is... all It can be expressed by formula (2).

[0063]

[0064] During the partitioning of the annotation call graph, the cut line may intersect with four types of edges: data-related edges, control-related edges, edges originating from pseudo-node PIM, and edges originating from pseudo-node CPU. Assuming the existence of the edge-attribute correspondences shown in Table 1, the annotation call graph partitioning problem can be transformed into a minimum cut problem, i.e., determining the partitioning result G = (S, T) of the annotation call graph to minimize the program execution time.

[0065] Table 1 describes the attributes of the edge types in the graph.

[0066]

[0067] Solving the partitioning algorithm: The above objective problem can be equivalent to a 0-1 integer linear programming (ILP) problem. As shown in formula (2), the optimization objective is to minimize the program's execution time, which requires determining the execution location of each non-pseudo-node (basic block) in the comment call graph; let variable I v It is a binary variable representing the execution location of the basic block v: when I v When the value is 0, it indicates that the instruction corresponding to basic block v is executed in the on-chip processor; I v If the value of is 1, it means that the instruction corresponding to basic block v is executed on the in-memory computation unit. Therefore, the program partitioning problem can be transformed into: finding a set of binary variables {I}. v}(v∈V), so that the total execution time of the program in formula (2) is minimized.

[0068] Introducing variable I v After that, time T CPU T PIM and T MIt can be represented by formulas (3) to (5); in addition, in order to characterize the block that can only be executed on the on-chip processor and cannot be executed in the memory computing unit (such as the starting basic block and the ending basic block, etc.), another binary variable C is introduced for each basic block. v , used to limit I v The value of is shown in formula (6). When C v When the value of I is 1, the basic block v can be executed in the in-memory computation unit; otherwise, I v The value can only be 0, meaning it can only be executed on the on-chip processor.

[0069]

[0070]

[0071]

[0072]

[0073] Combining formulas (1) to (6), we can solve for a partitioning result {Iv} (v∈V) for each basic block in a given program, based on the I corresponding to each basic block v. v The value can ultimately determine the basic blocks that run on the in-memory computing units and processor, thus realizing the division of program execution.

[0074] When a program is converted into an annotation call graph, it has a large number of blocks and a large solution space. Solving it often requires multiple iterations to converge to the optimal solution. Therefore, this paper proposes an algorithm to accelerate the solution and convergence speed of the partitioning problem, as shown in Algorithm 2.

[0075] First, the basic block u with the highest execution frequency among all basic blocks is executed in the in-memory computation unit, i.e., its variable I. u The value of is 1, and the remaining basic blocks are executed on the on-chip processor. The partitioning scheme of the program is used as the initial solution, and the total execution time according to the partitioning scheme is calculated according to formulas (2)-(5) (algorithm lines 1-2). Then, in each iteration, the execution times exceeding the threshold T are selected. H The basic blocks are distributed to the set of basic blocks {U} to be executed by the in-memory computing unit, and a basic block is randomly selected from it to obtain its number j (algorithm lines 4-5); subsequently, in the current optimal solution {I} opt Based on this, the optimal solution {I} opt Corresponding to the optimal partitioning scheme, the variable I of the basic block j with inverted numbering is... j , if I j =0, the inverted I j =1, if I j =1, the inverted I j=0, and form a new feasible solution {I}. i (Algorithm line 6); Next, recalculate the partitioning scheme {I} according to formulas (2) to (5). i The corresponding execution time, and its comparison with the current optimal time T. opt Comparison, T opt The current optimal solution {I} opt The corresponding execution time T i The difference ΔT = T is obtained. i -T opt If ΔT is negative, then a feasible solution {I} is possible. i Execution time T i Shorter than the current optimal solution, feasible solution {I} i That is, find the current optimal solution and update the current optimal time to the execution time T. i (Algorithm lines 7-10); Once a feasible solution {I} is found... i and the current optimal solution {I} opt If the execution time is the same, compare the data transfer power consumption ΔE corresponding to the two partitioning schemes, and take the partitioning scheme with lower data transfer power consumption as the current optimal solution (Algorithm lines 11-15). If ΔT is positive, it means that the feasible solution {I} is valid. i If the execution time is longer than the current optimal solution, a feasible solution {I} is accepted with a certain probability r. i (Algorithm lines 16-21), the feasible solution {I} is about to be found. i As the current optimal solution, the probability r is calculated using the following formula: The formula for calculating probability r is an empirical formula, where k represents the current negation I. j The percentage of executions of the basic block relative to the maximum number of executions, where ΔT is the number of executions of the i-th feasible solution {I}. i The corresponding execution time T i The execution time T of the current optimal solution opt The difference. In this algorithm, a correction coefficient k is introduced for the Metropolis criterion, representing the current inversion of I. j The percentage of basic blocks executed relative to the maximum number of executions is used to assign higher update weights to basic blocks with more executions (line 18 of the algorithm), thus avoiding getting trapped in local optima. After Iter... max After several iterations, the convergent solution {I} is finally obtained. opt This corresponds to the optimal partitioning scheme for program performance.

[0076] Algorithm 2: Solution algorithm for calculating partitions

[0077] Input: Comment call graph G = (V, E, P), maximum number of iterations Iter max ,

[0078] Basic block candidate set {C v}, v∈V, candidate threshold T H

[0079] Output: Calculate the partition solution set {I} v} opt ,v∈V

[0080]

[0081] Based on offline analysis of the program, this invention proposes a computation partitioning algorithm between the on-chip processor and the in-memory computing unit. Ultimately, the computation partitioning problem of the in-memory computing system is transformed into a minimum cut problem of the annotation call graph. The computation partitioning obtained by this method can effectively improve system performance and reduce the energy consumption caused by unnecessary data movement.

[0082] The present invention has been described by way of example. Obviously, the specific implementation of the present invention is not limited to the above-described manner. Any non-substantial improvements made using the inventive concept and technical solution of the present invention, or the direct application of the inventive concept and technical solution of the present invention to other occasions without modification, are all within the protection scope of the present invention.

Claims

1. A static computation partitioning method for improving the performance of an in-memory computing system, characterized in that, The method includes the following steps: S1. Divide the program into several basic blocks and transform the program into a comment call graph. The nodes in the comment call graph correspond to the basic blocks in the program. S2. Call the annotations to the nodes in the graph. The program is divided into multiple partitioning schemes, which are then assigned to in-memory computing units or on-chip processors. The program partitioning scheme with the shortest execution time is then output. The specific method for obtaining the program partitioning scheme with the shortest execution time is as follows: The basic block with the highest execution frequency The remaining basic blocks are distributed to the in-memory computing unit for execution, and the remaining basic blocks are distributed to the on-chip processor for execution. The partitioning scheme of the program is used as the initial solution, and the total execution time of the partitioning scheme is calculated. In each iteration, the percentage of executions exceeding a threshold is selected. The basic blocks are distributed to the set of basic blocks executed by the in-memory computing units. In the current optimal solution Based on this, a random inversion is performed to form the i-th feasible solution. ; Calculate the partitioning scheme Corresponding execution time Calculate execution time Execution time compared to the current optimal solution The difference ,like If it is negative, then a feasible solution is possible. That is, to find the current optimal solution and update the current optimal time to the execution time. ,like If positive, then by probability feasible solution As the current optimal solution, update the current optimal execution time. .

2. The static computation partitioning method for improving the performance of an in-memory computing system as described in claim 1, characterized in that, The method for generating the graph by calling annotations is as follows: S11. Use the LLVM intermediate layer to abstract high-level programming languages ​​into assembly language, and then instrument the assembly language to form the program's execution flowchart. S12. Generate the post-order dominance tree of the execution flowchart based on the Lengauer-Tarjan algorithm; S13. Based on the dominance relationship between basic blocks in the post-order dominance tree, control dependency edges are formed in the annotation call graph. After adding data dependency edges, adding the attributes of edges and nodes, the annotation call graph is formed.

3. The static computation partitioning method for improving the performance of an in-memory computing system as described in claim 2, characterized in that, The process of generating control dependency edges is as follows: S131. Check if there is a loop in the execution flowchart of the detection program. If there is, execute step S132 and then step S133. If there is no loop, execute step S133 directly. S132, Traversing the Post-Order Dominator Tree and its Edge Set All edges In the edge set of the execution process Deletion and edge Identical edges form control dependency edges in the annotation call graph; S133. All nodes in the ring depend on the head node, thereby extracting control dependencies.

4. The static computation partitioning method for improving the performance of an in-memory computing system as described in claim 1, characterized in that, The specific formula for calculating the execution time of the program partitioning scheme is as follows: ； in, The total execution time on the on-chip processor, The total execution time in the in-memory computing unit. This represents the total data transfer time between the on-chip processor and the in-memory computing unit.

5. The static computation partitioning method for improving the performance of an in-memory computing system as described in claim 4, characterized in that, , , The specific calculation formula is as follows: ； ； ； ； in, Represents a point set The total execution time of all basic blocks on the on-chip processor is represented by this. Represents a point set The total time taken to execute all basic blocks on in-memory computing units. This represents the total time for data transfer between the on-chip processor and the in-memory computing unit. Representing basic blocks and basic blocks The amount of data transferred between them Indicates the read / write bandwidth of memory; To identify basic blocks A binary variable representing the execution location. Represents a binary variable; Basic blocks When the corresponding instructions are executed on the in-memory computing unit, Basic blocks When the corresponding instructions are executed on the on-chip processor, .

6. The static computation partitioning method for improving the performance of an in-memory computing system as described in claim 1, characterized in that, like A more feasible solution and the current optimal solution Data transfer power consumption corresponding to the partitioning scheme The partitioning scheme with lower data transfer power consumption is selected as the current optimal solution.

7. The static computation partitioning method for improving the performance of an in-memory computing system as described in claim 6, characterized in that, probability The specific calculation formula is as follows: ； Where k is the correction coefficient, representing the current inversion. The percentage of times the basic block is executed out of the maximum number of executions. For the i-th feasible solution Corresponding execution time Execution time compared to the current optimal solution The difference.

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