Shift register, gate driving circuit and driving method thereof

Abstract

The embodiment of the present application discloses a shift register, a gate drive circuit and a driving method thereof, wherein a first control module is configured to control a start signal and a first level signal to be transmitted to a first node according to a signal of a first clock signal terminal, a signal of a second clock signal terminal and a level of a second node; a second control module is configured to control a second level signal and a signal of a third clock signal terminal to be transmitted to a second node according to the start signal and the signal of the third clock signal terminal; and an output module is configured to control the signal of the second clock signal terminal to be transmitted to a shift register output terminal according to a level of the first node. The technical scheme of the present application can control the existence of overlap or the non-existence of overlap of effective level signals output by adjacent two levels of shift registers by controlling the existence of overlap or the non-existence of overlap of the signal of the first clock signal terminal and the signal of the second clock signal terminal, thereby increasing the flexibility of the gate drive circuit output by the shift register comprising the embodiment, and meeting the application requirements of a display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a shift register, a gate driving circuit, and a driving method thereof. Background Technology

[0002] The display panel includes a scanning circuit, which includes multiple cascaded shift registers. The output of the shift registers is connected to the scan lines, thereby outputting scan signals to the scan lines.

[0003] However, the scanning signals output by existing scanning circuits have low flexibility. Summary of the Invention

[0004] This invention provides a shift register, a gate driving circuit, and a driving method thereof to improve the flexibility of the scanning circuit output scanning signal, thereby meeting the application requirements of display panels.

[0005] In a first aspect, embodiments of the present invention provide a shift register, including: a first control module, a second control module, and an output module; wherein the output terminal of the first control module is connected to a first node, and the output terminal of the second control module is connected to a second node;

[0006] The first control module is used to control the transmission of the start signal and the first level signal to the first node based on the signal from the first clock signal terminal, the signal from the second clock signal terminal, and the level of the second node.

[0007] The second control module is used to control the transmission of the second level signal and the signal of the third clock signal to the second node based on the start signal and the signal of the third clock signal terminal.

[0008] The output module is used to control the transmission of the signal from the second clock signal terminal to the output terminal of the shift register according to the level of the first node, and to control the transmission of the first level signal to the output terminal of the shift register according to the level of the second node;

[0009] Specifically, the effective level pulse of the second clock signal terminal is delayed relative to the effective level pulse of the first clock signal terminal, and the delay time is greater than or equal to 1 / 2 of the corresponding time of the effective level pulse; the effective level pulse of the third clock signal terminal is delayed relative to the effective level pulse of the second clock signal terminal; and the effective level pulse of the start signal overlaps with at least one effective level pulse of the signal at the first clock signal terminal.

[0010] Optionally, the effective level pulse of the signal at the third clock signal terminal does not overlap with the effective level pulse of the signal at the second clock signal terminal;

[0011] The second control module is specifically used to set the level of the second node to an invalid level based on the signal of the third clock signal terminal and the start signal after the level of the first node jumps to an active level and before the active level pulse of the signal at the second clock signal terminal arrives.

[0012] Optionally, the second control module includes a first control unit and a second control unit. The first control unit is used to control the transmission of the signal from the third clock signal terminal to the second node according to the start signal, and the second control unit is used to control the transmission of the second level signal to the second node according to the signal from the third clock signal terminal.

[0013] Optionally, the first control unit includes a first transistor, the gate of the first transistor is connected to a start signal, the first terminal of the first transistor is connected to a signal from a third clock signal terminal, and the second terminal of the first transistor is electrically connected to a second node; the second control unit includes a second transistor, the gate of the second transistor is connected to a signal from a third clock signal terminal, the first terminal of the second transistor is connected to a second level signal, and the second terminal of the second transistor is electrically connected to a second node.

[0014] Optionally, the output module includes a first output unit and a second output unit. The control terminal of the first output unit is electrically connected to the first node, the first terminal of the first output unit is connected to the signal of the second clock signal terminal, and the second terminal of the first output unit is electrically connected to the output terminal of the shift register.

[0015] The control terminal of the second output unit is electrically connected to the second node, the first terminal of the second output unit is connected to the first level signal, and the second terminal of the second output unit is electrically connected to the output terminal of the shift register.

[0016] Optionally, the output module also includes a bootstrap unit, which is used to couple the level of the first node according to the voltage change of the signal at the second clock signal terminal;

[0017] Optionally, the bootstrap unit includes a third transistor and a bootstrap capacitor. The gate of the third transistor is electrically connected to the first node, the first terminal of the third transistor is connected to the signal of the second clock signal terminal, the second terminal of the third transistor is connected to the first terminal of the bootstrap capacitor, and the second terminal of the bootstrap capacitor is electrically connected to the first node.

[0018] Optionally, the first control module includes an input unit and a third control unit. The input unit is used to control the transmission of a start signal to the first node according to the signal from the first clock signal terminal connected to its own control terminal.

[0019] The third control unit is used to control the transmission of the first level signal to the first node based on the level of the second node and the signal at the second clock signal terminal;

[0020] Optionally, the input unit includes a fourth transistor, the gate of the fourth transistor is connected to the signal of the first clock signal terminal, the first terminal of the fourth transistor is connected to the start signal, and the second terminal of the fourth transistor is electrically connected to the first node.

[0021] Optionally, the third control unit includes a fifth transistor and a sixth transistor, the gate of the fifth transistor is electrically connected to the second node, the first terminal of the fifth transistor is connected to a first level signal, and the second terminal of the fifth transistor is electrically connected to the first terminal of the sixth transistor.

[0022] The gate of the sixth transistor is connected to the signal of the second clock signal terminal, and the second terminal of the sixth transistor is electrically connected to the first node;

[0023] Optionally, the first control module also includes a seventh transistor, the gate of which is connected to a second-level signal, and the second terminals of the fourth and sixth transistors are electrically connected to the first node through the seventh transistor.

[0024] Optionally, the first control module further includes a fourth control unit, which is used to control the transmission of the first level signal to the second node according to the potential of the first node and the signal of the second clock signal terminal;

[0025] Optionally, the fourth control unit includes an eighth transistor and a ninth transistor, the gate of the eighth transistor is electrically connected to the first node, the first terminal of the eighth transistor is connected to a first level signal, and the second terminal of the eighth transistor is electrically connected to the first terminal of the ninth transistor.

[0026] The gate of the ninth transistor is connected to the second clock signal terminal, and the second terminal of the ninth transistor is electrically connected to the second node.

[0027] In a second aspect, embodiments of the present invention also provide a gate driving circuit, including a multi-stage cascaded shift register as described in the first aspect;

[0028] The gate drive circuit further includes: a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line, wherein the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line are configured to transmit clock signals with sequentially delayed timings;

[0029] The first clock signal terminal of the 4n-3rd stage shift register is connected to the first clock signal line, the second clock signal terminal of the 4n-3rd stage shift register is connected to the second clock signal line, and the third clock signal terminal of the 4n-3rd stage shift register is connected to the fourth clock signal line.

[0030] The first clock signal terminal of the 4n-2 stage shift register is connected to the second clock signal line, the second clock signal terminal of the 4n-2 stage shift register is connected to the third clock signal line, and the third clock signal terminal of the 4n-2 stage shift register is connected to the first clock signal line.

[0031] The first clock signal terminal of the 4n-1 stage shift register is connected to the third clock signal line, the second clock signal terminal of the 4n-1 stage shift register is connected to the fourth clock signal line, and the third clock signal terminal of the 4n-1 stage shift register is connected to the second clock signal line.

[0032] The first clock signal terminal of the 4n-stage shift register is connected to the fourth clock signal line, the second clock signal terminal of the 4n-stage shift register is connected to the first clock signal line, and the third clock signal terminal of the 4n-stage shift register is connected to the third clock signal line.

[0033] Where n is an integer greater than or equal to 1, and 4n is less than or equal to the total number of shift registers;

[0034] The first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line are configured to transmit clock signals with a timing delay of a preset duration, wherein the preset duration is greater than or equal to 1 / 2 of the duration corresponding to the effective level pulse of the clock signal.

[0035] Thirdly, embodiments of the present invention also provide a driving method for a gate driving circuit, comprising:

[0036] A start signal is input to the first control module, and corresponding signals are input to the first clock signal terminal and the second clock signal terminal, so that the first control module controls the transmission of the start signal and the first level signal to the first node according to the signal of the first clock signal terminal, the signal of the second clock signal terminal, and the level of the second node;

[0037] A start signal is input to the second control module, and a corresponding signal is input to the third clock signal terminal, so that the second control module controls the transmission of the second level signal and the signal of the third clock signal terminal to the second node according to the start signal and the signal of the third clock signal terminal;

[0038] The output module controls the transmission of the signal at the second clock signal terminal to the output terminal of the shift register based on the level of the first node, and controls the transmission of the first level signal to the output terminal of the shift register based on the level of the second node;

[0039] Specifically, the effective level pulse of the second clock signal terminal is delayed relative to the effective level pulse of the first clock signal terminal, and the delay time is greater than or equal to 1 / 2 of the corresponding time of the effective level pulse; the effective level pulse of the third clock signal terminal is delayed relative to the effective level pulse of the second clock signal terminal; and the effective level pulse of the start signal overlaps with at least one effective level pulse of the signal at the first clock signal terminal.

[0040] Optionally, the effective level pulses of the signals at the first clock signal terminal and the second clock signal terminal overlap;

[0041] Preferably, the clock periods of the signals at the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal are equal, and within one clock cycle, the duration of the effective level pulse is greater than the row period, wherein the row period is equal to the quotient of 1 and the refresh frequency, divided by the total number of rows of pixel circuits in the display panel.

[0042] Optionally, the periods of the signals at the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal are equal to 4 times the line period. The signal at the second clock signal terminal is delayed by one line period relative to the signal at the first clock signal terminal, and the signal at the third clock signal terminal is delayed by two line periods relative to the signal at the second clock signal terminal. Within one clock cycle, the effective level pulse duration of the signals at the first clock signal terminal and the second clock signal terminal is greater than one line period and less than two line periods.

[0043] Alternatively, the effective level pulses of the signals at the first clock signal terminal and the second clock signal terminal do not overlap; the delay time of the signal at the third clock signal terminal relative to the signal at the second clock signal terminal is equal to m times the delay time of the signal at the second clock signal terminal relative to the signal at the first clock signal terminal, where m is a positive integer.

[0044] The shift register, gate driving circuit, and driving method of this embodiment of the invention introduce more clock signals. The first control module controls the transmission of a start signal and a first-level signal to the first node based on the signals from the first clock signal terminal, the second clock signal terminal, and the level of the second node. The second control module controls the transmission of a second-level signal and a third clock signal terminal to the second node based on the start signal and the signal from the third clock signal terminal. The output module controls the transmission of the signal from the second clock signal terminal to the output terminal of the shift register based on the level of the first node. Furthermore, the signal from the second clock signal terminal has a delay relative to the signal from the first clock signal terminal, and the delay time is greater than or equal to 1 / 2 of the time corresponding to the effective level pulse. The signal from the third clock signal terminal also has a delay relative to the signal from the second clock signal terminal. The timing of the effective level pulse of the start signal overlapping with at least one effective level pulse of the signal from the first clock signal terminal is controlled. The overlap of the effective level signals output by adjacent shift registers can be controlled by controlling whether the signals from the first clock signal terminal and the second clock signal terminal overlap. This increases the flexibility of the gate driving circuit output of the shift register included in this embodiment, meeting the application requirements of the display panel. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the structure of a shift register provided in an embodiment of the present invention;

[0046] Figure 2 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0047] Figure 3 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0048] Figure 4 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0049] Figure 5 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0050] Figure 6 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0051] Figure 7 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0052] Figure 8 This is a timing diagram of a shift register provided in an embodiment of the present invention;

[0053] Figure 9This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0054] Figure 10 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0055] Figure 11 This is a timing diagram of another shift register provided in an embodiment of the present invention;

[0056] Figure 12 This is a timing diagram of another shift register provided in an embodiment of the present invention;

[0057] Figure 13 This is a timing diagram of another shift register provided in an embodiment of the present invention;

[0058] Figure 14 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention;

[0059] Figure 15 This is a schematic diagram of the driving timing of a gate driving circuit provided in an embodiment of the present invention;

[0060] Figure 16 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0061] Figure 17 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0062] Figure 18 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0063] Figure 19 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0064] Figure 20 This is a flowchart of a driving method for a gate driving circuit provided in an embodiment of the present invention. Detailed Implementation

[0065] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0066] As described in the background section, the scanning signals output by existing scanning circuits have low flexibility. The inventors discovered that this problem arises because the shift registers in existing scanning circuits receive two clock signals, such as a first clock signal and a second clock signal. Both the first and second clock signals are alternating high and low levels, with one level being active and the other inactive. For example, when all transistors in the shift register are P-type transistors, the low level is active and the high level is inactive. In the prior art, to ensure the shift register functions correctly, the active level pulses of the first and second clock signals cannot overlap. Consequently, the scanning signals output by each stage of the shift register also cannot overlap, resulting in a relatively simple form of the scanning signal output by the scanning circuit. If the existing shift registers are applied to display panels where odd and even row pixel circuits connect different data lines, two sets of scanning circuits are required. This results in a large bezel area occupied by the scanning circuits, increases the number of components in the bezel area, leads to high parasitic capacitance, and increases signal delay, making it difficult to meet the application requirements of display panels.

[0067] For the reasons stated above, embodiments of the present invention provide a shift register. Figure 1 This is a schematic diagram of a shift register provided in an embodiment of the present invention, for reference. Figure 1 The shift register includes a first control module 110, a second control module 120, and an output module 130. The output of the first control module 110 is connected to a first node N1, and the output of the second control module 120 is connected to a second node N2. The first control module 110 controls the transmission of a start signal SIN and a first-level signal VGH to the first node N1 based on the signals of the first clock signal SCK1, the second clock signal SCK2, and the level of the second node N2. The second control module 120 controls the transmission of a second-level signal VGL and a third clock signal SCK3 to the second node N2 based on the start signal SIN and the signal of the third clock signal SCK3. The output module 130 controls the transmission of the second clock signal SCK2 to the shift register output OUT based on the level of the first node N1, and controls the transmission of the first-level signal VGH to the shift register output OUT based on the level of the second node N2.

[0068] Specifically, the effective level pulse of the second clock signal terminal is delayed relative to the effective level pulse of the first clock signal terminal, and the delay time is greater than or equal to 1 / 2 of the corresponding time of the effective level pulse; the effective level pulse of the third clock signal terminal is delayed relative to the effective level pulse of the second clock signal terminal; and the effective level pulse of the start signal overlaps with at least one effective level pulse of the signal at the first clock signal terminal.

[0069] The first control module 110 is used to control the transmission of the start signal SIN and the first level signal VGH to the first node N1 based on the signal of the first clock signal terminal SCK1, the signal of the second clock signal terminal SCK2, and the level of the second node N2. Specifically, when the signal of the first clock signal terminal SCK1 is a valid level signal, the first control module 110 transmits the start signal SIN to the first node N1; and during the period when the second node N2 is a valid level and the signal of the second clock signal terminal SCK2 is a valid level signal, the first control module 110 transmits the first level signal VGH to the first node N1.

[0070] The second control module 120 is used to control the transmission of the second level signal VGL and the third clock signal SCK3 to the second node N2 according to the start signal SIN and the third clock signal SCK3. Specifically, when the start signal SIN is an active level signal, the second control module 120 transmits the signal of the third clock signal SCK3 to the second node N2; when the signal of the third clock signal SCK3 is an active level signal, the second control module 120 transmits the second level signal VGL to the second node N2.

[0071] The output module 130 is used to control the transmission of the signal of the second clock signal terminal SCK2 to the output terminal OUT of the shift register according to the level of the first node N1, and to control the transmission of the first level signal VGH to the output terminal OUT of the shift register according to the level of the second node N2. Specifically, when the level of the first node N1 is active, the output module 130 transmits the signal of the second clock signal terminal SCK2 to the output terminal of the shift register; and when the level of the second node N2 is active, the output module 130 transmits the first level signal VGH to the output terminal of the shift register.

[0072] Within a single frame, the signals from the first clock signal terminal SCK1, the second clock signal terminal SCK2, and the third clock signal terminal SCK3 each include multiple high-level pulses and multiple low-level pulses, with the high-level pulses and low-level pulses alternating. Optionally, the signals from the first clock signal terminal SCK1, the second clock signal terminal SCK2, and the third clock signal terminal SCK3 have the same period, and the widths of the high-level pulses and low-level pulses in these signals are equal, meaning that the waveforms of the signals from the first clock signal terminal SCK1, the second clock signal terminal SCK2, and the third clock signal terminal SCK3 are identical. The signal from the second clock signal terminal SCK2 is delayed relative to the signal from the first clock signal terminal SCK1, and the signal from the third clock signal terminal SCK3 is delayed relative to the signal from the second clock signal terminal SCK2. Optionally, the high-level voltage amplitudes of the signals at the first clock signal terminal SCK1, the second clock signal terminal SCK2, and the third clock signal terminal SCK3 are equal, and the low-level voltage amplitudes of the signals at the first clock signal terminal SCK1, the second clock signal terminal SCK2, and the third clock signal terminal SCK3 are equal.

[0073] Within a frame, the start signal SIN consists of a high-level pulse and a low-level pulse.

[0074] The signals from the first clock signal terminal SCK1, the second clock signal terminal SCK2, the third clock signal terminal SCK3, and the start signal SIN are collectively referred to as control signals. For any control signal, the effective level is determined by the device type of the module in the shift register controlled by the control signal. Specifically, the effective level of the control signal is the signal that enables the corresponding device to conduct. For example, when the control signal controls a P-type transistor, the effective level is low; when the control signal controls an N-type transistor, the effective level is high.

[0075] Both the first level signal VGH and the second level signal VGL can be fixed signals. The levels of the first level signal VGH and the second level signal VGL are opposite. Optionally, the first level signal VGH is a high level signal and the second level signal VGL is a low level signal; or the first level signal VGH is a low level signal and the second level signal VGL is a high level signal.

[0076] Optionally, for each control signal, the voltage magnitude of the high-level signal can be equal, for example, +7V, and the voltage magnitude of the low-level signal can also be equal, for example, -7V. The voltage magnitude of the high-level signal in the first level signal VGH and the second level signal VGL can also be +7V, and the voltage magnitude of the low-level signal can also be -7V. In the embodiments of the present invention, the first level signal VGH is used as an invalid level signal, and the second level signal VGL is used as an valid level signal for illustration.

[0077] In this embodiment, the signal at the second clock signal terminal SCK2 is delayed relative to the signal at the first clock signal terminal SCK1, and the signal at the third clock signal terminal SCK3 is delayed relative to the signal at the second clock signal terminal SCK2. The effective level pulses of the second clock signal terminal SCK2 and the first clock signal terminal SCK1 may or may not overlap. The effective level pulses of the third clock signal terminal SCK3 do not overlap with the effective level pulses of the second clock signal terminal SCK2.

[0078] When the effective level pulses of the second clock signal terminal SCK2 and the first clock signal terminal SCK1 overlap, and the first clock signal terminal SCK1 is an effective level signal and the start signal SIN is an effective level signal, the first control module 110 will transmit the effective level signal of the start signal SIN to the first node N1, so that the output module 130 will output the signal of the second clock signal terminal SCK2 to the output terminal of the shift register according to the effective level of the first node N1. Since the effective level pulses of the second clock signal terminal SCK2 and the first clock signal terminal SCK1 overlap, the output module 130 will output the effective level of the second clock signal terminal SCK2 to the output terminal of the shift register. Therefore, the effective level signal in the output signal of the shift register output terminal OUT will overlap with the effective level signal in the start signal SIN. For the gate drive circuit, the start signal SIN is the output signal of the previous shift register. Therefore, the shift register in this embodiment can achieve the overlap of the effective level signals of the output of two adjacent shift registers. Optionally, if the effective level pulse of the signal at the third clock signal terminal SCK3 does not overlap with the effective level pulse of the signal at the second clock signal terminal SCK2, then when the signal at the first clock signal terminal SCK1, the start signal SIN, and the signal at the second clock signal terminal SCK2 are all effective level signals, the signal at the third clock signal terminal SCK3 is an ineffective level signal. The second control module 120 transmits the ineffective level signal of the signal at the third clock signal terminal SCK3 to the second node N2 based on the effective level signal of the start signal SIN, so that the output module 130 will not output the first level signal VGH, and the output of the effective level signal of the signal at the second clock signal terminal SCK2 will not be affected. As can be seen from the above analysis, including the gate drive circuit of the shift register in this embodiment, when the effective level pulse of the signal at the second clock signal terminal SCK2 and the effective level pulse of the signal at the first clock signal terminal SCK1 overlap, the effective level signals output by the two adjacent shift register stages can overlap. When the effective level signals output by two adjacent shift registers can overlap, the shift registers can be applied to display panels where the odd and even row pixel circuits are connected to different data lines. In this case, only one set of gate drive circuits needs to be set in the display panel, which occupies a small area of ​​the bezel, reduces signal delay, and can meet the application requirements of the display panel.

[0079] When the effective level pulses of the second clock signal terminal SCK2 and the first clock signal terminal SCK1 do not overlap, and when the first clock signal terminal SCK1 is an effective level signal and the start signal SIN is an effective level signal, the first control module 110 will transmit the effective level signal of the start signal SIN to the first node N1, so that the output module 130 will output the signal of the second clock signal terminal SCK2 to the output terminal of the shift register according to the effective level of the first node N1. Since the effective level pulses of the second clock signal terminal SCK2 and the first clock signal terminal SCK1 do not overlap, the signal of the second clock signal terminal SCK2 is an invalid level signal at this time, and the output of the shift register is an invalid level signal. When both the first clock signal SCK1 and the start signal SIN are valid, the shift register outputs an invalid signal. The valid signal of the shift register is only output when the second clock signal SCK2 transitions to a valid level. When SCK2 transitions to a valid level, the first clock signal SCK1 is invalid, and the valid pulse of the start signal SIN overlaps with one valid pulse of the first clock signal SCK1 (i.e., the valid pulse of the start signal SIN completely overlaps with one valid pulse of the first clock signal SCK1). Therefore, the start signal SIN is invalid. Thus, when the shift register outputs a valid pulse, the start signal SIN is invalid. For the gate drive circuit, the start signal SIN is the output signal of the previous shift register. Therefore, in this embodiment, the shift register ensures that the valid output signals of adjacent shift registers do not overlap.

[0080] In this embodiment, the gate driving circuit that the shift register can be used can be a scanning circuit or a light emission control circuit to increase the flexibility of the signals output by the scanning circuit and the light emission control circuit.

[0081] The shift register in this embodiment introduces more clock signals. The first control module controls the transmission of a start signal and a first-level signal to the first node based on the signals from the first clock signal terminal, the second clock signal terminal, and the level of the second node. The second control module controls the transmission of a second-level signal and a third clock signal terminal to the second node based on the start signal and the third clock signal terminal. The output module controls the transmission of the signal from the second clock signal terminal to the shift register output terminal based on the level of the first node. Furthermore, the signal from the second clock signal terminal has a delay relative to the signal from the first clock signal terminal, and the delay time is greater than or equal to 1 / 2 of the time corresponding to the effective level pulse. The signal from the third clock signal terminal also has a delay relative to the signal from the second clock signal terminal. The timing of the effective level pulse of the start signal overlapping with at least one effective level pulse of the signal from the first clock signal terminal is controlled. The overlap of the effective level signals output by adjacent shift registers can be controlled by controlling whether the signals from the first clock signal terminal and the second clock signal terminal overlap, thereby increasing the flexibility of the gate drive circuit output of the shift register in this embodiment and meeting the application requirements of the display panel.

[0082] Based on the above technical solution, optionally, the effective level pulse of the signal at the third clock signal terminal SCK3 does not overlap with the effective level pulse of the signal at the second clock signal terminal SCK2; the second control module 120 is specifically used to set the level of the second node N2 to an invalid level according to the signal at the third clock signal terminal SCK3 and the start signal SIN after the level of the first node N1 jumps to an effective level and before the effective level pulse of the signal at the second clock signal terminal SCK2 arrives.

[0083] Specifically, after the level of the first node N1 transitions to an active level, the output module 130 can transmit the signal of the second clock signal terminal SCK2 to the output terminal of the shift register based on the active level of the first node N1. When the active level pulse of the second clock signal terminal SCK2 arrives, the output module 130 will transmit the active level to the output terminal of the shift register. By configuring the active level pulse of the third clock signal terminal SCK3 to not overlap with the active level pulse of the second clock signal terminal SCK2, before the active level pulse of the second clock signal terminal SCK2 arrives, the signal of the third clock signal terminal SCK3 transitions to an inactive level signal. This allows the second control module 120 to set the level of the second node N2 to an inactive level based on the inactive level signal of the third clock signal terminal SCK3 and the active level signal of the start signal SIN before the active level pulse of the second clock signal terminal SCK2 arrives. This prevents the output module 130 from transmitting the first level signal VGH to the output terminal of the shift register, thereby ensuring the stability of the active level pulse of the second clock signal terminal SCK2 output to the output terminal of the shift register.

[0084] Figure 2 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, see reference. Figure 2 Optionally, the second control module 120 includes a first control unit 121 and a second control unit 122. The first control unit 121 is used to control the signal of the third clock signal terminal SCK3 to be transmitted to the second node N2 according to the start signal SIN. The second control unit 122 is used to control the second level signal VGL to be transmitted to the second node N2 according to the signal of the third clock signal terminal SCK3.

[0085] Specifically, when the start signal SIN is a valid level signal, the first control unit 121 is turned on and transmits the signal of the third clock signal terminal SCK3 to the second node N2; when the signal of the third clock signal terminal SCK3 is a valid level signal, the second control unit 122 is turned on and transmits the second level signal VGL to the second node N2. Because the signal of the third clock signal terminal SCK3 is delayed relative to the signal of the second clock signal terminal SCK2, the effective level pulses of the signal of the third clock signal terminal SCK3 and the signal of the second clock signal terminal SCK2 do not overlap. Therefore, when the signal of the second clock signal terminal SCK2 changes from an invalid level to an effective level, the signal of the third clock signal terminal SCK3 is still an invalid level. Before the signal of the second clock signal terminal SCK2 changes from an invalid level to an effective level, and when the signal of the third clock signal terminal SCK3 is an invalid level, by controlling the start signal SIN to an effective level, the first control unit 121 will be turned on, and the invalid signal of the third clock signal terminal SCK3 will be transmitted to the second node N2. Before the effective level pulse of the signal of the second clock signal terminal SCK2 arrives, the level of the second node N2 will be set to an invalid level according to the signal of the third clock signal terminal SCK3 and the start signal SIN.

[0086] Continue to refer to Figure 2 Optionally, the first control unit 121 includes a first transistor T1, the gate of the first transistor T1 is connected to the start signal SIN, the first terminal of the first transistor T1 is connected to the signal of the third clock signal terminal SCK3, and the second terminal of the first transistor T1 is electrically connected to the second node N2; the second control unit 122 includes a second transistor T2, the gate of the second transistor T2 is connected to the signal of the third clock signal terminal SCK3, the first terminal of the second transistor T2 is connected to the second level signal VGL, and the second terminal of the second transistor T2 is electrically connected to the second node N2.

[0087] Figure 3 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, see reference. Figure 3 Optionally, the output module 130 includes a first output unit 131 and a second output unit 132. The control terminal of the first output unit 131 is electrically connected to the first node N1, the first terminal of the first output unit 131 is connected to the signal of the second clock signal terminal SCK2, and the second terminal of the first output unit 131 is electrically connected to the output terminal of the shift register. The control terminal of the second output unit 132 is electrically connected to the second node N2, the first terminal of the second output unit 132 is connected to the first level signal VGH, and the second terminal of the second output unit 132 is electrically connected to the output terminal of the shift register.

[0088] Specifically, when the level of the first node N1 is active, the first output unit 131 is turned on, transmitting the signal from the second clock signal terminal SCK2 to the output terminal of the shift register; when the level of the second node N2 is active, the second output unit 132 is turned on, transmitting the first level signal VGH to the output terminal of the shift register. Optionally, the first output unit 131 includes a first output transistor T10 and a storage capacitor C2. The second output unit 132 includes a second output transistor T20.

[0089] Continue to refer to Figure 3 Optionally, the output module 130 further includes a bootstrap unit 133. In some optional embodiments of the present invention, the bootstrap unit 133 is used to couple the level of the first node N1 according to the voltage change of the signal of the second clock signal terminal SCK2.

[0090] Specifically, when the first node N1 is at an effective level, the first output unit 131 of the output module 130 can transmit the signal of the second clock signal terminal SCK2 to the output terminal of the shift register. However, since the effective level of the first node N1 is obtained through the effective level of the start signal SIN, when both the signals of the first node N1 and the second clock signal terminal SCK2 are at effective levels, the voltage values ​​of the first node N1 and the second clock signal terminal SCK2 are almost equal (e.g., both are -7V). This causes the first output transistor T10 of the first output unit 131 to be only in a critical conducting state, and it cannot fully transmit the effective level of the second clock signal terminal SCK2 to the output terminal of the shift register. Consequently, the signal output by the shift register output terminal OUT cannot reach the voltage amplitude corresponding to the effective level of the second clock signal terminal SCK2. In this embodiment, by setting the output module 130 to also include a coupling unit, when the voltage of the second clock signal terminal SCK2 changes, the potential of the first node N1 will also be coupled and change accordingly. Taking the first output transistor T10 as a P-type transistor with a corresponding effective level of low as an example, when the first node N1 is at an effective level, and the signal of the second clock signal terminal SCK2 changes from high to low, the level of the first node N1 is coupled down even further, allowing the first output transistor T10 to be fully turned on. This ensures that the low level of the signal of the second clock signal terminal SCK2 can be transmitted normally to the output terminal of the shift register, and the output signal of the shift register can reach the voltage amplitude corresponding to the low level of the signal of the second clock signal terminal SCK2, such as -7V.

[0091] Continue to refer to Figure 3Optionally, the bootstrap unit 133 includes a third transistor T3 and a bootstrap capacitor C1. The gate of the third transistor T3 is electrically connected to the first node N1. The first terminal of the third transistor T3 is connected to the signal of the second clock signal terminal SCK2. The second terminal of the third transistor T3 is connected to the first terminal of the bootstrap capacitor C1. The second terminal of the bootstrap capacitor C1 is electrically connected to the first node N1.

[0092] Specifically, when the first node N1 is at an active level, the third transistor T3 is turned on. If the signal of the second clock signal terminal SCK2 changes during this stage, the first terminal of the bootstrap capacitor C1 will change its potential, and the second terminal of the bootstrap capacitor C1 will also change its potential accordingly, thus achieving the effect of coupling the potential of the first node N1 through the voltage change of the signal of the second clock signal terminal SCK2.

[0093] Figure 4 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, see reference. Figure 4 In another optional embodiment of the present invention, the bootstrap unit 133 may include only the bootstrap capacitor C1. The first end of the bootstrap capacitor C1 is connected to the output of the shift register, and the second end of the bootstrap capacitor C1 is connected to the first node N1, thereby coupling the potential of the first node N1 through the potential change of the output of the shift register.

[0094] It should be noted that because the output of the shift register needs to be connected to the scan lines in the display panel, and the scan lines connect to multiple pixel circuits, the load on the shift register output OUT is relatively large. Consequently, the magnitude of the potential change at the output of the shift register is smaller than the potential change of the signal at the second clock signal SCK2. Furthermore, the potential change at the output of the shift register can only be reflected after the signal at the second clock signal SCK2 undergoes a potential jump and is output by the first control unit. Therefore, the potential change at the output of the shift register is relatively slow compared to the potential change of the signal at the second clock signal SCK2. Therefore, in this embodiment, the bootstrap unit 133 directly connects to the signal of the second clock signal terminal SCK2, and the scheme of coupling the level of the first node N1 according to the voltage change of the signal of the second clock signal terminal SCK2 can, on the one hand, make the voltage change amplitude of the first node N1 be large, and on the other hand, make the first node N1 be quickly coupled and changed according to the level jump of the signal of the second clock signal terminal SCK2. When the signal of the second clock signal terminal SCK2 jumps from an invalid level to an effective level, the output terminal of the shift register can also quickly output the voltage amplitude of the effective level signal of the second clock signal terminal SCK2, ensuring the speed and stability of the output signal.

[0095] Figure 5This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, see reference. Figure 5 In some optional embodiments of the present invention, the first control module 110 includes an input unit 111 and a third control unit 112. The input unit 111 is used to control the transmission of the start signal SIN to the first node N1 according to the signal of the first clock signal terminal SCK1 connected to its own control terminal; the third control unit 112 is used to control the transmission of the first level signal VGH to the first node N1 according to the level of the second node N2 and the signal of the second clock signal terminal SCK2.

[0096] Specifically, when the signal at the first clock signal terminal SCK1 is at an effective level, the input unit 111 is turned on and transmits the start signal SIN to the first node N1; when the level of the second node N2 is at an effective level and the signal at the second clock signal terminal SCK2 is at an effective level, the third control unit 112 transmits the first level signal VGH to the first node N1.

[0097] Continue to refer to Figure 5 Based on the above technical solution, optionally, the input unit 111 includes a fourth transistor T4, the gate of the fourth transistor T4 is connected to the signal of the first clock signal terminal SCK1, the first terminal of the fourth transistor T4 is connected to the start signal SIN, and the second terminal of the fourth transistor T4 is electrically connected to the first node N1.

[0098] Optionally, the third control unit 112 includes a fifth transistor T5 and a sixth transistor T6. The gate of the fifth transistor T5 is electrically connected to the second node N2, the first terminal of the fifth transistor T5 is connected to the first level signal VGH, and the second terminal of the fifth transistor T5 is electrically connected to the first terminal of the sixth transistor T6. The gate of the sixth transistor T6 is connected to the signal of the second clock signal terminal SCK2, and the second terminal of the sixth transistor T6 is electrically connected to the first node N1.

[0099] Optionally, the first control module 110 further includes a seventh transistor T7. The gate of the seventh transistor T7 is connected to the second-level signal VGL. The second terminals of the fourth transistor T4 and the sixth transistor T6 are both electrically connected to the first node N1 through the seventh transistor T7. Taking the seventh transistor T7 as a P-type transistor as an example, the setting of the seventh transistor T7 allows the first node N1 to be isolated by the seventh transistor T7 when the level is coupled to an extremely low level by the bootstrap unit of the output module 130, preventing it from being transmitted to the third node N3. This protects the fourth transistor T4 and the sixth transistor T6 from damage due to excessive voltage difference, improving the reliability of the shift register.

[0100] Figure 6 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, see reference. Figure 6Based on the above embodiments, in some optional embodiments of the present invention, the first control module 110 further includes a fourth control unit 113, which is used to control the transmission of the first level signal VGH to the second node N2 according to the potential of the first node N1 and the signal of the second clock signal terminal SCK2.

[0101] Specifically, the fourth control unit 113 is used to control the transmission of the first level signal VGH to the second node N2 according to the potential of the first node N1 and the signal of the second clock signal terminal SCK2. When the potential of the first node N1 is a valid potential signal and the signal of the second clock signal terminal SCK2 is a valid potential signal, the fourth control unit 113 transmits the first level signal VGH to the second node N2.

[0102] Optionally, the fourth control unit 113 includes an eighth transistor T8 and a ninth transistor T9. The gate of the eighth transistor T8 is electrically connected to the first node N1, the first terminal of the eighth transistor T8 is connected to the first level signal VGH, and the second terminal of the eighth transistor T8 is electrically connected to the first terminal of the ninth transistor T9. The gate of the ninth transistor T9 is connected to the second clock signal terminal SCK2, and the second terminal of the ninth transistor T9 is electrically connected to the second node N2.

[0103] Specifically, when the potential of the first node N1 is active, the eighth transistor T8 is turned on, and when the second clock signal is active, the ninth transistor T9 is turned on. When both the eighth transistor T8 and the ninth transistor T9 are turned on, the first level signal VGH reaches the second node N2 through the eighth transistor T8 and the ninth transistor T9.

[0104] Figure 7 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, see reference. Figure 7 The shift register includes a first control module 110, a second control module 120, and an output module 130. The second control module 120 includes a first control unit 121 and a second control unit 122. The first control unit 121 includes a first transistor T1, and the second control unit 122 includes a second transistor T2. The output module 130 includes a first output unit 131 and a second output unit 132. The first output unit 131 includes a first output transistor T10, and the second output unit 132 includes a second output transistor T20. The output module 130 also includes a bootstrap unit 133, which includes a third transistor T3 and a bootstrap capacitor C1. The first control module 110 includes an input unit 111 and a third control unit 112. The input unit 111 includes a fourth transistor T4, and the third control unit 112 includes a fifth transistor T5 and a sixth transistor T6. The first control module 110 also includes a seventh transistor T7. Figure 8This is a timing diagram of a shift register provided in an embodiment of the present invention. This timing diagram is applicable to... Figure 7 The shift register shown is used to... Figure 7 Taking the shift registers shown as all being P-type transistors as an example, the first level signal VGH is a high-level signal, and the second level signal VGL is a low-level signal. (Reference) Figure 7 and Figure 8 The operation of this shift register includes the following stages.

[0105] In the first stage t1, the start signal SIN is always high. When the signal at the first clock signal terminal SCK1 is low, the fourth transistor T4 turns on, transmitting the high-level start signal SIN to the third node N3, and then through the seventh transistor T7 to the first node N1, causing the first output transistor T10 to turn off. When the signal at the third clock signal terminal SCK3 is low, the second transistor T2 turns on, transmitting the second-level signal VGL (low-level signal) to the second node N2. The second output transistor T20 responds to the low-level signal at the second node N2 and turns on, transmitting the first-level signal VGH (high-level signal) to the output of the shift register. That is, in the first stage t1, the output signal of the shift register is a high-level signal.

[0106] In the second stage t2, the start signal SIN and the first clock signal SCK1 are both low, the second clock signal SCK2 is both high, and the third clock signal SCK3 is low. The first transistor T1 turns on in response to the low-level start signal SIN, transmitting the low-level signal from the third clock signal SCK3 to the second node N2. The second transistor T2 turns on in response to the low-level signal from the third clock signal SCK3, transmitting the second-level signal VGL (low-level signal) to the second node N2. Simultaneously, the fourth transistor T4 turns on in response to the low-level signal from the first clock signal SCK1, transmitting the low-level start signal SIN to the first node N1. The first output transistor T10 turns on in response to the low level of the first node N1, transmitting the high-level signal from the second clock signal SCK2 to the output of the shift register. The second output transistor T20 turns on in response to the low level of the second node N2, transmitting the first-level signal VGH (high-level signal) to the output of the shift register. Therefore, in the second stage t2, the output signal of the shift register is a high-level signal.

[0107] In the third stage t3, the start signal SIN and the first clock signal SCK1 remain at a low level, the second clock signal SCK2 remains at a high level, and the third clock signal SCK3 transitions from low to high. The first transistor T1 turns on in response to the low-level start signal SIN, transmitting the high-level third clock signal SCK3 to the second node N2, causing the second output transistor T20 to turn off, and simultaneously turning off the fifth transistor T5. Meanwhile, the fourth transistor T4 continues to turn on in response to the low-level first clock signal SCK1, transmitting the low-level start signal SIN to the first node N1, causing the first output transistor T10 to turn on, transmitting the high-level second clock signal SCK2 to the output of the shift register. Therefore, in the third stage t3, the output signal of the shift register is a high-level signal. Analysis of the working process of the third stage t3 shows that when the effective level pulses of the signals at the first clock signal terminal SCK1 and the second clock signal terminal SCK2 overlap, and the effective level pulse of the signal at the third clock signal terminal SCK3 does not overlap with the signal at the second clock signal terminal SCK2, the second node N2 can be pulled to a high level by the transition of the signal at the third clock signal terminal SCK3. This eliminates the need for the intermediate state process in the prior art where the signal at the first clock signal terminal SCK1 transitions from a low level to a high level and the signal at the second clock signal terminal SCK2 remains at a high level to pull the second node N2 to an invalid level.

[0108] In the fourth stage t4, the signal at the second clock signal terminal SCK2 transitions from high to low. While the start signal SIN and the first clock signal terminal SCK1 remain low, the fourth transistor T4 continues to conduct in response to the low-level first clock signal terminal SCK1, transmitting the low-level start signal SIN to the first node N1. This causes the first output transistor T10 to conduct, transmitting the low-level second clock signal terminal SCK2 to the output of the shift register. That is, the output signal at the shift register output terminal OUT transitions to a low level as the second clock signal terminal SCK2 transitions down. Since the third transistor T3 is also turned on according to the potential of the first node N1, the drop-down of the second clock signal terminal SCK2 causes the potential of the first node N1 to be coupled by the coupling capacitor to a level lower than the low level of the start signal SIN. The low level of the second clock signal terminal SCK2 has the same amplitude as the low level of the start signal SIN, allowing the first output transistor T10 to be fully turned on, ensuring that the output signal of the shift register output terminal OUT reaches the voltage amplitude corresponding to the low level of the second clock signal terminal SCK2. Furthermore, during the period when the start signal SIN and the first clock signal terminal SCK1 remain low, the signal of the third clock signal terminal SCK3 is high. Therefore, the first transistor T1 remains on, transmitting the high-level signal of the third clock signal terminal SCK3 to the second node N2, while the second output transistor T20 is turned off. During the period when the start signal SIN and the first clock signal terminal SCK1 transition to a high level, the first transistor T1 is turned off according to the high-level start signal SIN; when the start signal SIN and the first clock signal terminal SCK1 are at a high level, the signal at the third clock signal terminal SCK3 is also at a high level, therefore the second transistor T2 is turned off. The output module 130 includes a storage capacitor for maintaining the potential of the second node N2, such that when the second control unit does not transmit potential to the second node N2 (i.e., when both the first transistor T1 and the second transistor T2 are turned off), the storage capacitor can maintain the potential of the second node N2, thus the second node N2 remains at a high level. Therefore, both the fifth transistor T5 and the second output transistor T20 are turned off in response to the high level of the second node N2. The fourth transistor T4 turns off in response to the high-level signal at the first clock signal terminal SCK1. Since the signal at the second clock signal terminal SCK2 remains low, the potential of the first node N1 is kept low by the bootstrap capacitor C1, and the first output transistor T10 remains on, continuously transmitting the low-level signal at the second clock signal terminal SCK2 to the output of the shift register. Furthermore, the shift register maintains the same level as the signal at the second clock signal terminal SCK2 until the signal at the third clock signal terminal SCK3 transitions to low. Therefore, in the fourth stage t4, the output signal of the shift register is a low-level signal.

[0109] Between stage t4 (fourth stage) and stage t5 (fifth stage), there is a transition stage t0. This is due to the clock cycle setting, because the low level of the third clock signal terminal SCK3 does not immediately arrive after stage t3. During transition stage t0, the signal of the second clock signal terminal SCK2 jumps upward relative to stage t0, i.e., the signal of the second clock signal terminal SCK2 jumps to a high level. Other control signals (including the signals of the first clock signal terminal SCK1, the third clock signal terminal SCK3, and the start signal SIN) remain unchanged relative to stage t4. Therefore, the second node N2 remains at the high level of stage t4, and the second output transistor T20 remains off. Because the signal of the second clock signal terminal SCK2 jumps upward relative to stage t0, the level of the first node N1 is upward coupled. However, the amplitude of the coupling of the first node N1 is limited, so the first output transistor T10 can still be turned on, outputting the high-level signal of the second clock signal terminal SCK2 to the shift register output terminal OUT.

[0110] In the fifth stage t5, the signal at the third clock signal terminal SCK3 drops to a low level. The second transistor T2 responds to the low-level signal at the third clock signal terminal SCK3 and turns on, transmitting the second-level signal VGL (low-level signal) to the second node N2 of the shift register. This causes the fifth transistor T5 and the second output transistor T20 to turn on, and the second output transistor T20 transmits the first-level signal VGH (high-level signal) to the output of the shift register. During this stage, both the first clock signal terminal SCK1 and the second clock signal terminal SCK2 are high. Therefore, the fourth transistor T4 and the sixth transistor T6 are turned off, the first node N1 remains low, and the first output transistor T10 turns on, transmitting the high-level signal at the second clock signal terminal SCK2 to the output of the shift register. Therefore, in the fifth stage t5, the output signal of the shift register is a high-level signal.

[0111] In stage t6, the signal at the first clock signal terminal SCK1 drops to a low level, and the start signal SIN becomes high. The fourth transistor T4 responds to the low-level signal at the first clock signal terminal SCK1 and turns on, transmitting the high-level start signal SIN to the first node N1, causing the third transistor T3 and the first output transistor T10 to turn off. The second node N2 remains low, the second output transistor T20 turns on, and the shift register output maintains the first-level signal VGH (high-level signal). Therefore, in stage t6, the output signal of the shift register is a high-level signal.

[0112] It should be noted that, Figure 8The timing sequence is such that the effective level pulses of the first clock signal terminal SCK1 and the effective level pulses of the second clock signal terminal SCK2 overlap. Figure 8 As shown in the timing diagram, the signals at the first clock signal terminal SCK1 and the second clock signal terminal SCK2 overlap, causing the output signal of the shift register to overlap with the start signal SIN. In the gate drive circuit, the start signal SIN is the output signal of the upper-level shift register. In other words, in this embodiment, by setting the signals at the first clock signal terminal SCK1 and the second clock signal terminal SCK2 to overlap, the effective level pulses of the output signals of adjacent shift registers can be made to overlap.

[0113] Figure 9 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. (Reference) Figure 9 and Figure 7 ,and Figure 7 The similarity is that Figure 9 The shift register shown includes a first control module 110, a second control module 120, and an output module 130. The second control module 120 includes a first control unit 121 and a second control unit 122. The first control unit 121 includes a first transistor T1, and the second control unit 122 includes a second transistor T2. The output module 130 includes a first output unit 131 and a second output unit 132. The first output unit 131 includes a first output transistor T10, and the second output unit 132 includes a second output transistor T20. The output module 130 also includes a bootstrap unit 133, which includes a third transistor T3 and a bootstrap capacitor C1. The first control module 110 includes an input unit 111 and a third control unit 112. The input unit 111 includes a fourth transistor T4, and the third control unit 112 includes a fifth transistor T5 and a sixth transistor T6. The first control module 110 also includes a seventh transistor T7. Figure 7 The difference is, Figure 9 The first control module 110 in the shift register shown also includes a fourth control unit 113, which includes an eighth transistor T8 and a ninth transistor T9.

[0114] Among them, for Figure 9 The shift register shown is Figure 7 The parts of the shift register structure shown are identical, and their operation at each stage is the same as... Figure 7 The operation of the shift registers shown is the same, and will not be repeated here. The following only applies to... Figure 9 The shift register shown is Figure 7The operation of different parts of the shift register structure shown will be explained, that is, the operation of the eighth transistor T8 and the ninth transistor T9 included in the fourth control unit 113 at each stage will be explained. (Still using...) Figure 9 Taking a scenario where all transistors are P-type transistors as an example, refer to... Figure 8 and Figure 9 The shift register's operation process includes the first stage t1, the second stage t2, the third stage t3, the fourth stage t4, the transition stage t0, the fifth stage t5, and the sixth stage t6.

[0115] In the first stage t1, the potentials of the third node N3 and the first node N1 are high, so the eighth transistor T8 is turned off, and the first level signal VGH cannot be transmitted to the second node N2 through the eighth transistor T8 and the ninth transistor T9.

[0116] In the second stage t2, the potentials of the third node N3 and the first node N1 are low, so the eighth transistor T8 is turned on; the signal at the second clock signal terminal SCK2 is high, the ninth transistor T9 is turned off, and the first level signal VGH cannot be transmitted to the second node N2 through the eighth transistor T8 and the ninth transistor T9.

[0117] In the third stage t3, the potentials of the third node N3 and the first node N1 are low, so the eighth transistor T8 is turned on; the signal at the second clock signal terminal SCK2 is high, the ninth transistor T9 is turned off, and the first level signal VGH cannot be transmitted to the second node N2 through the eighth transistor T8 and the ninth transistor T9.

[0118] In the fourth stage t4, the potentials of the third node N3 and the first node N1 are low, so the eighth transistor T8 is turned on; the second clock signal terminal SCK2 is low, the ninth transistor T9 is turned on, and the first level signal VGH is transmitted to the second node N2 through the eighth transistor T8 and the ninth transistor T9. Thus, when the potential of the first node N1 is low, the fourth control unit 113 (the eighth transistor T8 and the ninth transistor T9) can set the second node N2 to a high level, realizing mutual control of the potential signals of the first node N1 and the second node N2, and maintaining the potential stability of the internal nodes.

[0119] During the transition phase t0, the potentials of the third node N3 and the first node N1 are low, so the eighth transistor T8 is turned on; the signal at the second clock signal terminal SCK2 is high, the ninth transistor T9 is turned off, and the first level signal VGH cannot be transmitted to the second node N2 through the eighth transistor T8 and the ninth transistor T9.

[0120] In the fifth stage t5, the potentials of the third node N3 and the first node N1 are low, so the eighth transistor T8 is turned on; the signal at the second clock signal terminal SCK2 is high, the ninth transistor T9 is turned off, and the first level signal VGH cannot be transmitted to the second node N2 through the eighth transistor T8 and the ninth transistor T9.

[0121] In the sixth stage t6, the potentials of the third node N3 and the first node N1 are high, so the eighth transistor T8 is turned off, and the first level signal VGH cannot be transmitted to the second node N2 through the eighth transistor T8 and the ninth transistor T9.

[0122] Optionally, when the effective level pulses of the first clock signal terminal SCK1 and the second clock signal terminal SCK2 overlap, the clock periods of the first clock signal terminal SCK1, the second clock signal terminal SCK2, and the third clock signal terminal SCK3 are equal, and within one clock period, the time of the effective level pulse is greater than the line period, wherein the line period is equal to the quotient of 1 and the refresh frequency, divided by the total number of rows of pixel circuits in the display panel.

[0123] Specifically, the formula for calculating the row period is as follows:

[0124] Where h represents the line period, f represents the refresh rate, and w represents the total number of rows of pixel circuits in the display panel. The total number of rows of pixel circuits in the display panel is equal to the sum of the actual number of pixel circuit rows and the number of blank rows, where blank rows do not actually exist in the display panel. Figure 10 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, for reference. Figure 10 In this display panel, a column of pixel circuits connects to two data lines (first data line D1 and second data line D2, respectively). For example, odd-numbered row pixel circuits 10 are connected to the first data line D1, and even-numbered row pixel circuits 10 are connected to the second data line D2. Each row of pixel circuits 1 is connected to the output of a shift register 100 via a scan line. The following will... Figure 10 The display panel structure shown is referred to as a Dual Data panel. When the effective level pulses of the signals at the first clock signal terminal SCK1 and the second clock signal terminal SCK2 overlap, the effective level pulse duration of each clock signal (including the signals at the first clock signal terminal SCK1, the second clock signal terminal SCK2, and the third clock signal terminal SCK3) is greater than the row period within one clock cycle. This allows the first row pixel circuit to write data while the second row pixel circuit is writing data, thereby increasing the data writing time of each row pixel circuit and meeting the application requirements of the display panel, such as the Dual Data panel.

[0125] Optionally, the periods of the signals at the first clock signal terminal SCK1, the second clock signal terminal SCK2, and the third clock signal terminal SCK3 are equal to 4 times the line period. The signal at the second clock signal terminal SCK2 is delayed by one line period relative to the signal at the first clock signal terminal SCK1, and the signal at the third clock signal terminal SCK3 is delayed by two line periods relative to the signal at the second clock signal terminal SCK2. Within one clock cycle, the effective level pulse duration of the signals at the first clock signal terminal SCK1 and the second clock signal terminal SCK2 is greater than one line period and less than two line periods.

[0126] Within one clock cycle, the duration of the effective level pulses of each clock signal (including the signal from the first clock signal terminal SCK1, the signal from the second clock signal terminal SCK2, and the signal from the third clock signal terminal SCK3) is greater than the row period. Furthermore, the signal from the second clock signal terminal SCK2 is delayed by one row period relative to the signal from the first clock signal terminal SCK1. This allows the effective level pulses of the signal from the second clock signal terminal SCK2 to overlap with the effective level pulses of the signal from the first clock signal terminal SCK1, thereby achieving the overlap of effective level pulses output by adjacent shift registers in the gate drive circuit.

[0127] If the effective level pulse duration of the first clock signal terminal SCK1 and the second clock signal terminal SCK2 is greater than one row period and less than two row periods, then when the shift register is applied to the scanning circuit and the Dual Data panel, the effective level pulse duration in the scanning signal output by the scanning circuit is greater than one row period, which allows the data writing time of each row pixel circuit to be longer than that of the existing display panel, which is less than one row period. The effective level pulse duration in the scanning signal output by the scanning circuit is less than two row periods, which allows time to be reserved for the switching of control signals such as clock signals, ensuring the normal output of the scanning signal.

[0128] Figure 11 This is another timing diagram of a shift register provided in an embodiment of the present invention, which is applicable to... Figure 7 The shift register shown is still based on Figure 7 Taking the shift registers shown as all being P-type transistors as an example, the first level signal VGH is a high-level signal, and the second level signal VGL is a low-level signal. (Reference) Figure 7 and Figure 11 The operation of this shift register includes the following stages.

[0129] In the first stage t1, the start signal SIN is always high. When the signal at the third clock signal terminal SCK3 is low, the second transistor T2 turns on, transmitting the second level signal VGL (low level signal) to the second node N2. The second output transistor T20 turns on in response to the low level signal at the second node N2, transmitting the first level signal VGH (high level signal) to the output of the shift register. That is, in the first stage t1, the signal output by the shift register is a high level signal.

[0130] In the second stage t2, the start signal SIN and the first clock signal SCK1 are both low, the second clock signal SCK2 is high, and the third clock signal SCK3 is high. The first transistor T1 turns on in response to the low-level start signal SIN, transmitting the high-level signal from the third clock signal SCK3 to the second node N2. The second transistor T2 turns off in response to the high-level signal from the third clock signal SCK3. Simultaneously, the fourth transistor T4 turns on in response to the low-level signal from the first clock signal SCK1, transmitting the low-level start signal SIN to the first node N1. The first output transistor T10 turns on in response to the low level of the first node N1, transmitting the high-level signal from the second clock signal SCK2 to the output of the shift register. Therefore, in the second stage t2, the output signal of the shift register is high.

[0131] In the third stage t3, the start signal SIN and the first clock signal SCK1 transition from low to high, the second clock signal SCK2 transitions from high to low, and the third clock signal SCK3 remains high. The first transistor T1 turns off according to the high-level start signal SIN; the second transistor T2 turns off according to the high-level third clock signal SCK3. The output module 130 includes a storage capacitor C2 for maintaining the potential of the second node N2, such that when the second control unit does not transmit potential to the second node N2 (i.e., when both the first transistor T1 and the second transistor T2 are off), the storage capacitor can maintain the potential of the second node N2, thus keeping the second node N2 at a high level. Therefore, both the fifth transistor T5 and the second output transistor T20 turn off in response to the high level of the second node N2. The fourth transistor T4 turns off in response to the high-level signal at the first clock signal terminal SCK1. Since the signal at the second clock signal terminal SCK2 remains low, the potential of the first node N1 is kept low by the bootstrap capacitor C1, and the first output transistor T10 remains on, transmitting the low-level signal at the second clock signal terminal SCK2 to the output of the shift register. Furthermore, before the signal at the third clock signal terminal SCK3 transitions to low, the shift register maintains the same level as the signal at the second clock signal terminal SCK2. Therefore, in the third stage t3, the output signal of the shift register is a low-level signal.

[0132] In the fourth stage t4, the signal at the third clock signal terminal SCK3 drops to a low level. The second transistor T2 responds to the low-level signal at the third clock signal terminal SCK3 and turns on, transmitting the second-level signal VGL (low-level signal) to the second node N2 of the shift register. This causes the fifth transistor T5 and the second output transistor T20 to turn on, and the second output transistor T20 transmits the first-level signal VGH (high-level signal) to the output of the shift register. During this stage, both the first clock signal terminal SCK1 and the second clock signal terminal SCK2 are high. Therefore, the fourth transistor T4 is turned off, the sixth transistor T6 is also turned off, the first node N1 remains low, and the first output transistor T10 turns on, transmitting the high-level signal at the second clock signal terminal SCK2 to the output of the shift register. Therefore, in the fourth stage t4, the output signal of the shift register is a high-level signal.

[0133] In the fifth stage t5, the signal at the first clock signal terminal SCK1 jumps to a low level, the start signal SIN is high, and the signal at the third clock signal terminal SCK3 jumps to a high level. The second transistor T2 turns off based on the high-level signal at the third clock signal terminal SCK3, and the first transistor T1 turns off based on the high-level start signal SIN. Therefore, the second node N2 remains at a low level as in the previous stage, and the second output transistor T20 turns on. The fourth transistor T4 turns on in response to the low-level signal at the first clock signal terminal SCK1, transmitting the high-level start signal SIN to the first node N1, causing the third transistor T3 and the first output transistor T10 to turn off. The second node N2 remains at a low level, the second output transistor T20 turns on, and the output of the shift register maintains the first-level signal VGH (high-level signal). Therefore, in the fifth stage t5, the output signal of the shift register is a high-level signal.

[0134] It should be noted that, Figure 11 The working timing shown indicates that the effective level pulses of the signal at the first clock signal terminal SCK1 and the effective level pulses of the signal at the second clock signal terminal SCK2 do not overlap. Figure 11 As shown in the timing diagram, since the signals at the first clock signal terminal SCK1 and the second clock signal terminal SCK2 do not overlap, the output signal of the shift register does not overlap with the start signal SIN. In the gate drive circuit, the start signal SIN is the output signal of the upper-level shift register. That is, in this embodiment, by setting the signals at the first clock signal terminal SCK1 and the second clock signal terminal SCK2 to not overlap, the effective level pulses of the output signals of adjacent shift registers can be made to not overlap.

[0135] It should also be noted that, for Figure 11 The driving timing shown has transition phases between the second stage t2 and the third stage t3, and between the third node t3 and the fourth stage t4. The working principle of these transition phases is similar to... Figure 8 The working principle of the shown timing sequence is similar and will not be repeated here.

[0136] Figure 11 The working timing shown also applies to Figure 9 The shift register shown is an example. Specifically, for... Figure 9 The shift register shown is Figure 7 The parts of the shift register structure shown are identical, and their operation at each stage is the same as... Figure 7 The operation of the shift registers shown is the same, and will not be repeated here. The following only applies to... Figure 9 The shift register shown is Figure 7The operation of different parts of the shift register structure shown will be explained, that is, the operation of the eighth transistor T8 and the ninth transistor T9 included in the fourth control unit 113 at each stage will be explained. (Still using...) Figure 9 Taking a scenario where all transistors are P-type transistors as an example, refer to... Figure 9 and Figure 11 The shift register's operation process includes the first stage t1, the second stage t2, the third stage t3, the fourth stage t4, and the fifth stage t5.

[0137] In the first stage t1, the potentials of the third node N3 and the first node N1 are high, so the eighth transistor T8 is turned off, and the first level signal VGH cannot be transmitted to the second node N2 through the eighth transistor T8 and the ninth transistor T9.

[0138] In the second stage t2, the potentials of the third node N3 and the first node N1 are low, so the eighth transistor T8 is turned on; the signal at the second clock signal terminal SCK2 is high, the ninth transistor T9 is turned off, and the first level signal VGH cannot be transmitted to the second node N2 through the eighth transistor T8 and the ninth transistor T9.

[0139] In the third stage t3, the potentials of the third node N3 and the first node N1 are low, so the eighth transistor T8 is turned on; the signal of the second clock signal terminal SCK2 is low, the ninth transistor T9 is turned on, and the first level signal VGH is transmitted to the second node N2 through the eighth transistor T8 and the ninth transistor T9. Thus, when the potential of the first node N1 is low, the second node N2 can be set to a high level through the fourth control unit 113 (the eighth transistor T8 and the ninth transistor T9), realizing mutual control of the potential signals of the first node N1 and the second node N2, and maintaining the potential stability of the internal nodes.

[0140] In the fourth stage t4, the potentials of the third node N3 and the first node N1 are low, so the eighth transistor T8 is turned on; the signal at the second clock signal terminal SCK2 is high, the ninth transistor T9 is turned off, and the first level signal VGH cannot be transmitted to the second node N2 through the eighth transistor T8 and the ninth transistor T9.

[0141] In the fifth stage t5, the potentials of the third node N3 and the first node N1 are high, so the eighth transistor T8 is turned off, and the first level signal VGH cannot be transmitted to the second node N2 through the eighth transistor T8 and the ninth transistor T9.

[0142] Optionally, the effective level pulses of the signals at the first clock signal terminal SCK1 and the second clock signal terminal SCK2 do not overlap, and the delay time of the signal at the third clock signal terminal SCK3 relative to the signal at the second clock signal terminal SCK2 is equal to m times the delay time of the signal at the second clock signal terminal SCK2 relative to the signal at the first clock signal terminal SCK1, where m is a positive integer.

[0143] When m equals 1, the delay time of the signal at the third clock signal terminal SCK3 relative to the signal at the second clock signal terminal SCK2 is equal to the delay time of the signal at the second clock signal terminal SCK2 relative to the signal at the first clock signal terminal SCK1. In some optional embodiments, the clock periods of the signals at the first clock signal terminal SCK1, the second clock signal terminal SCK2, and the third clock signal terminal SCK3 are 3 times the line period. The delay time of the signal at the third clock signal terminal SCK3 relative to the signal at the second clock signal terminal SCK2 is equal to 1 time the line period, and the delay time of the signal at the second clock signal terminal SCK2 relative to the signal at the first clock signal terminal SCK1 is also equal to 1 time the line period. Within one clock period, the duration of the effective level pulse of the clock signal is less than 1 time the line period. In some optional embodiments, the clock periods of the signals at the first clock signal terminal SCK1, the second clock signal terminal SCK2, and the third clock signal terminal SCK3 are 4 times the line period. The delay time of the signal at the third clock signal terminal SCK3 relative to the signal at the second clock signal terminal SCK2 is equal to 2 times the line period, and the delay time of the signal at the second clock signal terminal SCK2 relative to the signal at the first clock signal terminal SCK1 is equal to 1 time the line period. Within one clock period, the duration of the effective level pulse of the clock signal is less than 1 time the line period. In other optional embodiments of the present invention, the clock periods of the signals at the first clock signal terminal SCK1, the second clock signal terminal SCK2, and the third clock signal terminal SCK3 may also be set to n times the line period (n is an integer greater than or equal to 4). This embodiment does not impose a specific limitation here. Figure 11 The working timing shown corresponds to the case where the clock period of the signals at the first clock signal terminal SCK1, the second clock signal terminal SCK2, and the third clock signal terminal SCK3 is 4 times the row period, and the delay time of the signal at the third clock signal terminal SCK3 relative to the signal at the second clock signal terminal SCK2 is equal to 2 times the row period.

[0144] Through the Figure 8 and Figure 11As can be seen from the analysis of the working timing of the shift register shown, the shift register in this embodiment can control whether the effective level pulses of the output signals of the two adjacent shift registers of the gate shift register overlap by controlling whether the effective level pulses of the signals of the first clock signal terminal SCK1 and the second clock signal terminal SCK2 overlap, thereby improving the flexibility of the gate drive signal output by the gate drive circuit.

[0145] It should also be noted that, Figure 8 and Figure 11 The working timing diagram shows the intermediate clock signal SCK0. The delay time of the intermediate clock signal SCK0 relative to the signal of the second clock signal terminal SCK2 is equal to the delay time of the signal of the third clock signal terminal SCK3 relative to the signal of the intermediate clock signal SCK0. Figure 12 This is a timing diagram of another shift register provided in an embodiment of the present invention. Figure 13 This is another timing diagram of a shift register provided in an embodiment of the present invention. Both are applicable to driving the shift registers of any of the above embodiments of the present invention. See also Figure 12 and Figure 13 When the low-level time interval of the start signal SIN covers two consecutive low-level time intervals of the first clock signal terminal SCK1, the third clock signal terminal SCK3, or the second clock signal terminal SCK2, the signal output by the scan signal output terminal OUT includes two low levels.

[0146] As can be seen from the above analysis, the number of pulses in the signal output by the shift register output terminal OUT is determined by the number of continuous pulses in the first clock signal terminal SCK1, the second clock signal terminal SCK2, or the third clock signal terminal SCK3 covered by the pulse width of the start signal SIN. By adjusting the pulse width of the start signal SIN, the number of pulses in the scan signal output by the shift register can be adjusted, so that the shift register provided in this embodiment can provide scan signals with multiple pulse counts, further improving the flexibility of the shift register application.

[0147] This invention also provides a gate driving circuit. Figure 14 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention, for reference. Figure 14 The gate drive circuit includes multiple cascaded shift registers, which can be shift register 50 in any of the above embodiments of the present invention.

[0148] refer to Figure 14The gate drive circuit also includes a start signal line 50 (the start signal line 50 is used to transmit the start signal SIN to the first-stage shift register, and the start signal of other-stage shift registers is the output signal of the previous-stage shift register) and multiple clock signal lines. The multiple clock signal lines include a first clock signal line 710, a second clock signal line 720, a third clock signal line 730 and a fourth clock signal line 740. The first clock signal line 710, the second clock signal line 720, the third clock signal line 730 and the fourth clock signal line 740 are configured to transmit clock signals with sequentially delayed timings.

[0149] Figure 15 This is a schematic diagram of the driving timing of a gate driving circuit provided in an embodiment of the present invention. (Combined with...) Figure 14 and Figure 15 The first clock signal line 710 is used to transmit the first clock signal CLK1, the second clock signal line 720 is used to transmit the second clock signal CLK2, the third clock signal line 730 is used to transmit the third clock signal CLK3, and the fourth clock signal line 740 is used to transmit the fourth clock signal CLK4. The pulse timing of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 is delayed sequentially.

[0150] Furthermore, the first clock signal terminal SCK1 of the 4n-3rd stage shift register 50 is connected to the first clock signal line 710, the second clock signal terminal SCK2 of the 4n-3rd stage shift register 50 is connected to the second clock signal line 720, and the third clock signal terminal SCK3 of the 4n-3rd stage shift register 50 is connected to the fourth clock signal line 740.

[0151] The first clock signal terminal SCK1 of the 4n-2 stage shift register 50 is connected to the second clock signal line 720, the second clock signal terminal SCK2 of the 4n-2 stage shift register 50 is connected to the third clock signal line 730, and the third clock signal terminal SCK3 of the 4n-2 stage shift register 50 is connected to the first clock signal line 710.

[0152] The first clock signal terminal SCK1 of the 4n-1 stage shift register 50 is connected to the third clock signal line 730, the second clock signal terminal SCK2 of the 4n-1 stage shift register 50 is connected to the fourth clock signal line 740, and the third clock signal terminal SCK3 of the 4n-1 stage shift register 50 is connected to the second clock signal line 720.

[0153] The first clock signal terminal SCK1 of the 4n-stage shift register 50 is connected to the fourth clock signal line 740, the second clock signal terminal SCK2 of the 4n-stage shift register 50 is connected to the first clock signal line 710, and the third clock signal terminal SCK3 of the 4n-stage shift register 50 is connected to the third clock signal line 730.

[0154] Where n is an integer greater than or equal to 1, and 4n is less than or equal to the total number of shift registers 50.

[0155] Figure 14 The image only shows the first to fourth level shift registers 50 in the display panel, satisfying the case where n=1. In practical applications, the display panel may include multiple levels of shift registers 50, with each four levels of shift registers 50 forming a cycle. This ensures that the timing of the turn-on levels of the first clock signal terminal SCK1, the third clock signal terminal SCK3, and the second clock signal terminal SCK2 of each level of shift register 50 is sequentially delayed. Furthermore, in adjacent levels of shift register 50, the arrival time of the turn-on level of the first clock signal terminal SCK1 of the next level of shift register 50 is later than the arrival time of the turn-on level of the first clock signal terminal SCK1 of the previous level of shift register 50, the arrival time of the turn-on level of the second clock signal terminal SCK2 of the next level of shift register 50 is later than the arrival time of the turn-on level of the second clock signal terminal SCK2 of the previous level of shift register 50, and the arrival time of the turn-on level of the third clock signal terminal SCK3 of the next level of shift register 50 is later than the arrival time of the turn-on level of the third clock signal terminal SCK3 of the previous level of shift register 50. Figure 15 The diagram schematically illustrates the waveforms of the scan signals S1 to S12 output by the shift registers 50 of the first to twelfth stages in the display panel. It can be seen that, in this embodiment of the invention, multiple cascaded shift registers 50 realize the output of scan signals with sequentially shifted timing.

[0156] Combination Figure 14 and Figure 15 Furthermore, the first clock signal line 710, the second clock signal line 720, the third clock signal line 730 and the fourth clock signal line 740 are configured to transmit clock signals whose timing is sequentially delayed by a preset unit duration, wherein the preset duration is greater than or equal to 1 / 2 of the duration corresponding to the effective level pulse of the clock signal.

[0157] For example, taking a preset duration equal to the row period h as an example, the periods of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 are all 4h. The pulse timing of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 is delayed by h in sequence. The duration of the effective level pulse of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 is W, and 0 < W < 2h. Preferably, h < W < 2h is set. This can meet the clock signal requirements of the first clock signal terminal SCK1, the second clock signal terminal SCK2, and the third clock signal terminal SCK3 of each scanning circuit 50.

[0158] The technical solution of this invention enables the scanning circuit 50 in the display panel to provide diverse scanning signals by adjusting the duration of the effective level pulse of the start signal SIN provided by the start signal line 60 to the first-stage scanning circuit 50, as well as the timing of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3 and the fourth clock signal CLK4.

[0159] Figure 16 This is a driving timing diagram for another display panel provided in an embodiment of the present invention; Figure 17 This is a driving timing diagram for another display panel provided in an embodiment of the present invention; Figure 18 This is a driving timing diagram for another display panel provided in an embodiment of the present invention.

[0160] in, Figure 15 and Figure 16 Each example illustrates the time interval of the effective level pulse of the start signal SIN of the first-stage shift register 50, covering the time interval of one effective level pulse from the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4. Combined with... Figure 14 and Figure 15 When the pulse timings of the first clock signal CLK1 and the second clock signal CLK2 overlap, the pulse timings of the second clock signal CLK2 and the third clock signal CLK3 overlap, and the pulse timings of the third clock signal CLK3 and the fourth clock signal CLK4 overlap, the pulse timings of the scan signals output by the two adjacent shift registers 50 overlap. Combined with... Figure 14 and Figure 16 When the pulse timings of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 do not overlap, the pulse timings of the scan signals output by the two adjacent shift registers 50 do not overlap.

[0161] Figure 17 and Figure 18 The diagram illustrates the case where the effective level pulse interval of the start signal SIN of the first-stage shift register 50 covers the time interval of two adjacent effective level pulses in the first clock signal CLK1, ensuring that the scan signal output by each stage shift register 50 includes two effective level pulses. When the effective level pulse interval of the start signal SIN of the first-stage shift register 50 covers the time interval of m consecutive effective level pulses in the first clock signal CLK1, the scan signal output by each stage shift register 50 includes p effective level pulses. Preferably, 1 ≤ p ≤ 4.

[0162] Combination Figure 14 and Figure 17 When the pulse timings of the first clock signal CLK1 and the second clock signal CLK2 overlap, the pulse timings of the second clock signal CLK2 and the third clock signal CLK3 overlap, and the pulse timings of the third clock signal CLK3 and the fourth clock signal CLK4 overlap, the pulse timings of the scan signals output by the two adjacent shift registers 50 overlap. Combined with... Figure 14 and Figure 18 When the pulse timings of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 do not overlap, the pulse timings of the scan signals output by the two adjacent shift registers 50 do not overlap.

[0163] However, it should be noted that when the effective level pulses of the first and second clock signals input to each shift register do not overlap, three clock signal lines can also be set. Figure 19 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention, for reference. Figure 19When the effective level pulses of the first clock signal terminal SCK1 and the second clock signal terminal SCK2 input to each shift register do not overlap, the gate drive circuit may include a start signal line 50, a first clock signal line 710, a second clock signal line 720, and a third clock signal line 730. Starting with the first-stage shift register, every three cascaded shift registers form a register group. Within each register group, the first clock signal SCK1 of the first-stage shift register is provided by the first clock signal line 710, the second clock signal SCK2 is provided by the second clock signal line 720, and the third clock signal SCK3 is provided by the third clock signal line 730. Similarly, for the second-stage shift register, the first clock signal SCK1 is provided by the second clock signal line 720, the second clock signal SCK2 is provided by the third clock signal line 730, and the third clock signal SCK3 is provided by the first clock signal line 710. Likewise, for the third-stage shift register, the first clock signal SCK1 is provided by the third clock signal line 730, the second clock signal SCK2 is provided by the first clock signal line 710, and the third clock signal SCK3 is provided by the second clock signal line 720.

[0164] This invention also provides a driving method for a gate driving circuit, which is used to drive the gate driving circuit of the above embodiments of this invention. Figure 20 This is a flowchart of a driving method for a gate driving circuit provided in an embodiment of the present invention, see reference. Figure 20 The driving method of the gate driving circuit includes:

[0165] Step 210: Input a start signal to the first control module, and input corresponding signals to the first clock signal terminal and the second clock signal terminal, so that the first control module controls the transmission of the start signal and the first level signal to the first node according to the signal of the first clock signal terminal, the signal of the second clock signal terminal, and the level of the second node;

[0166] Step 220: Input a start signal to the second control module and input a corresponding signal to the third clock signal terminal, so that the second control module controls the transmission of the second level signal and the signal of the third clock signal terminal to the second node according to the start signal and the signal of the third clock signal terminal;

[0167] Step 230: The output module controls the transmission of the signal from the second clock signal terminal to the shift register output terminal according to the level of the first node, and controls the transmission of the first level signal to the shift register output terminal according to the level of the second node.

[0168] Specifically, the effective level pulse of the second clock signal terminal is delayed relative to the effective level pulse of the first clock signal terminal, and the delay time is greater than or equal to 1 / 2 of the corresponding time of the effective level pulse; the effective level pulse of the third clock signal terminal is delayed relative to the effective level pulse of the second clock signal terminal; and the effective level pulse of the start signal overlaps with at least one effective level pulse of the signal at the first clock signal terminal.

[0169] Optionally, the periods of the first clock signal, the second clock signal, and the third clock signal are equal to 4 times the line period, the second clock signal is delayed by one line period relative to the first clock signal, and the third clock signal is delayed by two line periods relative to the second clock signal; within one clock period, the effective level pulse duration of the first clock signal and the second clock signal is greater than one line period and less than two line periods.

[0170] Optionally, the effective level pulses of the first clock signal and the second clock signal do not overlap; the delay time of the third clock signal relative to the second clock signal is equal to m times the delay time of the second clock signal relative to the first clock signal, where m is a positive integer.

[0171] The present invention also provides a driving method for a gate driving circuit, which is used to drive the gate driving circuit of the above embodiments of the present invention and has the beneficial effects of the gate driving circuit of any of the above embodiments of the present invention.

[0172] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A shift register, characterized in that, include: The system comprises a first control module, a second control module, and an output module. The output of the first control module is connected to the first node, and the output of the second control module is connected to the second node. The first control module is used to control the transmission of the start signal and the first level signal to the first node based on the signal of the first clock signal terminal, the signal of the second clock signal terminal and the level of the second node; The second control module is used to control the transmission of the second level signal and the signal of the third clock signal terminal to the second node according to the start signal and the signal of the third clock signal terminal; The output module is used to control the signal of the second clock signal terminal to be transmitted to the output terminal of the shift register according to the level of the first node, and to control the first level signal to be transmitted to the output terminal of the shift register according to the level of the second node; Wherein, the effective level pulse of the second clock signal terminal is delayed relative to the effective level pulse of the first clock signal terminal, and the delay time is greater than or equal to 1 / 2 of the corresponding time of the effective level pulse; the effective level pulse of the third clock signal terminal is delayed relative to the effective level pulse of the second clock signal terminal; the effective level pulse of the start signal overlaps with at least one effective level pulse of the signal of the first clock signal terminal; the effective level pulse of the signal of the third clock signal terminal does not overlap with the effective level pulse of the signal of the second clock signal terminal; The second control module is specifically used to set the level of the second node to an invalid level according to the signal of the third clock signal terminal and the start signal after the level of the first node transitions to an active level and before the active level pulse of the signal at the second clock signal terminal arrives.

2. The shift register according to claim 1, characterized in that, The second control module includes a first control unit and a second control unit. The first control unit is used to control the transmission of the signal from the third clock signal terminal to the second node according to the start signal. The second control unit is used to control the transmission of the second level signal to the second node according to the signal from the third clock signal terminal.

3. The shift register according to claim 2, characterized in that, The first control unit includes a first transistor, the gate of which is connected to the start signal, the first terminal of which is connected to the signal of the third clock signal terminal, and the second terminal of which is electrically connected to the second node; the second control unit includes a second transistor, the gate of which is connected to the signal of the third clock signal terminal, the first terminal of which is connected to the second level signal, and the second terminal of which is electrically connected to the second node.

4. The shift register according to claim 1, characterized in that, The output module includes a first output unit and a second output unit. The control terminal of the first output unit is electrically connected to the first node. The first terminal of the first output unit is connected to the signal of the second clock signal terminal. The second terminal of the first output unit is electrically connected to the output terminal of the shift register. The control terminal of the second output unit is electrically connected to the second node, the first terminal of the second output unit is connected to the first level signal, and the second terminal of the second output unit is electrically connected to the output terminal of the shift register.

5. The shift register according to claim 4, characterized in that, The output module further includes a bootstrap unit, which is used to couple the level of the first node according to the voltage change of the signal at the second clock signal terminal.

6. The shift register according to claim 5, characterized in that, The bootstrap unit includes a third transistor and a bootstrap capacitor. The gate of the third transistor is electrically connected to the first node. The first terminal of the third transistor is connected to the signal of the second clock signal terminal. The second terminal of the third transistor is connected to the first terminal of the bootstrap capacitor. The second terminal of the bootstrap capacitor is electrically connected to the first node.

7. The shift register according to claim 1, characterized in that, The first control module includes an input unit and a third control unit. The input unit is used to control the transmission of the start signal to the first node according to the signal from the first clock signal terminal connected to its own control terminal. The third control unit is used to control the transmission of the first level signal to the first node based on the level of the second node and the signal of the second clock signal terminal.

8. The shift register according to claim 7, characterized in that, The input unit includes a fourth transistor, the gate of which is connected to the signal of the first clock signal terminal, the first terminal of which is connected to the start signal, and the second terminal of which is electrically connected to the first node.

9. The shift register according to claim 8, characterized in that, The third control unit includes a fifth transistor and a sixth transistor. The gate of the fifth transistor is electrically connected to the second node, the first terminal of the fifth transistor is connected to the first level signal, and the second terminal of the fifth transistor is electrically connected to the first terminal of the sixth transistor. The gate of the sixth transistor is connected to the signal of the second clock signal terminal, and the second terminal of the sixth transistor is electrically connected to the first node.

10. The shift register according to claim 9, characterized in that, The first control module further includes a seventh transistor, the gate of which is connected to a second-level signal, and the second terminals of the fourth transistor and the sixth transistor are both electrically connected to the first node through the seventh transistor.

11. The shift register according to claim 7, characterized in that, The first control module further includes a fourth control unit, which is used to control the transmission of the first level signal to the second node according to the potential of the first node and the signal of the second clock signal terminal.

12. The shift register according to claim 11, characterized in that, The fourth control unit includes an eighth transistor and a ninth transistor. The gate of the eighth transistor is electrically connected to the first node, the first terminal of the eighth transistor is connected to the first level signal, and the second terminal of the eighth transistor is electrically connected to the first terminal of the ninth transistor. The gate of the ninth transistor is connected to the second clock signal terminal, and the second terminal of the ninth transistor is electrically connected to the second node.

13. A gate driving circuit, characterized in that, Including the multi-stage cascaded shift registers of any one of claims 1-12; The gate driving circuit further includes: a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line, wherein the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line are configured to transmit clock signals with sequentially delayed timings; The first clock signal terminal of the shift register of stage 4n-3 is connected to the first clock signal line, the second clock signal terminal of the shift register of stage 4n-3 is connected to the second clock signal line, and the third clock signal terminal of the shift register of stage 4n-3 is connected to the fourth clock signal line. The first clock signal terminal of the shift register of stage 4n-2 is connected to the second clock signal line, the second clock signal terminal of the shift register of stage 4n-2 is connected to the third clock signal line, and the third clock signal terminal of the shift register of stage 4n-2 is connected to the first clock signal line. The first clock signal terminal of the shift register of stage 4n-1 is connected to the third clock signal line, the second clock signal terminal of the shift register of stage 4n-1 is connected to the fourth clock signal line, and the third clock signal terminal of the shift register of stage 4n-1 is connected to the second clock signal line. The first clock signal terminal of the shift register of the 4nth stage is connected to the fourth clock signal line, the second clock signal terminal of the shift register of the 4nth stage is connected to the first clock signal line, and the third clock signal terminal of the shift register of the 4nth stage is connected to the third clock signal line. Where n is an integer greater than or equal to 1, and 4n is less than or equal to the total number of the shift registers; The first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line are configured to transmit clock signals with a timing delay of a preset duration, wherein the preset duration is greater than or equal to 1 / 2 of the duration corresponding to the effective level pulse of the clock signal.

14. A driving method for a gate driving circuit, characterized in that, include: A start signal is input to the first control module, and corresponding signals are input to the first clock signal terminal and the second clock signal terminal, so that the first control module controls the transmission of the start signal and the first level signal to the first node according to the signal of the first clock signal terminal, the signal of the second clock signal terminal, and the level of the second node; The start signal is input to the second control module, and a corresponding signal is input to the third clock signal terminal, so that the second control module controls the second level signal and the signal of the third clock signal terminal to be transmitted to the second node according to the start signal and the signal of the third clock signal terminal. The output module controls the transmission of the signal at the second clock signal terminal to the output terminal of the shift register according to the level of the first node, and controls the transmission of the first level signal to the output terminal of the shift register according to the level of the second node; Wherein, the effective level pulse of the second clock signal terminal is delayed relative to the effective level pulse of the first clock signal terminal, and the delay time is greater than or equal to 1 / 2 of the corresponding time of the effective level pulse; the effective level pulse of the third clock signal terminal is delayed relative to the effective level pulse of the second clock signal terminal; the effective level pulse of the start signal overlaps with at least one effective level pulse of the signal of the first clock signal terminal; The effective level pulse of the signal at the third clock signal terminal does not overlap with the effective level pulse of the signal at the second clock signal terminal. The second control module is specifically used to set the level of the second node to an invalid level according to the signal of the third clock signal terminal and the start signal after the level of the first node transitions to an active level and before the active level pulse of the signal at the second clock signal terminal arrives.

15. The driving method for the gate driving circuit according to claim 14, characterized in that, The effective level pulses of the signals at the first clock signal terminal and the second clock signal terminal overlap.

16. The driving method for the gate driving circuit according to claim 15, characterized in that, The clock periods of the signals at the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal are equal, and within one clock cycle, the duration of the effective level pulse is greater than the line period, wherein the line period is equal to the quotient of 1 and the refresh frequency, divided by the total number of rows of pixel circuits in the display panel.

17. The driving method for the gate driving circuit according to claim 15, characterized in that, The period of the signals at the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal is equal to 4 times the line period. The signal at the second clock signal terminal is delayed by one line period relative to the signal at the first clock signal terminal, and the signal at the third clock signal terminal is delayed by two line periods relative to the signal at the second clock signal terminal. Within one clock cycle, the effective level pulse duration of the signals at the first clock signal terminal and the second clock signal terminal is greater than one line period and less than two line periods. Alternatively, the effective level pulses of the signals at the first clock signal terminal and the second clock signal terminal do not overlap; The delay time of the signal at the third clock signal terminal relative to the signal at the second clock signal terminal is equal to m times the delay time of the signal at the second clock signal terminal relative to the signal at the first clock signal terminal, where m is a positive integer.

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