A method for manufacturing a three-dimensional fan-out packaging structure and its product

Abstract

The present invention discloses a manufacturing method of a three-dimensional fan-out packaging structure and a product thereof. The manufacturing method comprises the following steps: after the flip chip is flipped and plastic-sealed, a through hole is formed by laser opening or the like, and then a conductive material is filled in the through hole, and then three-dimensional stacking is performed, and finally a ball is planted. In the manufacturing method of the three-dimensional fan-out packaging structure provided by the present invention, a laser opening process is adopted, yellow light and etching are omitted; a high-cavity PVD seed layer is not required to grow, and there is no problem of metal coverage; no electroplating process is required, and cost is saved; the punching and dispensing method can cope with high aspect ratios; there is no need to realize copper column exposure by grinding, and there is no copper pollution problem; it is applicable to both RDL first and chip first technical routes.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a manufacturing method of a three-dimensional fan-out packaging structure and a product thereof. Background Art

[0002] In the traditional three-dimensional fan-out packaging (3DFO) method, after the bottom chip is molded, in order to further realize the vertical inter-layer interconnection, it is necessary to form a metallized via in the epoxy molding compound (EMC), dry film (Dry Film) or silicon (Si) structure used in the bottom mold. According to the timing of via formation, it can be divided into two technical routes: via first (via first) and via last (via last).

[0003] In the via first route, copper pillars are first grown through yellow light and electroplating processes, and then wafer-level compression molding is performed to produce metallized through-holes.

[0004] In the via last route, wafer-level plastic encapsulation is first performed, and then holes are opened in the plastic encapsulation material. Then, depending on the material, mechanical drilling, laser drilling, photolithography, and etching are used to complete the hole opening. Subsequently, a metal seed layer is formed by high-cavity PVD. Then, the metal filling of the through hole is completed by electroplating. Finally, the copper column exposure and end surface flattening are achieved by grinding.

[0005] However, the above two routes have the following shortcomings:

[0006] 1) In the via first route, during the plastic encapsulation process, the copper pillar is at risk of being squeezed, deformed, or even collapsed;

[0007] 2) In the via last route, the metallization of the through hole needs to use high-cavity physical vapor deposition (PVD). When the through hole is deep, there may be a problem of insufficient metal coverage;

[0008] 3) The deep hole filling electroplating process takes a long time and is costly;

[0009] 4) The process of grinding to expose the copper pillar may cause copper contamination;

[0010] 5) The corresponding through-hole depth-to-width ratio is limited. Summary of the invention

[0011] In order to solve the technical problems existing in the prior art, the object of the present invention is to provide a manufacturing method and product of a three-dimensional fan-out packaging structure.

[0012] In order to achieve the above purpose and the above technical effect, the technical solution adopted by the present invention is:

[0013] The present invention discloses a method for manufacturing a three-dimensional fan-out packaging structure, comprising the following steps:

[0014] 1) Apply temporary bonding material on the carrier and prepare RDL circuits;

[0015] 2) soldering the flip chip to the RDL line in step 1);

[0016] 3) Wafer-level plastic packaging;

[0017] 4) Laser drilling to form multiple through holes to expose some pads on the RDL circuit;

[0018] 5) Plug the through hole and solidify;

[0019] 6) Make the top pad;

[0020] 7) Solder the chip on the top pad to achieve three-dimensional stacking;

[0021] 8) Secondary plastic sealing or bottom filling;

[0022] 9) Remove the carrier board and temporary bonding materials;

[0023] 10) Planting balls.

[0024] Furthermore, in step 1), the RDL circuit includes a redistribution layer, a top pad and a bottom pad, the redistribution layer is arranged in the passivation layer, the passivation layer is arranged on the temporary bonding layer formed by the temporary bonding material, the passivation layer is provided with a top pad, the temporary bonding layer is provided with a bottom pad on the side away from the carrier, and the top pad and the bottom pad are electrically connected through the redistribution layer.

[0025] Furthermore, in step 5), the conductive material filled in the through hole includes conductive glue or conductive nanomaterials, the conductive glue includes but is not limited to: conductive silver paste, conductive copper paste, solder paste, the conductive nanomaterials include but are not limited to: metal nanowires, metal nanoparticles, carbon nanotubes.

[0026] Furthermore, in step 2), the flip chip is connected to the top pad in the RDL circuit through micro bumps and tin-silver.

[0027] The present invention also discloses a three-dimensional fan-out packaging structure manufactured by the manufacturing method of the three-dimensional fan-out packaging structure as described above, comprising:

[0028] The RDL circuit includes a redistribution layer, a top pad and a bottom pad, wherein the top pad and the bottom pad are electrically connected via the redistribution layer; and a solder ball is disposed on the bottom pad;

[0029] Flip chip, connected to the top pad;

[0030] A plastic sealing layer is obtained by performing wafer-level plastic sealing with a plastic sealing material, wherein a plurality of through holes are formed on the plastic sealing layer by laser drilling, and the through holes are filled with a conductive material;

[0031] A top pad is disposed on the plastic packaging layer and is electrically connected to the top pad through a conductive material;

[0032] Chip, soldered to the top pad;

[0033] The secondary plastic encapsulation layer or the bottom filling glue layer, when the secondary plastic encapsulation layer is used, the secondary plastic encapsulation layer completely wraps the chip, and when the bottom filling glue layer is used, the bottom filling glue layer does not wrap the chip, but only wraps the connection part between the chip and the top pad.

[0034] The present invention also discloses another method for manufacturing a three-dimensional fan-out packaging structure, comprising the following steps:

[0035] 1) Forming a temporary bonding layer by coating a temporary bonding material on a carrier, and then transferring the flip chip to the temporary bonding layer;

[0036] 2) Wafer-level plastic packaging;

[0037] 3) Opening holes in the plastic packaging material (through molding via, TMV) to form multiple through holes;

[0038] 4) Plug the through hole and solidify;

[0039] 5) Make the top pad;

[0040] 6) Solder the chip on the top pad to achieve three-dimensional stacking;

[0041] 7) Secondary plastic sealing or bottom filling;

[0042] 8) Remove the carrier board and temporary bonding materials;

[0043] 9) Prepare RDL circuit;

[0044] 10) Planting balls.

[0045] Furthermore, in step 1), the flip chip is disposed on the temporary bonding layer through a passivation layer.

[0046] Furthermore, in step 4), the conductive material filled in the through hole includes conductive glue or conductive nanomaterials, the conductive glue includes but is not limited to: conductive silver paste, conductive copper paste, the conductive nanomaterials include but are not limited to: metal nanowires, metal nanoparticles, carbon nanotubes.

[0047] Furthermore, in step 9), the RDL circuit includes a redistribution layer and a bottom pad, the redistribution layer is arranged in the passivation layer, a bottom pad is arranged under the passivation layer, and the top pad and the bottom pad are electrically connected through the conductive material in the through hole and the redistribution layer.

[0048] The present invention also discloses a three-dimensional fan-out packaging structure manufactured by the manufacturing method of the three-dimensional fan-out packaging structure as described above, comprising:

[0049] The RDL circuit includes a redistribution layer and a bottom pad, wherein the redistribution layer is arranged in the passivation layer, the bottom pad is arranged below the passivation layer, and the bottom pad is arranged with a solder ball;

[0050] Flip chip, connected to the bottom pad;

[0051] The plastic sealing layer is obtained by performing wafer-level plastic sealing with a plastic sealing material, and a plurality of through holes 10 are formed on the plastic sealing layer by laser drilling, and the through holes are filled with a conductive material;

[0052] A top pad 11 is disposed on the plastic packaging layer, and the top pad is electrically connected to the bottom pad via the conductive material in the through hole and the redistribution layer;

[0053] Chip, soldered to the top pad;

[0054] The secondary plastic encapsulation layer or the bottom filling glue layer, when the secondary plastic encapsulation layer is used, the secondary plastic encapsulation layer completely wraps the chip, and when the bottom filling glue layer is used, the bottom filling glue layer does not wrap the chip, but only wraps the connection part between the chip and the top pad.

[0055] Compared with the prior art, the present invention has the following beneficial effects:

[0056] 1) Laser opening process is adopted, eliminating yellow light and etching;

[0057] 2) No high-cavity PVD seed layer is required, and there is no problem with metal coverage;

[0058] 3) No need for electroplating process, saving costs;

[0059] 4) Punching and dispensing can handle high aspect ratios;

[0060] 5) There is no need to grind to expose the copper column, and there is no copper pollution problem;

[0061] 6) Commonly used in both RDL first and chip first technology routes. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 This is a schematic diagram of the structure of step 1) of Example 1 of the present invention;

[0063] Figure 2 This is a schematic diagram of the structure of step 2) of Example 1 of the present invention;

[0064] Figure 3 This is a schematic diagram of the structure of step 3) of Example 1 of the present invention;

[0065] Figure 4 This is a schematic diagram of the structure of step 4) of Example 1 of the present invention;

[0066] Figure 5 This is a schematic diagram of the structure of step 5) of Example 1 of the present invention;

[0067] Figure 6 This is a schematic diagram of the structure of step 6) of Example 1 of the present invention;

[0068] Figure 7 This is a schematic diagram of the structure of step 7) of Example 1 of the present invention;

[0069] Figure 8 This is a schematic diagram of the structure after secondary plastic sealing in step 8) of embodiment 1 of the present invention;

[0070] Fig. 9 This is a schematic diagram of the structure after bottom filling in step 8) of Example 1 of the present invention;

[0071] Fig.10 For Example 1 of the present invention Figure 8 The structural diagram of step 9) is carried out;

[0072] Fig.11 For Example 1 of the present invention Fig. 9 The structural diagram of step 9) is carried out;

[0073] Fig.12 For Example 1 of the present invention Fig.10 A schematic diagram of the structure of step 10);

[0074] Fig.13 For Example 1 of the present invention Fig.11 A schematic diagram of the structure of step 10);

[0075] Fig.14 This is a schematic diagram of the structure of step 1) of Example 2 of the present invention;

[0076] Fig.15 This is a schematic diagram of the structure of step 2) of embodiment 2 of the present invention;

[0077] Fig.16 This is a schematic diagram of the structure of step 3) of embodiment 2 of the present invention;

[0078] Fig.17This is a schematic diagram of the structure of step 4) of embodiment 2 of the present invention;

[0079] Fig.18 This is a schematic diagram of the structure of step 5) of embodiment 2 of the present invention;

[0080] Fig.19 This is a schematic diagram of the structure of step 6) of embodiment 2 of the present invention;

[0081] Fig. 20 This is a schematic diagram of the structure after secondary plastic sealing in step 7) of embodiment 2 of the present invention;

[0082] Fig.21 This is a schematic diagram of the structure after bottom filling in step 7) of Example 2 of the present invention;

[0083] Fig. 22 For Example 2 of the present invention Fig. 20 The structural diagram of step 8) is carried out;

[0084] Fig.23 For Example 2 of the present invention Fig.21 The structural diagram of step 8) is carried out;

[0085] Fig.24 For Example 2 of the present invention Fig. 22 The structural diagram of step 9) is carried out;

[0086] Fig.25 For Example 2 of the present invention Fig.23 The structural diagram of step 9) is carried out;

[0087] Fig.26 For Example 2 of the present invention Fig.24 A schematic diagram of the structure of step 10);

[0088] Fig. 27 For Example 2 of the present invention Fig.25 The schematic diagram of the structure of step 10). DETAILED DESCRIPTION

[0089] The present invention is described in detail below so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention.

[0090] A brief summary of one or more aspects is given below to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all conceived aspects, and is neither intended to identify the key or critical elements of all aspects nor to define the scope of any or all aspects. Its only purpose is to give some concepts of one or more aspects in a simplified form as a prelude to a more detailed description that will be given later.

[0091] Example 1

[0092] A method for manufacturing a three-dimensional fan-out packaging structure comprises the following steps:

[0093] Re-routing (RDL first) route:

[0094] 1) Apply temporary bonding material on the carrier 1 and prepare RDL circuits, such as Figure 1 As shown;

[0095] Wherein, a temporary bonding layer 2 is formed by coating a temporary bonding material on the carrier 1, and a passivation layer 3 is provided on the temporary bonding layer 2;

[0096] The RDL circuit includes a redistribution layer 4, a top pad 5 and a bottom pad 6. The redistribution layer 4 is arranged in the passivation layer 3, the top pad 5 is arranged on the passivation layer 3, the bottom pad 6 is arranged on the side of the temporary bonding layer 2 away from the carrier 1, and the top pad 5 and the bottom pad 6 are electrically connected through the redistribution layer 4.

[0097] The temporary bonding layer 2 can be coated by spraying, spin coating, rolling glue, printing and other processes to complete the coating of liquid slurry, and can also be directly attached with a solid adhesive film with pyrolysis bonding ability;

[0098] 2) The flip chip 7 is flip-chip transferred and soldered to the top pad 5 of step 1) by chip to wafer bonding and reflow process, as shown in FIG. Figure 2 As shown;

[0099] Among them, the flip chip 7 is connected to the top pad 5 through micro bumps 8 and tin-silver 9;

[0100] 3) Wafer-level molding, including but not limited to using molding compound 100 (such as epoxy molding compound, etc.) or pressing dry film, such as Figure 3 As shown;

[0101] 4) Laser drilling is performed to form a plurality of through holes 10, so that the top pad 5 on the RDL circuit is partially exposed. Figure 4 As shown; more specifically, a laser is used to open multiple through holes 10 in the plastic encapsulation structure to partially expose the top pad 5 on the RDL circuit. The shape and size of the through hole 10 can be flexibly set according to the specific product needs. Its cross-sectional morphology along the thickness direction can be an oblique hole or a straight hole, and its top view morphology can be a circular hole, a square hole or other shapes of special-shaped slots. According to the light absorption characteristics of the plastic encapsulation material used, the laser wavelength used can be infrared, visible, or ultraviolet bands, but damage to the top pad 5 should be avoided. When a photosensitive dry film is used in step 3), a matching exposure and development process must be used to complete the opening;

[0102] 5) Plug the through hole 10, solidify, such as Figure 5As shown;

[0103] The conductive material 200 filled in the through hole 10 includes, but is not limited to, conductive pastes such as conductive silver paste, conductive copper paste, and solder paste, or conductive nanomaterials such as metal nanowires, metal nanoparticles, and carbon nanotubes; more specifically, the filling of the conductive material 200 includes, but is not limited to, dispensing, screen printing, and other processes. Depending on the selected conductive material 200, thermal treatment (temperature range 50-250° C.), ultraviolet exposure, ultrasound or microwave treatment, etc., can be used to complete the curing;

[0104] 6) Make the top pad 11, such as Figure 6 More specifically, in addition to using a combination of classic yellow light, PVD (physical vapor deposition), electroplating, etching and other processes, the top pad 11 can also be made by screen printing and curing in step 5) to directly form a corresponding graphical structure;

[0105] 7) The chip 12 is flip-chip transferred and soldered to the top pad 11 through chip to wafer bonding and reflow process to achieve three-dimensional stacking, such as Figure 7 As shown;

[0106] 8) Secondary plastic sealing (such as Figure 8 ), or use the bottom filling glue 300 to underfill (as shown in Fig. 9 shown);

[0107] 9) Remove the carrier board 1 and temporary bonding material, such as Fig.10 and Fig.11 As shown;

[0108] 10) Solder ball 13 or electroless tin-silver plating, reflow, such as Fig.12 and Fig.13 shown.

[0109] A three-dimensional fan-out packaging structure, comprising:

[0110] The RDL circuit includes a redistribution layer 4, a top pad 5 and a bottom pad 6, wherein the top pad 5 and the bottom pad 6 are electrically connected via the redistribution layer 4; a solder ball 13 is disposed on the bottom pad 6;

[0111] Flip chip 7, which is connected to top pad 5 via micro bumps 8 and tin-silver 9;

[0112] The plastic encapsulation layer is obtained by performing wafer-level plastic encapsulation with a plastic encapsulation material 100. A plurality of through holes 10 are formed on the plastic encapsulation layer by laser drilling. The through holes 10 are filled with a conductive material 200. The conductive material 200 includes, but is not limited to, conductive silver paste, conductive copper paste, solder paste and other conductive adhesives, or conductive nanomaterials such as metal nanowires, metal nanoparticles, and carbon nanotubes.

[0113] The top pad 11 is disposed on the plastic packaging layer and is electrically connected to the top pad 5 through the conductive material 200;

[0114] Chip 12, soldered to the top pad 11;

[0115] The secondary plastic encapsulation layer or the bottom filling glue layer, when the secondary plastic encapsulation layer is used, the secondary plastic encapsulation layer completely wraps the chip 12, and when the bottom filling glue layer is used, the bottom filling glue layer does not wrap the chip 12, and only wraps the connection part between the chip 12 and the top pad 11.

[0116] Example 2

[0117] A method for manufacturing a three-dimensional fan-out packaging structure comprises the following steps:

[0118] RDL Last or Chip First Routing:

[0119] 1) A temporary bonding layer 2 is formed by coating a temporary bonding material on a carrier 1, and a flip chip 7 is transferred to the temporary bonding layer 2 through a passivation layer 3 by a chip to wafer process, such as Fig.14 As shown;

[0120] 2) Wafer-level molding, including but not limited to the use of molding compound 100 (epoxy molding compound, etc.) or pressed dry film, such as Fig.15 As shown;

[0121] 3) The plastic encapsulation material 100 is opened with a through molding via (TMV) to form a plurality of through holes 10, such as Fig.16 As shown;

[0122] 4) Glue plugging and curing, such as Fig.17 As shown;

[0123] The conductive material 200 filled in the through hole 10 includes, but is not limited to, conductive pastes such as conductive silver paste, conductive copper paste, and solder paste, or conductive nanomaterials such as metal nanowires, metal nanoparticles, and carbon nanotubes;

[0124] 5) Make the top pad 11, such as Fig.18 As shown;

[0125] 6) The chip 12 is flip-chip transferred and soldered to the top pad 11 through chip to wafer bonding and reflow process to achieve three-dimensional stacking, such as Fig.19 As shown;

[0126] 7) Secondary plastic sealing (such as Fig. 20 ), or use underfill 300 to underfill (as shown Fig.21 shown);

[0127] 8) Remove the carrier board 1 and temporary bonding material, such as Fig. 22 and Fig.23 As shown;

[0128] 9) Prepare RDL circuits, such as Fig.24 and Fig.25 As shown; the RDL circuit in this step includes a redistribution layer 4 and a bottom pad 6, the redistribution layer 4 is arranged in the passivation layer 3, the bottom pad 6 is arranged below the passivation layer 3, and the top pad 11 and the bottom pad 6 are electrically connected through the conductive material 200 in the through hole 10 and the redistribution layer 4;

[0129] 10) Solder ball 13 or electroless tin-silver plating, reflow, such as Fig.26 and Fig. 27 shown.

[0130] A three-dimensional fan-out packaging structure, comprising:

[0131] The RDL circuit includes a redistribution layer 4 and a bottom pad 6. The redistribution layer 4 is disposed in the passivation layer 3. The bottom pad 6 is disposed below the passivation layer 3. The top pad 11 is electrically connected to the bottom pad 6 through the conductive material 200 in the through hole 10 and the redistribution layer 4. A solder ball 13 is disposed on the bottom pad 6.

[0132] A flip chip 7 connected to the bottom pad 6;

[0133] The plastic encapsulation layer is obtained by performing wafer-level plastic encapsulation with a plastic encapsulation material 100. A plurality of through holes 10 are formed on the plastic encapsulation layer by laser drilling. The through holes 10 are filled with a conductive material 200. The conductive material 200 includes, but is not limited to, conductive silver paste, conductive copper paste, solder paste and other conductive adhesives, or conductive nanomaterials such as metal nanowires, metal nanoparticles, and carbon nanotubes.

[0134] A top solder pad 11 is provided on the plastic packaging layer;

[0135] Chip 12, soldered to the top pad 11;

[0136] The secondary plastic encapsulation layer or the bottom filling glue layer, when the secondary plastic encapsulation layer is used, the secondary plastic encapsulation layer completely wraps the chip 12, and when the bottom filling glue layer is used, the bottom filling glue layer does not wrap the chip 12, and only wraps the connection part between the chip 12 and the top pad 11.

[0137] The rest is the same as in Example 1.

[0138] Parts or structures not specifically described in the present invention may adopt existing technologies or existing products and will not be described in detail here.

[0139] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for manufacturing a three-dimensional fan-out packaging structure, characterized in that: The following steps are involved: 1) Forming a temporary bonding layer by coating a temporary bonding material on a carrier, and then transferring the flip chip to the temporary bonding layer; 2) Wafer-level plastic packaging; 3) The plastic sealing material is opened to form a plurality of through holes; 4) Plug the through hole and solidify; 5) Make the top pad; 6) Solder the chip on the top pad to achieve three-dimensional stacking; 7) Secondary plastic sealing or bottom filling; 8) Remove the carrier board and temporary bonding materials; 9) Prepare RDL circuit; 10) Planting balls.

2. The method for manufacturing a three-dimensional fan-out packaging structure according to claim 1, characterized in that: In step 1), the flip chip is disposed on the temporary bonding layer through a passivation layer.

3. The method for manufacturing a three-dimensional fan-out packaging structure according to claim 1, characterized in that: In step 4), the conductive material filled in the through hole includes conductive glue or conductive nanomaterials, the conductive glue includes but is not limited to: conductive silver paste, conductive copper paste, solder paste, the conductive nanomaterials include but are not limited to: metal nanowires, metal nanoparticles, carbon nanotubes.

4. The method for manufacturing a three-dimensional fan-out packaging structure according to claim 1, characterized in that: In step 9), the RDL circuit includes a redistribution layer and a bottom pad, the redistribution layer is arranged in the passivation layer, a bottom pad is arranged under the passivation layer, and the top pad and the bottom pad are electrically connected through the conductive material in the through hole and the redistribution layer.

5. A three-dimensional fan-out packaging structure manufactured according to the manufacturing method of the three-dimensional fan-out packaging structure according to any one of claims 1 to 4, characterized in that: include: The RDL circuit includes a redistribution layer and a bottom pad, wherein the redistribution layer is arranged in the passivation layer, the bottom pad is arranged below the passivation layer, and the bottom pad is arranged with a solder ball; Flip chip, connected to the bottom pad; The plastic sealing layer is obtained by performing wafer-level plastic sealing with a plastic sealing material, and a plurality of through holes 10 are formed on the plastic sealing layer by laser drilling, and the through holes are filled with a conductive material; A top pad is disposed on the plastic packaging layer, and the top pad is electrically connected to the bottom pad via the conductive material in the through hole and the redistribution layer; Chip, soldered to the top pad; The secondary plastic encapsulation layer or the bottom filling glue layer, when the secondary plastic encapsulation layer is used, the secondary plastic encapsulation layer completely wraps the chip, and when the bottom filling glue layer is used, the bottom filling glue layer does not wrap the chip, but only wraps the connection part between the chip and the top pad.

Images