An SGT circuit integrating an SGT temperature sensor and its fabrication method

Abstract

This application relates to an SGT circuit, including an SGT power transistor and a temperature sensor disposed on the same substrate and epitaxial layer, and an isolation ring located between the two, which is formed in the epitaxial layer and opens on the upper surface of the epitaxial layer, closing and surrounding the temperature sensor; wherein the temperature sensor includes a temperature sensing diode, comprising: a substrate; an epitaxial layer formed on the substrate, having the same doping type as the substrate, and the doping concentration of the substrate being higher than that of the epitaxial layer; a first region formed in the epitaxial layer surrounded by the isolation ring, wherein the doping type of the first region is complementary to that of the epitaxial layer, and the depth of the first region extending in the epitaxial layer is less than the depth of the isolation ring extending in the epitaxial layer; wherein the first region and the epitaxial layer surrounded by the isolation ring together constitute the PN junction of the temperature sensing diode.

Description

Technical Field

[0001] This application relates to the field of power electronic components technology, and in particular to an SGT circuit integrating an SGT temperature sensor and its fabrication method. Background Technology

[0002] With the development of consumer electronics, industrial electronics, automobiles, and other fields, people have increasingly higher requirements for the performance of electronic devices. Power MOSFETs, due to their advantages such as low power consumption, light weight, and ease of control, are widely used in electronic terminals in industrial, automotive, and communication fields.

[0003] MOSFETs can be classified into shielded gate trench MOSFETs (SGTMOSFETs), planar MOSFETs, and trench MOSFETs according to different manufacturing processes. Among them, SGTMOSFETs are a new type of power semiconductor device characterized by low on-state resistance and fast switching speed. As a core component in power electronics products, SGT MOSFETs are increasingly being used in applications ranging from traditional products such as white goods, industrial frequency converters, and welding machines to high-end products such as new energy vehicles.

[0004] In automotive applications, SGT MOSFETs require real-time and accurate temperature monitoring. Traditional methods involve using a temperature sensor chip discretely integrated into the circuit, or attaching a temperature sensor patch to the surface of the SGT MOSFET chip via thermal conduction. However, these solutions suffer from low accuracy and slow detection speed. Summary of the Invention

[0005] To address the technical problems existing in the prior art, this application proposes an SGT circuit, including an SGT power transistor and a temperature sensor disposed on the same substrate and epitaxial layer, and an isolation ring located between the two, which is formed in the epitaxial layer and opens on the upper surface of the epitaxial layer, closing and surrounding the temperature sensor; wherein the temperature sensor includes a temperature sensing diode, comprising: a substrate; an epitaxial layer formed on the substrate, having the same doping type as the substrate, and the doping concentration of the substrate being higher than that of the epitaxial layer; a first region formed in the epitaxial layer surrounded by the isolation ring, wherein the doping type of the first region is complementary to that of the epitaxial layer, and the depth of the first region extending in the epitaxial layer is less than the depth of the isolation ring extending in the epitaxial layer; a dielectric layer formed above the epitaxial layer; a metal layer formed above the dielectric layer; and a plurality of contact holes respectively configured to electrically connect the first region to a first portion of the metal layer and to a second portion of the epitaxial layer, wherein the first portion and the second portion of the metal layer are electrically isolated from each other; wherein the first region and the epitaxial layer together constitute the PN junction of the temperature sensing diode.

[0006] Specifically, in the SGT circuit, the epitaxial layer surrounded by the isolation ring includes a second region with the same doping type as the epitaxial layer and a higher doping concentration.

[0007] In particular, in the SGT circuit, the first region extends to a greater depth in the epitaxial layer than the second region extends to a greater depth in the epitaxial layer.

[0008] Specifically, in the SGT circuit, a contact electrode is formed in the contact hole, and a third region for improving contact resistance is provided at the bottom of the contact electrode. The doping type of the third region is the same as that of the first region, but the doping concentration is higher than that of the first region.

[0009] Specifically, in the SGT circuit, the isolation ring includes a trench opening on the upper surface of the epitaxial layer, a dielectric layer located on the inner surface of the trench, and an isolation electrode surrounded by the dielectric layer in the trench, the isolation electrode being electrically connected to a first portion or a second portion of the metal layer.

[0010] Specifically, the SGT circuit wherein the number of isolation rings is more than one.

[0011] An electronic device comprising an SGT circuit as described in any of the above descriptions.

[0012] This application also provides a method for fabricating an SGT temperature sensor, comprising: forming a closed trench in an epitaxial layer on a substrate, the trench opening onto the upper surface of the epitaxial layer, wherein the doping type of the epitaxial layer is the same as that of the substrate, and the doping concentration of the substrate is higher than that of the epitaxial layer; doping the epitaxial layer surrounded by an isolation ring to form a first region, wherein the doping type of the first region is complementary to that of the epitaxial layer, and the depth of the first region extending in the epitaxial layer is less than the depth of the isolation ring extending in the epitaxial layer; forming a dielectric layer on the upper surface of the epitaxial layer; etching the dielectric layer and the epitaxial layer to form a first contact hole opening onto the upper surface of the dielectric layer and contacting the first region, and forming a second contact hole opening onto the upper surface of the dielectric layer and contacting the epitaxial layer surrounded by the isolation ring; forming metal contact electrodes in the first and second contact holes; forming a first metal layer on the surface of the dielectric layer and patterning it to form a first portion and a second portion electrically isolated from each other, wherein the first portion is electrically connected to the metal contact electrode in the first contact hole, and the second portion is electrically connected to the metal contact electrode in the second contact hole.

[0013] Specifically, the method further includes forming a second region around the epitaxial layer of the isolation ring, wherein the doping type of the second region is the same as that of the epitaxial layer and the doping concentration is higher than that of the epitaxial layer; wherein, when forming the second contact hole, the dielectric layer, the second region, and the epitaxial layer are etched sequentially to form a second contact hole that contacts both the second region and the epitaxial layer.

[0014] Specifically, the preparation method further includes forming a third region at the bottom of the first contact hole and the second contact hole, wherein the doping type of the third region is the same as that of the first region, but the doping concentration is higher than that of the first region.

[0015] Specifically, the preparation method further includes forming a dielectric layer on the inner wall of the groove of the isolation ring, and etching the dielectric layer to form an isolation electrode therein. Attached Figure Description

[0016] The preferred embodiments of this application will now be described in further detail with reference to the accompanying drawings, wherein:

[0017] Figure 1 This is a schematic diagram showing the relationship between the forward conduction voltage and temperature of a diode.

[0018] Figure 2 This is a partial side cross-sectional view of an SGT circuit integrating an SGT temperature sensor according to an embodiment of this application.

[0019] Figure 3 A flowchart illustrating a method for fabricating an SGT temperature sensor according to an embodiment of this application; and

[0020] Figures 4a to 4l This is a schematic diagram of the process flow for fabricating an SGT temperature sensor according to an embodiment of this application;

[0021] Figure 5 This is a schematic diagram of an SGT temperature sensor structure according to an embodiment of this application;

[0022] Figures 6a to 6b This is a schematic diagram showing the placement of the SGT temperature sensor in an SGT circuit according to an embodiment of this application. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] In the following detailed description, reference can be made to the accompanying drawings, which form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to implement the technical solutions of the present application. It should be understood that other embodiments may also be utilized, or structural, logical, or electrical changes may be made to the embodiments of the present application.

[0025] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. The lines connecting the units in the accompanying drawings are merely for illustrative purposes, indicating that at least the units at both ends of the line are communicating with each other, and are not intended to prevent unconnected units from communicating. Furthermore, the number of lines between two units is intended to indicate at least the number of signals involved in communication between the two units or at least the number of output terminals, and is not intended to limit communication between the two units to only the signals shown in the figures.

[0026] A transistor can refer to any type of transistor, such as a field-effect transistor (FET) or a bipolar junction transistor (BJT). When a transistor is a field-effect transistor, depending on the channel material, it can be hydrogenated amorphous silicon, metal oxide, low-temperature polycrystalline silicon, organic transistors, etc. Based on whether the charge carriers are electrons or holes, they can be divided into N-type transistors and P-type transistors. The gate of a field-effect transistor is its control electrode; the first electrode can be the drain or source, and the corresponding second electrode can be the source or drain. The gate or control electrode can be the control electrode. When a transistor is a bipolar junction transistor (BJT), the base is its control electrode; the first electrode can be the collector or emitter, and the corresponding second electrode can be the emitter or collector. The base or control electrode can be the control electrode. Transistors can be manufactured using amorphous silicon, polycrystalline silicon, oxide semiconductor, organic semiconductor, NMOS / PMOS, or CMOS processes.

[0027] This application proposes an SGT circuit with an integrated SGT temperature sensor and its fabrication method. Under the premise of making full use of the existing SGT MOSFET fabrication process and flow, the SGT temperature sensor is formed on the same substrate and epitaxial layer, realizing the monitoring of the temperature change of the SGT power transistor by the SGT temperature sensor, which has better sensitivity, improves the effectiveness of temperature detection, and enables the external IC circuit to accurately control the operating state of the power device.

[0028] Figure 1 The graph shows the relationship between the forward voltage and temperature of a diode. As shown, when the diode is forward-biased, the forward voltage exhibits a linear relationship with temperature, gradually decreasing as the temperature increases. For every 1°C increase in temperature, the forward voltage across the diode decreases by 2mV.

[0029] Based on the aforementioned temperature characteristics of diodes, in scenarios where temperature detection is required, temperature sensors, such as diodes, can be fabricated on the same substrate and epitaxial layer as SGTMOSFETs to detect temperature.

[0030] Figure 2 This is a partial side cross-sectional view of an SGT circuit integrating an SGT temperature sensor according to an embodiment of this application.

[0031] According to one embodiment, the SGT circuit includes an SGT power transistor 21 and a temperature sensor 22 disposed on the same substrate 23 and epitaxial layer 24, and an isolation ring 25 located between them.

[0032] According to one embodiment, the SGT temperature sensor 22 can be a diode. Since the forward conduction voltage of the diode PN junction is sensitive to temperature, and the SGT MOSFET and the SGT temperature sensor are fabricated on the same substrate and epitaxial layer, when the temperature of the SGT MOSFET changes, the forward conduction voltage of the diode in the SGT temperature sensor will change accordingly.

[0033] The following description, based on the fabrication process and flow of N-type power SGT MOSFET devices, details the structure and fabrication method of the SGT temperature sensor proposed in this application. However, it should not be assumed that the temperature sensor proposed in this application is limited to this type of N-type SGT MOSFET fabrication process and flow. Temperature sensors fabricated based on the fabrication process and flow of P-type SGT MOSFETs also fall within the protection scope of this application.

[0034] Figure 3 The diagram shows a flowchart of a method for preparing an SGT temperature sensor according to an embodiment of this application. Figures 4a to 4l The diagram shown is a schematic flow chart of the fabrication process of an SGT temperature sensor according to an embodiment of this application. Figure 5 This is a schematic diagram of the structure of an SGT temperature sensor according to an embodiment of this application.

[0035] According to one embodiment of this application, the N-type region serving as the cathode in the PN junction of the SGT temperature sensor 100 includes a partial epitaxial layer 103. The epitaxial layer 103 is a lightly doped N-type epitaxial layer located on a heavily doped N-type substrate 102.

[0036] In step 301, a closed trench is formed in the epitaxial layer 103 located on the substrate 102.

[0037] like Figure 4a and Figure 4b As shown, an isolation ring 106 is formed in the epitaxial layer 103.

[0038] According to one embodiment, the isolation ring 106 includes a closed-loop trench located in the epitaxial layer 103 and opening onto the upper surface of the epitaxial layer 103. According to one embodiment, the trench can be formed by etching the epitaxial layer 103.

[0039] According to one embodiment, a dielectric layer 1061, such as an oxide or nitride, is formed on the inner surface of the trench in the isolation ring 106. According to one embodiment, the dielectric layer 1061 is etched to form trenches within the dielectric layer, and a polysilicon isolation electrode 1062 is formed therein.

[0040] According to one embodiment of this application, the groove depth of the isolation ring 106 can range from 1 μm to 10 μm, and the width can range from 0.5 μm to 5 μm. Specifically, the groove depth of the isolation ring 106 can be 3 μm, and the width is 1 μm. According to another embodiment, the top-view closed shape of the isolation ring 106 can also be determined by design, and can be any shape such as a rectangle, square, circle, or ellipse.

[0041] According to one embodiment, the isolation electrode 1062 can be coupled to a suitable potential (e.g., the source or drain potential of the SGT MOSFET) to form electrical insulation between the temperature sensor 100 and the SGT MOSFET, so that the electrical performance between the SGT temperature sensor 100 and the SGT MOSFET does not affect each other.

[0042] According to one embodiment of this application, the SGT circuit may include multiple equally spaced and equally wide isolation rings 106 to achieve better electrical isolation.

[0043] In step 302, the epitaxial layer 103 surrounding the isolation ring 106 is doped to form a P-type region 105.

[0044] like Figure 4c and Figure 4d A P-type region 105 is formed in the epitaxial layer 103 surrounded by the isolation ring 106, serving as the anode of the diode in the temperature sensor. For example, the P-type region 105 is formed by doping a portion of the epitaxial layer 103.

[0045] According to one embodiment of this application, such as Figure 4c As shown, the P-type region 105 also surrounds the N-type region 104. The N-type region 104 is part of the N-type epitaxial layer 103.

[0046] According to one embodiment, the area where the P-type region 105 contacts the N-type region 104 forms the PN junction of the SGT temperature sensor 100, for example, on the lower surface and side surface of the P-type region 105 in contact with the N-type region 104. The contact area of ​​the PN junction of the temperature sensor 100 is related to the contact area between the P-type region 105 and the N-type epitaxial layer 103. According to one embodiment of this application, the depth to which the P-type region 105 extends in the epitaxial layer 103 can range from 0.5 μm to 5 μm. In particular, the depth of the P-type region 105 is 1 μm. According to different embodiments, the P-type region 105 may also have other depth values. However, the depth to which the P-type region 105 extends in the epitaxial layer 103 is less than the depth to which the isolation ring 106 extends in the epitaxial layer, so that the isolation ring 106 can electrically isolate the P-type region 105 it surrounds from the area outside the isolation ring. According to one embodiment of this application, the depth of the P-type region 105 can also conform to the parameters of the SGT MOSFET process fabricated on the same substrate.

[0047] According to different embodiments, the P-type region 105 and the N-type region 104 can be arranged in different positions within the closed area surrounded by the isolation ring 106 with different relative positions.

[0048] According to another embodiment of this application, such as Figure 4c As shown, in the top view, the N-type region 104 can be surrounded by the P-type region 105. Figure 4e As shown, in the top view, the P-type region 105 can be surrounded by the N-type region 104. According to yet another embodiment of this application, as... Figure 4f As shown, in the top view, P-type area 105 and N-type area 104 can also be located in parallel within the isolation ring, without surrounding each other.

[0049] Optionally, in step 303, an N+ region 107 is formed in the epitaxial layer 103 surrounded by the isolation ring 106.

[0050] like Figure 4g and Figure 4h As shown, taking the case where the P-type region 105 surrounds the N-type region 104 as an example, alternatively, an N+ region 107 can be formed within the N-type region 104. The doping type of the N+ region 107 is the same as that of the N-type region 104, but the doping concentration is higher than that of the N-type region 104.

[0051] According to one embodiment of this application, the depth of the N+ region 107 extending in the epitaxial layer 103 can range from 0.1 μm to 0.4 μm. Specifically, the depth of the N+ region 107 extending in the epitaxial layer 103 is 0.2 μm. According to one embodiment, the depth of the N+ region 107 extending in the epitaxial layer 103 does not exceed the depth of the P-type region 105. According to one embodiment of this application, the N+ region 107 can be formed simultaneously with the fabrication of the SGT MOSFET source region.

[0052] In step 304, a dielectric layer 108 is formed on the upper surface of the epitaxial layer 103.

[0053] like Figure 4i and Figure 4j As shown, a dielectric layer 108 is formed above the epitaxial layer 103. According to one embodiment, the dielectric layer 108 may be an insulating oxide or a nitride.

[0054] In step 305, the dielectric layer 108 and the epitaxial layer 103 are etched to form contact holes 1051, 1071 and 1063.

[0055] In some embodiments, a contact hole 1051 is formed that contacts the P-type region 105, a contact hole 1071 that contacts the epitaxial layer 103, and a contact hole 1063 that contacts the isolation electrode 1062. The contact holes 1051, 1071, and 1063 open into the dielectric layer 108.

[0056] In some embodiments, the dielectric layer 108, the N+ region 107, and the epitaxial layer 103 are etched sequentially to form a contact hole 1071 that contacts both the N+ region 107 and the epitaxial layer 103.

[0057] Optionally, in step 306, as Figure 4k and Figure 4l As shown, according to one embodiment of this application, a P+ layer 1052 may be provided at the bottom of contact hole 1051, a P+ layer 1072 may be provided at the bottom of contact hole 1071, and a P+ layer 1064 may be provided at the bottom of contact hole 1063. According to one embodiment, the doping concentration of P+ layers 1052, 1072, and 1064 is higher than the doping concentration of the P-type region 105. P+ layers 1052, 1072, and 1064 can improve the contact resistance within the contact holes.

[0058] In step 307, a metal contact electrode, such as tungsten metal, is formed in contact holes 1051, 1071 and 1063.

[0059] In step 308, metal layers 1011 and 1012 are formed over the dielectric layer.

[0060] Metal layers are located on the surface of dielectric layer 108, and metal layers 1011 and 1012 are electrically isolated from each other by patterning.

[0061] According to one embodiment, metal layer 1011 is electrically connected to a metal electrode within contact hole 1051. In some embodiments, metal layer 1012 is electrically connected to a metal electrode within contact hole 1071. According to one embodiment, metal layer 1011 or metal layer 1012 is electrically connected to a metal electrode within contact hole 1063.

[0062] In some embodiments, the contact hole 1071 of the epitaxial layer 103 is in contact with the N+ region 107, which can improve the contact resistance.

[0063] According to one embodiment, the depths of contact holes 1051 and 1071 can range from 0.2 μm to 1 μm. Specifically, the depths of contact holes 1051 and 1071 can be 0.4 μm. It is understood that the depths of contact holes 1051 and 1071 can also be set according to the SGT MOSFET process parameters, with a maximum depth less than the depth of the P-type region 105.

[0064] In the embodiment shown in Figure 4, the drain metal layer 101 of the SGT MOSFET and the substrate 102 do not serve as the cathode electrode of the diode in the temperature sensor 100. The cathode electrode of the diode in the temperature sensor is the metal layer 1012.

[0065] Figure 5 The diagram shown is a schematic diagram of an SGT temperature sensor structure according to an embodiment of this application.

[0066] According to one embodiment, an isolation ring 106 is provided between the diode serving as an SGT temperature sensor and the SGT power transistor disposed on the same substrate 102 and epitaxial layer 103. The isolation ring 106 includes a trench formed in the epitaxial layer 103 and opening onto the upper surface of the epitaxial layer 103, closing and surrounding the temperature sensor 100. According to one embodiment, the isolation ring 106 further includes a dielectric layer 1061 located on the inner surface of the trench. According to one embodiment, the isolation ring 106 further includes an isolation electrode 1062 located within the dielectric layer 1061.

[0067] According to one embodiment, the number of isolation rings 106 may be more than one.

[0068] According to one embodiment, the SGT temperature sensor 100 includes a P-type region 105 formed in an epitaxial layer 103 surrounded by an isolation ring 106, wherein the doping type of the P-type region 105 is complementary to that of the epitaxial layer 103. The depth to which the P-type region 105 extends in the epitaxial layer 103 is less than the depth to which the isolation ring 106 extends in the epitaxial layer 103.

[0069] According to one embodiment, the SGT temperature sensor 100 further includes an N-type region 104. The N-type region 104 is located within the area surrounded by the isolation ring 106. The N-type region 104 includes a portion of the N-type epitaxial layer 103. According to one embodiment, the P-type region 105 and the N-type region 107 together form the PN junction of the temperature sensor 100.

[0070] Optionally, according to one embodiment, the SGT temperature sensor 100 further includes an N+ region 107 located within the area surrounded by the N-type region 104. The N+ region 107 has the same doping type as the N-type region 104, but with a higher doping concentration.

[0071] According to one embodiment, the extension depth of the N+ region 107 in the epitaxial layer 103 is less than the extension depth of the P-type region 105 in the epitaxial layer 103.

[0072] According to one embodiment, the SGT temperature sensor 100 includes a dielectric layer 108 formed over the epitaxial layer 103.

[0073] According to one embodiment, the SGT temperature sensor 100 further includes metal layers 1011 and 1012 formed above the dielectric layer 108. According to one embodiment, metal layers 1011 and 1012 are electrically isolated from each other.

[0074] According to one embodiment, the SGT temperature sensor 100 further includes contact holes 1051, 1071, and 1063. Contact electrodes are formed in contact holes 1051, 1071, and 1063 respectively. Metal layer 1011 is electrically connected to the metal electrode in contact hole 1051; metal layer 1012 is electrically connected to the metal electrode in contact hole 1071; and metal layer 1011 or 1012 is electrically connected to the metal electrode in contact hole 1063.

[0075] Optionally, according to one embodiment, P+ layers 1052 and 1072 are provided at the bottom of contact holes 1051, 1071, and 1063, and P+ layer 1064 is provided at the bottom of contact hole 1063. The doping type of P+ layers 1052, 1072, and 1064 is the same as that of P-type region 105, but the doping concentration is higher than that of P-type region 105.

[0076] In some embodiments, the metal layer 1012 may be coupled to an external differential circuit input.

[0077] According to one embodiment of this application, the metal layer 1011 can be coupled to a voltage source. The potential of the voltage source is higher than the drain or source potential of the SGT MOSFET device on the same substrate as the temperature sensor. The cathode of the temperature sensor can be coupled to the drain or source of the SGT MOSFET to forward bias the diode in the temperature sensor. In one embodiment, the difference between the potential of the voltage source and the drain potential of the SGT MOSFET device can be the forward conduction voltage of the temperature sensing diode.

[0078] In some embodiments, the metal layer 1011 can be coupled to the input of an external control circuit, for example, to a current source of the external control circuit, configured to provide a stable current for the SGT temperature sensor, so that the PN junction of the diode in the temperature sensor always has a positive current flowing through it during application, and the temperature change is monitored by monitoring the change in the cathode voltage of the diode in the temperature sensor.

[0079] Alternatively, the method for fabricating the SGT temperature sensor may include fabricating a substrate 102 for the SGT MOSFET device and growing an epitaxial layer 103 on the substrate 102. Furthermore, it may also include fabricating a drain metal layer 101 for the SGT MOSFET.

[0080] According to one embodiment of this application, the performance characteristics of the SGT temperature sensor are affected by factors such as the doping concentration of the P-type region 105, the epitaxial layer 103, the N+ region 107, the PN junction contact area of ​​the diode in the temperature sensor, and the excitation current of the temperature sensor.

[0081] Figures 6a to 6b The diagram illustrates the placement of the SGT temperature sensor in an SGT circuit according to one embodiment of this application. According to one embodiment, in the SGT circuit layout design, the SGT temperature sensor is placed close to the SGT MOSFET, which serves as the main power device. Depending on the location of the main power device, the SGT temperature sensor can be placed in the middle of the SGT circuit, or it can be placed at a corner of the SGT circuit. In some embodiments, the number of SGT temperature sensors can be more than one, depending on actual needs.

[0082] The temperature sensor proposed in this application is integrated with the SGT MOSFET device on the same substrate. Temperature monitoring is achieved by monitoring the forward conduction voltage of the SGT temperature sensor, which has higher sensitivity and accuracy, and better practicality.

[0083] The temperature sensor fabrication method proposed in this application utilizes the manufacturing process and flow of SGT MOSFETs. Without increasing the process flow, it achieves the goal of integrating a temperature sensor into the IC circuit while fabricating SGT MOSFETs. It is not affected by device manufacturers, batches, or manufacturing processes, and is simple, low-cost, more economical, and more widely applicable.

[0084] The above embodiments are for illustrative purposes only and are not intended to limit the scope of this application. Those skilled in the art can make various changes and modifications without departing from the scope of this application. Therefore, all equivalent technical solutions should also fall within the scope of this application.

Claims

1. An SGT circuit, comprising: An SGT power transistor and a temperature sensor are disposed on the same substrate and epitaxial layer, and an isolation ring is formed in the epitaxial layer and opens on the upper surface of the epitaxial layer, closing and surrounding the temperature sensor. The temperature sensor includes a temperature sensing diode, comprising: Substrate; An epitaxial layer is formed on the substrate, having the same doping type as the substrate, wherein the doping concentration of the substrate is higher than that of the epitaxial layer; A first region is formed in the epitaxial layer surrounded by the isolation ring, wherein the doping type of the first region is complementary to that of the epitaxial layer, and the depth to which the first region extends in the epitaxial layer is less than the depth to which the isolation ring extends in the epitaxial layer. A dielectric layer is formed over the epitaxial layer; A metal layer is formed above the dielectric layer; Multiple contact holes are respectively configured to electrically connect the first region to a first portion of the metal layer and to electrically connect the epitaxial layer to a second portion of the metal layer, wherein the first and second portions of the metal layer are electrically isolated from each other; The first region and the epitaxial layer together form the PN junction of the temperature sensing diode.

2. The SGT circuit according to claim 1, wherein, The epitaxial layer surrounded by the isolation ring includes a second region, which has the same doping type as the epitaxial layer but a higher doping concentration.

3. The SGT circuit according to claim 2, wherein, The first region extends to a greater depth in the epitaxial layer than the second region extends to a greater depth in the epitaxial layer.

4. The SGT circuit according to claim 1, wherein, A contact electrode is formed in the contact hole, and a third region for improving contact resistance is provided at the bottom of the contact electrode. The doping type of the third region is the same as that of the first region, but the doping concentration is higher than that of the first region.

5. The SGT circuit according to claim 1, wherein, The isolation ring includes a trench opening on the upper surface of the epitaxial layer, a dielectric layer located on the inner surface of the trench, and an isolation electrode surrounded by the dielectric layer in the trench. The isolation electrode is electrically connected to a first portion or a second portion of the metal layer.

6. The SGT circuit according to claim 1, wherein the number of isolation rings is more than one.

7. An electronic device comprising the SGT circuit as described in any one of claims 1-6.

8. A method for fabricating an SGT temperature sensor, comprising: A closed trench is formed in an epitaxial layer located on a substrate, the trench opening at the upper surface of the epitaxial layer, wherein the doping type of the epitaxial layer is the same as that of the substrate, and the doping concentration of the substrate is higher than that of the epitaxial layer; An epitaxial layer surrounding an isolation ring is doped to form a first region, wherein the doping type of the first region is complementary to that of the epitaxial layer, and the depth to which the first region extends in the epitaxial layer is less than the depth to which the isolation ring extends in the epitaxial layer. A dielectric layer is formed on the upper surface of the epitaxial layer; The dielectric layer and the epitaxial layer are etched to form a first contact hole that opens on the upper surface of the dielectric layer and contacts the first region, and a second contact hole that opens on the upper surface of the dielectric layer and contacts the epitaxial layer surrounded by the isolation ring is formed in the epitaxial layer. Metal contact electrodes are formed in the first and second contact holes; A first metal layer is formed on the surface of the dielectric layer and patterned to form a first portion and a second portion that are electrically isolated from each other, wherein the first portion is electrically connected to a metal contact electrode in the first contact hole and the second portion is electrically connected to a metal contact electrode in the second contact hole.

9. The preparation method according to claim 8, further comprising: A second region is formed around the epitaxial layer surrounded by the isolation ring, wherein the doping type of the second region is the same as that of the epitaxial layer, and the doping concentration is higher than that of the epitaxial layer; in, When forming the second contact hole, the dielectric layer, the second region, and the epitaxial layer are etched sequentially to form a second contact hole that contacts both the second region and the epitaxial layer.

10. The preparation method according to claim 8 further includes forming a third region at the bottom of the first contact hole and the second contact hole, wherein the doping type of the third region is the same as that of the first region, and the doping concentration is higher than that of the first region.

11. The preparation method according to claim 8 further includes forming a dielectric layer on the inner wall of the groove of the isolation ring, and etching the dielectric layer to form an isolation electrode therein.

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