A semiconductor field effect transistor device and a method of manufacturing the same

Abstract

A semiconductor field effect transistor device and its manufacturing method, the present invention relates to in power semiconductor device, the semiconductor device also includes the active region for providing the current conduction area when the device is turned on, the terminal trench region makes the electric field between the source-drain in the active region to prevent the breakdown of the device peripheral region, the gate-source capacitance region provides additional Cgs for the device and improves the switching characteristic, the stress release region for reducing the stress generated by the periodic arrangement of the device trench and the electric field cutoff region, compared with the traditional structure and process, the gate-source capacitance-gate-drain capacitance ratio can be improved, and the device terminal structure with high reliability is provided.

Description

TECHNICAL FIELD

[0001] The present application relates to a structure of a power semiconductor device, in particular a shielded gate trench field effect transistor device, and a manufacturing method thereof. BACKGROUND

[0002] The following will describe the related technical background of the existing shielded gate trench field effect transistor. It should be noted that the corresponding position words such as "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", "vertical" in this document are corresponding to the relative positions of the reference drawings. The specific implementation does not limit the fixed direction. It should be noted that the devices in the drawings are not necessarily drawn in specific proportions. The straight lines shown by the boundaries of the doped regions and trenches in the drawings, and the sharp corners formed by the boundaries, are generally not straight lines and precise angles in actual applications.

[0003] The shielded gate trench field effect transistor, as a new type of power device, has the characteristics of low on-resistance and fast switching speed. The structural feature of the shielded gate trench field effect transistor is that there are mutually isolated gate electrodes and shielded gate electrodes in the trench, wherein the shielded gate electrode is located below the gate electrode and needs to be connected to the upper surface metal.

[0004] During the switching process of the field effect transistor device, especially in the case of parallel use of multiple field effect transistors, improving the ratio of gate-source capacitance (Cgs) to gate-drain capacitance (Cgd) is beneficial to prevent device damage caused by device mis-turn-on. In the traditional design, the ratio of gate-source capacitance (Cgs) to gate-drain capacitance (Cgd) is usually determined by the structure of the device.

[0005] High-reliability applications such as automobiles and rail transit require that the parameters of the field effect transistor device remain stable over a long period of use to ensure circuit safety. However, in actual application processes, water vapor or foreign contaminant ions may invade the field effect transistor device chip, affecting threshold voltage, leakage, breakdown voltage and other parameters. Therefore, a high-reliability device terminal region needs to be set to prevent foreign contaminants or mobile ions from entering the active region of the chip.

[0006] In the shielded gate trench field effect transistor, the deep trench structure can cause serious stress on the surface of the chip, and the surface oxide layer and passivation layer of the terminal region are prone to cracking or delamination under thermal expansion and contraction, which can cause water vapor or foreign contaminant ions to more easily invade the semiconductor interior, leading to device failure.

[0007] In addition, part of the high reliability of the gate electrode of the device has certain requirements for the electrostatic protection performance, need to set up between the gate and the source of the field effect transistor clamping protection circuit, such as parallel zener diode structure. The above integrated electrostatic protection circuit of field effect transistor, the total process flow usually needs eight to ten photolithography steps, the process cost is relatively high, it is necessary to put forward to reduce the photolithography step manufacturing process to save cost. SUMMARY

[0008] For the problems mentioned above in the existing shield gate trench type field effect transistor device, there is a need to propose a high reliability process simple shield gate trench type field effect transistor structure and process flow.

[0009] A semiconductor field effect transistor device, the device includes a drain metal layer at the bottom of the device, a first conductive type heavily doped substrate layer above the drain metal layer and a first conductive type epitaxial layer above the first conductive type heavily doped substrate layer; a second conductive type doped body region and a first conductive type heavily doped source region on the upper surface of the device; an oxide layer, a source metal layer and a gate metal layer on the top of the device; a passivation layer on the edge of the device and above the source metal layer and the gate metal layer; the upper surface of the device extends downwardly with a first type of trench and a second type of trench, the first type of trench contains a first shield gate electrode and a gate electrode, the second type of trench contains a second shield gate electrode and a surface polysilicon layer formed upwardly from the second shield gate electrode; the device includes at least an active region for providing a current conduction area when the device is turned on, a termination trench region for locating the electric field between the source and the drain in the active region when the device is reverse biased to prevent the breakdown of the peripheral region of the device, a gate-source capacitance region for providing additional Cgs for the device and improving the switching performance, a stress release region for reducing the stress generated by the periodic arrangement of the trenches of the device and an electric field cutoff region.

[0010] The active region is composed of a series of first type of trenches; the termination trench region is composed of more than one second type of trench which are parallel to each other, the second shield gate electrode in the second type of trench in this region is connected with the source metal layer; the gate-source capacitance region contains more than one second type of trench which are parallel to each other, the second shield gate electrode in this region is connected with the source metal layer, the gate metal in this region and the surface polysilicon layer in this region form a vertical gate-source capacitance; the stress release region contains at least one first type of trench which surrounds the gate-source capacitance region; the electric field cutoff region includes at least one first type of trench which surrounds the stress release region, a second type of trench which surrounds the first type of trench in this region, a semiconductor region which surrounds the second type of trench in this region for connecting the periphery of the device and a contact hole of the second shield gate electrode in the second type of trench in this region.

[0011] Preferably, the first, second and third isolation layers are sequentially arranged between the shield gate electrode and the trench sidewall, wherein the second isolation layer is made of a material different from the first and third isolation layers.

[0012] Further, the third type of trench dielectric layer has a thickness wider below the trench than above the trench.

[0013] Preferably, the electric field cutoff region further comprises an electric field cutoff metal layer above the electric field cutoff region, the electric field cutoff metal layer being connected to the gate electrode in the first type of trench in the electric field cutoff region through a contact hole and being connected to the peripheral contact hole.

[0014] Preferably, the second type of trench in the terminal trench region is directly below a second conductive type ion implantation region.

[0015] Preferably, the gate-source capacitance region is provided with a gate polysilicon layer in the oxide layer, the gate polysilicon layer and the surface polysilicon layer of the region forming a vertical gate-source capacitance.

[0016] Preferably, the stress release region is provided with a plurality of invalid trenches peripherally around the first type of trench.

[0017] Further, the invalid trench is a first type of trench and the gate electrode and the first shield gate electrode in the trench are not connected to an external electrode and are in a floating potential, or the invalid trench is an insulator-filled trench.

[0018] Preferably, the device further comprises an electrostatic protection region adjacent to the terminal trench region and a gate trench region adjacent to the electrostatic protection region; the electrostatic protection region comprises a surface polysilicon layer above the semiconductor, the polysilicon layer being connected to the second shield gate electrode in the terminal trench region and the gate trench region respectively; the polysilicon layer is provided with a horizontal zener diode structure.

[0019] Preferably, the electrostatic protection region is further provided with the second type of trench for defining the position of the electrostatic protection region.

[0020] Preferably, the gate metal and the polysilicon layer above the device form a vertical capacitance structure.

[0021] Preferably, the device comprises two or more active regions, the trenches in each active region being parallel or perpendicular, and the active regions being connected to the gate trench region through the electrostatic protection region.

[0022] A method for manufacturing a semiconductor field effect transistor device, the method comprising the following steps:

[0023] First, form a first conductive type epitaxial layer on a first conductive type heavily doped substrate layer, and form a series of first type trenches and second type trenches on the first conductive type epitaxial layer;

[0024] Second, form an isolation layer in the trenches;

[0025] Fourth, fill the trenches with polysilicon and above the semiconductor upper surface, the thickness of the polysilicon on the semiconductor upper surface is between 2000A and 8000A after filling;

[0026] Fifth, etch the polysilicon above the first type trenches under the protection of photoresist, and form a shield gate electrode in the first type trenches;

[0027] Sixth, form a thick oxide layer on the surface of the shield gate electrode by thermal oxidation, and at the same time, the upper surface and side surface of the polysilicon layer above the second type trenches are partially oxidized into oxide; after thermal oxidation, the polysilicon remaining on the semiconductor upper surface forms a surface polysilicon layer;

[0028] Seventh, etch back the thick oxide layer to form an inter-electrode isolation layer, and remove the isolation layer to expose the upper half of the trench;

[0029] Eighth, form a gate oxide layer and a gate electrode respectively, then perform ion implantation to form a second conductive type doped body region and a first conductive type heavily doped source region;

[0030] Ninth, form an oxide layer, a contact hole, an upper surface metal layer, a passivation layer and a back metal layer respectively, and finally form a device.

[0031] As a preferred, after forming the photoresist protection area in step five, or after forming the shield gate electrode, an additional vertical ion implantation is performed under the protection of photoresist to increase the oxidation rate of the polysilicon in the exposed area in the subsequent thermal oxidation process.

[0032] As a preferred, in step five, the surface polysilicon and surface oxide layer above the second type trenches act as a hard mask to limit the ion implantation area to the position between the first type trenches during ion implantation of the second conductive type doped body region and the first conductive type heavily doped source region.

[0033] As a preferred, in the eighth step, a Zener diode structure is formed on the polysilicon on the semiconductor upper surface in the electrostatic protection area, which is located between two segments of the second type trenches.

[0034] As preferred, after the second conductivity type body region is formed in the eighth step, the oxide layer above the polysilicon is etched to form discontinuous openings; then, in the subsequent step of ion implantation to form the first conductivity type heavily doped source region, the first conductivity type heavily doped polysilicon above the polysilicon is simultaneously formed, and the first conductivity type heavily doped polysilicon and the second conductivity type polysilicon form a Zener diode structure.

[0035] As preferred, after the first conductivity type heavily doped source region is formed in the eighth step, the oxide layer above the polysilicon is etched to form discontinuous openings under the protection of the photoresist, and then the first conductivity type heavily doped polysilicon above the polysilicon is formed by additional ion implantation.

[0036] The present application has the advantages that a novel shielded gate trench field effect transistor device structure and manufacturing process are provided, which can improve the ratio of gate-source capacitance to gate-drain capacitance and provide a high-reliability device terminal structure compared with the conventional structure and process.

[0037] In addition, a device structure integrated with electrostatic protection is provided based on the above structure.

[0038] In addition, a manufacturing method of the above structure is provided, which can save at least two photoetching steps and effectively reduce the manufacturing cost. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 Fig. 1 is a sectional view of a shielded gate trench field effect transistor of the present application;

[0040] Figure 2 Fig. 4 is a schematic view of the position of the P-type ion implantation region;

[0041] Figure 3 Fig. 6 is a schematic view of the position of the gate polysilicon layer;

[0042] Figure 4 Fig. 8 is a sectional view of the electrostatic protection region of the shielded gate trench field effect transistor of the present application;

[0043] Figure 5 Fig. 10 is a top view of a possible device layout of the shielded gate trench field effect transistor of the present application;

[0044] Figures 6-13 Fig. 12 is a sectional view of a possible key manufacturing step of the shielded gate trench field effect transistor of the present application;

[0045] Figure 14 Fig. 14 is a sectional view of a key manufacturing step of the electrostatic protection region of the shielded gate trench field effect transistor of the present application. DETAILED DESCRIPTION

[0046] The present application will be described in detail below with reference to the accompanying drawings and examples. It should be noted that in the following description of the shielded gate trench field effect transistor device and its manufacturing method, the semiconductor substrate of the shielded gate trench field effect transistor device is considered to be composed of silicon (Si) material. However, the substrate can also be composed of any other suitable material for manufacturing a shielded gate trench field effect transistor, such as gallium nitride (GaN), silicon carbide (SiC), etc. In the following description, the conductivity type of the semiconductor region is divided into P-type (second conductivity type) and N-type (first conductivity type). A P-type conductivity semiconductor region can be formed by doping one or several impurities into the original semiconductor region, which can be but are not limited to boron (B), aluminum (Al), gallium (Ga), etc. An N-type conductivity semiconductor region can also be formed by doping one or several impurities into the original semiconductor region, which can be but are not limited to phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), proton (H+), etc. In the following description, a heavily doped P-type conductivity semiconductor region is denoted as P+ region, and a heavily doped N-type conductivity semiconductor region is denoted as N+ region. For example, in a silicon material substrate, the impurity concentration of a heavily doped region is generally between 1 x 1019cm-3and 1 x 1021cm-3, unless otherwise specified. Those skilled in the art should know that the P-type (second conductivity type) and N-type (first conductivity type) described in the present application can be interchanged. 19 cm -3 to 1 x 1021cm 21 cm -3 Those skilled in the art should know that the P-type (second conductivity type) and N-type (first conductivity type) described in the present application can be interchanged.

[0047] Figure 1 A semiconductor field effect transistor device of the first embodiment includes a bottom drain metal layer (213), an N+ substrate layer (200) above the drain metal layer, an N-type epitaxial layer (201) above the N+ substrate layer, a P-doped body region (220) and an N+ doped source region (221) on the top surface of the device, a source metal layer (240) and a gate metal layer (241) on the top of the device, and a passivation layer (242) on the edge of the device, on top of the source metal layer (240) and the gate metal layer (241).

[0048] In addition, two types of trenches are included: the first type of trench (202) and the second type of trench (211).

[0049] The first type of trench (202) contains at least a gate electrode (209) above the trench and a shield gate electrode (205) below. The gate electrode (209) is separated from the trench sidewall by a gate oxide layer. The gate electrode (209) is separated from the shield gate electrode (205) by an inter-electrode separation layer (206). The shield gate electrode (205) is connected to the source metal (240) on the top surface of the device. In addition, the shield gate electrode (205) is separated from the trench sidewall by a first separation layer (225), a second separation layer (226), and a third separation layer (227). The second separation layer (226) is made of a different material than the first and third separation layers, and is used to reduce the stress on the adjacent semiconductor caused by the first and third separation layers during thermal processes. The first separation layer (225) is typically an oxide with a thickness of 100A to 1000A. The second separation layer (226) can be a nitride or other oxidation-resistant insulating material with a thickness of 100A to 2000A. The third separation layer (227) can be an oxide with a thickness of 500A to 5000A.

[0050] The second type of trench (211) contains at least a shield gate electrode (205). The shield gate electrode (205) extends to the top surface of the semiconductor and forms a surface polysilicon layer (247). The shield gate electrode (205) is separated from the trench sidewall by a first separation layer (225), a second separation layer (226), and a third separation layer (227).

[0051] The embodiment contains at least the following regions: an active region (251), a termination trench region (252), a gate-source capacitance region (253), a stress relief region (254), and an electric field cutoff region (255).

[0052] The active region (251) is formed by a series of the first type of trenches (202) arranged horizontally.

[0053] The active region (251) is used to provide a current conduction region when the device is turned on.

[0054] The termination trench region (252) contains one or more segments of the second type of trenches (211) arranged parallel to each other. The second type of trenches surround the active region (251) and the shield gate electrodes (205) in the second type of trenches are connected to the source metal layer (240).

[0055] The termination trench region (252) is used to prevent breakdown in the peripheral region of the device by locating the electric field between the source and drain when the device is reverse biased within the active region of the device.

[0056] The gate-source capacitance region (253) contains one or more segments of second-type trenches (211) that are parallel to each other, and a gate metal (241) on top of them. The shield gate electrode (205) in it is connected to the source metal layer (240), and the shield gate electrode (205) extends to the part of the semiconductor upper surface and the gate metal (241) forms a vertical gate-source capacitance. The second-type trenches (211) in the gate-source capacitance region (253) can have multiple segments and be arranged parallel to each other, and the spacing between the trenches can be larger than the spacing of the trenches in the active region (251).

[0057] The gate-source capacitance region (253) serves to provide additional Cgs for the device and improve switching performance; in addition, when reverse biased, the interior of the device upper surface is at the source potential and the device edge is close to the drain potential, and the positively charged foreign contaminant ions (such as Na + , K + , H + , Zn + , etc.) are easily moved from the edge to the interior of the device under the influence of the electric field, accumulated at the terminal region (or other process defects), and cause breakdown weakness and affect the breakdown voltage of the device. The vertical gate-source capacitance in the above structure can alleviate the movement and accumulation of positively charged foreign contaminant ions in the interior of the device during the charging and discharging process of the device switching, and prevent the influence of mobile ions on the terminal trench region (252).

[0058] The stress release region (254) has a length greater than 5um and contains at least one segment of first-type trenches (202) surrounding the gate-source capacitance region (253). The depth of the trenches can be shallower than the trenches in the terminal trench region. In some embodiments, the filling material in the trenches in the (254) region can be different from the filling material in the trenches in other regions. For example, the gate electrode (209) material in the first-type trenches (202) in the (254) region is metal, while the material in the other trenches is polysilicon. For another example, the gate electrode (209) material in the first-type trenches (202) in the (254) region is undoped polysilicon, while the material in the other trenches is doped polysilicon. The purpose is to reduce the stress in the trenches in the release region (254).

[0059] The stress release region (254) serves to reduce the stress generated by the periodically arranged trenches in the device, reduce micro-cracks and warping in the peripheral region of the device due to stress, and the trenches in this region also serve to block the migration of contaminant ions into the interior of the device.

[0060] In addition, outside the above-mentioned first-type trenches (202), there can be multiple segments of first-type trenches (202) with different lengths and directions.

[0061] The field stop region (255) includes at least a first type of trench (202) surrounding the termination trench region (252), a second type of trench (211) surrounding the first type of trench (202), and a peripheral via trench (219) surrounding the second type of trench (211). The via trench (219) is filled with a metal or a metal compound to connect the semiconductor region at the periphery of the device to the shield gate electrode (205) in the second type of trench (211).

[0062] In addition, the field stop region (255) can further include an overlying field stop metal layer (243). The field stop metal layer (243) can be connected to the gate electrode (209) of the first type of trench (202) in the field stop region (255) through a contact hole and connected to the peripheral via trench (219).

[0063] The field stop region (255) functions to prevent the electric field between the source and the drain from extending to the edge region of the device when the device is reverse biased, and to form an equipotential region at the outermost periphery of the device to prevent mobile ions at the edge of the device from accumulating at the edge of the device and to prevent mobile ions on the edge cut defect from invading the interior of the device.

[0064] The above structure provides a high-reliability shield gate trench field effect transistor device structure, which can have various embodiments.

[0065] In one embodiment, a P-type implanted ion region (261) is provided directly below the second type of trench (211) in the termination trench region (252), as shown in FIG. 2B. The P-type implanted ion region can increase the breakdown voltage of the termination trench region and increase the UIS capability of the device. Figure 2

[0066] In one embodiment, the gate-source capacitance region (253) does not have an overlying gate metal layer 241, but instead has an additional gate polysilicon layer (262) in the oxide layer (230) above the shield gate electrode in the second type of trench (211), as shown in FIG. 2C. The gate polysilicon layer and the shield gate electrode below it form a vertical gate-source capacitance. This structure can save device area by avoiding the minimum width limitation of the metal, and the gate-source capacitance can be larger because the gate polysilicon can be placed closer to the shield gate electrode. Figure 3

[0067] ​​In one embodiment, the stress relief region (254) comprises one or more first type trenches (202) surrounding the gate-source capacitance region (253), and outside the first type trenches (202), there are inactive trenches. The inactive trenches have a lower density than the active region. In one embodiment, the inactive trenches have a lower density closer to the device periphery in the stress relief region (254). The inactive trenches are usually first type trenches, and the gate electrodes and the shield gate electrodes inside the inactive trenches are not connected to external electrodes and are floating. In addition, the inactive trenches can also be insulator-filled trenches. The inactive trenches can be multiple short trenches, and the multiple short trenches have different directions. The inactive trenches can also be multiple needle-shaped trenches, and the multiple needle-shaped trenches are distributed as dots on the layout.

[0068] Figure 4 For another embodiment of the present application, based on the above embodiment, an electrostatic protection region (256) is additionally provided. The electrostatic protection region (256) is adjacent to the termination trench region (252) and the gate trench region (257), respectively.

[0069] In the gate trench region (257), there is at least one second type trench (211), and the shield gate electrode (205) of the second type trench is connected to the gate metal layer (241) on the upper surface.

[0070] The electrostatic protection region (256) comprises a surface polysilicon layer (247) above the semiconductor. The polysilicon layer (247) is connected to the shield gate electrode (205) in the second type trench (211) in the termination trench region (252) and the gate trench region (256), respectively. In the polysilicon layer, there are horizontally arranged Zener diode structures (266). The Zener diode structures can be composed of an alternating set of P-type polysilicon and N-type polysilicon.

[0071] In addition, the electrostatic protection region (256) can also comprise more second type trenches for defining the position of the electrostatic protection region (256). The gate metal (241) above the device and the polysilicon layer (247) can form a vertically arranged capacitor structure and increase the gate-source capacitance.

[0072] Figure 5 For a possible chip layout embodiment of the present application, the trench top view is shown in the figure, where the dashed line A corresponds to the cross-sectional structure in Figure 1 Figure 4

[0073] ​​As shown in the figure, the layout structure can include a plurality of active regions (251), and the trench direction in each active region can be different. The active regions (251) are connected to the gate trench region (257) through the static protection region (256). There are terminal trench regions (252), gate-source capacitance regions (253), stress release regions (254), and electric field cutoff regions (255) between the active regions (251) and the chip periphery, respectively. In the above structure, the second type of trench (211) has a surface polysilicon layer (247) above it, and the polysilicon layer is cut off on the adjacent first type of trench (202). The first type of trench (202) surrounding the second type of trench (211) functions to limit the position of the surface polysilicon layer, and thereby limits the gate-source capacitance region (253) and the static protection region (256).

[0074] The following describes the manufacturing process steps of the above-mentioned shielded gate trench type field effect transistor device, as shown in Figures 6 to 13 .

[0075] In the first step, an N-type epitaxial layer (201) is formed on an N+ substrate layer (200), and a series of first type of trenches (202) and second type of trenches (211) are formed on the N-type epitaxial layer (201), as shown in Figure 5 . Among them, the N+ substrate can be red phosphorus or arsenic doped, with a thickness of 50-800um. The N-type epitaxial layer can be phosphorus doped, with a thickness of 0.5-15um. In a specific embodiment, the doping concentration in the N-type epitaxial layer is distributed from light to heavy. The lightest place with the highest doping concentration is between 5e17 cm -3 and 1e16 cm -3 , and the densest place is between 5e17 cm -3 and 1e18 cm -3 .

[0076] Before the formation of the trenches, it can be necessary to preform a hard mask on the upper surface of the epitaxial layer through lithography. The hard mask can be a semiconductor oxide or nitride, or a combination of the two. The hard mask can be removed after trench etching, or it can be partially or completely retained on the upper surface of the epitaxial layer after trench etching.

[0077] The above-mentioned first type of trench (202) and second type of trench (211) can be formed by dry etching at the same time, and the etching depth is determined by the size of the etching window on the upper surface of the semiconductor during etching. In one embodiment, the trenches can be formed by reactive ion etching. In a specific embodiment, the width of the upper surface of the first type of trench is 0.2-0.5um, and the depth is 1.2-3um. In another specific embodiment, the width of the upper surface of the first type of trench is 0.5-1.5um, and the depth is 3-6um.

[0078] Second, a trench insulating layer, or isolation layer, is formed in the trench. The trench insulating layer is composed of a first isolation layer (225), a second isolation layer (226), and a third isolation layer (227), as shown in FIG. 2B. Figure 5

[0079] The first isolation layer (225) is typically an oxide, and can be formed by thermal oxidation or deposition, or a combination of the two. The first trench dielectric layer typically has a thickness of 100 A to 1000 A.

[0080] The second isolation layer (226) can be a nitride or other oxidation-resistant insulating material, such as silicon-rich silicon nitride, and can be formed by deposition. The second trench dielectric layer typically has a thickness of 100 A to 2000 A. In one embodiment, the second trench dielectric layer is formed by depositing 1000 A of nitride on the first trench dielectric layer by chemical vapor deposition.

[0081] The third isolation layer (227) can be an oxide, and can be formed by deposition. The third trench dielectric layer typically has a thickness of 500 A to 5000 A.

[0082] In one embodiment, the third isolation layer (227) is thicker below the trench than above the trench. In one embodiment, the third isolation layer (227) is an oxide with boron or phosphorus doping.

[0083] Fourth, the trench is filled with polysilicon (245) to a level above the top surface of the semiconductor, as shown in FIG. 2D. Figure 8

[0084] The thickness of the polysilicon (245) above the top surface of the semiconductor is typically 2000 A to 8000 A. After the trench is filled with polysilicon (245), chemical mechanical polishing is typically performed to planarize the top surface of the polysilicon.

[0085] In one embodiment, the polysilicon (245) is low-doped or undoped. This facilitates the formation of a static protection structure in a subsequent process by adjusting the doping concentration.

[0086] Fifth, photolithography is performed to etch the polysilicon above the first trench (202) and form a shield gate electrode (205) in the first trench, with the photoresist (246) protecting the polysilicon (245) above the second trench (211), as shown in FIG. 2E. Figure 9

[0087] During photolithography, the photoresist protects the polysilicon (245) above the second trench (211) so that the polysilicon in this region remains on the top surface of the semiconductor after etching.

[0088] The polysilicon is typically etched by dry etching to a depth of 0.3 to 1 μm below the top surface of the semiconductor.​​​

[0089] In one embodiment, after the photoresist protection area is formed, or after the shield gate electrode (205) is formed, an additional vertical ion implantation is performed under the protection of the photoresist to increase the oxidation rate of the polysilicon in the exposed area in the subsequent thermal oxidation process.

[0090] In one embodiment, the polysilicon (245) is undoped or low doped polysilicon, and after the shield gate electrode (205) is formed, an additional vertical ion implantation is performed under the protection of the photoresist to increase the doping concentration and oxidation rate of the polysilicon of the shield gate electrode (205), which is beneficial to achieving different thicknesses of the oxide layer in different areas in the subsequent thermal oxidation process.

[0091] In one embodiment, the polysilicon (245) is undoped or low doped polysilicon, and after the shield gate electrode (205) is formed, an additional vertical ion implantation is performed under the protection of the photoresist to increase the doping concentration and oxidation rate of the polysilicon of the shield gate electrode (205), which is beneficial to achieving different thicknesses of the oxide layer in different areas in the subsequent thermal oxidation process. Figure 10

[0092] The thickness of the thick oxide layer (206) formed by thermal oxidation is between 0.2 and 1 um, and the thickness of the polysilicon layer (247) remaining on the upper surface of the semiconductor after thermal oxidation is between 0.05 um and 3 um. The polysilicon layer (247) serves as the vertical capacitance structure and electrostatic protection structure of the final device. Its width and length are defined by the distance between adjacent second-type trenches (211). In one embodiment, its length and width are between 1-1000 um.

[0093] In one embodiment, the polysilicon (245) is undoped or low doped polysilicon, and after the shield gate electrode (205) is formed, an additional vertical ion implantation is performed under the protection of the photoresist to increase the doping concentration and oxidation rate of the polysilicon of the shield gate electrode (205), which is beneficial to achieving different thicknesses of the oxide layer in different areas in the subsequent thermal oxidation process. Figure 11

[0094] The method of etching the oxide layer (249) can be wet etching. When etching the thick oxide layer (249), the oxide layer (248) above the polysilicon layer (247) on the upper surface is partially etched, which serves to protect the polysilicon layer (247). The first isolation layer (225) can be an oxide, which can also be completely removed at the same time when etching the thick oxide layer (249). After etching, the thickness of the inter-electrode isolation layer (206) is between 0.1 and 0.5 um.

[0095] ​​The second isolation layer (226) can be removed by wet etching. After etching, a recess structure can be formed between the first isolation layer (225) and the third isolation layer (227). In one embodiment, after the second isolation layer (226) is removed, an oxide layer can be deposited to fill the recess, and the oxide layer can be etched back at the same time when the third isolation layer (227) is removed.

[0096] In the eighth step, a gate oxide layer (208) and a gate electrode (209) are formed, and then ion implantation is performed to form a P-type doped body region (220) and an N + -type doped source region (221), as shown in FIG. 8. Figure 12

[0097] The gate electrode (209) is usually polysilicon, and the method for forming the gate electrode (209) can include two steps of depositing polysilicon and etching back the polysilicon. The method for etching back the polysilicon can be dry etching. The distance between the upper surface of the etched back gate electrode (209) and the upper surface of the semiconductor is 0-0.2 μm.

[0098] During the ion implantation, the surface polysilicon (247) and the surface oxide layer (248) above the second type of trench (211) can act as a hard mask to limit the ion implantation region to the position between the first type of trench (202). Therefore, the number of photolithography steps for ion implantation can be reduced by one or two, for example, by the arrangement of the first and second type of trench. Figure 5

[0099] In the ninth step, an oxide layer (230), a contact hole (219), an upper surface metal layer (240, 241, 243), a passivation layer (242), and a back surface metal layer (213) are formed, and finally a device is formed, as shown in FIG. 9. Figure 13

[0100] The oxide layer (230) is usually composed of an oxide, and the thickness is 0.3-1.5 μm. In one embodiment, the oxide layer (230) includes a lower layer of undoped silicon oxide with a thickness of 0.05-1.0 μm and an upper layer of boron phosphorus silicon glass with a thickness of 0.1-1.5 μm. The method for forming the oxide layer (230) can include oxide deposition and oxide planarization.

[0101] Some of the contact holes (219) are located directly above the trenches and extend into the shield gate electrode (205) or the gate electrode (209); some of the contact holes (219) are located between the trenches and the trenches and extend into the semiconductor and contact the P-type doped body region (220) and the N + -type doped source region (221).

[0102] ​​​The top surface metal is usually Al or Al compound, such as Al / Cu, Al / Si / Cu, with a thickness of 3-5 μm. Before the top surface metal is formed, the diffusion barrier metal material can be first filled in the contact hole (219).

[0103] The top surface metal can also be a combination of layers, such as an Al / Cu layer on top and a Ti / W layer on bottom, and the layers can be formed by different photolithography steps.

[0104] The passivation layer (242) is formed on top of the metal layer, and the material can be an oxide layer, a nitride layer, a silicon-rich nitride layer, a polyimide, or a combination thereof. In one embodiment, the passivation layer is a combination of a 3000 A - 10000 A oxide layer, a 3000 A - 8000 A nitride layer, and a 3 μm - 8 μm polyimide layer.

[0105] Based on the above process flow, a process flow for a device structure with an electrostatic protection structure is as follows: in the above eighth step, a Zener diode structure (266) is formed on the polysilicon (247) on the top surface of the semiconductor in the electrostatic protection region (256), as shown in Figure 14

[0106] The electrostatic protection region (256) is located between two segments of the second type of trench (211).

[0107] In one embodiment, the surface polysilicon (247) is P-type polysilicon. After the P-type doped body region (220) is formed in the above seventh step, photolithography is used to etch the oxide layer (248) on top of the polysilicon (247) to form a discontinuous opening. Then, when the N+ type doped source region (221) is formed in the subsequent ion implantation step, the N-type doped polysilicon (244) on top of the polysilicon (247) is also formed. The P-type polysilicon and the N-type doped polysilicon (244) form the Zener diode structure (266).

[0108] In another embodiment, the surface polysilicon (247) is P-type polysilicon. After the N+ type doped source region (221) is formed in the above seventh step, photolithography is used to etch the oxide layer (248) on top of the polysilicon (247) to form a discontinuous opening under the protection of the photoresist, and then an additional ion implantation is performed to form the N-type doped polysilicon (244) on top of the polysilicon (247).

[0109] The above-described embodiments and related process steps can be appropriately added or removed to achieve the same effect, and those skilled in the relevant art should recognize that the above-described embodiments of the present application are not limiting but exemplary, and the present application can be implemented in a wider range than the above-described embodiments.​

Claims

1. A semiconductor field effect transistor device, said device comprising a drain metal layer at the bottom of the device, a heavily doped first conductivity type substrate layer over the drain metal layer, and a first conductivity type epitaxial layer over the heavily doped first conductivity type substrate layer. A second-conductivity-type doped body region on the top surface of the device and a first-conductivity-type heavily doped source region; An oxide layer, a source metal layer and a gate metal layer on the top of the device; A passivation layer on the edge of the device and above the source metal layer and the gate metal layer; the top surface of the device extends downwardly with first type of trenches and second type of trenches, the first type of trenches contain first shield gate electrodes and gate electrodes, and the second type of trenches contain second shield gate electrodes and surface polysilicon layers formed upwardly from the second shield gate electrodes; The device further comprises, from inside to outside, an active region for providing a current conduction region when the device is turned on, a termination trench region for locating the electric field between the source and the drain in the active region when the device is reverse biased to prevent the breakdown of the peripheral region of the device, a gate-source capacitance region for providing additional Cgs for the device and improving the switching performance, a stress release region for reducing the stress caused by the periodically arranged trenches of the device, and an electric field cutoff region; the active region is provided with a series of first type of trenches; the termination trench region is provided with more than one second type of trenches parallel to each other, and the second shield gate electrodes in the second type of trenches in this region are connected to the source metal layer; the gate-source capacitance region is provided with more than one second type of trenches parallel to each other, and the second shield gate electrodes in the second type of trenches in this region are connected to the source metal layer, the gate metal in this region and the surface polysilicon layer extending to the top surface of the semiconductor form a vertical gate-source capacitance; the stress release region is provided with at least one first type of trench surrounding the gate-source capacitance region; the electric field cutoff region is provided with at least one first type of trench surrounding the stress release region, a second type of trench surrounding the first type of trench, a semiconductor region surrounding the second type of trench for connecting the periphery of the device, and a contact hole for connecting the second shield gate electrodes in the second type of trench in this region; The surface polysilicon layers formed upwardly are distributed in the termination trench region and the gate-source capacitance region, and the surface polysilicon layers in the two regions are connected.

2. The semiconductor field effect transistor device of claim 1, wherein, The first, second and third isolation layers are sequentially arranged between the shield gate electrodes and the sidewalls of the trenches, and the second isolation layer is made of a material different from that of the first and third isolation layers.

3. The semiconductor field effect transistor device of claim 2, wherein, The third type of trench dielectric layer is thicker below the trench than above the trench.

4. The semiconductor field effect transistor device of claim 1, wherein, The electric field cutoff region further comprises an electric field cutoff metal layer above, which is connected to the gate electrodes in the first type of trenches in the electric field cutoff region through the contact hole and connected to the peripheral contact hole.

5. The semiconductor field effect transistor device of claim 1, wherein, The second-conductivity-type ion implantation region is directly below the second type of trenches in the termination trench region.

6. The semiconductor field effect transistor device of claim 1, wherein, The gate polysilicon layer is arranged in the oxide layer in the gate-source capacitance region, and the gate polysilicon layer and the surface polysilicon layer in this region form a vertical gate-source capacitance.

7. The semiconductor field effect transistor device of claim 1, wherein, The first type of trenches in the stress release region are surrounded by a plurality of invalid trenches.

8. The semiconductor field effect transistor device of claim 7, wherein, The invalid trenches are first type of trenches, and the gate electrodes and the first shield gate electrodes in the trenches are not connected to external electrodes and are floating at a floating potential, or the invalid trenches are insulator-filled trenches.

9. The semiconductor field effect transistor device of claim 1, wherein: The device further comprises an electrostatic protection region adjacent to the terminal trench region and a gate trench region adjacent to the electrostatic protection region; the electrostatic protection region comprises a surface polysilicon layer on the semiconductor, and the polysilicon layer is connected to the second shielding gate electrode in the terminal trench region and the gate trench region respectively; The polysilicon layer is provided with a horizontal Zener diode structure.

10. The semiconductor field effect transistor device of claim 9, wherein, The electrostatic protection region is further provided with a second type of trench for limiting the position of the electrostatic protection region.

11. The semiconductor field effect transistor device of claim 8, wherein: The gate metal and the polysilicon layer on the device form a vertical capacitor structure.

12. The semiconductor field effect transistor device of claim 9, wherein: The device comprises two or more active regions, and the trenches in each active region are parallel or perpendicular, and the active regions are connected to the gate trench region through the electrostatic protection region.

13. A method of manufacturing a semiconductor field effect transistor device, characterized by, The method comprises the following steps: First, forming a first conductive type epitaxial layer on a first conductive type heavily doped substrate layer, and forming a series of first type trenches and second type trenches on the first conductive type epitaxial layer; The device is sequentially arranged from inside to outside as follows: an active region for providing a current conduction region when the device is turned on, a terminal trench region for locating the electric field between the source and the drain in the reverse bias in the active region to prevent breakdown of the peripheral region of the device, a gate-source capacitor region for providing additional Cgs for the device and improving the switching performance, a stress release region for reducing the stress generated by the periodically arranged trenches of the device, and an electric field cutoff region; the active region is provided with a series of first type trenches; the terminal trench region is provided with a plurality of parallel second type trenches; the gate-source capacitor region is provided with a plurality of parallel second type trenches; the stress release region is provided with at least one first type trench surrounding the gate-source capacitor region; The electric field cutoff region is provided with at least one first type trench surrounding the stress release region, a second type trench surrounding the first type trench of the region, and a semiconductor region surrounding the second type trench of the region for connecting the periphery of the device; Second, forming an isolation layer in the trench; Third, filling the trench with polysilicon and making the polysilicon higher than the upper surface of the semiconductor, and the thickness of the polysilicon on the upper surface of the semiconductor is between 2000A and 8000A after filling; Fourth, etching the polysilicon above the first type trench under the protection of photoresist, and forming a first shielding gate electrode in the first type trench; the polysilicon (245) above the second type trench (211) is still retained on the upper surface of the semiconductor; Fifth, forming a thick oxide layer on the upper surface of the first shielding gate electrode by thermal oxidation, and at the same time, the upper surface and the side surface of the polysilicon layer above the second type trench are partially oxidized into oxide; after thermal oxidation, the polysilicon remaining on the upper surface of the semiconductor forms a surface polysilicon layer, and the surface polysilicon layer is distributed in the terminal trench region (252) and the gate-source capacitor region (253); the polysilicon layer in the second trench forms a second shielding gate electrode in the trench; Seventh, etching back the thick oxide layer to form an inter-electrode isolation layer, and removing the isolation layer to expose the upper half of the trench. In the eighth step, gate oxide layer and gate electrode are formed respectively, then ion implantation is performed and second conductive type doped body region and first conductive type heavily doped source region are formed; In the ninth step, oxide layer, contact hole, upper surface metal layer, passivation layer and back surface metal layer are formed respectively, and finally the device is formed; The second shielding gate electrode in the second type of trench in the gate-source capacitance region is connected with the source metal layer; the gate metal in the gate-source capacitance region and the surface polysilicon layer extending to the semiconductor upper surface form vertical gate-source capacitance.

14. The method of manufacturing a semiconductor field effect transistor device according to claim 13, wherein, In step five, after forming the photoresist protection area, or after forming the shielding gate electrode, an additional vertical ion implantation is performed under the protection of photoresist to increase the oxidation rate of the polysilicon in the exposed area in the subsequent thermal oxidation process.

15. The method of manufacturing a semiconductor field effect transistor device of claim 13, wherein, In step five, when ion implantation is performed on the second conductive type doped body region and the first conductive type heavily doped source region, the surface polysilicon and surface oxide layer above the second type of trench serve as a hard mask to limit the ion implantation area to the position between the first type of trench.

16. The method of manufacturing a semiconductor field effect transistor device of claim 13, wherein, In the eighth step, a Zener diode structure is formed on the polysilicon on the semiconductor upper surface in the electrostatic protection area, and the electrostatic protection area is located between two second type of trenches.

17. The method of manufacturing a semiconductor field effect transistor device of claim 13, wherein, After forming the second conductive type doped body region in the eighth step, the oxide layer above the polysilicon is etched to form a discontinuous opening; then, when ion implantation is performed to form the first conductive type heavily doped source region in the subsequent step, the first conductive type heavily doped polysilicon on the polysilicon is also formed, and the second conductive type polysilicon and the first conductive type heavily doped polysilicon form a Zener diode structure.

18. The method of manufacturing a semiconductor field effect transistor device of claim 13, wherein, After forming the first conductive type heavily doped source region in the above-mentioned eighth step, under the protection of photoresist, the oxide layer above the polysilicon is etched to form a discontinuous opening, and then additional ion implantation is performed to form the first conductive type heavily doped polysilicon on the polysilicon.

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