A high speed burst mode laser driver circuit and method

Abstract

The application discloses a high-speed burst mode laser driver circuit and method, and relates to the technical field of optical communication, which comprises an input adjusting circuit, an output driving circuit and a burst control circuit; the noninverting output end and the inverting output end of the input adjusting circuit are connected with the noninverting input end and the inverting input end of the output driving circuit; the noninverting output end and the inverting output end of the output driving circuit are connected with the positive terminal and the negative terminal of the laser; the input end of the enable conversion circuit of the burst control circuit is used for acquiring an external burst enable level signal, the output end is connected with the input end of the enable control circuit of the burst control circuit, and the output end of the enable control circuit is connected with the positive terminal of the laser; the enable conversion circuit disconnects / turns on the output end of the enable control circuit from the ground according to the low / high state of the burst enable level signal, so as to turn on / off the laser. The application improves the working speed of the output driving signal of the laser driver circuit, and realizes the fast turning on and off of the laser.

Description

A high-speed burst mode laser driving circuit and method Technical Field

[0001] This invention relates to the field of optical communication technology, and in particular to a high-speed burst mode laser driving circuit and method. Background Technology

[0002] Currently, home broadband has fully transitioned from the early Kbps copper wire era to the hundred Mbps fiber optic era. The rise and widespread adoption of broadband services such as e-commerce and 4K high-definition video have propelled domestic broadband access networks into the fiber optic (Optical Access Network) era, seamlessly evolving and upgrading from the G / EPON (Gigabit-Capable / Ethernet Passive Optical Network) system architecture to the 10G G / EPON system architecture. The recent emergence of cloud computing, 8K video, autonomous driving, artificial intelligence (AI), and virtual reality (VR) has further driven operators to upgrade existing networks to achieve ultra-broadband capabilities, supporting real-time ultra-high-definition video transmission, real-time monitoring and rapid response, and the coexistence of numerous real-time services. These demands have accelerated the development of standards and prototypes for the next-generation 50G PON optical access network, requiring optical module manufacturers to provide 50G PON optical modules and optical / electrical chip manufacturers to develop and provide related 50Gbps / 25Gbps optical / electrical chips.

[0003] In optical access networks, downlink service data is transmitted continuously in broadcast form, while uplink service data is transmitted in time-division multiplexed burst mode. For the optical signal receiving power chips (such as trans-impedance amplifiers, TIAs) of the OLT (optical line terminal), since the transmitted signal is an uplink burst signal (multiple ONUs transmit uplink signals in time-division mode), the ONU's laser driver circuit is required to be able to quickly turn the laser on and off to transmit uplink signals according to the input drive signal. That is, it must operate in high-speed burst mode, and its response time is usually on the order of tens of nanoseconds to avoid mutual interference between uplink signals from different ONUs and to prevent data transmission failures.

[0004] Chinese invention patent CN201480001223.8A discloses a burst mode laser control circuit. The burst mode laser driver circuit and the laser are connected by an AC coupling capacitor, and the burst control circuit is designed with a series switch. This scheme has large parasitic capacitance and parasitic resistance, which limits the working rate and response time of the drive signal output by the laser driver circuit. It is suitable for 10G G / E PON system architecture with a maximum uplink signal transmission of 10Gbps, but it is difficult to meet the working rate and response time requirements of 50G PON system architecture with a maximum uplink signal transmission of 25 / 50Gbps. Summary of the Invention

[0005] This invention provides a high-speed burst mode laser driving circuit and method to solve the technical problem in the related art where the existing laser driving circuit uses an AC coupling capacitor connection between the laser and the laser, and adopts a series switch design for the burst control circuit. This results in large parasitic capacitance and resistance, which limits the working rate and response time of the driving signal output by the laser driving circuit and makes it difficult to meet the requirements of the 50G PON system architecture.

[0006] In a first aspect, a high-speed burst mode laser driving circuit is provided, including: an input adjustment circuit, an output driving circuit, and a burst control circuit;

[0007] The input adjustment circuit obtains the input differential voltage signal at its non-inverting input terminal and inverting input terminal, and the non-inverting output terminal and inverting output terminal of the input adjustment circuit are connected to the non-inverting input terminal and inverting input terminal of the output driving circuit, respectively.

[0008] The positive and negative output terminals of the output driving circuit are connected to the positive and negative terminals of the laser, respectively.

[0009] The burst control circuit includes an enable switching circuit and an enable control circuit. The input terminal of the enable switching circuit is used to acquire an external burst enable level signal, and the output terminal is connected to the input terminal of the enable control circuit. The output terminal of the enable control circuit is connected to the positive terminal of the laser.

[0010] The enable switching circuit is used to disconnect / connect the output terminal of the enable control circuit to ground according to the low / high state of the burst enable level signal, so as to turn the laser on / off.

[0011] In some embodiments, the enable control circuit includes a first NPN transistor, a first PNP transistor, a first resistor, and a second resistor;

[0012] The first end of the first resistor is connected to the positive terminal of the laser as the output terminal of the enable control circuit, the second end of the first resistor is connected to the collector of the first NPN transistor and the base of the first PNP transistor, and the emitter of the first NPN transistor is grounded.

[0013] The emitter of the first PNP transistor is connected to the power supply, the first end of the second resistor is connected to the base of the first NPN transistor, the collector of the first PNP transistor and the output terminal of the enable switching circuit, and the second end of the second resistor is grounded.

[0014] In some embodiments, the enable switching circuit includes an operational amplifier, a third resistor, a fourth resistor, and a fifth resistor;

[0015] The first end of the third resistor serves as the input terminal of the enable switching circuit, used to acquire an external burst enable level signal. The second end of the third resistor is connected to the first end of the fourth resistor and the non-inverting input terminal of the operational amplifier. The second end of the fourth resistor is grounded.

[0016] The first end of the fifth resistor is connected to the inverting input of the operational amplifier; the second end of the fifth resistor serves as the output of the enable switching circuit and is connected to the output of the operational amplifier and the base of the first NPN transistor.

[0017] In some embodiments, the enable switching circuit includes a second NPN transistor and a third NPN transistor, a first current source, a second current source, a sixth resistor, and a seventh resistor;

[0018] The first end of the sixth resistor is connected to the power supply, and the second end of the sixth resistor is connected to the collector of the second NPN transistor; the base of the second NPN transistor serves as the input terminal of the enable conversion circuit, used to acquire an external burst enable level signal; the emitter of the second NPN transistor is connected to the first end of the first current source and the base of the third NPN transistor, and the second end of the first current source is grounded.

[0019] The first end of the seventh resistor is connected to the power supply, and the second end of the seventh resistor is connected to the collector of the third NPN transistor. The emitter of the third NPN transistor serves as the output terminal of the enable conversion circuit and is connected to the first end of the second current source and the base of the first NPN transistor. The second end of the second current source is grounded.

[0020] In some embodiments, the enable control circuit includes a fourth NPN transistor and a fifth NPN transistor;

[0021] The collector of the fourth NPN transistor is connected to the positive terminal of the laser as the output terminal of the enable control circuit.

[0022] The base of the fourth NPN transistor is shorted to the base of the fifth NPN transistor and then connected to the input terminal of the enable control circuit and the output terminal of the enable conversion circuit.

[0023] The emitter of the fourth NPN transistor is connected to the collector of the fifth NPN transistor, and the emitter of the fifth NPN transistor is grounded.

[0024] In some embodiments, the input regulation circuit includes a first input coupling capacitor and a second input coupling capacitor, a first input resistor and a second input resistor, an input DC common-mode voltage generation circuit, an input buffer stage circuit, and an amplification stage circuit;

[0025] The first terminal of the first input coupling capacitor and the second input coupling capacitor are differential input terminals used to acquire the input differential voltage signal; the second terminal of the first input coupling capacitor is connected to the first terminal of the first input resistor and the non-inverting input terminal of the input buffer stage circuit.

[0026] The second terminal of the second input coupling capacitor is connected to the first terminal of the second input resistor and the inverting input terminal of the input buffer stage circuit;

[0027] The output terminal of the input DC common-mode voltage generating circuit is connected to the second terminal of the first input resistor and the second input resistor.

[0028] The non-inverting output terminal and the inverting output terminal of the input buffer stage circuit are connected to the non-inverting input terminal and the inverting input terminal of the amplifier stage circuit, respectively.

[0029] The non-inverting output terminal and the inverting output terminal of the amplifier stage circuit are connected to the non-inverting input terminal and the inverting input terminal of the output drive circuit, respectively.

[0030] In some embodiments, the input DC common-mode voltage generation circuit includes an eighth resistor, a ninth resistor, and a sixth NPN transistor;

[0031] The first end of the series connection between the eighth resistor and the ninth resistor is connected to the power supply, and the second end is connected to the collector and base of the sixth NPN transistor. The common terminal of the eighth resistor and the ninth resistor serves as the output terminal of the input DC common-mode voltage generation circuit and is connected to the second terminal of the first input resistor and the second input resistor. The emitter of the sixth NPN transistor is grounded.

[0032] In some embodiments, the output driving circuit includes multiple differential pair amplifier circuits, a first output resistor, and a second output resistor;

[0033] The first end of the first output resistor is connected to the power supply, and the second end is connected to the non-inverting output terminal of each of the differential pair amplifier circuits and the positive terminal of the laser.

[0034] The first end of the second output resistor is connected to the power supply, and the second end is connected to the inverting output terminal of each of the differential pair amplifier circuits and the negative terminal of the laser.

[0035] The non-inverting input and inverting input of each differential pair amplifier circuit are connected to the non-inverting output and inverting output of the amplifier stage circuit, respectively.

[0036] In some embodiments, each differential pair amplifier circuit includes a differential pair amplifier module, two bias MOSFETs for modulation current, a modulation current control signal generation module, a modulation current multiplexer, a modulation current bias voltage generation module, two bias MOSFETs for bias current, a bias current control signal generation module, a bias current multiplexer, and a bias current bias voltage generation module.

[0037] Secondly, a method for driving a high-speed burst-mode laser is provided, including the following steps:

[0038] The input of the enable switching circuit acquires an external burst enable level signal, and according to the low / high state of the external burst enable level signal, disconnects / connects the output of the enable control circuit to ground to turn the laser on / off.

[0039] The beneficial effects of the technical solution provided by this invention include:

[0040] This invention provides a high-speed burst-mode laser driving circuit and method. The circuit includes an input adjustment circuit, an output driving circuit, and a burst control circuit. The positive and negative output terminals of the output driving circuit are connected to the positive and negative terminals of the laser, respectively, achieving ultra-short-distance DC coupling between the laser driving circuit and the external laser. This eliminates the need for coupling capacitors and their parasitic parameters required by AC coupling, significantly improving the operating speed of the driving signal output by the laser driving circuit. Furthermore, the burst control circuit includes an enable conversion circuit and an enable control circuit. The output terminal of the enable control circuit is connected to the positive terminal of the laser. The enable conversion circuit disconnects / connects the output terminal of the enable control circuit to ground based on the low / high state of the burst enable signal, enabling rapid laser switching on and off. This achieves a fast burst response time on the order of nanoseconds, meeting the operating speed and response time requirements of 25 / 50Gbps uplink signal transmission for 50G PON. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 is a schematic diagram of a high-speed burst mode laser driving circuit provided in an embodiment of the present invention;

[0043] Figure 2 is another structural schematic diagram of a high-speed burst mode laser driving circuit provided in an embodiment of the present invention;

[0044] Figure 3a is a schematic diagram of an enable switching circuit provided in an embodiment of the present invention;

[0045] Figure 3b is another schematic diagram of the enable switching circuit provided in an embodiment of the present invention;

[0046] Figure 3c is another schematic diagram of the enable switching circuit provided in an embodiment of the present invention;

[0047] Figure 4a is a schematic diagram of an enable control circuit provided in an embodiment of the present invention;

[0048] Figure 4b is another schematic diagram of the enable control circuit provided in an embodiment of the present invention;

[0049] Figure 4c is another structural schematic diagram of the enable control circuit provided in an embodiment of the present invention;

[0050] Figure 4d is another schematic diagram of the enable control circuit provided in an embodiment of the present invention;

[0051] Figure 5a is a schematic diagram of an input DC common-mode voltage generation circuit provided in an embodiment of the present invention;

[0052] Figure 5b is another schematic diagram of the input DC common-mode voltage generation circuit provided in an embodiment of the present invention;

[0053] Figure 5c is a schematic diagram of the input DC common-mode voltage generation circuit provided in an embodiment of the present invention.

[0054] Figure 6a is a schematic diagram of the transient simulation results of the high-speed burst mode laser driving circuit provided in the embodiment of the present invention in burst mode;

[0055] Figure 6b is another schematic diagram of the transient simulation results of the high-speed burst mode laser driving circuit provided in the embodiment of the present invention in burst mode;

[0056] Figure 6c is another schematic diagram of the transient simulation results of the high-speed burst mode laser driving circuit provided in the embodiment of the present invention in burst mode;

[0057] Figure 6d is another schematic diagram of the transient simulation results of the high-speed burst mode laser driving circuit provided in the embodiment of the present invention in burst mode. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0059] This invention provides a high-speed burst mode laser driving circuit that solves the problems of existing laser driving circuit schemes: "(1) using AC coupling capacitors to connect with the laser; (2) using series switches to design the burst control circuit". The AC coupling capacitors, enable switches, etc., result in large parasitic capacitance and parasitic resistance, which in turn limit the working rate and response time of the driving signal output by the laser driving circuit, making it difficult to meet the requirements of the 50G PON system architecture.

[0060] Referring to Figure 1, an embodiment of the present invention provides a high-speed burst mode laser driving circuit, including: an input adjustment circuit, an output driving circuit, and a burst control circuit.

[0061] The non-inverting and inverting input terminals of the input adjustment circuit are connected to the input differential voltage signals Vinp and Vinn, respectively. The non-inverting and inverting output terminals of the input adjustment circuit are connected to the corresponding non-inverting and inverting input terminals of the output driving circuit. The input adjustment circuit is used to buffer and amplify the input differential voltage signal before outputting it to the output driving circuit.

[0062] The non-inverting and inverting output terminals of the output driving circuit are connected to the positive and negative terminals of the laser, respectively. The output driving circuit further amplifies the input differential voltage signal, which has been buffered and amplified by the input adjustment circuit, before outputting it to the laser. This further amplified input differential voltage signal provides sufficient output drive current to drive and modulate the laser to transmit optical signals.

[0063] The burst control circuit includes an enable switching circuit and an enable control circuit. The input terminal of the enable switching circuit is used to acquire an external burst enable level signal, and the output terminal is connected to the input terminal of the enable control circuit. The output terminal of the enable control circuit is connected to the positive terminal of the laser.

[0064] The enable switching circuit disconnects / connects the output terminal of the enable control circuit to ground based on the low / high state of the burst enable level signal, thereby turning the laser on / off. Specifically, the enable switching circuit converts the level of the external burst enable level signal into a signal level mode compatible with the operating state of the enable control circuit, and then disconnects / connects the output terminal of the enable control circuit to ground.

[0065] The laser driving circuit in this embodiment of the invention includes an input adjustment circuit, an output driving circuit, and a burst control circuit. The positive and negative output terminals of the output driving circuit are respectively connected to the positive and negative terminals of the laser, achieving ultra-short-distance DC coupling between the laser driving circuit and the external laser. This eliminates the need for coupling capacitors and their parasitic parameters required by AC coupling, significantly improving the operating speed of the driving signal output by the laser driving circuit. Furthermore, the burst control circuit of this invention includes an enable conversion circuit and an enable control circuit. The output terminal of the enable control circuit is connected to the positive terminal of the laser. The enable conversion circuit disconnects / connects the output terminal of the enable control circuit to ground based on the low / high state of the burst enable signal, enabling rapid laser switching on and off. This achieves a fast burst response time on the order of nanoseconds, meeting the operating speed and response time requirements of 25 / 50Gbps uplink signal transmission for 50G PON.

[0066] As an optional implementation, in one embodiment of the invention, referring to FIG2, the enable control circuit includes a first NPN transistor Q1, a first PNP transistor QP1, a first resistor R1, and a second resistor R2.

[0067] The first end of the first resistor R1 is connected to the positive terminal of the laser as the output terminal of the enable control circuit, and the second end is connected to the collector of the first NPN transistor Q1 and the base of the first PNP transistor QP1. The emitter of the first NPN transistor Q1 is grounded.

[0068] The emitter of the first PNP transistor QP1 is connected to the power supply. The first end of the second resistor R2 is connected to the base of the first NPN transistor Q1, the collector of the first PNP transistor QP1, and the output terminal of the enable switching circuit. The second end of the second resistor is grounded.

[0069] The main function of the first resistor R1 is to act as an isolation resistor to reduce the influence of the parasitic parameters of the first NPN transistor Q1 and the first PNP transistor QP1 on the bandwidth of the non-inverting output terminal outp of the output drive circuit, and to reduce the collector voltage of the first NPN transistor Q1 to prevent the first NPN transistor Q1 from being broken down. It is generally a small-value metal resistor with a current carrying capacity of up to 200mA and a width of about 100um, and the resistance value is generally 0 to 5Ω.

[0070] Furthermore, the enable switching circuit includes an operational amplifier U1, a third resistor R3, a fourth resistor R4, and a fifth resistor R5.

[0071] The first terminal of the third resistor R3 serves as the input terminal of the power conversion circuit, used to acquire the external burst enable signal BMEN. The second terminal of the third resistor R3 is connected to the first terminal of the fourth resistor R4 and the non-inverting input terminal of the operational amplifier U1, and the second terminal of the fourth resistor R4 is grounded. The third resistor R3 and the fourth resistor R4 together form a voltage divider.

[0072] The output voltage of the voltage divider = V(BMEN)×R4 / (R3+R4);

[0073] In the above formula, V(BMEN) is the voltage value of the burst enable level signal BMEN, and R3 and R4 represent the resistance values ​​of the third resistor R3 and the fourth resistor R4, respectively.

[0074] The first end of the fifth resistor R5 is connected to the inverting input of the operational amplifier U1; the second end of the fifth resistor R5 serves as the output of the enable switching circuit and is connected to the output of the operational amplifier U1 and the base of the first NPN transistor Q1.

[0075] Specifically, when the burst enable signal BMEN is low, the first NPN transistor Q1 is turned off, turning on the laser; when the burst enable signal BMEN is high, the first NPN transistor Q1 is turned on, turning off the laser.

[0076] As an optional implementation, in one embodiment of the invention, referring to Figures 1 and 2, the input adjustment circuit includes a first input coupling capacitor C1 and a second input coupling capacitor C2, a first input resistor R1P and a second input resistor R1N, an input DC common-mode voltage generation circuit, an input buffer stage circuit, and an amplification stage circuit.

[0077] The first terminal of the first input coupling capacitor C1 and the second input coupling capacitor C2 are differential input terminals used to obtain the input differential voltage signal. The second terminal of the first input coupling capacitor C1 is connected to the first terminal of the first input resistor R1P and the non-inverting input terminal of the input buffer stage circuit.

[0078] The second terminal of the second input coupling capacitor C2 is connected to the first terminal of the second input resistor R1N and the inverting input terminal of the input buffer stage circuit.

[0079] The output terminal of the input DC common-mode voltage generating circuit is connected to the second terminal of the first input resistor and the second input resistor. The non-inverting output terminal and the inverting output terminal of the input buffer stage circuit are connected to the non-inverting input terminal and the inverting input terminal of the amplifier stage circuit, respectively. The non-inverting output terminal and the inverting output terminal of the amplifier stage circuit are connected to the non-inverting input terminal and the inverting input terminal of the output drive circuit, respectively.

[0080] The amplification stage circuit pre-amplifies the amplitudes of the input differential voltage signals Vinp and Vinn. The input buffer stage circuit isolates the equivalent input impedance and capacitance of the amplification stage circuit from the input differential voltage signals Vinp and Vinn, thus preventing degradation of the signal quality of Vinp and Vinn.

[0081] The first input coupling capacitor C1 and the second input coupling capacitor C2 isolate the DC state of the input differential voltage signals Vinp and Vinn from the DC state of the input buffer stage circuit, preventing the input buffer stage circuit from affecting the quality of the input differential voltage signals Vinp and Vinn. The first input resistor R1P and the second input resistor R1N serve as input impedance matching resistors, matching the impedance to the output impedance of the circuit providing the input differential voltage signals Vinp and Vinn. The first input resistor R1P and the second input resistor R1N can be designed to be 50Ω ± 20%. The input DC common-mode voltage generation circuit provides a DC bias voltage to the input buffer stage circuit, ensuring that the input buffer stage circuit is in normal operating condition.

[0082] Further, referring to Figure 5a, the input DC common-mode voltage generating circuit includes an eighth resistor R8, a ninth resistor R9, and a sixth NPN transistor Q6.

[0083] The first end of the series connection between the eighth resistor R8 and the ninth resistor R9 is connected to the power supply, and the second end is connected to the collector and base of the sixth NPN transistor Q6. The common terminal of the eighth resistor R8 and the ninth resistor R9 serves as the output terminal of the input DC common-mode voltage generation circuit, providing the input DC common-mode voltage. It is connected to the second end of the first input resistor R1P and the second input resistor R1N. The emitter of the sixth NPN transistor Q6 is grounded.

[0084] Referring to Figure 5b, the input DC common-mode voltage generation circuit may include an eleventh NPN transistor Q11, a twelfth NPN transistor Q12, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, and a first PMOS transistor MP1. The source of the first PMOS transistor MP1 is connected to the power supply, the gate of the first PMOS transistor MP1 is connected to the external input bias voltage VBP1, the drain of the first PMOS transistor MP1 is connected to the first terminal of the sixteenth resistor R16, the base and collector of the twelfth NPN transistor Q12 are shorted and then connected to the second terminal of the sixteenth resistor R16 and the base of the eleventh NPN transistor Q11, and the emitter of the twelfth NPN transistor Q12 is grounded. The twelfth NPN transistor Q12 forms a diode and provides a bias voltage to the base of the eleventh NPN transistor Q11. The emitter of the eleventh NPN transistor Q11 is grounded, and the collector of the eleventh NPN transistor Q11 is connected to the first terminal of the fourteenth resistor R14. The second terminal of the fourteenth resistor R14 is connected to the first terminal of the fifteenth resistor R15 and serves as the output terminal of the input DC common-mode voltage generation circuit, providing the input DC common-mode voltage. The second terminal of the fifteenth resistor R15 is connected to the power supply.

[0085] Referring to Figure 5c, the input DC common-mode voltage generation circuit may include a thirteenth NPN transistor Q13, a seventeenth resistor R17, and a second PMOS transistor MP2. The source of the second PMOS transistor MP2 is connected to the power supply, its gate is connected to the external input bias voltage VBP2, and its drain is connected to the first terminal of the seventeenth resistor R17, serving as the output terminal of the input DC common-mode voltage generation circuit to provide the input DC common-mode voltage. The base and collector of the thirteenth NPN transistor Q13 are shorted and connected to the second terminal of the seventeenth resistor R17. The emitter of the thirteenth NPN transistor Q13 is grounded, thus forming a diode.

[0086] As an optional implementation, in one embodiment of the invention, referring to Figures 1 and 2, the output driving circuit includes multiple differential pair amplifier circuits, a first output resistor R2P, and a second output resistor R2N.

[0087] The first output resistor R2P has its first terminal connected to the power supply and its second terminal connected to the non-inverting output terminal of each differential pair amplifier circuit and the positive terminal of the laser. The second output resistor R2N has its first terminal connected to the power supply and its second terminal connected to the inverting output terminal of each differential pair amplifier circuit and the negative terminal of the laser. The non-inverting and inverting input terminals of each differential pair amplifier circuit are connected to the corresponding non-inverting and inverting output terminals of the amplifier stage circuit. The use of multiple parallel differential pair amplifier circuits increases the available output drive current.

[0088] Further, referring to Figures 1 and 2, each of the differential pair amplifier circuits includes a differential pair amplifier module, two bias MOS transistors for modulation current (a first bias MOS transistor for modulation current and a second bias MOS transistor for modulation current), a modulation current control signal generation module, a modulation current multiplexer, a modulation current bias voltage generation module, two bias MOS transistors for bias current, a bias current control signal generation module, a bias current multiplexer, and a bias current bias voltage generation module;

[0089] The non-inverting and inverting input terminals of the differential pair amplifier module are connected to the non-inverting and inverting output terminals of the amplifier stage circuit, respectively. The non-inverting and inverting output terminals of the differential pair amplifier module are connected to the positive and negative terminals of the laser, respectively.

[0090] The output terminal of the modulation current control signal generation module is connected to the control signal input terminal of the modulation current multiplexer. The output terminal of the modulation current bias voltage generation module is connected to the first transmission signal input terminal of the modulation current multiplexer. The output terminal of the modulation current multiplexer is connected to the gate of the first modulation current bias MOS transistor. The drain of the first modulation current bias MOS transistor is connected to the gate of the second modulation current bias MOS transistor and serves as the modulation current output terminal, which is connected to the bias current input terminal IB of the differential pair amplifier module.

[0091] The output terminal of the bias current control signal generation module is connected to the control signal input terminal of the bias current multiplexer. The bias current bias voltage generation module is connected to the first transmission signal input terminal of the bias current multiplexer. The output terminal of the bias current multiplexer is connected to the gate of the bias MOS transistor of the first bias current. The drain of the bias MOS transistor of the first bias current is connected to the gate of the bias MOS transistor of the second bias current as the bias current output terminal, which is connected to the bias current input terminal IB of the differential pair amplifier module.

[0092] In this circuit, the modulation current control signal generation module and the bias current control signal generation module of each differential pair amplifier circuit can each be integrated into a single module, requiring only the provision of multiple corresponding output terminals. Similarly, the modulation current bias voltage generation module and the bias current bias voltage generation module of each differential pair amplifier circuit can each be integrated into a single module, requiring only the provision of one corresponding output terminal. The first output resistor R2P and the second output resistor R2N can be designed to be 25Ω ± 10%.

[0093] Referring to Figure 2, taking the differential pair amplifier module 11 as an example, the bias current input port IB of the differential pair amplifier module 11 is connected to the drain of the first modulation current bias MOSFET MM11S and the gate of the second modulation current bias MOSFET MM11, respectively. The drain of the second modulation current bias MOSFET MM11 is connected to the source of the first modulation current bias MOSFET MM11S, and the source of the second modulation current bias MOSFET MM11 is grounded. The gate of the first modulation current bias MOSFET MM11S is connected to the output terminal of the modulation current multiplexer MUX_M1.

[0094] The output terminal VM1 of the modulation current control signal generation module is connected to the control signal input terminal of the modulation current multiplexer MUX_M1. The output terminal of the modulation current bias voltage generation module is also connected to the first transmission signal input terminal of the modulation current multiplexers MUX_M1, MUX_M2, ..., MUX_MN. The second transmission signal input terminals of the modulation current multiplexers MUX_M1, MUX_M2, ..., MUX_MN are all grounded.

[0095] The bias current input port IB of the differential pair amplifier module 11 is also connected to the drain of the first bias current bias MOSFET MB11S and the gate of the second bias current bias MOSFET MB11, respectively. The drain of the second bias current bias MOSFET MB11 is connected to the source of the first bias current bias MOSFET MB11S, and the source of the second bias current bias MOSFET MB11 is grounded. The gate of the first bias current bias MOSFET MB11S is connected to the output of the bias current multiplexer MUX_B1.

[0096] The output terminal VB1 of the bias current control signal generation module is connected to the control signal input terminal of the modulation current multiplexer MUX_B1. The output terminal of the bias current and bias voltage generation module is connected to the first transmission signal input terminal of the bias current multiplexers MUX_B1, MUX_B2, ..., MUX_BN. The second transmission signal input terminals of the bias current multiplexers MUX_B1, MUX_B2, ..., MUX_BN are all grounded.

[0097] For the modulated current multiplexers MUX_M1, MUX_M2, ..., MUX_MN and the bias current multiplexers MUX_B1, MUX_B2, ..., MUX_BN, when the level of their control signal input terminal is high (low), the signal at the first transmission signal input terminal is selected as the output signal; when the level of their control signal input terminal is low (high), the signal at the second transmission signal input terminal is selected as the output signal.

[0098] Figures 6a-6d are schematic diagrams of the transient simulation results of the high-speed burst mode laser driving circuit shown in Figure 2 in burst mode.

[0099] Figure 6a shows the transient simulation results of the input voltage signal, output voltage signal, and output drive current signal of the laser driver circuit in burst mode. The simulation duration is 900 ns, and the operating speed is 25 Gbps. In Figure 6a, / Vinp and / Vinn are the input differential voltage signals, with / Vinp being a solid line and / Vinn being a dashed line; / inp and / inn are a pair of input differential voltage signals provided to the input buffer stage circuit after passing through the first input coupling capacitor C1 and the second input coupling capacitor C2 inside the laser driver circuit, with / inp being a solid line and / inn being a dashed line; / outp and / outn are the output differential voltage signals of the laser driver circuit, with / outp being a solid line and / outn being a dashed line; / BMEN is the external output voltage signal. When the burst enable signal BMEN is low, the first NPN transistor Q1 is turned off, opening the channel to provide bias current and modulation current signals to the external laser, i.e., the laser driver circuit turns on the laser. When the burst enable signal BMEN is high, the first NPN transistor Q1 is turned on, closing the channel to provide bias current and modulation current signals to the external laser, i.e., the laser driver circuit turns off the laser. / D1 / A is the drive current signal flowing through the external laser D1.

[0100] Figure 6b shows the changes in the output differential voltage signal of the laser driver circuit and the drive current signal flowing through the external laser D1 during the transient interval from 509ns to 519ns, as / BMEN abruptly changes from low to high. As shown in Figure 6b, when / BMEN rapidly changes from low to high, the output differential voltage signal of the laser driver circuit and the drive current signal flowing through the external laser D1 also change rapidly with / BMEN. / outp and / outn quickly change from the voltage difference state maintaining the external laser D1 on ( / outp approximately 2.6655V, / outn approximately 2.2044V) to the low voltage state where the external laser D1 is off ( / outp approximately 601mV, / outn approximately 508mV). The drive current signal / D1 / A also rapidly switches from a modulation signal state of approximately 60mA to 150mA with / BMEN to a zero value. The response settling time for this sudden change is approximately 3.55ns.

[0101] Figure 6c shows the changes in the output differential voltage signal of the laser driver circuit and the drive current signal flowing through the external laser D1 during the transient interval from 560ns to 570ns, as / BMEN abruptly changes from high to low. As shown in Figure 6c, when / BMEN rapidly changes from high to low, the output differential voltage signal of the laser driver circuit and the drive current signal flowing through the external laser D1 also change rapidly with / BMEN. / outp and / outn quickly change from a low voltage state ( / outp approximately 596mV, / outn approximately 559mV) maintaining the external laser D1 off to a voltage difference state ( / outp approximately 2.6655V, / outn approximately 2.2044V) maintaining the external laser D1 on. The drive current signal / D1 / A also rapidly switches from zero to a modulation signal state of approximately 60mA~150mA with / BMEN. The response settling time for this sudden change is approximately 4.29ns.

[0102] Figure 6d shows the superimposed eye diagram of the laser drive current signal / D1 / A output by the laser drive circuit in the transient range of 570ns to 900ns after / BMEN abruptly changes from high to low, and the drive current signal / D1 / A flowing through the external laser D1 stabilizes at a modulation signal state of approximately 60mA~150mA. As shown in Figure 6d, the eye diagram jitter is approximately 2.13ps, the equivalent bias current is approximately 104mA, and the equivalent modulation current is approximately 93.36mA. pp .

[0103] In summary, the laser driver circuit in this embodiment of the invention achieves ultra-short-distance DC coupling between the laser driver chip and the external laser. This not only significantly improves the operating rate of the drive signal output by the laser driver circuit, but also enables the laser to be turned on and off quickly, achieving a fast burst response time on the order of nanoseconds, thus meeting the uplink signal transmission requirements of the 50GPON system architecture.

[0104] As an optional implementation, in one embodiment of the invention, referring to FIG3a, the enable switching circuit includes a second NPN transistor Q2 and a third NPN transistor Q3, a first current source IB1, a second current source IB2, a sixth resistor R6, and a seventh resistor R7.

[0105] The first end of the sixth resistor R6 is connected to the power supply, and the second end of the sixth resistor R6 is connected to the collector of the second NPN transistor Q2; the base of the second NPN transistor Q2 serves as the input terminal of the enable switching circuit, used to acquire the external burst enable level signal BMEN; the emitter of the second NPN transistor Q2 is connected to the first end of the first current source IB1 and the base of the third NPN transistor Q3, and the second end of the first current source IB1 is grounded.

[0106] The first end of the seventh resistor R7 is connected to the power supply, the second end of the seventh resistor R7 is connected to the collector of the third NPN transistor Q3, the emitter of the third NPN transistor Q3 serves as the output terminal of the enable switching circuit, and is connected to the first end of the second current source IB2 and the base of the first NPN transistor Q1, and the second end of the second current source IB2 is grounded.

[0107] As an optional implementation, in one embodiment of the invention, referring to Figure 3b, the enable switching circuit can replace the operational amplifier U1 and the fifth resistor R5 in Figure 2 with a first inverter, a second inverter, a bandgap reference voltage generation circuit, and a voltage regulator. The input terminal of the first inverter is connected to the common terminal of the third resistor R3 and the fourth resistor R4, and the output terminal of the first inverter is connected to the input terminal of the second inverter. The output terminal of the second inverter is connected to the base of the first NPN transistor Q1. The power input terminals of the first and second inverters are connected to the output power supply terminal of the voltage regulator. The input reference voltage of the voltage regulator is the reference voltage VBG output by the bandgap reference voltage generation circuit. The function of the voltage regulator is to provide power to the first and second inverters.

[0108] As an optional implementation, in one embodiment of the invention, referring to FIG3c, the enable switching circuit includes a first NMOS transistor NM1, a second NMOS transistor NM2, a third current source IB3, a fourth current source IB4, a tenth resistor R10, and an eleventh resistor R11. The gate of the first NMOS transistor NM1 serves as the input terminal of the enable switching circuit, used to acquire an external burst enable level signal BMEN. The drain of the first NMOS transistor NM1 is connected to the first terminal of the tenth resistor R10, and the second terminal of the tenth resistor R10 is connected to a power supply. The source of the first NMOS transistor NM1 is connected to the gate of the second NMOS transistor NM2 and the first terminal of the third current source IB3, and the second terminal of the third current source IB3 is grounded. The drain of the second NMOS transistor NM2 is connected to the first terminal of the eleventh resistor R11, and the second terminal of the eleventh resistor R11 is connected to a power supply. The source of the second NMOS transistor NM2 is the output terminal of the enable switching circuit and is connected to the first terminal of the fourth current source IB4, and the second terminal of the fourth current source IB4 is grounded.

[0109] As an optional implementation, in one embodiment of the invention, referring to FIG4a, the enable control circuit includes a fourth NPN transistor Q4 and a fifth NPN transistor Q5.

[0110] The collector of the fourth NPN transistor Q4 serves as the output of the enable control circuit and is connected to the positive terminal of the laser. The base of the fourth NPN transistor Q4 is connected to the base of the fifth NPN transistor Q5 and serves as the input of the enable control circuit, which is connected to the output of the enable switching circuit. The emitter of the fourth NPN transistor Q4 is connected to the collector of the fifth NPN transistor Q5, and the emitter of the fifth NPN transistor Q5 is grounded. Compared with the enable control circuit shown in Figure 2, the enable control circuit shown in Figure 4a has stronger breakdown resistance.

[0111] As an optional implementation, in one embodiment of the invention, referring to Figure 4b, the enable control circuit includes a seventh NPN transistor Q7 and an eighth NPN transistor Q8. The base of the seventh NPN transistor Q7 is shorted to the base of the eighth NPN transistor Q8, serving as the input terminal of the enable control circuit. The emitter of the seventh NPN transistor Q7 is grounded, the emitter of the eighth NPN transistor Q8 is grounded, and the collector of the seventh NPN transistor Q7 is shorted to the collector of the eighth NPN transistor Q8, serving as the output terminal of the enable control circuit, which is connected to the positive terminal of the laser. Compared to the enable control circuit shown in Figure 2, the enable control circuit shown in Figure 4b has a stronger overcurrent capability.

[0112] As an optional implementation, in one embodiment of the invention, referring to Figure 4c, the enable control circuit includes a ninth NPN transistor Q9, a twelfth resistor R12, and a thirteenth resistor R13. The base of the ninth NPN transistor Q9 is the input terminal of the enable control circuit. The emitter of the ninth NPN transistor Q9 is connected to the first terminal of the twelfth resistor R12, and the second terminal of the twelfth resistor R12 is grounded. The collector of the ninth NPN transistor Q9 is connected to the first terminal of the thirteenth resistor R13; the second terminal of the thirteenth resistor R13 serves as the output terminal of the enable control circuit and is connected to the positive terminal of the laser. The main function of the thirteenth resistor R13 is to act as an isolation resistor to reduce the influence of the parasitic parameters of the ninth NPN transistor Q9 on the bandwidth of the non-inverting output terminal (outp) of the laser driver circuit, and to reduce the collector voltage of the ninth NPN transistor Q9, preventing the ninth NPN transistor Q9 from being broken down. It is a small-value metal resistor with a current carrying capacity of up to 200mA and a width of approximately 100um, and its resistance is typically 0 to 5Ω. The main function of the twelfth resistor R12 is to reduce the voltage difference between the base and emitter of the ninth NPN transistor Q9, so as to prevent the ninth NPN transistor Q9 from being broken down. Its overcurrent capability needs to reach 200mA, and its resistance value is generally 0 to 5Ω.

[0113] Figure 4d shows a simplified version of the enable control circuit, which only has the tenth NPN transistor Q10. The base of the tenth NPN transistor Q10 serves as the input terminal of the enable control circuit, and the emitter of the tenth NPN transistor Q10 is grounded. The collector of the tenth NPN transistor Q10 serves as the output terminal of the enable control circuit and is connected to the positive terminal of the laser.

[0114] This invention also provides a method for driving a high-speed burst-mode laser, comprising the following steps:

[0115] The input of the enable switching circuit acquires an external burst enable level signal, and according to the low / high state of the external burst enable level signal, disconnects / connects the output of the enable control circuit to ground to turn the laser on / off.

[0116] In the description of this invention, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two elements. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.

[0117] It should be noted that in this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0118] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A high-speed burst-mode laser driving circuit, characterized in that, include: Input regulation circuit, output drive circuit, and burst control circuit; The input adjustment circuit acquires input differential voltage signals at its non-inverting and inverting input terminals, and its non-inverting and inverting output terminals are connected to the corresponding non-inverting and inverting input terminals of the output drive circuit. The output drive circuit's non-inverting and inverting output terminals are connected to the corresponding positive and negative terminals of the laser. The burst control circuit includes an enable switching circuit and an enable control circuit. The enable switching circuit's input terminal acquires an external burst enable level signal, and its output terminal is connected to the input terminal of the enable control circuit. The enable control circuit's output terminal is connected to the positive terminal of the laser. The enable switching circuit adjusts the enable control circuit according to the low / high state of the burst enable level signal. The output terminal of the circuit is disconnected / connected to ground to turn the laser on / off. The enable control circuit includes a first NPN transistor, a first PNP transistor, a first resistor, and a second resistor. The first terminal of the first resistor serves as the output terminal of the enable control circuit and is connected to the positive terminal of the laser. The second terminal of the first resistor is connected to the collector of the first NPN transistor and the base of the first PNP transistor. The emitter of the first NPN transistor is grounded. The emitter of the first PNP transistor is connected to the power supply. The first terminal of the second resistor is connected to the base of the first NPN transistor, the collector of the first PNP transistor, and the output terminal of the enable control circuit. The second terminal of the second resistor is connected to... Alternatively, the enable control circuit includes a fourth NPN transistor and a fifth NPN transistor; the collector of the fourth NPN transistor is connected to the positive terminal of the laser as the output terminal of the enable control circuit; the base of the fourth NPN transistor is shorted to the base of the fifth NPN transistor and then connected to the output terminal of the enable conversion circuit as the input terminal of the enable control circuit; the emitter of the fourth NPN transistor is connected to the collector of the fifth NPN transistor, and the emitter of the fifth NPN transistor is grounded; the enable conversion circuit includes an operational amplifier, a third resistor, a fourth resistor, and a fifth resistor; the first terminal of the third resistor serves as the input terminal of the enable conversion circuit, used to obtain... An external burst enable signal is received. The second terminal of the third resistor is connected to the first terminal of the fourth resistor and the non-inverting input terminal of the operational amplifier, and the second terminal of the fourth resistor is grounded. The first terminal of the fifth resistor is connected to the inverting input terminal of the operational amplifier. The second terminal of the fifth resistor serves as the output terminal of the enable switching circuit and is connected to the output terminal of the operational amplifier and the base of the first NPN transistor. Alternatively, the enable switching circuit includes a second NPN transistor and a third NPN transistor, a first current source, a second current source, a sixth resistor, and a seventh resistor. The first terminal of the sixth resistor is connected to the power supply, and the second terminal of the sixth resistor is connected to the collector of the second NPN transistor.The base of the second NPN transistor serves as the input terminal of the enable switching circuit, used to acquire an external burst enable level signal; the emitter of the second NPN transistor is connected to the first terminal of the first current source and the base of the third NPN transistor, and the second terminal of the first current source is grounded; the first terminal of the seventh resistor is connected to the power supply, and the second terminal of the seventh resistor is connected to the collector of the third NPN transistor; the emitter of the third NPN transistor serves as the output terminal of the enable switching circuit, connected to the first terminal of the second current source and the base of the first NPN transistor, and the second terminal of the second current source is grounded.

2. The high-speed burst mode laser driving circuit according to claim 1, characterized in that: The input regulation circuit includes a first input coupling capacitor and a second input coupling capacitor, a first input resistor and a second input resistor, an input DC common-mode voltage generation circuit, an input buffer stage circuit and an amplification stage circuit; The first terminal of the first input coupling capacitor and the second input coupling capacitor are differential input terminals, used to acquire the input differential voltage signal; The second end of the first input coupling capacitor is connected to the first end of the first input resistor and the non-inverting input terminal of the input buffer stage circuit; The second terminal of the second input coupling capacitor is connected to the first terminal of the second input resistor and the inverting input terminal of the input buffer stage circuit; the output terminal of the input DC common-mode voltage generating circuit is connected to the second terminals of the first input resistor and the second input resistor; the non-inverting output terminal and the inverting output terminal of the input buffer stage circuit are connected to the non-inverting input terminal and the inverting input terminal of the amplifier stage circuit, respectively; the non-inverting output terminal and the inverting output terminal of the amplifier stage circuit are connected to the non-inverting input terminal and the inverting input terminal of the output driving circuit, respectively.

3. The high-speed burst mode laser driving circuit according to claim 2, characterized in that: The input DC common-mode voltage generating circuit includes an eighth resistor, a ninth resistor, and a sixth NPN transistor; the first end of the series connection between the eighth resistor and the ninth resistor is connected to the power supply, and the second end is connected to the collector and base of the sixth NPN transistor; the common terminal of the eighth resistor and the ninth resistor serves as the output terminal of the input DC common-mode voltage generating circuit and is connected to the second end of the first input resistor and the second input resistor; the emitter of the sixth NPN transistor is grounded.

4. The high-speed burst mode laser driving circuit according to claim 2, characterized in that: The output driving circuit includes multiple differential pair amplifier circuits, a first output resistor, and a second output resistor. The first end of the first output resistor is connected to a power supply, and the second end is connected to the non-inverting output terminal of each differential pair amplifier circuit and the positive terminal of the laser. The first end of the second output resistor is connected to a power supply, and the second end is connected to the inverting output terminal of each differential pair amplifier circuit and the negative terminal of the laser. The non-inverting input terminal and the inverting input terminal of each differential pair amplifier circuit are connected to the non-inverting output terminal and the inverting output terminal of the amplifier stage circuit, respectively.

5. The high-speed burst mode laser driving circuit according to claim 4, characterized in that: Each differential pair amplifier circuit includes a differential pair amplifier module, two bias MOSFETs for modulation current, a modulation current control signal generation module, a modulation current multiplexer, a modulation current bias voltage generation module, two bias MOSFETs for bias current, a bias current control signal generation module, a bias current multiplexer, and a bias current bias voltage generation module.

6. A method for driving a high-speed burst-mode laser, using the high-speed burst-mode laser driving circuit according to any one of claims 1-5, characterized in that, Includes the following steps: The input of the enable switching circuit acquires an external burst enable level signal, and according to the low / high state of the external burst enable level signal, disconnects / connects the output of the enable control circuit to ground to turn the laser on / off.

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