Silicon carbide-based finfet power device and preparation method and chip thereof

Abstract

The application belongs to the technical field of semiconductors, and provides a silicon carbide-based FINFET power device and a preparation method and a chip thereof, wherein an N-type drift layer and a P-type switch isolation layer are epitaxially grown on the front surface of a silicon carbide substrate in sequence, the P-type switch isolation layer is divided into a first switch isolation area and a second switch isolation area by a voltage channel layer, a current diffusion layer is formed on the voltage channel layer, a first source doped layer, a second source doped layer, a plurality of isolation structures and a plurality of gate channel structures are formed on both sides of the current diffusion layer, a gate metal layer is formed on the gate channel structure, a plurality of current channels are obtained by the gate metal layer and the gate channel structure of the fin structure to reach the source, and a Schottky metal layer is formed on the current diffusion layer, so that a Schottky diode is integrated in the device at the lowest cost and chip area, and the switching speed and reliability of the silicon carbide-based FINFET power device are improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductors, and particularly relates to a silicon carbide-based FINFET power device and a preparation method and chip thereof. BACKGROUND

[0002] The breakdown voltage (BV) of a power transistor is a very important parameter. In order to increase the BV of the power transistor and save the chip area, the power transistor is converted from a planar structure to a vertical structure. Pursuing high breakdown voltage, high current density and small device area is still the further development direction of the power transistor. The vertical FinFET power device is widely concerned due to its advantages of high current density, high withstand voltage and small chip area.

[0003] However, in the vertical FinFET power device, the surge current generated by the device turn-off is usually discharged by a parasitic diode in the device, and the parasitic diode is relatively fragile, which has a great negative impact on the reliability of the device. SUMMARY

[0004] In order to solve the above technical problems, the application provides a silicon carbide-based FINFET power device and a preparation method and chip thereof, aiming at solving the problem that the parasitic diode in the vertical FinFET power device is relatively fragile, resulting in a decrease in the reliability of the device.

[0005] The first aspect of the application provides a preparation method of a silicon carbide-based FINFET power device, and the preparation method comprises the following steps:

[0006] An N-type drift layer and a P-type switch isolation layer are epitaxially grown on the front surface of a silicon carbide substrate in sequence;

[0007] A specified region of the P-type switch isolation layer is doped with N-type to form a voltage channel layer, so as to divide the P-type switch isolation layer into a first switch isolation region and a second switch isolation region;

[0008] A current diffusion layer is formed on the voltage channel layer, and a first source doped layer, a second source doped layer, a plurality of isolation structures and a plurality of gate region channel structures are formed on both sides of the current diffusion layer; wherein the first source doped layer is located on the first switch isolation region and connected to the current diffusion layer through the gate region channel structure, and the second source doped layer is located on the second switch isolation region and connected to the current diffusion layer through the gate region channel structure;

[0009] A gate metal layer is formed on the gate region channel structure; wherein the gate metal layer is insulated from the gate region channel structure;

[0010] forming a Schottky metal layer on the current diffusion layer; wherein a Schottky contact is formed between the Schottky metal layer and the current diffusion layer;

[0011] forming a drain metal layer on the back surface of the silicon carbide substrate.

[0012] In one embodiment, the forming a Schottky metal layer on the current diffusion layer comprises:

[0013] depositing a Schottky metal material on the current diffusion layer, and performing etching treatment on the Schottky metal material to form a first Schottky metal region and a second Schottky metal region which are not in contact with each other; wherein the first Schottky metal region is in contact with the gate channel structure close to the first source doped layer, and the second Schottky metal region is in contact with the gate channel structure close to the second source doped layer.

[0014] In one embodiment, the first Schottky metal region and the second Schottky metal region are arranged in parallel, and the length of the first Schottky metal region and the second Schottky metal region is the same.

[0015] In one embodiment, the width of the first Schottky metal region and the second Schottky metal region is the same.

[0016] In one embodiment, the gap width between the first Schottky metal region and the second Schottky metal region is greater than the width of the first Schottky metal region and the second Schottky metal region.

[0017] In one embodiment, the forming a current diffusion layer on the voltage channel layer, and forming a first source doped layer, a second source doped layer, a plurality of isolation structures and a plurality of gate channel structures on both sides of the current diffusion layer comprises:

[0018] epitaxially growing an N-type epitaxial layer on the voltage channel layer and the P-type switch isolation layer;

[0019] performing etching on a first preset etching area on the N-type epitaxial layer to form a plurality of first etching deep grooves and a plurality of first gate channel structures, and performing etching on a second preset etching area on the N-type epitaxial layer to form a plurality of second etching deep grooves and a plurality of second gate channel structures, so as to form the current diffusion layer, the first source doped layer and the second source doped layer on the voltage channel layer; wherein the first source doped layer and the current diffusion layer are located on both sides of the first gate channel structure, and the second source doped layer and the current diffusion layer are located on both sides of the second gate channel structure.

[0020] In one embodiment, the forming the current diffusion layer on the voltage channel layer, and forming the first source doped layer, the second source doped layer, the plurality of isolation structures and the plurality of gate channel structures on both sides of the current diffusion layer, further comprises:

[0021] depositing P-type semiconductor material in the first etching deep groove to form the first isolation structure;

[0022] depositing P-type semiconductor material in the second etching deep groove to form the second isolation structure.

[0023] In one embodiment, the current diffusion layer, the first source doped layer and the second source doped layer are arranged in parallel. The second aspect of the embodiment of the application further provides a silicon carbide-based FINFET power device prepared by using the preparation method of any one of the above.

[0024] The third aspect of the embodiment of the application further provides a chip, in which a vertical transistor prepared by using the preparation method of any one of the above is integrated.

[0025] Compared with the prior art, the embodiment of the application has the beneficial effects that: by sequentially epitaxially growing the N-type drift layer and the P-type switch isolation layer on the front surface of the silicon carbide substrate, the P-type switch isolation layer is divided into the first switch isolation region and the second switch isolation region by the voltage channel layer, the current diffusion layer is formed on the voltage channel layer, and the first source doped layer, the second source doped layer, the plurality of isolation structures and the plurality of gate channel structures are formed on both sides of the current diffusion layer, the gate metal layer is formed on the gate channel structure of the fin structure, a plurality of current channels reaching the source are obtained through the gate metal layer and the gate channel structure of the fin structure, and the Schottky metal layer is formed on the current diffusion layer, so that the Schottky diode is integrated in the device at the lowest cost and chip area, and the switching speed and reliability of the silicon carbide-based FINFET power device are improved. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is a flowchart of the preparation method of the vertical transistor provided by one embodiment of the application;

[0027] Figure 2 is a schematic diagram of forming the N-type drift layer 200 and the P-type switch isolation layer 300;

[0028] Figure 3 is a schematic diagram of forming the voltage channel layer 210;

[0029] Figure 4 is a schematic diagram of forming the current diffusion layer 830;

[0030] Figure 5 is a flowchart diagram of step S30 provided by one embodiment of the present application;

[0031] Figure 6 is a schematic diagram of an epitaxial growth process of the voltage channel layer 210 and the P-type switch isolation layer provided by one embodiment of the present application;

[0032] Figure 7 is a schematic diagram of forming the first isolation structure 312 and the second isolation structure 322 provided by one embodiment of the present application;

[0033] Figure 8 is another flowchart diagram of step S30 provided by one embodiment of the present application;

[0034] Figure 9 is a first structure schematic diagram of a vertical transistor provided by one embodiment of the present application;

[0035] Figure 10 is a first current schematic diagram of a vertical transistor provided by one embodiment of the present application;

[0036] Figure 11 is a first structure schematic diagram of a vertical transistor provided by one embodiment of the present application;

[0037] Figure 12 is a second current schematic diagram of a vertical transistor provided by one embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the technical problems to be solved by the present application, technical solutions and beneficial effects clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application.

[0039] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0040] It should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0041] Furthermore, the terms "first", "second", etc. are used herein only to describe different instances, and do not imply or suggest relative importance or a number of the technical features indicated. Thus, the features defined with "first", "second", etc. can include one or more of the features explicitly or implicitly. In the description of the present application, the meaning of "a plurality" is one or more than one, unless otherwise specifically limited.

[0042] The description of "one embodiment", "some embodiments" or "an embodiment" in the present application description means that the specific features, structures or characteristics described in connection with the embodiment are included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in other some embodiments", "in further some embodiments", "in a specific embodiment", "in a specific application", etc. appearing in different places in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized. In addition, in one or more embodiments, the specific features, structures or characteristics can be combined in any suitable manner.

[0043] The BV of a power transistor is a very important parameter. In order to increase the BV while saving chip area, the power transistor is converted from a planar structure to a vertical structure. Since the invention of fin-shaped transistors (FINFET), fin-shaped transistors have successfully verified the feasibility of CMOS process on 14nm process, and even 3-5nm process. However, in the vertical FinFET power device, the surge current generated by the device turn-off is usually discharged by the parasitic diode in the device, and the parasitic diode is relatively fragile, which has a great negative impact on the reliability of the device. In order to solve the above technical problems, the present application provides a preparation method of a silicon carbide-based FINFET power device, as shown in Figure 1 The preparation method includes steps S10 to S50.

[0044] In combination with Figure 2 As shown in the figure, in step S10, an N-type drift layer 200 and a P-type switch isolation layer 300 are sequentially epitaxially grown on the front surface of a silicon carbide substrate 100.

[0045] In the present embodiment, the N-type drift layer 200 is formed on the front surface of the silicon carbide substrate 100, and the P-type switch isolation layer 300 is formed on the surface of the N-type drift layer 200. The silicon carbide substrate 100 is an N-type semiconductor.

[0046] In one embodiment, the silicon carbide substrate 100 can be an intrinsic silicon carbide or a P-type doped silicon carbide material, or an N-type doped silicon carbide material.

[0047] In combination Figure 3 As shown in step S20, a specified region of the P-type switch isolation layer 300 is doped with N-type to form a voltage channel layer 210, so as to divide the P-type switch isolation layer 300 into a first switch isolation region 311 and a second switch isolation region 321.

[0048] The voltage channel layer 210 is formed by doping a specified region of the P-type switch isolation layer 300 with N-type, and the P-type switch isolation layer 300 is divided into the first switch isolation region 311 and the second switch isolation region 321 by the voltage channel layer 210.

[0049] In one embodiment, the voltage channel layer 210 is formed in the P-type switch isolation layer 300 by implanting N-type doping ions into a central region of the P-type switch isolation layer 300, the first switch isolation region 311 and the second switch isolation region 321 are respectively located on two sides of the voltage channel layer 210, and the first switch isolation region 311 and the second switch isolation region 321 do not contact each other.

[0050] In one embodiment, the first switch isolation region 311 and the second switch isolation region 321 are symmetrically arranged with the voltage channel layer 210 as a symmetric axis.

[0051] In combination Figure 4 As shown in step S30, a current diffusion layer 830 is formed on the voltage channel layer 210, and a first source doping layer 810, a second source doping layer 820, and a plurality of alternately arranged isolation structures and gate channel structures are formed on both sides of the current diffusion layer 830.

[0052] In this embodiment, the current diffusion layer 830 is located on the voltage channel layer 210, the first source doping layer 810 is located on the first switch isolation region 311, and the first source doping layer 810 is connected to the current diffusion layer 830 through the gate channel structure, the second source doping layer 820 is located on the second switch isolation region 321, and the second source doping layer 820 is connected to the current diffusion layer 830 through the gate channel structure.

[0053] In one embodiment, the first source doping layer 810 and the current diffusion layer 830 are connected through a plurality of first gate channel structures 410, and the second source doping layer 820 and the current diffusion layer 830 are connected through a plurality of second gate channel structures 420.

[0054] In one embodiment, referring to Figure 5As shown, in step S30, the current diffusion layer 830 is formed on the voltage channel layer 210, and the first source doped layer 810, the second source doped layer 820 and the plurality of alternately arranged isolation structures and gate channel structures are formed on both sides of the current diffusion layer 830, including steps S311 to S312.

[0055] In step S311, the N-type epitaxial layer 400 is epitaxially grown on the voltage channel layer 210 and the P-type switch isolation layer 300.

[0056] In the embodiment, referring to Figure 6 As shown, the N-type epitaxial layer 400 is epitaxially grown on the voltage channel layer 210 and the P-type switch isolation layer (i.e. the first switch isolation region 311 and the second switch isolation region 321) by using the N-type semiconductor material epitaxial growth process.

[0057] In step S312, the first preset etching region on the N-type epitaxial layer 400 is etched to form a plurality of first etching deep grooves 301 and a plurality of first gate channel structures 410, and the second preset etching region on the N-type epitaxial layer 400 is etched to form a plurality of second etching deep grooves 302 and a plurality of second gate channel structures 420, so as to form the current diffusion layer 830, the first source doped layer 810 and the second source doped layer 820 on the voltage channel layer 210.

[0058] In the embodiment, referring to Figure 4 As shown, the first preset etching region on the N-type epitaxial layer 400 is etched to form a plurality of first etching deep grooves 301, the first etching deep grooves 301 extend into the first switch isolation region 311, so as to divide the N-type epitaxial layer 400 on the first switch isolation region 311 into the first gate channel structures 410, the first source doped layer 810 and the current diffusion layer 830, the first source doped layer 810 and the current diffusion layer 830 are located on both sides of the first gate channel structures 410, and the second preset etching region on the N-type epitaxial layer 400 is etched to form a plurality of second etching deep grooves 302, the second etching deep grooves 302 extend into the second switch isolation region 321, so as to divide the N-type epitaxial layer 400 on the second switch isolation region 321 into the second gate channel structures 420, the second source doped layer 820 and the current diffusion layer 830, the second source doped layer 820 and the current diffusion layer 830 are located on both sides of the second gate channel structures 420.

[0059] In one embodiment, the first etching deep grooves 301 extend into the first switch isolation region 311, so that the adjacent first gate channel structures 410 are not in contact with each other, and the second etching deep grooves 302 extend into the second switch isolation region 321, so that the adjacent second gate channel structures 420 are not in contact with each other.

[0060] In the embodiment, referring toFigure 7 As shown, the first etching deep groove 301 reaches the first switch isolation region 311, and the second etching deep groove 302 reaches the second switch isolation region 321.

[0061] In some embodiments, referring to Figure 8 As shown, the step S30 further comprises steps S313 and S314.

[0062] In the step S313, P-type semiconductor material is deposited in the first etching deep groove 301 to form a first isolation structure 312 in contact with the first switch isolation region 311.

[0063] In the present embodiment, the first isolation structure 312 is formed by filling P-type doped material in the first etching deep groove 301 under the cover of the P-type doped mask, and the first source doped layer 810 and the current diffusion layer 830 are located on both sides of the first isolation structure 312, and both the first source doped layer 810 and the current diffusion layer 830 are in contact with the first isolation structure 312.

[0064] In the step S314, P-type semiconductor material is deposited in the second etching deep groove 302 to form a second isolation structure 322 in contact with the second switch isolation region 321.

[0065] In the present embodiment, the second isolation structure 322 is formed by filling P-type doped material in the second etching deep groove 302 under the cover of the P-type doped mask, and since the second etching deep groove 302 reaches the second switch isolation region 321, the N-type epitaxial layer 400 at the positions of the second source doped layer 820 and the current diffusion layer 830 is not etched, so that the second source doped layer 820 and the current diffusion layer 830 are located on both sides of the second isolation structure 322, and both the second source doped layer 820 and the current diffusion layer 830 are in contact with the second isolation structure 322.

[0066] In the present embodiment, in combination with Figure 9 As shown, the first etching deep groove 301 reaches the first switch isolation region 311, and the first isolation structure 312 is in contact with the first switch isolation region 311, the second etching deep groove 302 reaches the second switch isolation region 321, and the second isolation structure 322 is in contact with the second switch isolation region 321.

[0067] In one embodiment, in combination with Figure 9 As shown, the number of the first isolation structures 312 can be multiple, and the multiple first isolation structures 312 are arranged in parallel and formed by filling P-type doped material in the multiple first etching deep grooves 301.

[0068] In one embodiment, in combination with Figure 9As shown, the first preset etching region is used to determine the position of the first isolation structure 312 in the N-type epitaxial layer 400, and the second preset etching region is used to determine the position of the second isolation structure 322 in the N-type epitaxial layer 400. The structure between the first isolation structure 312 and the second isolation structure 322 is taken as the current diffusion layer 830 by determining the positions of the first isolation structure 312 and the second isolation structure 322. Therefore, the first preset etching region is located above the first isolation structure 312, the second preset etching region is located above the second isolation structure 322, and the current diffusion layer 830 is located between the first preset etching region and the second preset etching region.

[0069] In one embodiment, the plurality of first isolation structures 312 are arranged in parallel.

[0070] In one embodiment, the plurality of first isolation structures 312 have equal widths.

[0071] In one embodiment, the plurality of second isolation structures 322 are arranged in parallel.

[0072] In one embodiment, the plurality of second isolation structures 322 have equal widths.

[0073] In one embodiment, the N-type semiconductor material is epitaxially grown on the voltage channel layer 210 and the P-type switch isolation layer 300 under the first mask to form the current diffusion layer 830, the first gate region channel structure 410, the second gate region channel structure 420, the first source doped layer 810, and the second source doped layer 820.

[0074] In the present embodiment, the positions of the current diffusion layer 830, the first gate region channel structure 410, the second gate region channel structure 420, the first source doped layer 810, and the second source doped layer 820 are defined by the first mask, and then the N-type semiconductor material is deposited or epitaxially grown under the cover of the first mask, so as to form the current diffusion layer 830 on the voltage channel layer 210, the plurality of first gate region channel structures 410 and the first source doped layer 810 on the first switch isolation region 311, and the plurality of second gate region channel structures 420 and the second source doped layer 820 on the second switch isolation region 321.

[0075] In the present embodiment, the first source doped layer 810 and the current diffusion layer 830 are located on both sides of the first gate region channel structure 410, and the second source doped layer 820 and the current diffusion layer 830 are located on both sides of the second gate region channel structure 420.

[0076] In one embodiment, the N-type semiconductor material can be N-type silicon carbide, N-type silicon, or N-type gallium nitride.

[0077] In one embodiment, the first gate channel structure in contact with the first switch isolation region is formed between the adjacent first gate channel structures 410 under the masking of the second mask, and the second isolation structure 322 in contact with the second switch isolation region 321 is formed between the adjacent second gate channel structures 420.

[0078] In the present embodiment, the second mask is used to cover the positions of the current diffusion layer 830, the first gate channel structure 410, the second gate channel structure 420, the first source doped layer 810 and the second source doped layer 820, and the P-type semiconductor material is deposited under the masking of the second mask to form the first isolation structure 312 in contact with the first switch isolation region 311 between the adjacent first gate channel structures 410 and the second isolation structure 322 in contact with the second switch isolation region 321 between the adjacent second gate channel structures 420.

[0079] In one embodiment, the P-type semiconductor material can be P-type silicon carbide, P-type silicon or P-type gallium nitride.

[0080] In one embodiment, in order to increase the thickness of the current diffusion layer 830, the first gate channel structure 410, the second gate channel structure 420, the first source doped layer 810 and the second source doped layer 820, the above steps S321 and S322 can be alternately performed, and the N-type semiconductor material and the P-type semiconductor material are alternately epitaxially grown by using the first mask and the second mask, so as to increase the thickness of the current diffusion layer 830, the first gate channel structure 410, the second gate channel structure 420, the first source doped layer 810, the second source doped layer 820, the first isolation structure 312 and the second isolation structure 322 by multiple epitaxial preparation processes.

[0081] In one embodiment, the first gate channel structure 410 is located on both sides of the first isolation structure 312, and the second gate channel structure 420 is located on both sides of the second isolation structure 322.

[0082] In one embodiment, the plurality of first gate channel structures 410 and the plurality of second gate channel structures 420 are arranged one by one.

[0083] In one embodiment, the width of the first gate channel structure 410 is equal to the width of the second gate channel structure 420.

[0084] In one embodiment, the thickness of the wafer can be designed to improve the voltage resistance of the device, so as to match the switching of the vertical transistor, and the width of the device is increased, so as to achieve the purpose of realizing high current density and high breakdown voltage in the same chip area. Compared with general device design, although the current diffusion layer 830 is added, more high aspect ratio technology can be developed with the evolution of process, so that the vertical transistor in the embodiment has a deeper development potential.

[0085] In step S40, a gate metal layer is formed on the gate region channel structure.

[0086] In the embodiment, the gate metal layer is formed on the first isolation structure 312 and the second isolation structure 322, and the gate metal layer is insulated from the first gate region channel structure 410 and the second gate region channel structure 420.

[0087] In one embodiment, the first gate metal layer is formed on the first isolation structure 312, and the second gate metal layer is formed on the second isolation structure 322.

[0088] In step S50, a Schottky metal layer 600 is formed on the current diffusion layer 830, as shown in Figure 9 .

[0089] In the embodiment, the Schottky metal layer 600 and the current diffusion layer 830 form a Schottky contact, so as to integrate a Schottky diode in the vertical FinFET power device. In some embodiments, the Schottky metal layer 600 is connected to the source electrode, so that the anode of the Schottky diode is connected to the source electrode of the device, the cathode of the Schottky diode is connected to the drain electrode of the device, the Schottky diode is connected in series between the source electrode and the drain electrode of the device, the reverse recovery characteristics of the MOSFET are improved, and the switching speed of the device is improved. The current flow direction diagram when the vertical FinFET power device in the embodiment works is shown in Figure 10 .

[0090] In some embodiments, due to the limitation of the device structure of the vertical FinFET power device, integrating the Schottky diode (SBD) in the region of the current diffusion layer 830 can reduce the cost and chip area of the device.

[0091] In some embodiments, integrating the SBD in the region of the current diffusion layer 830 can increase the negative effects and reduce the performance of the vertical FinFET power device, such as possible leakage or increase of the on-state voltage of the device. According to the current flow direction diagram shown in Figure 10 , most of the Schottky metal in the middle of the Schottky metal layer 600 does not work, so as to Figure 11As shown, in this embodiment, a split Schottky metal structure is proposed, in which the Schottky metal layer 600 is composed of a first Schottky metal region 610 and a second Schottky metal region 620, so that the fin-shaped switching MOSFET device of the vertical FinFET power device has the benefit of SBD in improving switching speed while minimizing its negative effects, Figure 11 The current flow diagram of the vertical FinFET power device in operation is shown in Figure 12 As shown, it can be seen that the design of the Schottky metal layer 600 as a split Schottky metal structure does not affect its current relationship.

[0092] In some embodiments, the first Schottky metal region 610 and the second Schottky metal region 620 that are not in contact with each other can be formed by depositing Schottky metal material on the current diffusion layer 830 and etching the deposited Schottky metal material. 。

[0093] In this embodiment, in combination with Figure 10 As shown, the first Schottky metal region 610 is in contact with the first gate region channel structure 410 close to the first source doped layer 810, and the second Schottky metal region 620 is in contact with the second gate region channel structure 420 close to the second source doped layer 820.

[0094] In some embodiments, the first gate region channel structure 410 and the second gate region channel structure 420 are a MOS structure, and in operation, the current of the vertical FinFET power device flows from the drain to the current diffusion layer 830, passes through the gate region (the first gate region channel structure 410 and the second gate region channel structure 420) of the FinFET, and induces a channel at the outer edge of the gate, and the current flows to the source of the device through the induced channel.

[0095] In step S60, a drain metal layer 850 is formed on the back surface of the silicon carbide substrate 100.

[0096] In this embodiment, referring to Figure 9 As shown, the drain metal layer 850 can be formed on part of the back surface of the silicon carbide substrate 100 or cover the entire back surface of the silicon carbide substrate 100.

[0097] In one embodiment, the current diffusion layer 830, the first source doped layer 810, and the second source doped layer 820 are arranged in parallel.

[0098] In one embodiment, the first isolation structure 312 and the first switch isolation region 311 are both P-type doped semiconductors, and the first gate region channel structure 410 is arranged alternately with the first isolation structure 312, thereby forming a fin-shaped JFET structure, and the first switch isolation region 311 is further used to isolate the first gate region channel structure 410 and the N-type drift layer 200. For example, in a case of a normally-on vertical transistor device, a high voltage is applied to the first gate metal layer, so as to reduce the depletion region of the JFET structure under the fin-shaped gate, thereby turning on the device. If the voltage applied to the first gate metal layer is less than the off threshold voltage, the depletion region of the JFET structure under the fin-shaped gate remains unchanged, thereby turning off the device.

[0099] In actual applications, if the transistor device is a normally-on depletion type device, a negative voltage needs to be applied to the first gate metal layer, so as to turn off the transistor.

[0100] Similarly, the fin-shaped JFET structure formed by the second switch isolation region 321, the second source doped layer 820, the current diffusion layer 830, the second isolation structure 322 and the second gate region channel structure 420 has the same working mechanism.

[0101] The embodiment of the present application further provides a silicon carbide-based FINFET power device, which is prepared by using the preparation method in any one of the above embodiments.

[0102] The embodiment of the present application further provides a chip, in which a vertical transistor prepared by using the preparation method in any one of the above embodiments is integrated.

[0103] In one embodiment, the chip integrates the vertical transistor prepared by using the preparation method in the above embodiment.

[0104] In the embodiment, the chip includes a chip substrate, and one or more vertical transistors are arranged on the substrate. The vertical transistors can be prepared by using the preparation method in any one of the above embodiments, or the vertical transistors in any one of the above embodiments can be arranged on the chip substrate.

[0105] In a specific application embodiment, other related semiconductor devices can be integrated on the chip substrate, so as to form an integrated circuit together with the vertical transistors.

[0106] In a specific application embodiment, the chip can be a switch chip or a driving chip.

[0107] Compared with the prior art, the embodiment of the application has the beneficial effects that: by epitaxially growing the N-type drift layer and the P-type switch isolation layer on the front surface of the silicon carbide substrate in sequence, the P-type switch isolation layer is divided into a first switch isolation region and a second switch isolation region by the voltage channel layer, the current diffusion layer is formed on the voltage channel layer, the first source doped layer, the second source doped layer, the plurality of isolation structures and the plurality of gate channel structures are formed on both sides of the current diffusion layer, and the gate metal layer is formed on the gate channel structure of the fin structure, a plurality of current channels are induced to reach the source through the gate metal layer and the gate channel structure of the fin structure, and the Schottky metal layer is formed on the current diffusion layer, so that the Schottky diode is integrated in the device at the lowest cost and chip area, and the switching speed and reliability of the silicon carbide-based FINFET power device are improved.

[0108] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned doped regions is exemplified, and in actual application, the above-mentioned functional regions can be allocated by different doped regions, that is, the internal structure of the device is divided into different doped regions to complete all or part of the functions described above.

[0109] The doped regions in the embodiment can be integrated in one functional region, or each doped region can exist physically alone, or two or more doped regions can be integrated in one functional region, and the integrated functional region can be realized by the same doped ion or by a plurality of doped ions. In addition, the specific names of the doped regions are only for the convenience of mutual differentiation, and are not used to limit the protection scope of the application. The specific working process of the doped regions in the preparation method of the device can refer to the corresponding process in the foregoing method embodiment, and will not be repeated here.

[0110] The above-described embodiments are only used to illustrate the technical solutions of the application, rather than limit them; although the application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the application, and should be included in the protection scope of the application.

Claims

1. A method for fabricating a silicon carbide-based FINFET power device, characterized in that, The preparation method includes: An N-type drift layer and a P-type switch isolation layer are epitaxially grown sequentially on the front side of a silicon carbide substrate. A voltage channel layer is formed by N-type doping of a designated area of ​​the P-type switch isolation layer, thereby dividing the P-type switch isolation layer into a first switch isolation region and a second switch isolation region. A current diffusion layer is formed on the voltage channel layer, and a first source doped layer, a second source doped layer, multiple isolation structures, and multiple gate channel structures are formed on both sides of the current diffusion layer; wherein, the first source doped layer is located on the first switch isolation region and is connected to the current diffusion layer through the gate channel structures, and the second source doped layer is located on the second switch isolation region and is connected to the current diffusion layer through the gate channel structures; A gate metal layer is formed on the gate channel structure; wherein the gate metal layer is insulated from the gate channel structure. A Schottky metal layer is formed on the current diffusion layer; wherein a Schottky contact is formed between the Schottky metal layer and the current diffusion layer; A drain metal layer is formed on the back side of the silicon carbide substrate.

2. The preparation method according to claim 1, characterized in that, The formation of a Schottky metal layer on the current diffusion layer includes: Schottky metal material is deposited on the current diffusion layer and etched to form a first Schottky metal region and a second Schottky metal region that do not contact each other; wherein, the first Schottky metal region is in contact with the gate channel structure near the first source doped layer, and the second Schottky metal region is in contact with the gate channel structure near the second source doped layer.

3. The preparation method according to claim 2, characterized in that, The first Schottky metal region and the second Schottky metal region are arranged in parallel, and the first Schottky metal region and the second Schottky metal region have the same length.

4. The preparation method according to claim 2 or 3, characterized in that, The first Schottky metal region and the second Schottky metal region have the same width.

5. The preparation method according to claim 2 or 3, characterized in that, The gap width between the first Schottky metal region and the second Schottky metal region is greater than the width of the first Schottky metal region and the second Schottky metal region.

6. The preparation method according to claim 1, characterized in that, The process of forming a current diffusion layer on the voltage channel layer, and forming a first source doped layer, a second source doped layer, multiple isolation structures, and multiple gate channel structures on both sides of the current diffusion layer, includes: An N-type epitaxial layer is epitaxially grown on the voltage channel layer and the P-type switch isolation layer; A first predetermined etching region on the N-type epitaxial layer is etched to form a plurality of first etch deep trenches and a plurality of first gate channel structures. A second predetermined etch region on the N-type epitaxial layer is etched to form a plurality of second etch deep trenches and a plurality of second gate channel structures, thereby forming the current diffusion layer, the first source doped layer, and the second source doped layer on the voltage channel layer. The first source doped layer and the current diffusion layer are located on both sides of the first gate channel structure, and the second source doped layer and the current diffusion layer are located on both sides of the second gate channel structure.

7. The preparation method according to claim 6, characterized in that, The method of forming a current diffusion layer on the voltage channel layer, and forming a first source doped layer, a second source doped layer, multiple isolation structures, and multiple gate channel structures on both sides of the current diffusion layer, further includes: A P-type semiconductor material is deposited within the first etched trench to form a first isolation structure; P-type semiconductor material is deposited within the second etched trench to form a second isolation structure.

8. The preparation method according to claim 2, characterized in that, The current diffusion layer, the first source doped layer, and the second source doped layer are arranged in parallel.

9. A silicon carbide-based FINFET power device, characterized in that, The silicon carbide-based FINFET power device is fabricated using the fabrication method described in any one of claims 1-8.

10. A chip, characterized in that, The chip integrates a vertical transistor fabricated by the fabrication method described in any one of claims 1-8.

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