Semiconductor processing apparatus and semiconductor processing system

Abstract

The present invention provides a semiconductor processing apparatus, which includes: a lower chamber having a first support area for supporting a wafer; an upper chamber having a second support area, wherein when the upper chamber is closed with the lower chamber, the wafer is placed between the first support area and the second support area; a temperature control component disposed adjacent to the upper chamber and / or the lower chamber, which adjusts the temperature of the upper chamber and / or the lower chamber by adjusting its own temperature; a first channel formed in an edge area of the first support area or the second support area, and the first channel provides a first space for flowing one or more chemical fluids for etching the edge area of the wafer; the temperature of the upper chamber and / or the lower chamber is adjusted by using the temperature control component, so as to adjust the etching width of the edge of the wafer. In this way, the etching width of the edge of the wafer can be finely adjusted.

Description

[Technical field]

[0001] The present invention relates to the field of surface treatment of semiconductor wafers or similar workpieces, and in particular to a semiconductor processing device and a semiconductor processing system. [Background technology]

[0002] In the semiconductor manufacturing process, semiconductor wafers need to go through many processes to meet the high standards of the semiconductor industry. In the advanced process of semiconductor wafers, the edge of the wafer is required to be uniform, flat, undamaged and smooth. The high requirement of uniform and precise etching of the edge surface of the wafer brings great challenges to the semiconductor wafer process.

[0003] Figure 1a 1 is a top view of the structure of a semiconductor wafer 100. The semiconductor wafer 100 includes a substrate layer 101 and a thin film layer 102 deposited on the substrate layer 101. Figure 1b for Figure 1a The AA cross-sectional view of FIG. Measurement points 1-8 are locations where relevant data of the semiconductor wafer is measured during operation. Figure 1b As shown, the corrosion width is the difference between the radius of the substrate layer 101 and the thin film layer 102. The corrosion width should be basically the same at each measurement point 1-8. The smaller the difference between the maximum corrosion width and the minimum corrosion width, the higher the uniformity. For example, when the edge width is designed to be 0.7mm, many high-end process technologies require that the difference between the maximum corrosion width and the minimum corrosion width should not be greater than 0.1mm, otherwise it will cause uneven corrosion width. If the difference between the maximum corrosion width and the minimum corrosion width exceeds 0.1mm, it will directly affect the effect of subsequent processing operations, ultimately leading to poor performance of the integrated circuit chip and affecting the chip manufacturing yield.

[0004] The wet processing technology for semiconductor wafers has the advantages of simple principle, flexible process and low cost. There are several traditional wet etching methods for the edges of semiconductor wafers. For example, there is a method of polishing the edge area of the semiconductor wafer. The semiconductor wafer is rotated, and a thin film layer is removed from the substrate layer by combining physical friction and chemical corrosion. Since it is easy to damage the remaining thin film layer and the substrate layer, the polishing method is mainly used for the manufacture of semiconductor wafers with relatively low precision requirements. Edge damage may cause misalignment and slip of the wafer edge during the hot processing, ultimately resulting in the scrapping of the wafer. Another commonly used method is to adsorb the semiconductor wafer with a vacuum. The vacuum adsorption method uses a vacuum chuck to hold the wafer. The function of the vacuum chuck is to hold the wafer and protect the part of the thin film to be retained inside the vacuum chuck, and expose the part of the thin film to be removed outside the vacuum chuck. Then, the vacuum chuck and the wafer are immersed in a chemical etching solution together to etch away the film part exposed outside the vacuum chuck. However, the vacuum adsorption method results in uneven removal of the thin layer and uneven etching width. There is also a commonly used method called the film pasting method. Pure anti-corrosion plastic films such as PTFE and PE are used to protect the part of the thin film to be retained, and then the whole is exposed to a chemical etching gas environment or immersed in a chemical etching solution to etch the exposed part. The film pasting method often leads to uneven etching width because the center of the pre-cut film may not be aligned with the center of the wafer substrate; and there are many process steps and multiple devices are required to complete, including film pasting, wet etching, cleaning and film removal devices. There is also a newly developed spraying method. Its working principle is to use a special nozzle to accurately spray the fluid for etching onto the area to be etched on the edge of the rotating wafer, achieving precise, uniform, flat and damage-free etching. Although the spraying method can achieve a high etching effect, it has extremely high requirements for the design of the equipment and the processing accuracy of the components, the equipment cost is very high, the process conditions are also relatively harsh, and the process cost is high.

[0005] In addition, since the vast majority of materials have a certain coefficient of thermal expansion. A semiconductor wafer edge processing device made of a material with a large coefficient of thermal expansion may have different etching widths at the edges of the wafer during manufacturing and use due to the difference between the manufacturing temperature and the use temperature, temperature changes during transportation, or changes in other unknown factors.

[0006] Furthermore, different processes and manufacturers often require different etching widths at the edges of the wafer. For example, some have an etching width of 0.5 mm, some have an etching width of 0.6 mm, and some have an etching width of 0.3 mm, etc. In order to meet the requirements of different processes and manufacturers, it is necessary to manufacture semiconductor wafer edge processing devices with different etching sizes, and the cost is very high.

[0007] In view of this, it is necessary to develop a new type of semiconductor wafer edge processing device that can solve the above problems.

Summary of the Invention

[0008] The object of the present invention is to provide a novel semiconductor processing apparatus and a semiconductor processing system, which can solve the problems existing in the prior art and realize the adjustment of the etching width of the edge of the wafer.

[0009] To achieve the above object, according to one aspect of the present invention, the present invention provides a semiconductor processing apparatus, which includes: a lower chamber having a first support area for supporting a wafer; an upper chamber having a second support area, wherein when the upper chamber is closed with the lower chamber, the wafer is accommodated between the first support area and the second support area; a temperature control component disposed adjacent to the upper chamber and / or the lower chamber, which adjusts the temperature of the upper chamber and / or the lower chamber by adjusting its own temperature; a first channel formed in the edge area of the first support area or the second support area, and the first channel provides a first space for circulating one or more chemical fluids for etching the edge area of the wafer; the temperature of the upper chamber and / or the lower chamber is adjusted by using the temperature control component, so as to finely adjust the position of the edge of the first support area and / or the second support area by using the thermal expansion and contraction characteristics of the upper chamber and / or the lower chamber, and further adjust the width of the edge area of the wafer extending into the first space, and finally adjust the etching width of the edge of the wafer.

[0010] According to another aspect of the present invention, the present invention provides a semiconductor processing system, including: the above-mentioned semiconductor processing apparatus; and a material storage device connected to the semiconductor processing apparatus, and the material storage device is used for storing and exchanging and transferring one or more chemical fluids with the semiconductor processing apparatus.

[0011] Embodiments of the present invention can be used in processing operations including semiconductor wafers, so that the edge surface is etched uniformly and precisely. At the same time, the influence of temperature change on the accuracy of the etched edge can also be reduced.

[0012] Compared with the existing solutions, the embodiments of the present invention can provide multiple advantages.

[0013] By providing the temperature control component, the present invention can adjust the temperature of the upper chamber and / or the lower chamber as needed, thereby adjusting the size of the upper chamber and / or the lower chamber, and further adjusting the etching width of the edge of the wafer.

[0014] The features, configurations and advantages of the present invention will be obvious by reading the following detailed description and the drawings. The present invention includes any combination of one or more features or elements, regardless of whether these features or elements are explicitly described or otherwise in the embodiments. The present invention is intended to be read as a whole, so that any separable feature or element of the present invention, in any aspect and embodiment, should be considered combinable, unless the context of the present invention clearly provides otherwise.

[0015] Therefore, it should be understood that this summary is provided only for the purpose of summarizing some embodiments to provide a basic understanding of some aspects of the present invention. Therefore, the above embodiments are merely examples and should not be construed as narrowing the scope or concept of the present invention in any way. By reading the following detailed description and the accompanying drawings, the features, appearances, and advantages of each embodiment will become apparent, and the drawings show the principles of some embodiments by way of example. **BRIEF DESCRIPTION OF THE DRAWINGS**

[0016] The present invention will be more readily understood by reference to the accompanying drawings and the following detailed description, in which like reference numerals correspond to like structural components, wherein:

[0017] Figure 1a It is a top view of the structure of a semiconductor wafer.

[0018] Figure 1b It is Figure 1a a cross-sectional view taken along line A-A of

[0019] Figure 2a It is a schematic cross-sectional view of the semiconductor processing apparatus 200 in an embodiment of the present invention.

[0020] Figure 2b It is Figure 2a an enlarged view of circle A in

[0021] Figure 2c It is Figure 2b an enlarged view of circle B in

[0022] Figure 2d It is Figure 2c an enlarged view of circle C in

[0023] Figure 2e It is Figure 2a a bottom view of the upper chamber 220 of the semiconductor processing apparatus 200.

[0024] Figure 2f It is Figure 2a a top view of the lower chamber 210 of the semiconductor processing apparatus 200.

[0025] Figure 3a It is a schematic cross-sectional view of the semiconductor processing apparatus 300 in an embodiment of the present invention.

[0026] Figure 3b It is Figure 3a an enlarged view of circle D in

[0027] Figure 3c It is Figure 3a an enlarged view of circle D with the protrusion 342 shown in

[0028] Figure 3d For Figure 3a An upward view of the upper chamber 320 of the semiconductor processing apparatus 300.

[0029] Figure 3e For Figure 3a A top view of the lower chamber 320 of the semiconductor processing apparatus 300.

[0030] Figure 4a A schematic cross-sectional view of the semiconductor processing apparatus 400 in an embodiment of the present invention.

[0031] Figure 4b For Figure 4a An enlarged schematic view of the circle E in

[0032] Figure 4c For Figure 4b An enlarged schematic view of the circle F in

[0033] Figure 4d For Figure 4a A top view of the lower chamber 420 of the semiconductor processing apparatus 400.

[0034] Figure 4e For Figure 4a An upward view of the upper chamber 410 of the semiconductor processing apparatus 400.

[0035] Figure 5 An exemplary system 500 in the present invention includes a semiconductor processing apparatus and a material storage apparatus.

[0036] Figure 6 An exemplary method for processing an edge region of a semiconductor wafer using a device in an embodiment of the present invention.

[0037] Figure 7 A schematic structural view of a semiconductor processing apparatus in which the corrosion width of an edge of a wafer can be finely adjusted in an embodiment of the present invention.

Specific Embodiment

[0038] Some embodiments of the present invention will be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all, embodiments are listed. In fact, the various embodiments of the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the present invention to those skilled in the art. For example, unless otherwise specified, referring to something as first, second, etc. should not be construed as implying a particular order. Additionally, something may be described as above something (unless otherwise specified) when in fact it is below something, and vice versa; similarly, something described as on the left may be on the right, and vice versa. The same reference numeral always represents the same element.

[0039] Figures 1a to 1b It is a schematic structural diagram of a semiconductor wafer 100. Figure 1a It is a top view of the structure of the semiconductor wafer 100. Figure 1b It is Figure 1a a cross-sectional view of the A-A section of Figures 1a-1b As shown, the semiconductor wafer 100 includes a substrate layer 101 and a thin film layer 102 deposited on the upper surface of the substrate layer 101, and the substrate layer 101 may be partially covered by the thin film layer 102. In another embodiment, the substrate layer 101 may be completely covered by the thin film layer 102. In another embodiment, both sides of the surface of the substrate layer 101 may be covered by the thin film layer 102 respectively.

[0040] In this embodiment, through the processing of the semiconductor wafer, the thin film layer 102 should be removed from the substrate layer 101. As Figures 1a-1b shown, the radius of the thin film layer 102 is smaller than that of the substrate layer 101, and the etching width refers to the difference between the two radii. Figure 1a The measurement points 1-8 in

[0041] are the test positions for measuring the relevant data of the semiconductor wafer. The etching width should be basically the same at the measurement points 1-8. The smaller the difference between the maximum value and the minimum value, the better the etching uniformity. For example, when the edge width is designed to be 0.7 mm, the advanced process requires that the difference between the maximum etching width and the minimum etching width shall not be greater than 0.1 mm. In some embodiments, the thin layers covering both sides of the surface of the substrate layer 101 should be partially or completely removed. The etching width on each side of the surface of the substrate layer 101 may be the same or different.

[0041] Referring to Figures 2a to 2f , this embodiment shows a schematic structural diagram of a semiconductor processing device 200. Figure 2a It is a cross-sectional schematic diagram of the semiconductor processing device 200. Figure 2b It is Figure 2a an enlarged schematic diagram of the circle A in Figure 2c It is Figure 2b (omitting the through hole) an enlarged schematic diagram of the circle B in Figure 2d It is Figure 2c an enlarged schematic diagram of the circle C in Figure 2e It is Figure 2a a bottom view of the upper chamber 220 of the semiconductor processing device 200. Figure 2f It is Figure 2a a top view of the lower chamber 210 of the semiconductor processing device 200.

[0042] In the embodiment, as shown in FIGS. 1 and 2, the semiconductor device 200 includes a lower chamber 210 having a first support area 212. The first support area 212 can support the wafer 100. As Figure 2aAs shown, the first support area 212 has an upper surface facing the wafer 100. The wafer 100 can be placed on the upper surface of the first support area 212. In some embodiments, the apparatus 200 includes an upper chamber 220 having a second support area 222. As Figure 2a shown, the second support area 222 has a lower surface facing the wafer 100. The upper chamber 220 is closed with the lower chamber 210, and the wafer 100 is placed between the first support area 212 and the second support area 222. Taking the lower chamber as the origin, the upper chamber 220 can move between two opposite positions. In the first position, the wafer 100 can be loaded and / or unloaded onto the first support area 212. As Figure 2a shown, in the second position, the upper chamber 220 and the lower chamber 210 are closed so that the wafer 100 is fixed by the upper surface of the first support area 212 and the lower surface of the second support area 222 and processed.

[0043] In some embodiments or any combination of the foregoing embodiments, referring Figures 2a to 2c to, the apparatus 200 includes a first channel 230 formed by an edge area of the first support area 212 or the second support area 222. The first channel 230 provides a first space 232 for one or more chemical fluids to etch the edge area of the wafer 100. Referring Figures 2a to 2c to, the first channel 230 is formed by an edge area of the second support area 222 in the upper chamber 220. The first channel 230 is formed on the lower surface of the upper chamber 220, and one side opening of the first channel 230 faces the wafer 100. In this embodiment, the first channel 230 provides the first space 232 such that one or more chemical fluids flow therein to etch the edge area of the wafer 100. Referring Figures 2a to 2c to, the first space 232 can be formed by the first channel 230 and the inner surface of the wafer 100. In this embodiment, the first channel 230 is annular and surrounds the edge area of the wafer 100. The entire edge area of the wafer 100 is received in the first space 232. In another embodiment, the first channel 230 can be designed as an arc less than 360 degrees, and the edge area of the wafer 100 can be accommodated in a specific area of the first space 232. Then, one or more chemical fluids can etch the wafer edge area along the arc of the first channel 230.

[0044] In some embodiments of the apparatus 200 or any combination of the foregoing embodiments, referring Figures 2a to 2c to, the upper chamber 220 includes a raised portion 240 abutting against the edge of the wafer 100. The raised portion can directly contact and abut against the edge of the wafer 100. Referring Figure 2a, the central axis X-X of the wafer 100 is perpendicular to the upper surface of the wafer 100. The central axis X'-X' of the second support area 222 is perpendicular to the lower surface of the second support area 222. The raised portion 240 will align the central axis X-X of the wafer 100 with the central axis X'-X' of the second support area 222. When the upper chamber 220 is in the first position, the wafer 100 is loaded onto the first support area 212. The central axis X-X of the wafer 100 may not be aligned with the central axis X'-X' of the second support area 222. During the movement of the upper chamber 220 from the first position to the second position, the raised portion 240 contacts the edge of the wafer 100, then abuts against the edge of the wafer 100, and pushes the wafer 100 to move on the upper surface of the first support area 212. When the upper chamber 220 is in the second position, the wafer is fixed on the upper surface of the first support area 212, and the central axis X-X of the wafer 100 is parallel to the central axis X'-X' of the second support area 222. Or the central axis X-X of the wafer 100 may overlap with the central axis X'-X' of the second support area 222.

[0045] In some embodiments of the device 200 or any combination of the foregoing embodiments, the raised portion 240 is adjacent to the second support area 222 and extends downward into the chamber 210. Refer to Figure 2a and 2b , the raised portion 240 is connected to the second support area 222. When the upper chamber 220 is in the second position, the raised portion 240 extends into the lower chamber 210. As Figure 2a and 2b shown, in this embodiment, the raised portion 240 is located beside the first channel 230. Refer to Figure 2a , the central axis X-X of the wafer 100 is perpendicular to the upper surface of the wafer 100 and the central axis X'-X' of the second support area 222 is perpendicular to the lower surface of the upper chamber 220. The upper surface of the wafer 100 is parallel to the lower surface of the second support area 222. In one embodiment, when the upper chamber 220 is in the second position, a part of the upper surface of the wafer 100 overlaps with the lower surface of the second support area 222, and the central axis X-X of the wafer 100 overlaps with the central axis X'-X' of the second support area 222.

[0046] In some embodiments of the device 200 or any combination of the foregoing embodiments, the raised portion 240 can be designed to form a closed loop around the wafer 100. Refer to Figure 2a, the raised portion 240 includes a closed loop. This closed loop can surround the entire edge region of the wafer 100. Thus, the raised portion 240 can fully abut against the edge region of the wafer 100, causing the central axis X-X of the wafer 100 to overlap with the central axis X'-X' of the second support region 222. In certain embodiments, the closed loop can be an arc with an angle less than 360 degrees, and a specific portion abuts against the edge region of the wafer 100, causing the central axis X-X of the wafer 100 to align and / or overlap with the central axis X'-X' of the second support region 222 through the raised portion 240. In certain embodiments, the raised portion 240 may be an open loop.

[0047] In some embodiments of the device 200 or any combination of the foregoing embodiments, the raised portion 240 includes an inner angle facing the central axis X'-X' of the second support region 222. Refer to Figure 2c , the raised portion 240 includes an inner surface 242 inclined at an angle α with respect to the first reference direction Y-Y. The first reference direction Y-Y is parallel to the lower surface of the second support region 222. The range of the angle α is within 20° - 90°. As Figure 2b and 2c shown, the inner angle is formed at the connection of the inner surface 242 and the inner surface of the first channel 230, and faces the central axis X'-X' of the second support region 222. In certain embodiments, the inner angle abuts against the edge region of the wafer 100. As Figure 2b shown, during the movement of the upper chamber 220 from the first position to the second position, the inner angle of the raised portion 240 will contact the edge region of the wafer 100 and then abut against the edge of the wafer 100, pushing the wafer 100. When the upper chamber 220 is in the second position, the wafer is fixed and the central axis X-X of the wafer 100 is parallel to the central axis X'-X' of the second support region 222. Alternatively, the central axis X-X of the wafer 100 overlaps with the central axis X'-X' of the second support region 222.

[0048] In some embodiments of the device 200 or any combination of the foregoing embodiments, the first channel 250 is formed by the edge region 214 of the lower chamber 210, and the first channel 250 provides a first channel space 252 for the flow of one or more chemical fluids. Refer to Figure 2a , 2b and 2f, the first channel 250 is formed by the edge region 214 of the lower chamber 210 and is close to the first support region 212 of the lower chamber 210. The first channel 250 forms a first channel space 252, and one or more chemical fluids can flow from the first space 232 of the first channel 230 to the first channel space 252.

[0049] In some embodiments of the device 200 or any combination of the foregoing embodiments, the aisle 260 is located between the upper chamber 220 and the lower chamber 210. Refer to Figure 2b and2f , the lower chamber 210 has a first upper surface 262 between the first support region 212 and the first channel 250. The aisle 260 is located between the first upper surface 262 of the lower chamber 210 and the inner surface 242 of the raised portion 240. The aisle 260 connects the first space 232 with the first channel space 252, such that one or more chemical fluids flow from the first space 232 to the first channel space 252 through the aisle 260. In one embodiment, the aisle 260 can be blocked by the raised portion 240 to prevent one or more chemical fluids from flowing from the first space 232 to the first channel space 252. In another embodiment, the aisle 260 is blocked by the first support region 210 to prevent one or more chemical fluids from flowing from the first space 232 to the first channel space 252.

[0050] In some embodiments of the device 200 or any combination of the foregoing embodiments, as Figures 2a to 2c shown, the first channel 230 is located at the edge region of the second support region 222. The upper chamber 220 includes a first through hole 270, and one or more chemical fluids flow between the first space 232 and the outside of the device 200 via the first through hole 270. The first through hole 270 can communicate with the first space 232 through the upper chamber 220 from the outside of the device 200. In one embodiment, one or more chemical fluids can flow between the first space 232 and the outside of the device 200 through the first through hole 270. In another embodiment, the upper chamber 220 can include two or more through holes substantially the same as the first through hole 270 (such as Figure 2a and 2e shown secondary first through hole 272). In this embodiment, at least one first through hole (such as the first through hole 270) can be used as an inlet and the remaining first through holes (such as the secondary first through hole 272) can be used as outlets. The first space 232 can be connected to the outside through the first through hole 270 and the secondary first through hole 272. In this embodiment, one or more chemical fluids can flow into the first space 232 of the first channel 230 from the outside of the device 200 via the first through hole 270 and flow out of the first space 232 to the outside of the device 200 via the secondary first through hole 272.

[0051] In some embodiments of the device 200 or any combination of the foregoing embodiments, the second channel 280 is formed by the edge region of the first support region 212 and provides a second space 282 for using one or more chemical fluids to etch the edge region of the wafer 100. Refer to Figures 2a to 2c , the second channel 280 is formed by the edge region of the first support region 212 in the lower chamber 210. Refer to Figures 2a to 2c, the second channel 280 is located on the upper surface of the lower chamber 210, and one side of the second channel 280 is open facing the wafer. In this embodiment, the second channel 280 provides a first space 232 for one or more chemical fluids to etch the edge region of the wafer 100. Refer to Figures 2a to 2c , the second space can be formed by the inner surface of the second channel 280 and the wafer 100. In one embodiment, the second channel 280 is annular and surrounds the edge region of the wafer 100. In another embodiment, the second channel 280 can be designed as an arc with an angle less than 360 degrees, and the edge region of the wafer 100 is exposed at a specific position in the second space 282. Then, one or more chemical fluids are used to etch a specific edge region of the wafer along the arc of the second channel 280. In some embodiments, the second channel 280 is designed to have the same shape as the first channel 230. The second channel 280 is located between the first support region 212 and the first channel 250 near the first upper surface 262. The aisle 260 is located between the first upper surface 262 of the lower chamber 210 and the inner surface 242 of the upper chamber. The aisle 260 is used for one or more chemical fluids to flow from the second space 282 to the first channel space 252 through the aisle 260. In one embodiment, the aisle 260 can be blocked by the raised portion 240 to prevent one or more chemical fluids from flowing from the second space 282 into the first channel space 252. In another embodiment, the channel 260 can be blocked by the first support region 210 to prevent one or more chemical fluids from flowing from the second space 282 to the first channel space 252.

[0052] In some embodiments of the apparatus 200 or any combination of the foregoing embodiments, there is a second through hole 290 in the lower chamber 210 for one or more chemical fluids to flow between the second space 282 and the outside of the apparatus 200. Refer to Figure 2a and 2b , the second through hole 290 can penetrate the lower chamber 210 from the outside of the apparatus 200 and communicate with the second space 282 of the second channel 280. In one embodiment, one or more chemical fluids can flow between the second space 282 and the outside of the apparatus 200 via the second through hole 290. In another embodiment, one or more chemical fluids can flow from the outside of the apparatus 200 to the second space 282 of the second channel 280 via the second through hole 290, and then flow from the second space 282 of the second channel 280 to the first channel space 252 of the first channel 250 via the aisle 260. In some embodiments, the lower chamber 210 may further include one or more second through holes substantially the same as the second through hole 290 (such as Figure 2aThe secondary second through-hole (e.g., the second through-hole 292) shown. In one embodiment, at least one second through-hole (e.g., the second through-hole 290) is used as an inlet, and the remaining second through-holes (e.g., the secondary second through-hole 292) are used as outlets. The second space 282 is connected to the outside of the device 200 through the second through-hole 290 and the secondary second through-hole 292. In one embodiment, one or more chemical fluids can flow into the second space 282 of the second channel 280 from the outside of the device 200 via the second through-hole 290 and flow out of the device 200 via the secondary second through-hole 292. In another embodiment, one or more chemical fluids can flow into the second space 282 of the second channel 280 from the outside of the device 200 via the second through-hole 290 and the second through-hole 292, and then flow into the first channel space 252 of the first channel 250 from the second space 282 of the second channel 280 via the aisle 260.

[0053] Reference Figures 3a to 3e , which shows a schematic structural diagram of a semiconductor processing apparatus 300 provided by an embodiment of the present invention. Among them, Figure 3a is a schematic cross-sectional view of the semiconductor processing apparatus 300 in an embodiment of the present invention. Figure 3b is Figure 3a an enlarged schematic view of the circled D in Figure 3c is Figure 3a an enlarged schematic view of the circled D with the raised portion 342 shown in Figure 3d is Figure 3a a bottom view of the upper chamber 320 of the semiconductor processing apparatus 300. Figure 3e is Figure 3a a top view of the lower chamber 320 of the semiconductor processing apparatus 300.

[0054] In this embodiment, reference Figures 3a to 3e , the device 300 includes a lower chamber 310 having a first support area 312. The lower chamber 310 and the first support area 312 can be respectively referred to Figures 2a to 2f the lower chamber 210 and the first support area 212 shown. The device 300 includes an upper chamber 320 having a second support area 322. The upper chamber 320 and the second support area 322 can be respectively referred to the upper chamber 220 and the second support area 222 shown above Figures 2a to 2f . As described above, the upper chamber 320 is closed with the lower chamber 310 to fix the wafer 100 between the first support area 312 and the second support area 322. The device 300 includes a first channel 330 formed by the edge area of the first support area 312 or the second support area 322. The first channel 330 can be referred to the above Figures 2a to 2fThe first channel 230 described above. The first channel 330 is formed by the edge region of the second support region 322 in the upper chamber 320 and provides a first space 332 for the flow of one or more chemical fluids for etching the edge region of the wafer 100. The first space 332 can refer to the first space 232 described above Figures 2a to 2f In some embodiments, the first space 332 of the first channel 330 can also be formed by the inner surface of the first channel 330, the lower chamber 310, and the wafer 100. The entire or part of the edge region of the wafer 100 is exposed in the first space 332 of the first channel 330 and is contacted and etched by one or more chemical fluids

[0055] In some embodiments of the device 300 or any combination of the foregoing embodiments, as Figures 3a to 3d shown, the upper chamber 320 includes a raised portion 340 for abutting against the edge of the wafer 100 and aligning the central axis X-X of the wafer 100 with the central axis X'-X' of the second support region 322. The raised portion 340 can refer to the raised portion 240 described above Figures 2a to 2e In some embodiments, the raised portion 340 includes a plurality of bumps 342 that uniformly surround and abut against the edge region of the wafer 100. Each bump 342 extends from the raised portion 340 into the first space 332 of the first channel 330. Referring to Figure 3c and 3d , the raised portion 340 includes four bumps (such as bumps 342a to 342d). Each bump 342 includes an inner surface 344 that is inclined at an angle β with respect to the reference direction Y-Y. The range of the angle β is within 20°-90°. The inner surface faces the edge of the wafer 100. The reference direction Y-Y is parallel to the upper surface of the wafer 100 or perpendicular to the central axis X'-X' of the second support region 322. For example, in Figure 3c the bump 342a includes an inner surface 344a that is inclined at an angle β with respect to the reference direction Y-Y. The inner surface 344a can abut against the edge of the wafer 100 and push the wafer 100 to align the central axis X-X of the wafer 100 with the central axis X'-X' of the second support region 322. The raised portion 340 includes a plurality of bumps 342. In some embodiments, the raised portion 340 can include six bumps 342. In some embodiments, the raised portion 340 can include eight bumps 342. In some embodiments, the raised portion 340 can include twelve bumps 342.

[0056] In some embodiments of the device 300 or any combination of the foregoing embodiments, referring to Figures 3a to 3cThe first channel 350 is formed at the edge region 314 of the lower chamber 310 and provides a first channel space 352 for flowing one or more chemical fluids. The first channel 350, the edge region 314 of the lower chamber 310, and the first channel space 352 of the first channel 350 can be respectively referred to in the previous Figures 2a to 2f The first channel 250, the edge area 214 of the lower chamber 220 and the first channel space 252 of the first channel 250 are described. In some embodiments, a passage 360 is formed between the upper chamber 320 and the lower chamber 310 to connect the first space 332 with the first channel space 352, and one or more chemical fluids flow from the first space 332 to the first channel space 352 through the passage 360. The passage 360 can be referred to above. Figures 2a to 2f In some embodiments, the passage 360 is formed between the raised portion 340 and the first upper surface 362 of the lower chamber 310. Figures 3a to 3c As shown in FIGS. 3 e , the first upper surface 362 is adjacent to the first supporting area 312 and is located between the first supporting area 312 and the first groove 350 .

[0057] In some embodiments of the apparatus 300 or any combination of the foregoing embodiments, such as Figure 3a , 3b As shown in FIG. 3d, the upper chamber 320 may include a first through hole 370, so that one or more chemical fluids flow between the first space 332 and the outside of the device 300. The first through hole 370 may refer to the above Figures 2a to 2e In some embodiments, the upper chamber 320 may further include one or more first through holes (such as Figure 3a and 3d The arrangement of one or more first through holes can be referred to above. Figure 2a and 2e The arrangement of one or more first through holes is described.

[0058] In some embodiments of the apparatus 300 or any combination of the foregoing embodiments, reference Figure 3a , 3b 3e, the lower chamber 310 includes a second through hole 380. Figure 3a and 3bAs shown, the second through hole 380 is for one or more chemical fluids to flow between the first space 332 and the outside of the device 300. The second through hole 380 penetrates the lower chamber 310 from the outside of the device 300 and communicates with the first space 332 of the first channel 330. In some embodiments, one or more chemical fluids can flow from the outside of the device 300 to the first space 332 via the second through hole 380, and then flow from the first space 332 to the first channel space 352 of the first channel 350 through the aisle 360. In some embodiments, one or more chemical fluids can flow from the outside of the device 300 to the first space 332 of the first channel 330 through the first through hole 370, then flow from the first space 332 to the first channel space 352 through the aisle 360 and flow to the outside of the device 300 through the second through hole 380.

[0059] In some embodiments of the device 300 or any combination of the foregoing embodiments, the second channel 390 is formed by the edge region 324 of the upper chamber 320 and is located above the first channel 350. Referring to Figures 3a to 3d , the second channel 390 is formed by the edge region 324 of the upper chamber 320 and is close to the raised portion 340. The second channel 390 provides a second channel space for the flow of chemicals. The opening of the second channel 390 faces the lower chamber 310. The second channel 390 is located above the first channel 350 such that the first channel space 352 of the first channel 350 can communicate with the second channel space of the second channel 390. The second channel 390 has the same design as the first channel 350. Figure 3d and 3e As shown, the first channel 350 and the second channel 390 are annular. In addition, the first channel 350 and the second channel 390 can also be designed as arcs less than 360 degrees.

[0060] In some embodiments of the device 300 or any combination of the foregoing embodiments, as Figures 3a to 3c shown, the elastic member 392 can be placed between the first channel 350 and the second channel 390. In some embodiments, the elastic member 392 is placed in the first channel space 352 or the second channel space. In some embodiments, the elastic member 392 is placed in both the first channel space 352 and the second channel space. In some embodiments, the elastic member 392 can be used to prevent one or more chemical fluids from flowing from the first space 332 to the first channel space 352. For example Figures 3a to 3c shown, the width of the elastic member 392 is wider than the widths of the first channel 350 and the second channel 390. The inner surface of the first channel 350 and / or the inner surface of the second channel 390 abuts against the elastic member 392 to prevent one or more chemical fluids from flowing from the first space 332 to the first channel space 352.

[0061] In some embodiments of apparatus 300 or any combination of the foregoing embodiments, the resilient member 392 can be an O-ring.

[0062] Reference Figures 4a to 4e , which shows a schematic structural view of a semiconductor processing apparatus 400 provided by an embodiment of the present invention. Figure 4b is Figure 4a an enlarged schematic view of circle E in Figure 4c is Figure 4b an enlarged schematic view of circle F in Figure 4d is Figure 4a a top view of the lower chamber 420 of the semiconductor processing apparatus 400. Figure 4e is Figure 4a a bottom view of the upper chamber 410 of the semiconductor processing apparatus 400.

[0063] In one embodiment, reference Figures 4a to 4e , apparatus 400 includes a lower chamber 410 having a first support region 412. The lower chamber 410 and the first support region 412 can refer to Figures 2a to 2f the lower chamber 210 and the first support region 212 shown. Apparatus 400 includes an upper chamber 420 having a second support region 422. The upper chamber 420 and the second support region 422 can respectively refer to the upper chamber 220 and the second support region 222 shown above Figures 2a to 2f . Apparatus 400 includes a first channel 430 formed by an edge region of the first support region 412. The first channel 430 can refer to the first channel 230 described above Figures 2a to 2f . Referring to Figures 4a to 4c and 4e, the first channel 430 is formed at an edge region of the first support region 412 in the lower chamber 420 and provides a first space 432 for flowing one or more chemical fluids to etch an edge region of the wafer 100. The first space 432 of the first channel 430 can also be formed by the inner surface of the first channel 430 and the wafer 100. The entire or part of the edge region of the wafer 100 is received in the first space 432 of the first channel 430, and one or more chemical fluids can be used to contact and etch the edge region of the wafer 100.

[0064] In some embodiments of apparatus 400 or any combination of the foregoing embodiments, as Figures 4a to 4d shown, the upper chamber 420 includes a raised portion 440 that abuts against the edge of the wafer 100 and aligns the central axis X-X of the wafer 100 with the central axis X'-X' of the second support region 422. The raised portion 440 can refer to the above Figures 2a to 2eThe described raised portion 240. In some embodiments, the raised portion 440 faces the lower chamber 410 and is near the lower surface 424 of the second support region 422. In some embodiments, the raised portion 440 includes a plurality of bumps that are evenly distributed around the wafer 100 and abut against the edge region of the wafer 100. The bumps can be referred to the bumps 342 described above Figures 3a to 3d The described bumps 342.

[0065] In some embodiments of the device 400 or any combination of the foregoing embodiments, the raised portion 440 includes an inner surface 442 that is angularly inclined relative to the central axis X'-X' of the second support region 442, and the inner surface 442 abuts against the edge region of the wafer 100. Refer to Figures 4a to 4d , the inner surface 442 faces the wafer 100 and contacts the edge of the wafer 100. The inner surface 442 is inclined at an angle γ relative to the reference axis Z-Z. The range of the angle γ can be within 20° - 90°. The reference axis Z-Z is parallel to the central axis X'-X' of the second support region 442. In some embodiments, the inner surface 442 of the raised portion 440 contacts and abuts against the edge of the wafer 100, so that the central axis X-X of the wafer 100 can be aligned with the central axis X'-X' of the second support region 422. In some embodiments, the inner surface 442 of the raised portion 440 can push the wafer 100 so that the central axis X-X of the wafer 100 overlaps with the central axis X'-X' of the second support region 422.

[0066] In some embodiments of the device 400 or any combination of the foregoing embodiments, refer to Figure 4a , 4c and 4e, the first channel 450 is formed by the edge region 414 of the lower chamber 410 and provides a first channel space 452 for the flow of one or more chemical fluids. The first channel 450, the edge region 414 of the lower chamber 410, and the first channel space 452 of the first channel 450 can be respectively referred to the first channel 250, the edge region 214 of the lower chamber 220, and the first channel space 252 of the first channel 250 described above. In some embodiments, the aisle 460 is located between the upper chamber 420 and the lower chamber 410 and connects the first space 432 with the first channel space 452 for one or more chemical fluids to flow from the first space 432 to the first channel space 452 through the aisle 460. The aisle 460 can be referred to the aisle 260 described above Figures 2a to 2f The described first channel 250, the edge region 214 of the lower chamber 220, and the first channel space 252 of the first channel 250. In some embodiments, the aisle 460 is located between the wafer 100 and the first upper surface 462 of the lower chamber 410. As Figures 2a to 2f shown above, the aisle 460 is located between the wafer 100 and the first upper surface 462 of the lower chamber 410. As Figure 4c shown, the first upper surface 462 is located between the first channel 430 and the first channel 450. Figure 4c and 4e shown, the first upper surface 462 is located between the first channel 430 and the first channel 450.

[0067] In some embodiments of apparatus 400 or any combination of the foregoing embodiments, with reference to Figures 4a to 4c and 4e, the lower chamber 420 includes a first through-hole 470 such that one or more chemical fluids flow between the first space 432 and the exterior of the apparatus 400. The first through-hole 470 may refer to the first through-hole 270 described above Figures 2a to 2e In some embodiments, the lower chamber 420 further includes one or more first through-holes that are substantially the same as the first through-hole 470 (such as Figure 4a and 4e the secondary first through-hole 472 shown). The arrangement of the one or more first through-holes may refer to Figure 2a and 2e described.

[0068] In some embodiments of apparatus 400 or any combination of the foregoing embodiments, with reference to Figure 4a , 4b and 4e, the second channel 480 is located in the edge region of the first support region 412 and provides a second space 482 for etching the edge region of the wafer 100 using one or more chemical fluids. The second channel 480 may refer to the second channel 280 described in Figure 2b , 2c and 2f above. In some embodiments, the first channel 430 and the second channel 480 may be connected by an aisle 484 such that one or more chemical fluids flow between the first space 432 in the first channel 430 and the second space 482 in the second channel 480. Referring to Figure 4b and 4c , the aisle 484 connecting the first channel 430 and the second channel 480 is formed by the wafer 100 and the first support region 412 of the lower chamber 410. One or more chemical fluids may flow between the first space 432 and the second space 482 through the aisle 484. In some embodiments, one or more chemical fluids may flow from the second space 482 through the aisle 484, the first space 432, and the aisle 460 to the first channel space 452.

[0069] In some embodiments of apparatus 400 or any combination of the foregoing embodiments, with reference to Figure 4a , 4b and 4e, the lower chamber 410 includes a second through-hole 490 such that one or more chemical fluids flow between the second space 482 and the exterior of the apparatus 400. The second through-hole 490 may refer to the second through-hole 290 described in Figures 2a-2c In some embodiments, the lower chamber 410 further includes one or more second through-holes that are substantially the same as the second through-hole 490 (such as Figure 4a and 4e the secondary second through-hole 492 shown). The arrangement of the one or more first through-holes may refer to the aboveFigure 2a Arrangement of one or more first through-holes described.

[0070] The present invention can improve the accuracy and uniformity of wafer edge corrosion by using a raised portion, and can obtain a flat surface of the wafer substrate layer by scientifically selecting the chemical fluid composition for corrosion and controlling the flow rate of the chemical fluid and the contact time with the wafer edge, which facilitates subsequent process operations of the wafer. At the same time, the cost of processing operations can be saved. It can selectively process the wafer edge surface, especially for precise control of the wafer edge corrosion area.

[0071] In the above-described embodiments, the raised portion is provided on the upper chamber as an example. In other embodiments, the raised portion may also be provided on the lower chamber. Of course, in some embodiments, other positioning structures may also be provided to abut against the outer end of the wafer edge and align the central axis of the wafer with the central axis of the second support area.

[0072] Figure 5 For the system 500 example in the present invention, it includes a semiconductor processing device 510 and a material storage device 520. The device 510 can refer to any one of the devices 200, 300, and 400 described above Figures 2a-2f 、3a - 3e and 4a - 4e. The device 510 includes a lower chamber having a first support area for supporting a wafer and an upper chamber having a second support area; the upper chamber is closed with the lower chamber to fix the wafer between the first support area and the second support area; a first channel is located in the edge area of the first support area or the second support area, and the first channel provides a first space to corrode the edge area of the wafer by one or more chemical fluids. In some embodiments, the upper chamber includes a raised portion that abuts against the wafer edge to align the central axis of the wafer with the central axis of the second support area. The material storage device 520 is connected to the device 510 and is a device for storing one or more chemical fluids and transferring one or more chemical fluids between the device 510 and the material storage device 520. In some embodiments, one or more chemical fluids may be selected from H3PO4, HF, HCl, HNO3, H2O2, or any combination thereof.

[0073] In some embodiments of the system 500 or any combination of the foregoing embodiments, the raised portion is adjacent to the second support area and extends toward the lower chamber. The central axis of the wafer is perpendicular to the upper surface of the wafer, the central axis of the second support area is perpendicular to the lower surface of the upper chamber, and the upper surface of the wafer is parallel to the lower surface of the second support area. In some embodiments, the raised portion includes a closed loop around the wafer, and the raised portion uniformly abuts against the edge area of the wafer to overlap the central axis of the wafer with the central axis of the second support area.

[0074] In some embodiments of system 500 or any combination of the foregoing embodiments, the raised portion is adjacent to the second support region and extends toward the lower chamber. The central axis of the wafer is perpendicular to the upper surface of the wafer, the central axis of the second support region is perpendicular to the lower surface of the upper chamber, and the upper surface of the wafer is parallel to the lower surface of the second support region. In some embodiments, the raised portion includes a plurality of bumps, which are annularly distributed around the wafer and are used to uniformly abut against the edge region of the wafer.

[0075] In some embodiments of system 500 or any combination of the foregoing embodiments, a first channel exists in the edge region of the lower chamber and provides a first channel space for one or more chemical fluids to flow through. In some embodiments, a channel is formed between the upper chamber and the lower chamber to connect the first space with the first channel space, so that one or more chemical fluids flow from the first space to the first channel space through the channel. In some embodiments, a second channel exists in the edge region of the upper chamber and is located above the first channel. In some embodiments, an elastic member can be added between the first channel and the second channel to prevent one or more chemical fluids from flowing from the first space to the first channel space.

[0076] In some embodiments of system 500 or any combination of the foregoing embodiments, system 500 includes a control device 530. The control device 530 can complete the communication and control of the device 510 and the material storage device 520. For example, the control device 530 can control the movement of the upper chamber between a first position for loading / unloading the wafer and a second position for closing the upper chamber and the lower chamber to process the wafer; it can control the flow rate and flow direction of one or more chemical fluids. The control device 530 can detect the flow rate, flow direction, state of one or more chemical fluids, and the faults of the device 510. In some embodiments, the control device can include a PLC, a controller, a sensor, a storage device (such as a memory, a hard disk drive, an SSD, etc.).

[0077] Figure 6 An exemplary method 600 for processing the edge region of the semiconductor wafer 100 by the device of the embodiment of the present invention. This method can adopt Figures 2a-2f any one of the devices 200, 300, 400, or 500 described in FIGS. 3a - 3e, 4a - 4e, and 5.

[0078] In an embodiment, as Figure 6In step 602, device 200 (or device 300, device 400, or device 500) receives a wafer and places it on the first support area of the lower chamber. In step 604, the device closes its upper chamber with its lower chamber to fix the wafer between the first support area and the second support area of the upper chamber. In step 606, an edge area of the first support area or the second support area forms a first channel, and the first channel provides a first space. In step 608, the device uses a raised portion to abut against the edge of the wafer and aligns the central axis of the wafer with the central axis of the second support area. In step 610, the device injects one or more chemical fluids into the first space to etch the edge area of the wafer.

[0079] In some embodiments of method 600 or any combination of the foregoing embodiments, in step 602, the wafer is placed by a wafer transfer device on the first support area of the lower chamber of device 200 (or device 300, device 400, or device 500). The upper surface of the first support area faces the wafer. The wafer transfer device may place the wafer on the upper surface of the first support area such that a part of the lower surface of the wafer is covered by the upper surface of the first support area. In some embodiments, when the upper chamber of device 200 (or device 300, device 400, or device 500) is in the first position, the wafer may be loaded or unloaded onto the first support area. That is, the wafer may be transferred from the wafer transfer device to the upper surface of the first support area.

[0080] In some embodiments of method 600 or any combination of the foregoing embodiments, in step 604, device 200 (or device 300, device 400, or device 500) may close the upper chamber with the lower chamber to fix the wafer between the first support area and the second support area of the upper chamber. When the upper chamber is in the second position, the lower chamber may be closed with the upper chamber and the wafer is fixed between the lower chamber and the upper chamber to process the edge area of the wafer. The upper chamber includes a second support area facing the lower surface of the wafer. The upper chamber and the lower chamber are closed to place the wafer between the first support area and the second support area. At this time, the wafer may be fixed between the lower surface of the second support area and the upper surface of the first support area.

[0081] In some embodiments of method 600 or any combination of the foregoing embodiments, at step 606, a first channel is formed in an edge region of the first support region or the second support region. The first channel may also be formed on the lower surface of the upper chamber, and the opening of the first channel faces the wafer. In some embodiments, the first channel provides a first space for processing the edge region of the wafer. For example, one or more chemical fluids flow in the first channel and etch the edge region of the wafer. In some embodiments, the first channel may be designed as a closed loop. In some embodiments, the first channel may be designed as a circle. The device 200 (or device 300, device 400, or device 500) or the wafer transfer device places the entire or a partial edge region of the wafer in the first space for processing. In some embodiments, the first channel may be designed as an arc with an angle less than 360 degrees. The device 200 (or device 300, device 400, or device 500) or the wafer transfer device places a partial edge region of the wafer in the first space for processing.

[0082] In some embodiments of method 600 or any combination of the foregoing embodiments, at step 608, a raised portion is provided on the upper chamber or the lower chamber of the device 200 (or device 300, 400, or 500). The device may use the raised portion to abut against the edge of the wafer. During the movement of the upper chamber from the first position to the second position, the raised portion contacts the edge of the wafer. Then, the raised portion abuts against the edge of the wafer and pushes the wafer to move on the upper surface of the first support region of the lower chamber. When the upper chamber and the lower chamber are closed, the wafer is fixed on the upper surface of the first support region, and the central axis X-X of the wafer is parallel to the central axis X'-X' of the second support region. The distance between the central axis X-X of the wafer and the central axis X'-X' of the second support region may be in the range of 0 mm to 0.1 mm. In some embodiments, the raised portion may be adjacent to the second support region and extend towards the lower chamber. In one embodiment, the raised portion is adjacent to the first channel.

[0083] In some embodiments, the raised portion includes an inner angle facing the central axis X'-X' of the second support region. The inner angle is formed by the intersection of the inner surface of the raised portion and the inner surface of the first channel and faces the central axis X'-X' of the second support region. In one embodiment, the inner angle abuts against the edge region of the wafer. When the upper chamber moves from the first position to the second position, the inner angle of the raised portion contacts the edge of the wafer, then abuts against the edge of the wafer, and pushes the wafer. In some other embodiments, the inner surface of the raised portion contacts the edge of the wafer, then abuts against the edge of the wafer, and pushes the wafer.

[0084] In some embodiments of method 600 or any combination of the foregoing embodiments, at step 610, device 200 (or device 300, device 400, or device 500) may inject one or more chemical fluids into the first space for etching the edge region of the wafer. The one or more chemical fluids flow around the edge of the wafer in the first space and etch the edge region of the wafer exposed to the first space. In some embodiments, the device includes through holes connecting the first space to the exterior of the device. The one or more chemical fluids may flow into the first space through the through holes. In some embodiments, the one or more chemical fluids may flow from the first space to the exterior of the device through the through holes. In other embodiments, the device includes two through holes, each connecting the first space to the exterior of the device respectively. The two through holes are spaced apart. The one or more chemical fluids flow into the first space through one through hole and flow out of the device from the first space through the other through hole.

[0085] As mentioned in the background art, since the vast majority of materials have a certain coefficient of thermal expansion. A semiconductor wafer edge processing device made of a material with a coefficient of thermal expansion may have different etching widths at the edges of the wafer during manufacturing and use due to the difference between the manufacturing temperature and the use temperature, the temperature difference change during transportation, or the change of other unknown factors. In addition, different processes and manufacturers often require different etching widths at the edges of the wafer. For example, some etching widths are 0.5 mm, some are 0.6 mm, some are 0.3 mm, etc. In order to meet the requirements of different processes and manufacturers, it is necessary to manufacture different semiconductor wafer edge processing devices, which is very costly.

[0086] To solve these problems, the present invention provides a semiconductor processing device in which the etching width at the edge of the wafer can be finely adjusted. As Figure 7 shown, it is a schematic structural diagram of a semiconductor processing device in which the etching width at the edge of the wafer can be finely adjusted in an embodiment of the present invention.

[0087] Figure 7 The semiconductor processing device in Figure 3a is mostly the same in structure as the semiconductor processing device in Figure 7The semiconductor processing device in [description] further includes: a temperature control component 810 disposed adjacent to the upper chamber and a temperature control component 810 disposed adjacent to the lower chamber. The structures of the two temperature control components may be the same or different. The temperature control component 810 can adjust the temperature of the upper chamber 320 and the temperature of the lower chamber 310 by adjusting its own temperature. By using the temperature control component 810 to adjust the temperatures of the upper chamber 320 and the lower chamber 310, the positions of the edges of the first support region and / or the second support region are finely adjusted by the thermal expansion and contraction of the upper chamber 320 and the lower chamber 310, and then the width of the edge region of the wafer 100 extending into the first space 332 is adjusted, and finally the etching width of the edge of the wafer 100 is obtained. Specifically, if the edges of the first support region and / or the second support region expand outward due to the expansion of the upper chamber 320 and the lower chamber 310, the width of the edge region of the wafer 100 extending into the first space 332 will decrease, thereby reducing the etching width of the edge of the wafer 100; if the edges of the first support region and / or the second support region contract inward due to the contraction of the upper chamber 320 and the lower chamber 310, the width of the edge region of the wafer 100 extending into the first space 332 will increase, thereby increasing the etching width of the edge of the wafer 100. It should be noted that the expansion and contraction here are relative. Similarly, Figure 2a and Figure 4a the temperature control component 810 can also be added to the semiconductor processing device shown.

[0088] Due to the provision of the temperature control component 810, the temperature of the upper chamber and the temperature of the lower chamber can be adjusted as needed. By adjusting the temperature of the temperature control component 810, the slight changes in the sizes of the upper chamber and the lower chamber caused by environmental temperature changes or other factors can be reduced, and the etching width of the edge of the wafer can also be actively adjusted. In this way, the same semiconductor processing device can meet various applications with different etching widths of the edge of the wafer, without the need to manufacture multiple semiconductor processing devices for such applications. At the same time, even if the etching width of the edge of the wafer obtained by a semiconductor processing device does not meet the requirements, the etching width of the edge of the wafer obtained can be made to meet the requirements by adjusting the temperature of the temperature control component 810.

[0089] In one embodiment, the temperature control component 810 includes a temperature adjustment component 811 and a diffusion component 812. The diffusion component 812 is disposed between the temperature adjustment component 811 and the upper chamber 320. The temperature adjustment component 811 includes a plurality of electric heating units. The temperature of the temperature adjustment component 811 is controlled by controlling the electric heating units. The diffusion component 812 transfers heat to the upper chamber 320, thereby adjusting the temperatures of the upper chamber 320 and the lower chamber. Specifically, the electric heating units may be electric heating resistance wires.

[0090] The temperature control component 810 may be separately designed from the upper chamber 320 and the lower chamber 310 and assembled together through a connection component, or may be provided integrally. In other embodiments, as needed, the temperature control component 810 may also be disposed only on the lower side of the lower chamber 310 or only on the upper side of the upper chamber 320.

[0091] By providing the temperature control component 810, the requirements for processing, transportation, and installation of the semiconductor processing device can be greatly reduced. At the same time, the corrosion width at the edge of the wafer can be adjusted, which promotes the application of the semiconductor processing device.

[0092] Some embodiments can be regarded as computer program products, including instructions stored on a non-transitory machine-readable medium. These instructions can be used to program a general-purpose or special-purpose processor to perform the described operations. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), such as software, a processing application. The machine-readable medium may include, but is not limited to, magnetic storage media (e.g., floppy disks), optical storage media (e.g., CD-ROMs), magneto-optical storage media, read-only memory (ROM), random access memory (RAM), erasable programmable memory (e.g., EPROM and EEPROM), flash memory, or other types of media suitable for storing electronic instructions. The machine-readable medium may be referred to as a non-transitory machine-readable medium.

[0093] The above description is intended to be illustrative, not restrictive. Although the present invention has been described with reference to specific illustrative examples, it should be understood that the present invention is not limited to the described embodiments. The scope of the present invention should be determined with reference to the claims and the entire scope of equivalents covered by the claims.

[0094] As used herein, the term "an example (embodiment)" or "example (embodiment)" means that a particular feature, structure, or characteristic related to the embodiment can be included in at least one implementation of the present invention. The phrase "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it have to be a separate or alternative embodiment that is mutually exclusive with other embodiments. The terms "a plurality" and "several" in the present invention mean two or more. The term "and / or" in the present invention means "and" or "or". In addition, the terms "first", "second", "third", "fourth", etc. used herein are intended as labels for distinguishing different elements, and may not necessarily have an order meaning according to their numerical designations. Therefore, the terms used herein are for the purpose of describing a particular implementation only and are not intended to be limiting.

[0095] It should also be noted that in some alternative embodiments, the indicated functions / actions may not occur in the order indicated in the figures. For example, depending on the functions / actions involved, two consecutively shown figures may actually be executed substantially simultaneously or sometimes in the reverse order.

[0096] Although method operations are described in a particular order, it should be understood that other operations may be performed between the described operations. The described operation process can be adjusted so that they occur at slightly different times, or the described operations can be distributed across the system. The system allows multiple unrelated programs to be processed simultaneously.

[0097] Many modifications and other embodiments of the present invention will occur to those of ordinary skill in the art having access to the relevant industry knowledge and some of the original data. Accordingly, it should be understood that the present invention is not limited to the specific embodiments disclosed, but also includes other embodiments modified within the scope of the appended claims. In addition, although the foregoing description and the related drawings describe the implementation of specific combinations of elements and functions, within the scope of the appended claims, different combinations of elements and functions through alternative implementations are also included. The appended claims also include combinations of elements and functions different from those explicitly described above. Although specific terms are used herein, they are for general descriptive purposes only and not for limiting purposes.

Claims

1. A semiconductor processing apparatus, characterized in that: It includes: A lower chamber having a first support area for supporting a wafer; An upper chamber having a second support area, wherein when the upper chamber is closed with the lower chamber, the wafer is placed between the first support area and the second support area; A temperature control component disposed adjacent to the upper chamber and / or the lower chamber, which adjusts the temperature of the upper chamber and / or the lower chamber by adjusting its own temperature; A first channel formed in the edge area of the first support area or the second support area, and the first channel provides a first space for circulating one or more chemical fluids for etching the edge area of the wafer; Adjust the temperature of the upper chamber and / or the lower chamber by using the temperature control component, so as to finely adjust the position of the edge of the first support area and / or the second support area by the thermal expansion and contraction of the upper chamber and / or the lower chamber, and further adjust the width of the edge area of the wafer extending into the first space, and finally adjust the etching width of the edge of the wafer.

2. The semiconductor processing apparatus according to claim 1, wherein Wherein the upper chamber and / or the lower chamber includes a positioning structure, and the positioning structure is used to abut against the outer end of the edge of the wafer and align the central axis of the wafer with the central axis of the second support area.

3. The semiconductor processing apparatus according to claim 2, wherein, The positioning structure is disposed on the upper chamber, and the positioning structure is a protruding part, and the protruding part is used to abut against the outer end of the edge of the wafer and align the central axis of the wafer with the central axis of the second support area.

4. The semiconductor processing apparatus according to claim 3, wherein, The protruding part of the upper chamber is adjacent to the second support area and extends downward to the lower chamber. The central axis of the wafer is perpendicular to the upper surface of the wafer, the central axis of the second support area is perpendicular to the lower surface of the upper chamber, and the upper surface of the wafer is parallel to the lower surface of the second support area. The protruding part includes a curved part designed in a ring shape around the outer end of the wafer, and the protruding part uniformly abuts against the outer end area of the edge of the wafer, so that the central axis of the wafer overlaps with the central axis of the second support area.

5. The semiconductor processing apparatus according to claim 3, wherein, The protruding part includes a plurality of bumps, which are evenly distributed in a ring around the outer end of the wafer and are used to evenly abut against the outer end area of the edge of the wafer.

6. The semiconductor processing apparatus according to claim 3, wherein, The protruding part includes an inner surface inclined at an angle with the central axis of the second support area, and the inner surface abuts against the outer end area of the edge of the wafer. The protruding part includes an inner angle facing the central axis of the second support area, and the inner angle abuts against the outer end area of the edge of the wafer.

7. The semiconductor processing apparatus according to claim 1, wherein, Wherein the first channel is located in the edge area of the lower chamber and provides a first channel space for flowing one or more chemical fluids. At the same time, an aisle is formed between the upper chamber and the lower chamber, and the aisle connects the first space and the first channel space, so that one or more chemical fluids flow from the first space into the first channel space through the aisle.

8. The semiconductor processing apparatus according to claim 7, wherein, Wherein the second channel is formed in the edge area of the upper chamber and is located above the first channel. An elastic member is disposed between the first channel and the second channel, and the elastic member is used to block one or more chemical fluids from flowing from the first space to the first channel space. A first channel is formed in the edge area of the second support area, and one or more chemical fluids flow between the first space and the outside of the device through a first through hole located in the upper chamber. Wherein a second channel is formed in the edge area of the first support area, providing a second space for circulating one or more chemical fluids for etching the edge area of the wafer. The lower cavity provides a second through-hole to enable the circulation of one or more chemical fluids between the second space of the lower cavity and the outside of the device. The edge region of the first support area forms a first channel. The lower chamber includes a first through-hole, and one or more chemical fluids flow through the first through-hole located in the lower chamber between the first space and the outside of the device.

9. The semiconductor processing device according to claim 1, wherein: The temperature control component includes a temperature adjustment component and a diffusion component. The diffusion component is disposed between the temperature adjustment component and the upper chamber and / or the lower chamber. The temperature adjustment component includes a plurality of electric heating units.

10. A semiconductor processing system, comprising: A semiconductor processing device according to any one of claims 1-9; A material storage device connected to the semiconductor processing device, the material storage device being configured to store and exchange and transfer one or more chemical fluids with the semiconductor processing device.

11. The semiconductor processing system according to claim 10, wherein: The upper chamber and / or the lower chamber includes a positioning structure configured to abut against the outer edge of the wafer and align the central axis of the wafer with the central axis of the second support area. The positioning structure is disposed on the upper chamber. The positioning structure is a raised portion configured to abut against the outer edge of the wafer and align the central axis of the wafer with the central axis of the second support area. The raised portion is adjacent to the second support area and extends towards the lower chamber. The central axis of the wafer is perpendicular to the upper surface of the wafer, the central axis of the second support area is perpendicular to the lower surface of the upper chamber, the upper surface of the wafer is parallel to the lower surface of the second support area. The raised portion includes a closed-loop portion designed around the outer edge of the wafer, and the raised portion uniformly abuts against the outer edge area of the wafer to overlap the central axis of the wafer with the central axis of the second support area.

12. The semiconductor processing system according to claim 10, wherein: The upper chamber and / or the lower chamber includes a positioning structure configured to abut against the outer edge of the wafer and align the central axis of the wafer with the central axis of the second support area. The positioning structure is disposed on the upper chamber. The positioning structure is a raised portion configured to abut against the outer edge of the wafer and align the central axis of the wafer with the central axis of the second support area. The raised portion is adjacent to the second support area and extends towards the lower chamber. The central axis of the wafer is perpendicular to the upper surface of the wafer, the central axis of the second support area is perpendicular to the lower surface of the upper chamber, the upper surface of the wafer is parallel to the lower surface of the second support area; the raised portion includes a plurality of protrusions evenly distributed in a ring around the outer edge of the wafer for uniformly abutting against the outer edge area of the wafer.

13. The semiconductor processing system according to claim 10, wherein: The first channel is located in the edge region of the lower chamber and provides a first channel space for one or more chemical fluids. Meanwhile, an aisle is formed between the upper chamber and the lower chamber, and this aisle connects the first space and the first channel space, enabling one or more chemical fluids to flow from the first space into the first channel space through this aisle. The second channel is formed in the edge region of the upper chamber and is located above the first channel. An elastic component is designed to be placed between the first channel and the second channel, and this elastic component is used to block one or more chemical fluids from flowing from the first space to the first channel space.

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