Cavity structure in bulk silicon and method of making the same

Abstract

The application provides a cavity structure in bulk silicon and a preparation method thereof. The preparation method comprises the following steps: providing a silicon substrate; etching a first porous layer on the upper surface of the silicon substrate; etching a second porous layer; removing the second porous layer by etching to form a cavity connected with the first porous layer; and forming a thin film layer on the upper surface of the silicon substrate and the upper surface of the first porous layer. The preparation method is simple, efficient and low in cost. Moreover, the size of the cavity and the uniformity of the thickness of the silicon thin film can be effectively controlled through the design of the first porous layer and the second porous layer.

Description

Technical Field

[0001] This invention relates to the field of electronic information technology, specifically to a bulk silicon internal cavity structure and its preparation method. Background Technology

[0002] The silicon cavity is a core functional structure in MEMS sensors, including pressure sensors, flow sensors, acoustic sensors, and ultrasonic transducers. Taking MEMS absolute pressure sensors as an example, common absolute pressure sensors have piezoresistive, capacitive, and resonant measurement methods. All three methods require a silicon thin film of a certain thickness to be suspended above the sealed vacuum cavity inside the bulk silicon to achieve the measurement of pressures in different ranges.

[0003] Current methods for fabricating silicon cavity structures typically involve back-side wet etching and thinning to create a cavity structure with a certain thickness of silicon film. This is followed by vacuum sealing of the cavity using methods such as silicon-glass anodic bonding or silicon-silicon direct bonding. Because these processes require fabrication on both sides of the silicon wafer and the corresponding structures must be aligned on both sides, coupled with the wafer-level bonding process required for sealing the entire vacuum cavity, the overall fabrication yield is low and the fabrication cost is high. Furthermore, ensuring the uniformity of the silicon film thickness is also a challenge that needs to be addressed during the process. Summary of the Invention

[0004] In order to overcome the shortcomings of the prior art, the main objective of the present invention is to provide a bulk silicon cavity structure and its preparation method. The preparation method is simple, efficient and low cost. Moreover, the size of the cavity and the uniformity of the silicon film thickness can be effectively controlled by the design of the first porous layer and the second porous layer.

[0005] To achieve the above objectives, according to a first aspect of the present invention, a method for preparing a bulk silicon internal cavity structure is provided.

[0006] The fabrication method of this bulk silicon internal cavity structure includes the following steps:

[0007] Provide silicon substrates;

[0008] A plurality of first pores spaced apart are etched on the upper surface of the silicon substrate to generate a first porous layer;

[0009] The silicon substrate located below the first porous layer is etched to form a plurality of spaced second pores, thereby generating a second porous layer; wherein the pore diameter of the first pore is larger than the pore diameter of the second pore, and the first pore is connected to the second pore;

[0010] The second porous layer is removed by etching to form a cavity that connects to the first pores;

[0011] A thin film layer is formed covering the upper surface of the silicon substrate and the upper surface of the first porous layer.

[0012] Furthermore, the first pore is a pore with a micron pore size, and the second pore is a pore with a nanon pore size.

[0013] Furthermore, the first pore and the second pore are formed using an electrochemical etching process;

[0014] Preferably, the etching current for forming the first pore is 10–100 mA / cm. 2 ;

[0015] Preferably, the etching current for forming the second pore is 10–100 mA / cm. 2 .

[0016] Furthermore, the etching solution that forms the first pore is an aqueous solution of hydrofluoric acid; or an aqueous solution of hydrofluoric acid containing a surfactant; or a hydrofluoric acid solution containing an organic solvent.

[0017] Preferably, the hydrofluoric acid aqueous solution contains 5-10% hydrofluoric acid by mass.

[0018] Preferably, the surfactant includes, but is not limited to, hexadecyltrimethylammonium chloride;

[0019] Preferably, the amount of surfactant added is 10. -3 mol / L;

[0020] Preferably, the organic solvent includes, but is not limited to, anhydrous ethanol, N,N-dimethylformamide, and dimethyl sulfoxide;

[0021] The preferred volume ratio of the hydrofluoric acid solution to the organic solvent is (1:3) to (1:9).

[0022] Furthermore, the etching solution that forms the second pore is a mixed solution of hydrofluoric acid and anhydrous ethanol;

[0023] Preferably, the volume ratio of the hydrofluoric acid to the anhydrous ethanol is 3:2.

[0024] Furthermore, the etching solution used to remove the second porous layer is a mixed solution of tetramethylammonium hydroxide solution, deionized water and anhydrous ethanol;

[0025] Preferably, the volume ratio of the tetramethylammonium hydroxide solution, the deionized water, and the anhydrous ethanol is 1:5:1.

[0026] Furthermore, the thin film layer is formed by chemical vapor deposition; or the thin film layer is grown on the outside of the first porous layer by epitaxial growth.

[0027] Preferably, the material of the thin film layer is polycrystalline silicon or monocrystalline silicon;

[0028] Preferably, the thickness of the thin film layer is ≥ 1 / 2 the pore diameter of the first pore.

[0029] Furthermore, it also includes forming a mask layer on the upper surface of the silicon substrate before forming the first porous layer, and forming an etching window on the mask layer.

[0030] Furthermore, the materials of the mask layer include, but are not limited to, silicon nitride, polycrystalline silicon / silicon oxide composite materials, gold, tungsten, and silicon carbide.

[0031] To achieve the above objectives, according to a second aspect of the present invention, a bulk silicon internal cavity structure is provided.

[0032] The bulk silicon cavity structure prepared by the above method includes a silicon substrate, the silicon substrate having a cavity inside, and a plurality of first pores spaced apart on the upper surface of the silicon substrate, the plurality of first pores being located above the cavity and communicating with the cavity; a thin film layer is covered on the upper surface of the silicon substrate, and the thin film layer seals the upper ports of the plurality of first pores.

[0033] The preparation method in this invention solves the problems of low yield, high preparation cost, difficulty in controlling the thickness of silicon thin films and poor uniformity that exist in conventional preparation methods, and is simple and efficient. Attached Figure Description

[0034] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0035] Figure 1 A flowchart illustrating the fabrication process of the bulk silicon internal cavity structure provided in the embodiments of the present invention;

[0036] Figures 2-6 This is a schematic diagram illustrating the process of forming the bulk silicon cavity structure in an embodiment of the present invention.

[0037] In the picture:

[0038] 100. Silicon substrate; 200. Mask layer; 300. First porous layer; 400. Second porous layer; 500. Thin film layer;

[0039] 1. Etched window; 2. Cavity. Detailed Implementation

[0040] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0041] This invention provides a process flow based on an electrochemical etching method to prepare silicon internal cavity structures.

[0042] The fabrication method provided by this invention only requires processing on one side of the silicon wafer to achieve precise control of the thin film thickness above the cavity, thus realizing the formation of the cavity within the silicon and the release of the thin film structure. Furthermore, the etching solution used in this invention has excellent compatibility with traditional CMOS processes and can be used to manufacture integrated devices compatible with both ICs and MEMS.

[0043] According to a specific embodiment of the present invention, a method for preparing a bulk silicon internal cavity structure is provided.

[0044] Figure 1 A flowchart illustrating the fabrication process of the bulk silicon internal cavity structure is shown.

[0045] Figures 2-6 A schematic diagram illustrating the fabrication process of the bulk silicon internal cavity structure is shown.

[0046] Provide such as Figure 2 The silicon substrate 100 shown.

[0047] In embodiments of the present invention, a moderately doped P-type can be selected. <100> A silicon wafer with a specific crystal orientation is used as a substrate.

[0048] Continue to refer to Figure 2 The silicon substrate 100 is pretreated by depositing an electrochemical etching mask on the upper surface of the silicon substrate 100 to form a mask layer 200.

[0049] Continue to refer to Figure 2 The mask layer 200 on the upper surface of the silicon substrate 100 is patterned using photolithography and etching processes, and an etching window 1 is formed on the mask layer 200 to expose the part where the cavity 2 needs to be fabricated.

[0050] In embodiments of the present invention, the material of the mask layer 200 includes, but is not limited to, silicon nitride, polycrystalline silicon / silicon oxide composite material, gold / tungsten, silicon carbide, etc.

[0051] like Figure 3 As shown, a plurality of first pores spaced apart are etched on the upper surface of the silicon substrate 100 to generate a first porous layer 300.

[0052] As an embodiment of the present invention, an electrochemical etching process is performed on the upper surface of the silicon substrate 100 to first prepare a plurality of first pores with micron-sized apertures to form a first porous layer 300.

[0053] The etching current is set to 10–100 mA / cm. 2 Within the range.

[0054] In one embodiment of the present invention, the etching current is set to 10 mA / cm. 2 .

[0055] In this invention, the thickness of the first porous layer 300, i.e. the longitudinal depth, can be controlled according to the etching time, such as controlling the depth of the first porous layer 300 to be 5μm or 10μm, etc., without specific limitation.

[0056] In one embodiment of the present invention, the etching solution is an aqueous solution of hydrofluoric acid.

[0057] In another embodiment of the invention, the etching solution is an aqueous solution of hydrofluoric acid containing a surfactant. A certain proportion (e.g., 10) is added to the aqueous hydrofluoric acid solution. -3 A surfactant (mol / L) is used to improve the uniformity of etching.

[0058] In another embodiment of the present invention, the etching solution is a hydrofluoric acid solution containing an organic solvent, or it can be understood as a mixed solution of an organic solvent and a hydrofluoric acid solution.

[0059] In embodiments of the present invention, the organic solvents include, but are not limited to, anhydrous ethanol, DMF (N,N-dimethylformamide), and DMSO (dimethyl sulfoxide).

[0060] In embodiments of the present invention, the volume ratio of hydrofluoric acid solution to organic solvent is in the range of (1:3) to (1:9).

[0061] In embodiments of the present invention, the mass fraction of hydrofluoric acid in the hydrofluoric acid aqueous solution is in the range of 5-10%.

[0062] In embodiments of the present invention, the surfactants include, but are not limited to, hexadecyltrimethylammonium chloride (CTAC).

[0063] In an embodiment of the present invention, the amount of surfactant added is 10. -3 mol / L.

[0064] like Figure 4 As shown, the silicon substrate 100 located below the first porous layer 300 is etched to form a plurality of second pores spaced apart, thereby generating a second porous layer 400.

[0065] As an embodiment of the present invention, the etching solution is switched to continue the electrochemical etching process on the silicon substrate 100, and a plurality of second pores with nanopore size are etched under the first porous layer 300 to form a second porous layer 400.

[0066] The etching current is set to 10–100 mA / cm. 2 Within the range.

[0067] In one embodiment of the present invention, the etching current is set to 100 mA / cm. 2 .

[0068] In one embodiment of the present invention, the etching solution is a mixed solution of hydrofluoric acid and anhydrous ethanol.

[0069] In an embodiment of the present invention, the volume ratio of hydrofluoric acid to anhydrous ethanol is 3:2.

[0070] In this invention, the thickness of the second porous layer 400, i.e. the longitudinal depth, can also be precisely controlled according to the etching time, without being specifically limited.

[0071] It is worth mentioning that, in this invention, when etching to form the second porous layer 400, a specific ratio of etching solution is used, the proportion of hydrofluoric acid is increased, and due to the driving effect of the reaction by the applied etching current, the corrosion reaction is formed at the interface between the first porous layer 300 and the bulk silicon, generating the nanoscale second porous layer 400. In the already formed first porous layer 300 structure, there is basically no etching current passing through, and the effect of this etching process on the first porous layer 300 can be ignored, which can be effectively controlled without causing substantial impact on the overall structure.

[0072] like Figure 5 As shown, the second porous layer 400 is removed by corrosion to form a cavity 2 that connects to the first pore.

[0073] As an embodiment of the present invention, the sample obtained in the previous step is immersed in a CMOS process-compatible etching solution to remove the second porous layer 400.

[0074] It is worth mentioning that, in the present invention, a specific ratio of corrosion solution is used when removing the second porous layer 400. The second porous layer 400 is completely removed by corrosion due to its small pore size and high porosity. The effect of the corrosion solution on the first porous layer 300 is negligible and can be effectively controlled without causing substantial impact on the overall structure.

[0075] Moreover, the mask layer 200 is removed at the same time as the second porous layer 400 is removed.

[0076] In an embodiment of the present invention, the corrosion solution is a mixed solution of tetramethylammonium hydroxide (TMAH) solution, deionized water and anhydrous ethanol.

[0077] Adding a certain proportion of anhydrous ethanol to the corrosion solution can accelerate the removal of the second porous layer 400.

[0078] In an embodiment of the present invention, the volumes of TMAH solution, deionized water, and anhydrous ethanol are 1:5:1.

[0079] In one specific embodiment of the present invention, the volume ratio of tetramethylammonium hydroxide solution, deionized water and anhydrous ethanol is 1:5:1.

[0080] It should be noted that in this invention, the second porous layer 400 serves as a sacrificial layer. Therefore, the size of the silicon cavity 2 can be determined by controlling the thickness of the generated second porous layer 400. For example, the longitudinal depth of the cavity 2 can be controlled to be 10 μm or 20 μm.

[0081] like Figure 6 As shown, a thin film layer 500 is formed on the upper surface of the silicon substrate 100 and the upper surface of the first porous layer 300 to close the upper port of the first porous layer 300, forming an integral silicon cavity.

[0082] In embodiments of the present invention, the material of the thin film layer 500 can be polycrystalline silicon or monocrystalline silicon.

[0083] In one embodiment of the present invention, a thin film layer 500 is formed using chemical vapor deposition. The chemical vapor deposition method can be low-pressure chemical vapor deposition (LPCVD).

[0084] In another embodiment of the present invention, a thin film layer 500 is formed on the outside of the first porous layer 300 by an epitaxial process.

[0085] In this invention, since the first porous layer 300 is silicon in the form of a single crystal, an epitaxial process can be used to grow a layer of single crystal silicon on the outside of the first porous layer 300.

[0086] It is worth mentioning that the thickness of the thin film layer 500 is ≥1 / 2 the pore diameter of the first pore, so as to better seal the upper port of the first porous layer 300.

[0087] According to a specific embodiment of the present invention, a bulk silicon internal cavity structure is also provided.

[0088] The bulk silicon cavity structure in this invention is prepared using the method described above.

[0089] like Figure 6As shown, the bulk silicon cavity structure includes a silicon substrate 100, the interior of which has a cavity 2. The upper surface of the silicon substrate 100 has a plurality of spaced first pores, which are located above the cavity and connected to the cavity 2. A thin film layer 500 covers the upper surface of the silicon substrate 100 and closes the upper ports of the plurality of first pores, thereby forming an integral silicon cavity structure.

[0090] It should be noted that the term "comprising" and any variations thereof in the specification and claims of this invention are intended to cover non-exclusive inclusion, for example, including a series of components that are not necessarily limited to those explicitly listed, but may include other components that are not explicitly listed or that are inherent to the component.

[0091] In this invention, the terms "upper," "lower," "bottom," "top," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing the invention and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0092] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in certain situations to indicate a dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0093] Furthermore, the descriptions of "first," "second," etc., involved in this invention are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

[0094] Furthermore, the technical solutions of the various embodiments can be combined with each other, but only if they are feasible for those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0095] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a cavity structure in bulk silicon, characterized by, The method comprises the following steps: providing a silicon substrate; etching a plurality of first pores in the upper surface of the silicon substrate by an electrochemical etching process to form a first porous layer; The etching current for forming the first aperture is 10 mA / cm 2 , and the etching solution is an aqueous hydrofluoric acid solution containing a surfactant, the amount of the surfactant added being 10 -3 mol / L. etching the silicon substrate under the first porous layer by an electrochemical etching process to form a plurality of second pores to form a second porous layer; wherein the first pores have a larger pore diameter than the second pores, and the first pores are connected to the second pores; The etching current for forming the second aperture is 100 mA / cm 2 The etching solution is a mixed solution of hydrofluoric acid and anhydrous ethanol, and the volume ratio of the hydrofluoric acid to the anhydrous ethanol is 3:

2. removing the second porous layer by etching to form cavities connected to the first pores; the etching solution used to remove the second porous layer is a mixed solution of tetramethylammonium hydroxide solution, deionized water and anhydrous ethanol, and the volume ratio of the tetramethylammonium hydroxide solution, the deionized water and the anhydrous ethanol is 1:5:1; forming a thin film layer on the upper surface of the silicon substrate and the upper surface of the first porous layer; the thickness of the thin film layer is greater than or equal to 1 / 2 of the pore diameter of the first pores.

2. The production method according to claim 1, wherein The first pores are pores with micrometer pore diameters, and the second pores are pores with nanometer pore diameters.

3. The production method according to claim 1, wherein The mass fraction of hydrofluoric acid in the aqueous hydrofluoric acid solution is 5-10%.

4. The production method according to claim 1, wherein The surfactant comprises cetyltrimethylammonium chloride.

5. The production method according to claim 1, wherein The thin film layer is formed by a chemical vapor deposition method, or is formed by growing on the outside of the first porous layer by an epitaxy process.

6. The production method according to claim 5, wherein The material of the thin film layer is polycrystalline silicon or monocrystalline silicon.

7. The production method according to claim 1, wherein The method further comprises forming a mask layer on the upper surface of the silicon substrate before forming the first porous layer, and forming an etching window on the mask layer.

8. The production method according to claim 7, wherein The material of the mask layer comprises silicon nitride, polycrystalline silicon / silicon oxide composite material, gold, tungsten or silicon carbide.

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