An APD focal plane device timing accuracy test system for active three-dimensional imaging

Abstract

The application discloses an APD focal plane device timing precision test system for active three-dimensional imaging, which comprises a control unit, a laser emission unit, a high-speed data acquisition unit and a software unit. The control unit provides timing and function control signals, multi-channel adjustable voltage signals and timing reference slope signals for the APD focal plane device. The laser emission unit is used for outputting flat-top monochromatic laser pulses with adjustable pulse energy. The high-speed data acquisition unit acquires timing voltage and intensity voltage. The software unit processes the timing voltage and intensity voltage signals, analyzes the timing precision of each pixel of the APD focal plane device, adjusts the slope length of the timing reference slope signal through the control unit, simulates the timing range of the APD focal plane device, and gradually adjusts the time difference between the slope starting time of the timing reference slope signal and the laser pulse emission time, so as to realize high-precision testing of the timing precision of the APD focal plane device at different timing moments within the timing range.

Description

Technical Field

[0001] This invention belongs to the field of photoelectric detector testing, and in particular relates to a timing accuracy testing system for APD focal plane devices used in active three-dimensional imaging. Background Technology

[0002] Active 3D imaging technology boasts advantages such as long detection range, high ranging accuracy, and high imaging resolution, and is widely used in remote sensing mapping, intelligent sensing, Earth observation, and military target detection, imaging, and tracking. Active 3D imaging technology actively emits laser signals towards the target, uses a photodetector to detect the reflected laser echo signal, measures the target distance by measuring the laser signal's time of flight, and measures the target's reflection characteristics by measuring the intensity of the laser echo signal. Avalanche photodiodes (APDs) focal plane arrays possess high internal gain, high sensitivity, low noise, and high resolution, making them promising high-performance photodetectors for active 3D imaging. Timing methods for APD focal plane arrays are mainly divided into analog voltage quantization time and digital quantization time. The test system proposed in this invention primarily targets APD focal plane arrays based on ramp signals using analog voltage quantization time. The working principle of this type of device is described below:

[0003] The APD focal plane array receives a light signal and generates photoelectrons. Under a certain reverse bias voltage, charge carriers in the PN junction gain kinetic energy and collide with atoms in the crystal lattice, exciting valence band electrons to the conduction band and forming new electron-hole pairs. The charge carriers moving within the depletion layer undergo avalanche multiplication due to collisional ionization. This forms a photocurrent that flows into a capacitive feedback transimpedance amplifier, which has two feedback capacitors: a small capacitor C3d and a large capacitor C2d. When the photocurrent flows into the capacitive feedback transimpedance amplifier, the small capacitor C3d begins to integrate, and the output voltage of the capacitive feedback transimpedance amplifier increases rapidly. The output terminal of the capacitive feedback transimpedance amplifier is connected to the non-inverting input of a voltage comparator. When the output voltage of the capacitive feedback transimpedance amplifier exceeds the threshold of the voltage comparator, the latch module is triggered. On the one hand, it locks the current ramp voltage value, and the sample-and-hold circuit operates in a holding state, obtaining a voltage value related to time information, called the timing voltage. On the other hand, it controls the large capacitor C2d to close, at which point the circuit enters the large capacitor integration mode until the integration time ends, obtaining the intensity voltage corresponding to the laser energy. The integration time is controlled by an external circuit. By acquiring the timing voltage, time measurement is achieved. Based on the time-of-flight ranging principle, the target distance is measured, thereby realizing three-dimensional imaging. With the development of active three-dimensional imaging technology, target detection accuracy is becoming increasingly higher. Timing accuracy is an important indicator for measuring the testing and conversion capability of laser pulse time of flight, and it is also an important indicator for measuring the imaging accuracy of APD focal plane devices. Therefore, the requirements for the timing accuracy of APD focal plane devices are also increasing accordingly.

[0004] Several solutions and principle-based testing platforms have been proposed and developed for testing systems of APD focal plane array devices both domestically and internationally. However, a complete testing method and system for timing accuracy testing has yet to be established. Firstly, due to the Gaussian spatial distribution of the laser beam energy output from pulsed lasers used in practice, the photocurrent of the APD focal plane array device is proportional to the intensity of the received optical signal, causing the timing voltage and intensity voltage to vary with the laser beam energy. Therefore, without laser beam processing, the calculation and analysis of timing accuracy will be affected by the Gaussian distribution. Secondly, in actual testing, the flight time of the APD focal plane array device is measured in the form of voltage. The ramp voltage, power supply voltage, and the accuracy of the data acquisition equipment provided by the testing system directly affect the timing accuracy of the APD focal plane array device. Finally, to achieve nanosecond-level timing accuracy in the testing system, factors such as laser trigger jitter, the timing and trigger signals of the APD focal plane array device, the synchronization accuracy between the ramp signal and the laser pulse, and the acquisition time control of the data acquisition card also affect the testing accuracy. Summary of the Invention

[0005] The purpose of this invention is to provide a timing accuracy testing system for APD focal plane array devices used in active three-dimensional imaging, so as to solve the problems existing in the prior art.

[0006] To achieve the above objectives, the present invention provides a timing accuracy testing system for an APD focal plane array device used in active three-dimensional imaging, comprising:

[0007] The control unit is used for overall control of the test system;

[0008] The laser emitting unit is used to generate flat-top monochromatic laser pulses in a wide spectral range and outputs the visible light reference beam and the laser beam to the APD focal plane device under test.

[0009] The high-speed data acquisition unit is used to acquire timing voltage and intensity voltage, and transmit them to the main control computer for processing and storage.

[0010] The APD focal plane device under test is used to receive the monochromatic laser pulse, latch the timing reference ramp signal, and output four timing voltages and intensity voltages.

[0011] The software unit, running on the main control computer, is used to process the acquired timing voltage and intensity voltage signals, calculate the timing error of each pixel of the APD focal plane device under test, and display the calculation results through images or curves.

[0012] Optionally, the control unit includes: a main control computer, an FPGA microprocessor, a timing control unit, a DAC programmable power supply, and a dual-channel waveform generation unit.

[0013] Optionally, the main control computer controls the timing control unit through the FPGA microprocessor to output the timing and functional control signals required by the APD focal plane device under test;

[0014] The main control computer also controls the DAC programmable power supply through the FPGA microprocessor to output multi-channel voltage signals;

[0015] The dual-channel waveform generation unit operates in external trigger mode, and is used to receive the trigger signal from the FPGA microprocessor and output the timing reference ramp signal and laser trigger pulse signal required by the APD focal plane device under test.

[0016] Optionally, the laser emitting unit includes: a supercontinuum laser, an acousto-optic tunable filter, a visible light reference beam, an optical fiber combiner, and a collimation, beam expansion, and homogenization system.

[0017] Optionally, the supercontinuum laser receives the laser trigger pulse signal and outputs a supercontinuum laser pulse;

[0018] The acousto-optic tunable filter is used for supercontinuum laser pulse filtering to output monochromatic laser pulses.

[0019] The fiber combiner is used to combine monochromatic laser pulses and visible light reference beams.

[0020] The collimation and beam expansion homogenization system employs an optical fiber collimator and a beam expander to adjust the divergence angle and spot diameter of the laser beam output from the optical fiber combiner, ensuring that the output laser beam covers all pixels of the APD focal plane device under test. Simultaneously, it uses an aspherical lens group to homogenize the collimated and expanded Gaussian beam, forming a collimated flat-top beam with uniform energy distribution, thus reducing the inconsistency in the laser pulse energy received by each pixel of the APD focal plane device under test.

[0021] Optionally, the main control computer controls the pulse energy of the supercontinuum laser pulse and the wavelength of the monochromatic laser pulse according to the test requirements;

[0022] The main control computer controls the dual-channel waveform generation unit to output a timing reference ramp signal with a ramp duration equal to the timing range and a laser trigger pulse signal with adjustable amplitude and pulse width, based on the timing range test requirements and the requirements of the supercontinuum laser for the laser trigger pulse signal.

[0023] The main control computer simulates the timing range of the APD focal plane device under test by adjusting the ramp duration of the timing reference ramp signal. Within the ramp duration range, by changing the phase of the timing reference ramp signal and the laser trigger pulse signal, the time difference between the start time of the timing reference ramp signal and the rising edge of the laser trigger pulse signal is gradually adjusted, so as to realize the timing accuracy test of the APD focal plane device under test at different timing times within the timing range.

[0024] Optionally, the software unit includes a test data acquisition section and a data processing section;

[0025] The test data acquisition section includes: an FPGA microprocessor and laser interface configuration module, a laser parameter configuration module, an APD focal plane device operating parameter configuration module, a data acquisition and display module, and a test control and status display module;

[0026] The FPGA microprocessor and laser interface configuration module is used for port selection, baud rate setting, and display of data sent and received by the FPGA microprocessor and laser interfaces.

[0027] The laser parameter configuration module is used for starting up, stopping, restoring factory settings, and querying real-time information of the laser, as well as setting the laser power, temperature, triggering mode, pulse width, and power.

[0028] The APD focal plane device operating parameter configuration module is used to set the APD focal plane device operating mode, integration time, ramp length, delay step size and number of single measurements, as well as the operating voltage of each pin of the APD focal plane device.

[0029] The data acquisition and display module is used to display the acquired eight-channel timing voltage and intensity voltage in real time;

[0030] The test control and status display module is used to control the start and stop of the test, display the test in progress and test stopped status, and display the waveform trigger count, acquisition card acquisition count, number of data saved, and test progress in real time.

[0031] Optionally, the data processing section includes a single data analysis module and multiple data analysis modules;

[0032] The single-group data analysis module includes a single-group data analysis button, an image display window, and a statistical result display table. The single-group data analysis module realizes the reading of multiple intensity voltage values ​​and timing voltage values ​​of each pixel of the APD focal plane device under a single delay, the calculation and display of the mean and standard deviation of intensity voltage and timing voltage, and the display of statistical results of the mean and standard deviation of voltage of all pixels.

[0033] The multiple data analysis modules include analysis buttons, image display, and statistical result display. The multiple data analysis modules realize the reading and analysis of timing voltage data under different delay times, display of timing reference ramp signal sampling values ​​and linear fitting, as well as the image display of fitting results, the image display of the mean and standard deviation of timing errors of all pixels, and the table display of statistical results of the maximum and minimum timing errors.

[0034] Optionally, the FPGA microprocessor and the software unit are connected via a serial bus, using a master-slave response mode and byte transmission to configure the operating parameters of the APD focal plane device under test.

[0035] The technical effects of this invention are as follows:

[0036] This invention, through the coordinated operation of a control unit, a laser emission unit, a high-speed data acquisition unit, the APD focal plane array device under test, and a software unit, enables the testing and evaluation of the timing performance of an APD focal plane array device. The system is flexible and adjustable, and provides calculation and display functions for timing error and timing standard deviation. Based on the performance characteristics of the APD focal plane array device, it achieves timing accuracy testing of the active 3D imaging APD focal plane array device over a wide spectral range. By gradually adjusting the time difference between the start time of the timing reference ramp signal and the laser pulse emission time, high-precision testing of the timing accuracy of the APD focal plane array device at different timing moments within the timing range is achieved. This provides support for the design and development of 3D imaging APD focal plane array devices, as well as the development of 3D imaging lidar based on this device. Attached Figure Description

[0037] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0038] Figure 1 This is a data acquisition interface diagram of the software unit of the timing accuracy testing system for an APD focal plane device used for active three-dimensional imaging in an embodiment of the present invention;

[0039] Figure 2 This is a block diagram of an APD focal plane device timing accuracy testing system for active three-dimensional imaging according to an embodiment of the present invention;

[0040] Figure 3 This is a single-group data analysis interface diagram of the software unit of the timing accuracy testing system for APD focal plane device used in active three-dimensional imaging, as described in this embodiment of the invention.

[0041] Figure 4This is a diagram of multiple data analysis interfaces of the software unit of the timing accuracy testing system for an APD focal plane device used for active three-dimensional imaging in an embodiment of the present invention.

[0042] Figure 5 This is a timing diagram of the APD focal plane device timing accuracy testing system for active three-dimensional imaging in an embodiment of the present invention. Detailed Implementation

[0043] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0044] This invention discloses a timing accuracy testing system for APD focal plane array devices used in active 3D imaging. The timing accuracy testing system can perform timing accuracy testing on APD focal plane array devices used in active 3D imaging over a wide spectral range. The system includes a control unit, a laser emission unit, a high-speed data acquisition unit, the APD focal plane array device under test, and a software unit. The control unit includes a main control computer, an FPGA microprocessor, a timing control unit, a DAC programmable power supply, and a dual-channel waveform generation unit. The laser emission unit includes a supercontinuum laser, an acousto-optic tunable filter, a visible light reference beam, an fiber combiner, and a collimation, beam expansion, and homogenization system. The main control computer in the control unit... The FPGA microprocessor controls the timing control unit to output the timing and function control signals required by the APD focal plane array device under test. These signals provide the necessary timing signals for the APD's operation and control the start time of its timing. The main control computer in the control unit, via the FPGA microprocessor, controls the DAC programmable power supply to output multi-channel voltage signals, powering different pins of the APD. The dual-channel waveform generation unit in the control unit operates in external trigger mode; upon receiving the trigger signal from the FPGA microprocessor, it outputs the timing reference ramp signal and laser trigger pulse required by the APD. The timing reference ramp signal's ramp length and amplitude, and the laser trigger pulse signal's pulse width and amplitude, are controlled by the main control computer in the control unit. The time difference between the start time of the timing reference ramp signal and the rising edge of the laser trigger pulse signal is also controlled by the main control computer in the control unit. The laser trigger pulse signal triggers the supercontinuum laser in the laser emitting unit to output a supercontinuum laser pulse. The pulse energy of the supercontinuum laser pulse is controlled by the main control computer in the control unit. The supercontinuum laser pulse is filtered by an acousto-optic tunable filter in the laser emitting unit and then converted into a monochromatic laser pulse for output. The wavelength of the monochromatic laser pulse is controlled. Controlled by the main control computer in the unit, the monochromatic laser pulse is combined with a visible light reference beam via an optical fiber combiner. The combined laser beam is then collimated, expanded, and homogenized by a system to become a flat-top monochromatic laser pulse, which is output to the APD focal plane array device under test. Upon receiving the monochromatic laser pulse, the APD latches the current timing reference ramp signal voltage value and outputs it as four timing voltages. It also measures the monochromatic laser pulse energy and outputs it as four intensity voltages. Simultaneously, the APD outputs a valid data signal. This valid data signal triggers a high-speed data acquisition unit to acquire the timing and intensity voltages and transmit them to the main control computer in the control unit for processing and storage.The sampling frequency, reference voltage, trigger acquisition mode, and trigger delay of the high-speed data acquisition unit are controlled by the main control computer in the control unit. The software unit runs on the main control computer in the control unit, processes the timing voltage and intensity voltage signals read by the main control computer, calculates the timing standard deviation of each pixel of the APD focal plane device under test, the average timing standard deviation of all pixels, and the minimum and maximum timing standard deviations, and displays the calculation results in the form of graphs or curves.

[0045] The laser emitting unit can achieve co-path output of a flat-top monochromatic laser pulse with tunable pulse energy across a wide spectral range and a visible light reference beam. The visible light reference beam is used to adjust the mounting position of the APD focal plane device under test. The laser emitting unit includes a supercontinuum laser, an acousto-optic tunable filter, a visible light reference beam, an fiber combiner, and a collimation, beam expansion, and homogenization system. The main control computer in the control unit controls the laser pulse energy output by the supercontinuum laser and the wavelength of the monochromatic laser pulse output by the acousto-optic tunable filter, thereby achieving co-path output of a flat-top monochromatic laser pulse with tunable pulse energy across a wide spectral range. The laser pulse output, the collimation and beam expansion homogenization system in the laser emitting unit, on the one hand, uses an optical fiber collimator and a beam expander to adjust the divergence angle and spot diameter of the laser beam output from the optical fiber combiner, so that the output laser beam covers all pixels of the APD focal plane device under test. On the other hand, it uses an aspherical lens group to homogenize the Gaussian beam after collimation and beam expansion, forming a collimated flat-top beam with uniform energy distribution, reducing the inconsistency of laser pulse energy received by each pixel of the APD focal plane device under test, and improving the measurement accuracy of the timing standard deviation of each pixel of the APD focal plane device under test.

[0046] The control unit can output timing and function control signals, as well as multi-channel adjustable voltage signals, according to the timing and voltage requirements of each pin of the APD focal plane array device under test. It can also output phase-adjustable timing reference signals and laser trigger pulse signals to simulate laser echo signals at different timing ranges and times. The control unit includes a main control computer, an FPGA microprocessor, a timing control unit, a DAC programmable power supply, and a dual-channel waveform generation unit. The main control computer, based on the timing and voltage requirements of each pin of the APD focal plane array device under test, controls the timing control unit and the DAC programmable power supply to output timing and function control signals, as well as multi-channel adjustable voltage signals, respectively, through the FPGA microprocessor. The main control computer, based on the timing range test requirements and the requirements of the supercontinuum laser for the laser trigger pulse signal, controls the dual-channel waveform generation unit to output a timing reference ramp signal with a ramp duration equal to the timing range, and a laser trigger pulse signal with adjustable amplitude and pulse width. The main control computer simulates the timing range of the APD focal plane device under test by adjusting the ramp duration of the timing reference ramp signal. Within the ramp duration range, by changing the phase of the timing reference ramp signal and the laser trigger pulse signal, the time difference between the start time of the timing reference ramp signal and the rising edge of the laser trigger pulse signal is gradually adjusted, thereby achieving timing accuracy testing of the APD focal plane device under test at different timing moments within the timing range.

[0047] The software unit includes a test data acquisition section and a data processing section. The test data acquisition section is divided into five functional modules: an FPGA microprocessor and laser interface configuration module, a laser parameter configuration module, an APD focal plane device operating parameter configuration module, a data acquisition and display module, and a test control and status display module. The FPGA microprocessor and laser interface configuration module enables port selection and baud rate setting for the FPGA microprocessor and laser interfaces, as well as displaying the data sent and received by the FPGA microprocessor and laser interfaces. The laser parameter configuration module enables laser startup, shutdown, factory reset, and real-time information query, as well as laser power, temperature, trigger mode, pulse width, and power settings. The APD focal plane device operating parameter configuration module enables setting the APD focal plane device's operating mode, integration time, ramp length, delay step, and number of measurements per measurement, as well as setting the operating voltage of each pin of the APD focal plane device. The data acquisition and display module displays the acquired eight-channel timing voltage and intensity voltage in real time. The control and status display module controls the start and stop of the test, displays the test in progress and stopped status, and provides real-time display of waveform trigger count, acquisition card acquisition count, number of data saved, and test progress. The data processing section includes a single-group data analysis module and a multi-group data analysis module. The single-group data analysis module includes a single-group data analysis button, an image display window, and a statistical result display table. This module reads multiple sets of intensity voltage and timing voltage values ​​for each pixel of the APD focal plane device under a single delay, calculates and displays the mean and standard deviation of the intensity and timing voltages, and displays the statistical results of the mean and standard deviation of voltages for all pixels. The multi-group data analysis module includes an analysis button, an image display, and a statistical result display. This module reads and analyzes timing voltage data under different delay times, displays the sampling values ​​of the timing reference ramp signal and performs linear fitting, displays the fitting result image, displays the mean and standard deviation of timing errors for all pixels, and displays the statistical results of the maximum and minimum timing errors in a table.

[0048] The FPGA microprocessor and software unit are connected via a serial bus, employing a master-slave response mode and transmitting data byte-wise to configure the operating parameters and multi-channel adjustable voltage signals of the APD focal plane array device under test. Each configuration parameter is transmitted in byte format: the first two bytes store the header, the third byte stores the command word, the fourth byte stores the data length n, the fifth to (n+5) bytes store the data, and the (n+5) to (n+7) bytes store the data checksum. In the configuration data for the APD focal plane array device under test, the first byte stores the operating mode and the test... In the quantity mode, bytes 2-3 store the ramp signal duration, bytes 4-5 store the delay step size, bytes 6-7 store the number of single measurements, and byte 8 is the stop bit. In the multi-channel adjustable voltage signal configuration data, bytes 1-2 store the voltage value of channel 1, bytes 3-4 store the voltage value of channel 2, bytes 5-6 store the voltage value of channel 3, bytes 7-8 store the voltage value of channel 4, bytes 9-10 store the voltage value of channel 5, bytes 11-12 store the voltage value of channel 6, bytes 13-14 store the voltage value of channel 7, and byte 15 is the stop bit.

[0049] Example 1

[0050] like Figure 1-5 As shown, this embodiment provides a timing accuracy testing system for an APD focal plane device used in active three-dimensional imaging. Before the system operates, the system operating parameters are set by the data acquisition part in the software unit. This mainly completes the configuration of the FPGA microprocessor and laser interface, the configuration of laser parameters, the configuration of APD focal plane device operating parameters, as well as the display of acquired data and the display of test status. Figure 1 This is an interface diagram of the data acquisition section of the software unit for the timing accuracy test system of the APD focal plane device used for active 3D imaging.

[0051] The data acquisition section of the software unit is developed based on the LabVIEW platform. The front panel interface is divided into: ① FPGA microprocessor and laser interface configuration section, which enables the selection of FPGA microprocessor and laser ports, baud rate settings, and display of data sent and received by the FPGA microprocessor and laser ports; ② Laser parameter configuration section, which enables the setting of laser output power, temperature, trigger mode selection (internal trigger or external trigger), and output laser pulse width; ③ APD focal plane device operating parameter configuration section, which enables the selection of APD focal plane device operating mode and measurement mode. Operating modes include passive mode and active mode, and measurement modes include single delay measurement and multiple delay measurement. It also enables the setting of APD focal plane device integration time and the voltages of seven different pins (VDDA, VDD, VDDO, VREF1, VREF2, VBLM, SUBPV). Finally, it enables the setting of the timing reference ramp signal ramp duration, which corresponds to the maximum timing range of the APD focal plane device. The system allows setting the delay step size, which is the time difference between the start time of the timing reference ramp signal and the laser pulse emitted by the laser, corresponding to the timing of the APD focal plane device during testing. It also allows setting the number of measurements per test, corresponding to the number of tests performed on the APD focal plane device. The data acquisition and display section displays the acquired timing voltage and intensity voltage in real time. The test control and status display section controls the start and stop of the test and displays the test status. The test status display shows whether the system is in progress or has completed the test, the number of laser pulses emitted, the number of data acquisitions, and the number of stored data.

[0052] After the data acquisition section of the software unit is set up, click the "Start Test" button on the software interface of the data acquisition section of the software unit. Under the control of the main control computer, the test system will start working. Figure 2This is a block diagram of an APD focal plane array device timing accuracy testing system for active 3D imaging. The software unit runs on the main control computer. After receiving the start test command from the software unit, the main control computer first sets the laser's power, temperature, triggering mode, emitted laser pulse width, and laser wavelength through the data port selected by the software unit, based on the laser's configuration. It then receives the data returned by the laser and uses this data to determine if the laser configuration was successful. After successful configuration, based on the ramp signal duration and delay step size set in the software unit, the main control computer sets the ramp duration of the timing reference ramp signal output by the dual-channel waveform generation unit via the data bus, and sets the delay between the ramp start time of the timing reference ramp signal and the rising edge of the laser trigger pulse signal based on the delay step size. Next, the main control computer sends the configuration parameters to the FPGA microprocessor via the data bus, based on the APD focal plane array device operating parameters configured in the software unit. The FPGA microprocessor receives parameters from the host computer. On one hand, it sets the DAC programmable power supply and, based on the voltage values ​​of each pin of the APD focal plane array device under test (APD) set by the software unit, outputs the multi-channel adjustable voltage signals required by each pin. On the other hand, based on the operating mode and integration time of the APD focal plane array device under test set by the software unit, the FPGA microprocessor configures the timing control unit, outputting the timing and control signals required by the APD focal plane array device under test. Simultaneously, based on the delay step size set by the software unit, the FPGA microprocessor outputs a waveform trigger signal. This waveform trigger signal activates the dual-channel waveform generation unit, which, according to the host computer's configuration, outputs a timing reference ramp signal and a laser trigger pulse signal. The timing reference ramp signal is connected to the APD focal plane array device under test.

[0053] A laser pulse trigger signal triggers a supercontinuum laser to output a supercontinuum laser pulse. This output pulse is transmitted via optical fiber to an acousto-optic tunable filter. The acousto-optic tunable filter performs spectral filtering on the supercontinuum laser pulse according to the settings of the main control computer, outputting a laser pulse of the required wavelength for testing, called the test laser pulse. The test laser pulse and a visible light reference beam are combined by an optical fiber combiner and then output to a collimation, beam expansion, and homogenization system. Since the test laser pulse may be non-visible, the laser beam may not be visible during testing, which is detrimental to the testing of the APD focal plane array device under test. A visible light reference beam is introduced through the optical fiber combiner for adjusting the optical path and mounting the APD focal plane array device under test during the testing process. Because the intensity of the test laser pulse beam cross-section is Gaussian, if the test laser pulse is directly applied to the APD focal plane array device under test, different pixels of the device will receive different laser pulse energies, thus introducing testing errors. To improve the accuracy of the testing system, the test laser pulse is first collimated and expanded. Then, an aspherical lens group is used to homogenize the collimated and expanded Gaussian beam to form a collimated flat-top beam with uniform energy distribution. This reduces the inconsistency of laser pulse energy received by each pixel of the APD focal plane device under test and improves the measurement accuracy of the timing standard deviation of each pixel of the APD focal plane device under test.

[0054] The collimated and homogenized test laser pulse irradiates the APD focal plane array device under test. The APD focal plane array device receives the optical signal and generates photoelectrons. Under a certain reverse bias voltage, the charge carriers in the PN junction gain kinetic energy and collide with atoms in the crystal lattice, exciting valence band electrons to the conduction band, forming new electron-hole pairs. The charge carriers moving in the depletion layer undergo avalanche multiplication due to the collisional ionization effect. This forms a photocurrent that flows into the capacitive feedback transimpedance amplifier, which has two feedback capacitors: a small capacitor C3d and a large capacitor C2d. When the photocurrent flows into the capacitive feedback transimpedance amplifier, the small capacitor C3d begins to integrate, and the output voltage of the capacitive feedback transimpedance amplifier increases rapidly. The output terminal of the capacitive feedback transimpedance amplifier is connected to the non-inverting input of a voltage comparator. When the output voltage of the capacitive feedback transimpedance amplifier is greater than the threshold of the voltage comparator, the latch module is triggered to lock the current ramp voltage value. The sample-and-hold circuit operates in the hold state, obtaining a voltage value related to time information, called the timing voltage. On the other hand, the switch of the large capacitor C2d is closed, at which point the circuit enters the large capacitor integration mode. This integration continues until the integration time ends, yielding the intensity voltage corresponding to the laser energy. The integration time is controlled by the FPGA microprocessor. After the APD focal plane array device under test completes integration, it outputs a valid data signal. This valid data signal triggers the high-speed data acquisition unit to acquire the timing voltage and intensity voltage. The acquired data is transmitted to the main control computer for display and storage. The sampling frequency, reference voltage, and external trigger delay of the high-speed data acquisition unit are controlled by the main control computer.

[0055] After the test, based on the number of delays (the number of data sets with different delay times collected) during the test, data processing was performed using the single-set data analysis and multi-set data analysis functions in the software unit. When analyzing data from a single delay, the single-set data analysis interface in the software unit was opened, as shown below. Figure 3 As shown, clicking the "Single Data Analysis" button brings up a data selection dialog box. Select the data you want to analyze and click "OK." The software unit will then rearrange the collected timing voltage and intensity voltage according to the pixel arrangement of the APD focal plane device and the number of measurements. It will calculate the mean intensity voltage, standard deviation of intensity voltage, mean timing voltage, and standard deviation of timing voltage for each pixel, displaying the data as a grayscale image. Furthermore, it will statistically display the mean intensity voltage and mean timing voltage of all pixels, as well as the set delay time, set number of measurements, and actual number of measurements. When analyzing data with multiple delays, open the multi-data analysis interface in the software unit, such as... Figure 4 As shown, clicking the "Multiple Data Analysis" button brings up a data selection dialog box. Selecting the desired data sets and clicking "OK" initiates the software unit. First, for each delay, the software calculates the mean and standard deviation of the timing voltage for each pixel, as well as the mean and standard deviation of the timing voltage for all pixels. Second, using the delay time as the independent variable and the mean timing voltage as the dependent variable, a linear fit is performed on the mean timing voltage and the delay time to obtain the slope of the timing reference ramp signal. Finally, for each delay, the mean of the standard deviation of the timing voltage for all pixels is divided by the slope of the timing reference ramp signal to obtain the mean timing error of the APD focal plane device under different delay times. The standard deviation of the standard deviation of the timing voltage for all pixels is divided by the slope of the timing reference ramp signal to obtain the standard deviation of the timing error of the APD focal plane device under different delay times. The mean and standard deviation of the timing error are displayed numerically and graphically. For each delay, the maximum and minimum values ​​of the timing error and the standard deviation of the timing error are calculated, along with the corresponding pixel coordinates, and displayed numerically.

[0056] Figure 5This is a timing diagram of an APD focal plane array device timing accuracy testing system for active 3D imaging. The FPGA microprocessor provides the APD focal plane array device with a master clock and integration time control pulses. Before the integration capacitor of the APD focal plane array device is reset, the FPGA microprocessor outputs a waveform trigger signal to trigger the dual-channel waveform generation unit to output a laser pulse trigger signal and a timing reference ramp signal. The laser pulse trigger signal triggers the laser to output a test laser pulse. The delay time between the rising edge of the test laser pulse and the start time of the timing reference ramp signal is set by the software unit. After the test laser pulse arrives at the APD focal plane array device, the APD focal plane array device latches the timing reference ramp signal at the current moment to obtain a timing voltage signal. Simultaneously, C2d begins integration and stops after the total integration time is reached, obtaining an intensity voltage signal. After the total integration time is completed, the APD focal plane array device transfers the timing voltage and intensity voltage. After the transfer is complete, the APD focal plane array device outputs a data valid signal. The data valid signal triggers the high-speed data acquisition unit to acquire the timing voltage and intensity voltage under the control of the sampling clock.

[0057] The above description is merely a preferred embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An APD focal plane device timing accuracy test system for active three-dimensional imaging, characterized by, The system comprises: a control unit for overall control of the test system; a laser emission unit for generating flat-top monochromatic laser pulses in a wide spectral range and outputting a visible reference light beam combined with the laser to a to-be-tested APD focal plane device; a high-speed data acquisition unit for collecting timing voltage and intensity voltage and transmitting to a host computer for processing and storage; the to-be-tested APD focal plane device for receiving the monochromatic laser pulses, latching a timing reference ramp signal, and outputting four-way timing voltage and intensity voltage; a software unit running on the host computer for processing the collected timing voltage and intensity voltage signals, calculating the timing error of each pixel of the to-be-tested APD focal plane device, and displaying the calculation results through images or curves. The laser emission unit comprises: an ultrashort pulse laser, an acousto-optic tunable filter, a visible reference light beam, a fiber combiner, and a collimating and expanding homogenization system. The host computer controls the pulse energy of the ultrashort pulse laser and the wavelength of the monochromatic laser pulse according to test requirements. The host computer controls a double-channel waveform generation unit to output a timing reference ramp signal with a slope duration equal to the timing range and a laser trigger pulse signal with adjustable amplitude and pulse width according to the timing range test requirements and the requirements of the ultrashort pulse laser on the laser trigger pulse signal. The host computer simulates the timing range of the to-be-tested APD focal plane device by adjusting the slope duration of the timing reference ramp signal. Within the slope duration range, the time difference between the start time of the timing reference ramp signal and the rising edge of the laser trigger pulse signal is gradually adjusted by changing the phase of the timing reference ramp signal and the laser trigger pulse signal, so as to realize the test of the timing accuracy of the to-be-tested APD focal plane device at different timing times within the timing range.

2. The APD focal plane device timing accuracy test system for active three-dimensional imaging according to claim 1, wherein the control unit comprises: a host computer, an FPGA microprocessor, a timing control unit, a DAC program-controlled power supply, and a double-channel waveform generation unit.

3. The APD focal plane device timing accuracy test system for active three-dimensional imaging according to claim 2, wherein the host computer controls the timing control unit through the FPGA microprocessor to output the timing and function control signals required by the to-be-tested APD focal plane device; the host computer further controls the DAC program-controlled power supply through the FPGA microprocessor to output multi-channel voltage signals; the double-channel waveform generation unit works in an external trigger mode, receives the trigger signal of the FPGA microprocessor, and outputs the timing reference ramp signal and the laser trigger pulse signal required by the to-be-tested APD focal plane device.

4. The APD focal plane device timing accuracy test system for active three-dimensional imaging according to claim 1, wherein the ultrashort pulse laser receives the laser trigger pulse signal and outputs an ultrashort pulse laser pulse. The acousto-optic tunable filter is used for filtering supercontinuum laser pulses, and outputs monochromatic laser pulses. The fiber combiner is used for combining monochromatic laser pulses and visible reference light beams. The collimation, beam expansion and homogenization system adjusts the divergence angle and spot diameter of the laser beam output by the fiber combiner through a fiber collimator and a beam expander, so that the output laser beam covers all pixels of the APD focal plane device to be tested. On the other hand, the aspheric lens group homogenizes the Gaussian beam after collimation and beam expansion, forms a collimated flat-top beam with uniform energy distribution, and reduces the inconsistency of the laser pulse energy received by each pixel of the APD focal plane device to be tested.

5. The APD focal plane device timing accuracy test system for active three-dimensional imaging according to claim 1, wherein The software unit comprises a test data acquisition part and a data processing part. The test data acquisition part comprises an FPGA microprocessor and a laser interface configuration module, a laser parameter configuration module, an APD focal plane device working parameter configuration module, a data acquisition display module, a test control and state display module. The FPGA microprocessor and the laser interface configuration module are used for port selection, baud rate setting of the FPGA microprocessor interface and the laser interface, and display of data sent and received by the FPGA microprocessor interface and the laser interface. The laser parameter configuration module is used for starting, stopping, restoring factory settings and real-time information query of the laser, and setting of laser power, temperature, trigger mode, pulse width and power. The APD focal plane device working parameter configuration module is used for setting APD focal plane device working mode, integration time, slope length, delay step and single measurement number, and setting APD focal plane device pin working voltage. The data acquisition display module is used for real-time display of the acquired eight-channel timing voltage and intensity voltage. The test control and state display module is used for test start and stop control, test in progress and test stop state display, real-time display of waveform trigger number, acquisition card acquisition number, acquisition data saving number and test progress.

6. The APD focal plane device timing accuracy test system for active three-dimensional imaging according to claim 5, wherein The data processing part comprises a single-group data analysis module and a multi-group data analysis module. The single-group data analysis module comprises a single-group data analysis button, an image display window and a statistical result display table. The single-group data analysis module realizes reading of multi-group intensity voltage values and timing voltage values of each pixel of the APD focal plane device under single delay, calculation and display of intensity voltage and timing voltage mean value and standard deviation, and display of statistical result of voltage mean value and standard deviation of all pixels. The multiple data analysis modules include analysis buttons, image display, and statistical result display. The multiple data analysis modules realize the reading and analysis of timing voltage data under different delay times, display of timing reference ramp signal sampling values ​​and linear fitting, as well as the image display of fitting results, the image display of the mean and standard deviation of timing errors of all pixels, and the table display of statistical results of the maximum and minimum timing errors.

7. The timing accuracy testing system for an APD focal plane array device for active three-dimensional imaging according to claim 1, characterized in that, The FPGA microprocessor and the software unit are connected via a serial bus, using a master-slave response mode and byte transmission to configure the operating parameters of the APD focal plane device under test.

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