Upgrade retention apparatus for embedded system and upgrade retention method thereof

Abstract

The application discloses an upgrading and maintaining device of an embedded system and an upgrading and maintaining method thereof. The device comprises a master control circuit, a network circuit, a bypass control circuit, a watchdog inhibit reset circuit, a maintaining function triggering circuit, a maintaining function releasing circuit and a maintaining signal circuit. The master control circuit is electrically connected with the bypass control circuit through the network circuit. The master control circuit is also electrically connected with the output ends of the bypass control circuit, the watchdog inhibit reset circuit, the maintaining function triggering circuit, the maintaining function releasing circuit and the watchdog inhibit reset circuit. The maintaining function triggering circuit and the maintaining function releasing circuit are both electrically connected with the maintaining signal circuit. The maintaining signal circuit is also electrically connected with the bypass control circuit and the watchdog inhibit reset circuit. The application can effectively ensure that the software upgrading process of the embedded system is not interrupted based on the disablement of the bypass function and the failure of the watchdog reset function during the software upgrading process. The bypass function and the watchdog reset function are restored after the software upgrading process is completed.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic devices, in particular to an upgrade maintaining device of an embedded system and an upgrade maintaining method thereof. BACKGROUND

[0002] In the embedded system, it is usually required to upgrade the software therein, which is mainly realized by connecting the network terminal device with bypass function to the network port of the embedded system through network cable.

[0003] However, during the software upgrade of the embedded system, the following problems exist: (1) the program of the embedded system is reset, the bypass function of the network terminal device is enabled, which leads to the disconnection between the network terminal device and the network port of the embedded system, and the upgrade process is interrupted; (2) the embedded system usually sets the feed watchdog function (i.e. sending the feeding signal to the watchdog of the embedded system at regular intervals to ensure the normal operation of the system), during the upgrade, the feed watchdog function cannot work normally, the watchdog does not receive the feeding signal, which leads to the reset of the watchdog, and the upgrade process cannot be completed.

[0004] However, there is no technology that can simultaneously prohibit the start of the bypass function and the reset function of the watchdog during the software upgrade of the embedded system, and then release the prohibition of the start of the bypass function and the reset function of the watchdog after the software upgrade is completed, so as to restore the normal work of the network terminal device and the watchdog. SUMMARY

[0005] Therefore, the present application provides an upgrade maintaining device of an embedded system and an upgrade maintaining method thereof, to solve the problem that the embedded system cannot be upgraded and maintained in the prior art, and the bypass function and the reset function of the watchdog are simultaneously prohibited during the software upgrade of the embedded system, and then the bypass function and the reset function of the watchdog are restored after the software upgrade is completed.

[0006] The present application provides an upgrade maintaining device of an embedded system, which comprises a master control circuit, a network circuit, a bypass control circuit, a watchdog prohibition reset circuit, a maintaining function triggering circuit, a maintaining function releasing circuit and a maintaining signal circuit.

[0007] The network signal input end and the network signal output end of the master control circuit are electrically connected with the network signal end of the bypass control circuit through the network circuit, the control signal output end of the master control circuit is electrically connected with the control signal end of the bypass control circuit, the input end of the watchdog inhibition reset circuit, the input end of the holding function trigger circuit and the input end of the holding function release circuit, the control signal input end of the master control circuit is electrically connected with the control signal end of the bypass control circuit and the output end of the watchdog inhibition reset circuit; the output end of the holding function trigger circuit and the output end of the holding function release circuit are electrically connected with the input end of the holding signal circuit, and the output end of the holding signal circuit is electrically connected with the control signal end of the bypass control circuit and the input end of the watchdog inhibition reset circuit;

[0008] The master control circuit is configured to send a holding function trigger signal to the holding function trigger circuit when the embedded system starts an upgrade process.

[0009] The holding function trigger circuit is configured to receive the holding function trigger signal and control the output channel of the holding signal circuit to be opened according to the holding function trigger signal.

[0010] The holding signal circuit is configured to generate a holding driving signal when the output channel is opened and send the holding driving signal to the bypass control circuit and the watchdog inhibition reset circuit respectively.

[0011] The bypass control circuit is configured to control the disablement of the bypass function of the embedded system according to the holding driving signal when the holding driving signal is received, so that the connection between the network circuit and the network signal end of the bypass control circuit is successful.

[0012] The watchdog inhibition reset circuit is configured to control the disablement of the watchdog reset function of the embedded system according to the holding driving signal when the holding driving signal is received.

[0013] The master control circuit is further configured to send a holding function release signal to the holding function release circuit when the embedded system completes the upgrade process.

[0014] The holding function release circuit is configured to receive the holding function release signal and control the output channel of the holding signal circuit to be closed according to the holding function release signal.

[0015] The bypass control circuit is also configured to, when the hold driving signal is not received, disable the bypass function of the embedded system, so that the connection between the network circuit and the network signal end of the bypass control circuit is disconnected.

[0016] The watchdog reset circuit is also configured to, when the hold driving signal is not received, disable the watchdog reset function of the embedded system.

[0017] Optionally, the hold signal circuit comprises a transistor Q10, a transistor Q11, a resistor R8, a resistor R78, a resistor R80, a resistor R81 and a resistor R93.

[0018] The emitter of the transistor Q10 is electrically connected to the circuit power supply end, the base of the transistor Q10 is electrically connected to the output end of the hold function triggering circuit and the output end of the hold function releasing circuit through the resistor R81, the base of the transistor Q10 is also electrically connected to the base of the transistor Q11 in turn through the resistor R81 and the resistor R93, the collector of the transistor Q10 is electrically connected to the control signal end of the bypass control circuit and the input end of the watchdog reset circuit, the first end of the resistor R78 is connected to the common connection end between the emitter of the transistor Q10 and the circuit power supply end, and the second end of the resistor R78 is connected to the common connection end between the base of the transistor Q10 and the resistor R81.

[0019] The emitter of the transistor Q11 is electrically connected to the circuit power supply end, the first end of the resistor R80 is connected to the common connection end between the emitter of the transistor Q11 and the circuit power supply end, and the second end of the resistor R80 is connected to the common connection end between the base of the transistor Q11 and the resistor R93; the collector of the transistor Q11 is electrically connected to the output end of the hold function releasing circuit through the resistor R8.

[0020] Optionally, the hold function triggering circuit comprises an operational amplifier U2, a diode D2, a transistor Q12, a resistor R7, a resistor R9, a resistor R11, a resistor R12, a resistor R15, a resistor R85, a resistor R90, a capacitor C3, a capacitor C4 and a capacitor C53.

[0021] The power supply pin of the operational amplifier U2 is electrically connected with the circuit power supply end, and the ground pin of the operational amplifier U2 is grounded; the positive input pin of the operational amplifier U2 is electrically connected with the control signal output end of the master control circuit through the resistor R12 and the capacitor C3 in sequence, the first end of the resistor R15 and the first end of the capacitor C4 are both connected on the common connection end between the positive input pin of the operational amplifier U2 and the resistor R12, the second end of the resistor R15 and the second end of the capacitor C4 are both grounded, the first end of the diode D2 is connected on the common connection end between the resistor R12 and the capacitor C3, and the second end of the diode D2 is grounded; the inverting input pin of the operational amplifier U2 is electrically connected with the circuit power supply end through the resistor R7, the first end of the resistor R9 is connected on the common connection end between the inverting input pin of the operational amplifier U2 and the resistor R7, and the second end of the resistor R9 is grounded; the output pin of the operational amplifier U2 is electrically connected with the base of the triode Q12 through the resistor R85, and the output pin of the operational amplifier U2 is also electrically connected with the circuit power supply end through the resistor R11; the first end of the resistor R90 and the first end of the capacitor C53 are both connected on the common connection end between the resistor R85 and the base of the triode Q12, the second end of the resistor R90 and the second end of the capacitor C53 are both grounded; the collector of the triode Q12 is connected on the common connection end between the resistor R81 and the resistor R93, and the emitter of the triode Q12 is grounded.

[0022] Optionally, the holding function release circuit comprises an operational amplifier U3, a diode D3, a triode Q5, a triode Q16, a resistor R10, a resistor R13, a resistor R14, a resistor R16, a resistor R17, a resistor R18, a resistor R89, a resistor R94, a capacitor C5, a capacitor C6 and a capacitor C52.

[0023] The power supply pin of the operational amplifier U3 is electrically connected with the circuit power supply end, and the ground pin of the operational amplifier U3 is grounded; the positive input pin of the operational amplifier U3 is electrically connected with the control signal output end of the master control circuit through the resistor R17 and the capacitor C5 in sequence, the first end of the resistor R18 and the first end of the capacitor C6 are both connected on the common connection end between the positive input pin of the operational amplifier U3 and the resistor R17, the second end of the resistor R18 and the second end of the capacitor C6 are both grounded, the first end of the diode D3 is connected on the common connection end between the resistor R17 and the capacitor C5, and the second end of the diode D3 is grounded; the inverting input pin of the operational amplifier U3 is electrically connected with the circuit power supply end through the resistor R10, and the first end of the resistor R13 is connected on the common connection end between the inverting input pin of the operational amplifier U3 and the resistor R10, and the second end of the resistor R13 is grounded; the output pin of the operational amplifier U3 is electrically connected with the base of the triode Q5, and the output pin of the operational amplifier U3 is also electrically connected with the circuit power supply end through the resistor R14; the first end of the resistor R16 is connected on the common connection end between the output pin of the operational amplifier U3 and the base of the triode Q5, and the second end of the resistor R16 is grounded; the emitter of the triode Q5 is grounded, the collector of the triode Q5 is electrically connected with the base of the triode Q16 through the resistor R94, and the resistor R8 in the holding signal circuit is connected on the common connection end between the collector of the triode Q5 and the resistor R94; the first end of the resistor R89 and the first end of the capacitor C52 are both connected on the common connection end between the resistor R94 and the base of the triode Q16, and the second end of the resistor R89 and the second end of the capacitor C52 are both grounded; the emitter of the triode Q16 is grounded, and the collector of the triode Q16 is connected on the common connection end between the resistor R81 and the resistor R93.

[0024] Optionally, the watchdog reset prevention circuit comprises a watchdog chip U1, a triode Q1, a triode Q2, a diode D1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a capacitor C1 and a capacitor C2.

[0025] The power supply pin VDD of the watchdog chip U1 is electrically connected with the circuit power supply end, the first end of the capacitor C1 is connected on the common connection end between the power supply pin VDD of the watchdog chip U1 and the circuit power supply end, and the second end of the capacitor C1 is grounded; the watchdog chip U1 is electrically connected with the control signal output end of the master control circuit through the watchdog signal input pin WDI, the first end of the resistor R6 is connected on the common connection end between the watchdog signal input pin WDI of the watchdog chip U1 and the control signal output end of the master control circuit, and the second end of the resistor R6 is grounded; the ground pin GND of the watchdog chip U1 is grounded, the manual reset pin MR# of the watchdog chip U1 is suspended, the hardware reset pin RESET# of the watchdog chip U1 is electrically connected with the collector of the transistor Q1 through the resistor R3, the positive electrode of the diode D1 is electrically connected with the control signal input end of the master control circuit, and the negative electrode of the diode D1 is connected on the common connection end between the resistor R3 and the collector of the transistor Q1;

[0026] The base of the transistor Q1 is electrically connected with the collector of the transistor Q2 through the resistor R2, the emitter of the transistor Q1 is electrically connected with the circuit power supply end, the first end of the resistor R1 is connected on the common connection end between the base of the transistor Q1 and the resistor R2, and the second end of the resistor R1 is connected on the common connection end between the emitter of the transistor Q1 and the circuit power supply end; the base of the transistor Q2 is electrically connected with the output end of the holding signal circuit through the resistor R4, the first end of the resistor R5 and the first end of the capacitor C2 are both connected on the common connection end between the base of the transistor Q2 and the resistor R4, and the second end of the resistor R5, the second end of the capacitor C2 and the emitter of the transistor Q2 are all grounded.

[0027] Optionally, the bypass control circuit comprises a bypass driving sub-circuit and a bypass relay sub-circuit.

[0028] The input end of the bypass driving sub-circuit is electrically connected with the control signal output end of the master control circuit and the output end of the holding signal circuit respectively, the output end of the bypass driving sub-circuit is electrically connected with the input end of the bypass relay sub-circuit and the control signal input end of the master control circuit respectively, and the bypass relay sub-circuit is also electrically connected with the network circuit.

[0029] Optionally, the bypass driving sub-circuit comprises a transistor Q3, a transistor Q4, a diode D8, a resistor R52, a resistor R53, a resistor R54, a resistor R55, a resistor R56 and a capacitor C42.

[0030] The negative electrode of the diode D8 is electrically connected with the control signal output end of the main control circuit, the positive electrode of the diode D8 is electrically connected with the base of the triode Q3 through the resistor R53, the emitter of the triode Q3 is electrically connected with the circuit power supply end, and the collector of the triode Q3 is electrically connected with the input end of the bypass relay sub-circuit and the control signal input end of the main control circuit respectively; the first end of the resistor R52 and the first end of the resistor R54 are both connected on the common connection end between the resistor R53 and the base of the triode Q3, the second end of the resistor R52 is connected on the common connection end between the emitter of the triode Q3 and the circuit power supply end, and the second end of the resistor R54 is electrically connected with the collector of the triode Q4;

[0031] The base of the triode Q4 is electrically connected with the output end of the holding signal circuit through the resistor R55, the first end of the resistor R56 and the first end of the capacitor C42 are both connected on the common connection end between the base of the triode Q4 and the resistor R55, and the second end of the resistor R56, the second end of the capacitor C42 and the emitter of the triode Q4 are all grounded.

[0032] Optionally, the bypass relay sub-circuit comprises a relay K1, a relay K2, a relay K3, a relay K4, a triode Q6, a triode Q7, a triode Q8, a triode Q9, a diode D9, a diode D10, a diode D11, a diode D12, a resistor R59, a resistor R60, a resistor R61, a resistor R62, a resistor R64, a resistor R65, a resistor R66, a resistor R67, a capacitor C45, a capacitor C46, a capacitor C47 and a capacitor C48; wherein the relay K1, the relay K2, the relay K3 and the relay K4 are all double-throw double-pole relays switched in two groups.

[0033] The base of the triode Q6 is electrically connected with the output end of the bypass drive sub-circuit through the resistor R59, the first end of the resistor R64 and the first end of the capacitor C45 are both connected on the common connection end between the base of the triode Q6 and the resistor R59, the second end of the resistor R64, the second end of the capacitor C45 and the emitter of the triode Q6 are all grounded, and the collector of the triode Q6 is electrically connected with the +5V power supply end through the diode D9.

[0034] The first end of the coil of the relay K1 is connected to a common connection between the collector of the triode Q6 and the diode D9, and the second end of the coil of the relay K1 is connected to a common connection between the diode D9 and the +5V power supply end; the first moving contact, the second moving contact, the first normally open static contact and the second normally open static contact of the relay K1 are electrically connected to the network circuit, the first normally closed static contact of the relay K1 is electrically connected to the first normally closed static contact of the relay K3, and the second normally closed static contact of the relay K1 is electrically connected to the second normally closed static contact of the relay K3;

[0035] The base of the triode Q7 is electrically connected to the output end of the bypass driving sub-circuit through the resistor R60, the first end of the resistor R65 and the first end of the capacitor C46 are both connected to a common connection between the base of the triode Q7 and the resistor R60, the second end of the resistor R65, the second end of the capacitor C46 and the emitter of the triode Q7 are all grounded; the collector of the triode Q7 is electrically connected to the +5V power supply end through the diode D10;

[0036] The first end of the coil of the relay K2 is connected to a common connection between the collector of the triode Q7 and the diode D10, and the second end of the coil of the relay K2 is connected to a common connection between the diode D10 and the +5V power supply end; the first moving contact, the second moving contact, the first normally open static contact and the second normally open static contact of the relay K2 are electrically connected to the network circuit, the first normally closed static contact of the relay K2 is electrically connected to the first normally closed static contact of the relay K4, and the second normally closed static contact of the relay K2 is electrically connected to the second normally closed static contact of the relay K4;

[0037] The base of the triode Q8 is electrically connected to the output end of the bypass driving sub-circuit through the resistor R61, the first end of the resistor R66 and the first end of the capacitor C47 are both connected to a common connection between the base of the triode Q8 and the resistor R61, the second end of the resistor R66, the second end of the capacitor C47 and the emitter of the triode Q8 are all grounded; the collector of the triode Q8 is electrically connected to the +5V power supply end through the diode D11; the first end of the coil of the relay K3 is connected to a common connection between the collector of the triode Q8 and the diode D11, and the second end of the coil of the relay K3 is connected to a common connection between the diode D11 and the +5V power supply end; the first moving contact, the second moving contact, the first normally open static contact and the second normally open static contact of the relay K3 are electrically connected to the network circuit;

[0038] The base of the triode Q9 is electrically connected with the output end of the bypass driving sub-circuit through the resistor R62, the first end of the resistor R67 and the first end of the capacitor C48 are both connected on the common connection end between the base of the triode Q9 and the resistor R62, the second end of the resistor R67, the second end of the capacitor C48 and the emitter of the triode Q9 are all grounded; the collector of the triode Q9 is electrically connected with the +5V power supply end through the diode D12; the first end of the coil of the relay K4 is connected on the common connection end between the collector of the triode Q9 and the diode D12, the second end of the coil of the relay K4 is connected on the common connection end between the diode D12 and the +5V power supply end; the first moving contact, the second moving contact, the first normally open static contact and the second normally open static contact of the relay K4 are all electrically connected with the network circuit.

[0039] Optionally, the network circuit comprises an Ethernet switch chip, a network transformer chip U5, a network transformer chip U4, an Ethernet connector J2A, an Ethernet connector J2B, a common mode inductor L4, a common mode inductor L5, a common mode inductor L6, a common mode inductor L7, a resistor R31, a resistor R36, a resistor R37, a resistor R38, a resistor R39, a resistor R40, a resistor R41, a resistor R42, a resistor R43, a capacitor C29, a capacitor C30, a capacitor C31, a capacitor C32, a capacitor C33, a capacitor C34, a capacitor C35, a capacitor C36 and a capacitor C37; wherein the Ethernet connector J2A and the Ethernet connector J2B are both Ethernet connectors with 8 pins and 1 port;

[0040] The network signal input end and the network signal output end of the master control circuit are both electrically connected with the Ethernet switch chip, the sending data positive pole pin TD+, the sending data negative pole pin TD-, the receiving data positive pole pin RD+ and the receiving data negative pole pin RD- of the network transformer chip U5 are all electrically connected with the Ethernet switch chip; the neutral point pin TCT1 of the network transformer chip U5 is grounded through the capacitor C37, the reverse point pin RCT1 of the network transformer chip U5 is grounded through the capacitor C36;

[0041] The same name end of the primary coil of the common mode inductor L4 is electrically connected with the forward differential signal transmission pin TX+ of the network transformer chip U5, and the non-same name end of the primary coil of the common mode inductor L4 is electrically connected with the first normally open static contact of the relay K1; the same name end of the secondary coil of the common mode inductor L4 is electrically connected with the reverse differential signal transmission pin TX- of the network transformer chip U5, and the non-same name end of the secondary coil of the common mode inductor L4 is electrically connected with the second normally open static contact of the relay K1; the non-same name end of the primary coil of the common mode inductor L6 is electrically connected with the forward differential signal receiving pin RX+ of the network transformer chip U5, and the same name end of the primary coil of the common mode inductor L6 is electrically connected with the first normally open static contact of the relay K2; the non-same name end of the secondary coil of the common mode inductor L6 is electrically connected with the reverse differential signal receiving pin RX- of the network transformer chip U5, and the same name end of the secondary coil of the common mode inductor L6 is electrically connected with the second normally open static contact of the relay K2; the clock output pin CMT1 of the network transformer chip U5 is grounded through the resistor R41 and the capacitor C33 in sequence, and the clock input pin CMT2 of the network transformer chip U5 is connected between the resistor R41 and the capacitor C33 through the resistor R43;

[0042] The port of the Ethernet connector J2A is connected with the port of the Ethernet connector J2B and grounded, the first end of the resistor R31 and the first end of the capacitor C29 are both connected on the common connection end between the port of the Ethernet connector J2A and the port of the Ethernet connector J2B, and the second end of the resistor R31 and the second end of the capacitor C29 are both grounded; the No.1 pin of the Ethernet connector J2A is electrically connected with the first moving contact of the relay K1, the No.2 pin of the Ethernet connector J2A is electrically connected with the second moving contact of the relay K1, the No.3 pin of the Ethernet connector J2A is electrically connected with the first moving contact of the relay K2, and the No.6 pin of the Ethernet connector J2A is electrically connected with the second moving contact of the relay K2; the No.4 pin and the No.5 pin of the Ethernet connector J2A are connected together and grounded through the resistor R39 and the capacitor C31 in sequence; the No.7 pin and the No.8 pin of the Ethernet connector J2A are connected together and connected on the common connection end between the resistor R39 and the capacitor C31 through the resistor R37;

[0043] The sending data positive pole pin TD+, the sending data negative pole pin TD-, the receiving data positive pole pin RD+ and the receiving data negative pole pin RD- of the network transformer chip U4 are electrically connected with the Ethernet exchange chip; the neutral point pin TCT1 of the network transformer chip U4 is grounded through the capacitor C35, and the reverse point pin RCT1 of the network transformer chip U4 is grounded through the capacitor C34;

[0044] The forward differential signal sending pin TX+ of the network transformer chip U4 is electrically connected with the same name end of the primary coil of the common mode inductor L5, and the non-same name end of the primary coil of the common mode inductor L5 is electrically connected with the first normally open static contact of the relay K3; the reverse differential signal sending pin TX- of the network transformer chip U4 is electrically connected with the same name end of the secondary coil of the common mode inductor L5, and the non-same name end of the secondary coil of the common mode inductor L5 is electrically connected with the second normally open static contact of the relay K3; the forward differential signal receiving pin RX+ of the network transformer chip U4 is electrically connected with the non-same name end of the primary coil of the common mode inductor L7, and the same name end of the primary coil of the common mode inductor L7 is electrically connected with the first normally open static contact of the relay K4; the reverse differential signal receiving pin RX- of the network transformer chip U4 is electrically connected with the non-same name end of the secondary coil of the common mode inductor L7, and the same name end of the secondary coil of the common mode inductor L7 is electrically connected with the second normally open static contact of the relay K4; the clock output pin CMT1 of the network transformer chip U4 is grounded in sequence through the resistor R40 and the capacitor C32, and the clock input pin CMT2 of the network transformer chip U4 is connected between the resistor R40 and the capacitor C32 on the common connection end through the resistor R42;

[0045] The 1st pin of the Ethernet connector J2B is electrically connected with the first moving contact of the relay K3, the 2nd pin of the Ethernet connector J2B is electrically connected with the second moving contact of the relay K3, the 3rd pin of the Ethernet connector J2B is electrically connected with the first moving contact of the relay K4, and the 6th pin of the Ethernet connector J2B is electrically connected with the second moving contact of the relay K4; the 4th pin and the 5th pin of the Ethernet connector J2B are connected together and grounded in sequence through the resistor R38 and the capacitor C30; the 7th pin and the 8th pin of the Ethernet connector J2B are connected together and connected between the resistor R38 and the capacitor C30 on the common connection end through the resistor R36.

[0046] In addition, the application further provides an upgrading and maintaining method of the embedded system, which adopts the upgrading and maintaining device of the embedded system to upgrade and maintain the embedded system, and the method comprises the following steps:

[0047] When the embedded system starts the upgrading process, the master control circuit sends a holding function trigger signal to the holding function trigger circuit;

[0048] The holding function trigger circuit receives the holding function trigger signal and controls the output channel of the holding signal circuit to open according to the holding function trigger signal;

[0049] When the output channel of the holding signal circuit is open, the holding signal circuit generates a holding drive signal and sends the holding drive signal to the bypass control circuit and the watchdog inhibit reset circuit respectively;

[0050] When the bypass control circuit receives the holding drive signal, it controls the bypass function of the embedded system to be disabled according to the holding drive signal, so that the connection between the network circuit and the network signal end of the bypass control circuit is successful; when the watchdog inhibit reset circuit receives the holding drive signal, it controls the watchdog reset function of the embedded system to be disabled according to the holding drive signal;

[0051] When the embedded system completes the upgrading process, the master control circuit sends a holding function release signal to the holding function release circuit;

[0052] The holding function release circuit receives the holding function release signal and controls the output channel of the holding signal circuit to close according to the holding function release signal;

[0053] When the bypass control circuit does not receive the holding drive signal, it releases the bypass function of the embedded system to be disabled, so that the connection between the network circuit and the network signal end of the bypass control circuit is disconnected; when the watchdog inhibit reset circuit does not receive the holding drive signal, it releases the watchdog reset function of the embedded system to be disabled.

[0054] The beneficial effects of the present application are as follows: when the main control circuit starts the upgrading process, the main control circuit sends a keep function trigger signal, opens the output channel of the keep signal circuit by using the keep function trigger circuit, and makes the keep signal circuit output keep driving signals to the bypass control circuit and the watchdog inhibit reset circuit respectively; based on the keep driving signals, on the one hand, the bypass control circuit controls the bypass function of the embedded system to be disabled, so that the connection between the network circuit and the network signal end of the bypass control circuit is successful, and the network terminal device and the embedded system are connected, and the upgrading process is not interrupted; on the other hand, the watchdog inhibit reset circuit controls the watchdog reset function of the embedded system to be disabled, so that the watchdog reset function is disabled, and the upgrading process cannot be completed due to the watchdog reset; based on the bypass function being disabled and the watchdog reset function being disabled, the software upgrading process of the embedded system can be effectively ensured not to be interrupted, the software upgrading is kept, and the embedded system is normally software upgraded.

[0055] When the embedded system completes the upgrading process, the main control circuit sends a keep function release signal, closes the output channel of the keep signal circuit by using the keep function release circuit, and makes the keep signal circuit not output keep driving signals to the bypass control circuit and the watchdog inhibit reset circuit respectively, and then the bypass control circuit and the watchdog inhibit reset circuit do not receive the keep driving signals, at this time, the bypass control circuit releases the bypass function from being disabled, restores the bypass function, makes the connection between the network circuit and the network signal end of the bypass control circuit disconnected, and then the network between the network terminal device and the embedded system is disconnected; at the same time, the watchdog inhibit reset circuit restores the watchdog reset function.

[0056] The upgrading keeping device and the upgrading keeping method of the embedded system can effectively ensure that the software upgrading process of the embedded system is not interrupted, keep the software upgrading, and ensure that the embedded system is normally software upgraded based on the bypass function being disabled and the watchdog reset function being disabled during the software upgrading process; and the bypass function and the watchdog reset function are restored after the software upgrading is completed. BRIEF DESCRIPTION OF DRAWINGS

[0057] The features and advantages of the present application will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, which are shown by way of illustration and not by way of limitation, in which:

[0058] Figure 1 Fig. 1 shows a structure diagram of an upgrading keeping device of an embedded system in an embodiment of the present application;

[0059] Figure 2The diagram shows the design of the hold signal circuit, the hold function trigger circuit, and the hold function release circuit in Embodiment 1 of the present invention;

[0060] Figure 3 This diagram shows a partial design of the watchdog reset disable circuit in Embodiment 1 of the present invention;

[0061] Figure 4 The design diagram of the bypass drive sub-circuit in Embodiment 1 of the present invention is shown;

[0062] Figures 5A-5D The design diagram of the bypass relay sub-circuit in Embodiment 1 of the present invention is shown;

[0063] Figures 6A-6B and Figure 7 The diagram shows the design of the network circuit in Embodiment 1 of the present invention;

[0064] Figure 8 The design diagram of the main control circuit in Embodiment 1 of the present invention is shown;

[0065] Figure 9 A flowchart of an upgrade retention method for an embedded system according to Embodiment 2 of the present invention is shown. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0067] Example 1

[0068] like Figure 1 As shown, an upgrade holding device for an embedded system includes a main control circuit, a network circuit, a bypass control circuit, a watchdog timer disable reset circuit, a holding function trigger circuit, a holding function release circuit, and a holding signal circuit.

[0069] The network signal input end and the network signal output end of the master control circuit are electrically connected with the network signal end of the bypass control circuit through the network circuit, the control signal output end of the master control circuit is electrically connected with the control signal end of the bypass control circuit, the input end of the watchdog inhibition reset circuit, the input end of the holding function trigger circuit and the input end of the holding function release circuit, the control signal input end of the master control circuit is electrically connected with the control signal end of the bypass control circuit and the output end of the watchdog inhibition reset circuit; the output end of the holding function trigger circuit and the output end of the holding function release circuit are electrically connected with the input end of the holding signal circuit, and the output end of the holding signal circuit is electrically connected with the control signal end of the bypass control circuit and the input end of the watchdog inhibition reset circuit;

[0070] The master control circuit is configured to send a holding function trigger signal to the holding function trigger circuit when the embedded system starts an upgrade process.

[0071] The holding function trigger circuit is configured to receive the holding function trigger signal and control the output channel of the holding signal circuit to be opened according to the holding function trigger signal.

[0072] The holding signal circuit is configured to generate a holding driving signal when the output channel is opened and send the holding driving signal to the bypass control circuit and the watchdog inhibition reset circuit respectively.

[0073] The bypass control circuit is configured to control the disablement of the bypass function of the embedded system according to the holding driving signal when the holding driving signal is received, so that the connection between the network circuit and the network signal end of the bypass control circuit is successful.

[0074] The watchdog inhibition reset circuit is configured to control the disablement of the watchdog reset function of the embedded system according to the holding driving signal when the holding driving signal is received.

[0075] The master control circuit is further configured to send a holding function release signal to the holding function release circuit when the embedded system completes the upgrade process.

[0076] The holding function release circuit is configured to receive the holding function release signal and control the output channel of the holding signal circuit to be closed according to the holding function release signal.

[0077] The bypass control circuit is also configured to, when the holding driving signal is not received, disable the bypass function of the embedded system, so that the connection between the network circuit and the network signal end of the bypass control circuit is disconnected.

[0078] The watchdog reset circuit is also configured to, when the holding driving signal is not received, disable the watchdog reset function of the embedded system.

[0079] In this embodiment, when the upgrade process is started, the master control circuit sends a holding function triggering signal, and uses the holding function triggering circuit to open the output channel of the holding signal circuit, so that the holding signal circuit outputs a holding driving signal to the bypass control circuit and the watchdog reset circuit respectively. Based on the holding driving signal, on the one hand, the bypass control circuit controls the bypass function of the embedded system to be disabled, so that the connection between the network circuit and the network signal end of the bypass control circuit is successful, and the network terminal device and the embedded system are connected, and the upgrade process is not interrupted; on the other hand, the watchdog reset circuit controls the watchdog reset function of the embedded system to be disabled, so that the watchdog reset function is invalid, and the upgrade process cannot be completed due to the watchdog reset. Based on the bypass function being disabled and the watchdog reset function being invalid, the software upgrade process of the embedded system can be effectively ensured not to be interrupted, the software upgrade is kept, and the normal software upgrade of the embedded system is ensured.

[0080] When the embedded system completes the upgrade process, the master control circuit sends a holding function release signal, and uses the holding function release circuit to close the output channel of the holding signal circuit, so that the holding signal circuit does not output the holding driving signal to the bypass control circuit and the watchdog reset circuit respectively. Then, the bypass control circuit and the watchdog reset circuit do not receive the holding driving signal. At this time, the bypass control circuit releases the bypass function due to not receiving the holding driving signal, restores the bypass function, so that the connection between the network circuit and the network signal end of the bypass control circuit is disconnected, and the network between the network terminal device and the embedded system is disconnected. At the same time, the watchdog reset circuit restores the watchdog reset function due to not receiving the holding driving signal.

[0081] The upgrade keeping device of the embedded system in this embodiment can effectively ensure that the software upgrade process of the embedded system is not interrupted based on the bypass function being disabled and the watchdog reset function being invalid, keep the software upgrade, and ensure the normal software upgrade of the embedded system. After the software upgrade is completed, the bypass function and the watchdog reset function are restored.

[0082] Preferably, as Figure 2As shown in the figure, the holding signal circuit comprises a transistor Q10, a transistor Q11, a resistor R8, a resistor R78, a resistor R80, a resistor R81 and a resistor R93;

[0083] The emitter of the transistor Q10 is electrically connected with the circuit power supply end, the base of the transistor Q10 is electrically connected with the output end of the holding function triggering circuit and the output end of the holding function releasing circuit through the resistor R81, the base of the transistor Q10 is further electrically connected with the base of the transistor Q11 through the resistor R81 and the resistor R93 in sequence, the collector of the transistor Q10 is electrically connected with the control signal end of the bypass control circuit and the input end of the watchdog inhibition reset circuit, the first end of the resistor R78 is connected on the common connection end between the emitter of the transistor Q10 and the circuit power supply end, and the second end of the resistor R78 is connected on the common connection end between the base of the transistor Q10 and the resistor R81;

[0084] The emitter of the transistor Q11 is electrically connected with the circuit power supply end, the first end of the resistor R80 is connected on the common connection end between the emitter of the transistor Q11 and the circuit power supply end, and the second end of the resistor R80 is connected on the common connection end between the base of the transistor Q11 and the resistor R93; the collector of the transistor Q11 is electrically connected with the output end of the holding function releasing circuit through the resistor R8.

[0085] In the holding signal circuit with the above structure, the output end of the holding function triggering circuit and the output end of the holding function releasing circuit are respectively connected between the resistor R81 and the resistor R93, and the resistor R81 is connected with the base of the transistor Q10, so that the transistor Q10 can be controlled to be turned on by the holding function triggering signal output by the holding function triggering circuit, and then the output channel of the holding signal circuit is opened to realize the software upgrade holding; on the other hand, the transistor Q10 can be controlled to be turned off by the holding function releasing signal output by the holding function releasing circuit, and then the output channel of the holding signal circuit is closed to release the software upgrade holding.

[0086] Preferably, as Figure 2 As shown in the figure, the holding function triggering circuit comprises an operational amplifier U2, a diode D2, a transistor Q12, a resistor R7, a resistor R9, a resistor R11, a resistor R12, a resistor R15, a resistor R85, a resistor R90, a capacitor C3, a capacitor C4 and a capacitor C53;

[0087] The power supply pin of the operational amplifier U2 is electrically connected with the circuit power supply end, and the grounding pin of the operational amplifier U2 is grounded; the positive input pin of the operational amplifier U2 is electrically connected with the control signal output end of the master control circuit through the resistor R12 and the capacitor C3 in sequence, the first end of the resistor R15 and the first end of the capacitor C4 are both connected to the common connection end between the positive input pin of the operational amplifier U2 and the resistor R12, the second end of the resistor R15 and the second end of the capacitor C4 are both grounded, the first end of the diode D2 is connected to the common connection end between the resistor R12 and the capacitor C3, and the second end of the diode D2 is grounded; the inverting input pin of the operational amplifier U2 is electrically connected with the circuit power supply end through the resistor R7, and the first end of the resistor R9 is connected to the common connection end between the inverting input pin of the operational amplifier U2 and the resistor R7, and the second end of the resistor R9 is grounded; the output pin of the operational amplifier U2 is electrically connected with the base of the triode Q12 through the resistor R85, and the output pin of the operational amplifier U2 is also electrically connected with the circuit power supply end through the resistor R11; the first end of the resistor R90 and the first end of the capacitor C53 are both connected to the common connection end between the resistor R85 and the base of the triode Q12, and the second end of the resistor R90 and the second end of the capacitor C53 are both grounded; the collector of the triode Q12 is connected to the common connection end between the resistor R81 and the resistor R93, and the emitter of the triode Q12 is grounded.

[0088] In the above-mentioned structure of the holding function trigger circuit, in combination with the holding signal circuit in Figure 2 , when the embedded system starts the software upgrade process, first, the master control circuit sends a series of pulse signals (i.e. holding function trigger signals) to one end of the capacitor C3 (specifically, the port SET in Figure 2 ), and then transmits the pulse signals to the positive input pin of the operational amplifier U2 through the capacitor C3 and the resistor R12, so that the + end voltage of the operational amplifier U2 is higher than the - end (i.e. the voltage of the positive input pin is higher than the voltage of the inverting input pin), the operational amplifier U2 outputs a high level, so that the triode Q12 is turned on, at this time, the triode Q10 is also turned on, the output channel is opened, and the collector of the triode Q10 (specifically, the port Rdy_Bypass_Disen in Figure 2 ) outputs a high level (i.e. outputs a holding driving signal), so as to realize the holding of the upgrade signal; the output holding driving signal simultaneously drives the bypass control circuit and the watchdog inhibit reset circuit, and simultaneously realizes the disablement of the bypass function and the watchdog reset function.

[0089] Preferably, as Figure 2As shown, the holding function release circuit comprises an operational amplifier U3, a diode D3, a transistor Q5, a transistor Q16, a resistor R10, a resistor R13, a resistor R14, a resistor R16, a resistor R17, a resistor R18, a resistor R89, a resistor R94, a capacitor C5, a capacitor C6 and a capacitor C52;

[0090] A power supply pin of the operational amplifier U3 is electrically connected to the circuit power supply end, and a ground pin of the operational amplifier U3 is grounded; a positive input pin of the operational amplifier U3 is electrically connected to the control signal output end of the master control circuit through the resistor R17 and the capacitor C5 in sequence, and a first end of the resistor R18 and a first end of the capacitor C6 are both connected to a common connection end between the positive input pin of the operational amplifier U3 and the resistor R17, a second end of the resistor R18 and a second end of the capacitor C6 are both grounded, a first end of the diode D3 is connected to a common connection end between the resistor R17 and the capacitor C5, and a second end of the diode D3 is grounded; an inverting input pin of the operational amplifier U3 is electrically connected to the circuit power supply end through the resistor R10, and a first end of the resistor R13 is connected to a common connection end between the inverting input pin of the operational amplifier U3 and the resistor R10, and a second end of the resistor R13 is grounded; an output pin of the operational amplifier U3 is electrically connected to a base of the transistor Q5, and the output pin of the operational amplifier U3 is also electrically connected to the circuit power supply end through the resistor R14; a first end of the resistor R16 is connected to a common connection end between the output pin of the operational amplifier U3 and the base of the transistor Q5, and a second end of the resistor R16 is grounded; an emitter of the transistor Q5 is grounded, a collector of the transistor Q5 is electrically connected to a base of the transistor Q16 through the resistor R94, and the resistor R8 in the holding signal circuit is connected to a common connection end between the collector of the transistor Q5 and the resistor R94; a first end of the resistor R89 and a first end of the capacitor C52 are both connected to a common connection end between the resistor R94 and the base of the transistor Q16, and a second end of the resistor R89 and a second end of the capacitor C52 are both grounded; an emitter of the transistor Q16 is grounded, and a collector of the transistor Q16 is connected to a common connection end between the resistor R81 and the resistor R93.

[0091] In the holding function release circuit with the above structure, in combination with the holding signal circuit in the Figure 2 , when the embedded system completes the software upgrading process, the master control circuit electrically connects one end of the capacitor C5 in the above holding function release circuit (specifically, the capacitor C5 is electrically connected to the control signal output end of the master control circuit through the resistor R17 and the capacitor C5 in sequence). Figure 2a series of pulse signals (i.e. the keep function release signal) is sent, and then the pulse signals are transmitted to the non-inverting input pin of the operational amplifier U3 through the capacitor C5 and the resistor R17 in sequence, so that the voltage at the + terminal of the operational amplifier U3 is higher than that at the - terminal (i.e. the voltage at the non-inverting input pin is higher than that at the inverting input pin), the operational amplifier U3 outputs a high level, so that the transistor Q5 is turned on, the transistor Q16 is thus turned off, and the transistor Q10 is also turned off, so that the output channel thereof is closed and cannot output the keep driving signal (specifically Figure 3 the keep driving signal) to the bypass control circuit and the watchdog reset disable circuit, thereby releasing the disable of the bypass function and the watchdog reset function.

[0092] Specifically, in the keep function trigger circuit, the keep function release circuit and the keep signal circuit, the operational amplifier U2 and the operational amplifier U3 are both of the LMC7211BIM5 / NOPB type, the transistors Q5, Q10, Q11, Q12 and Q16 are all of the L8050QLT1G type, the diodes D2 and D3 are both of the SS34 type, and the other resistors and capacitors can be selected according to actual conditions.

[0093] Preferably, as shown in Figure 3 the watchdog reset disable circuit includes a watchdog chip U1, a transistor Q1, a transistor Q2, a diode D1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a capacitor C1 and a capacitor C2.

[0094] The power supply pin VDD of the watchdog chip U1 is electrically connected to the circuit power supply end, the first end of the capacitor C1 is connected to a common connection end between the power supply pin VDD of the watchdog chip U1 and the circuit power supply end, and the second end of the capacitor C1 is grounded. The watchdog signal input pin WDI of the watchdog chip U1 is electrically connected to the control signal output end of the master control circuit, the first end of the resistor R6 is connected to a common connection end between the watchdog signal input pin WDI of the watchdog chip U1 and the control signal output end of the master control circuit, and the second end of the resistor R6 is grounded. The ground pin GND of the watchdog chip U1 is grounded, the manual reset pin MR# of the watchdog chip U1 is suspended, the hardware reset pin RESET# of the watchdog chip U1 is electrically connected to the collector of the transistor Q1 through the resistor R3, the anode of the diode D1 is electrically connected to the control signal input end of the master control circuit, and the cathode of the diode D1 is connected to a common connection end between the resistor R3 and the collector of the transistor Q1.

[0095] The base of the transistor Q1 is electrically connected with the collector of the transistor Q2 through the resistor R2, the emitter of the transistor Q1 is electrically connected with the circuit power supply end, the first end of the resistor R1 is connected on the common connection end between the base of the transistor Q1 and the resistor R2, and the second end of the resistor R1 is connected on the common connection end between the emitter of the transistor Q1 and the circuit power supply end; the base of the transistor Q2 is electrically connected with the output end of the holding signal circuit through the resistor R4, and the first end of the resistor R5 and the first end of the capacitor C2 are both connected on the common connection end between the base of the transistor Q2 and the resistor R4, and the second end of the resistor R5, the second end of the capacitor C2 and the emitter of the transistor Q2 are all grounded.

[0096] In the watchdog reset inhibition circuit with the above structure, one end (specifically, the port Rdy_Bypass_Disen in Figure 3 is electrically connected with the output end of the holding signal circuit, and when the output channel of the holding signal circuit is opened, the holding driving signal is received, at this time, the output of the watchdog chip U1 is disabled due to the high level output by the transistor Q2 and is locked at the high level, that is, the watchdog reset function is disabled, and further, it is ensured that the watchdog does not cause the reset of the chip when the embedded system is started and upgraded; and when the output channel of the holding signal circuit is closed, the port Rdy_Bypass_Disen in Figure 3 does not receive the holding driving signal, and the output of the watchdog chip U1 is not locked at the high level, then the watchdog reset function returns to normal, and it is ensured that the embedded system is normally reset after the upgrade is completed. The watchdog signal input pin WDI of the watchdog chip U1 is electrically connected with the control signal output end of the master control circuit, and when the watchdog reset function returns to normal, the watchdog signal (specifically, the port Feed Watchdog in Figure 3 receives the watchdog signal), so as to ensure the implementation of the watchdog reset function; the hardware reset pin RESET# of the watchdog chip U1 is also electrically connected with the control signal input end of the master control circuit through the resistor R3 and the diode D1, and the signal output by the collector of the transistor Q1 (specifically, the port NETX_RESET_IN# in Figure 4 ) is fed back to the master control circuit, so as to realize the state feedback of the watchdog chip.

[0097] Specifically, in the watchdog reset disable circuit described above in this embodiment, the watchdog chip U1 is a TPS3823-33DBVR model watchdog chip, the diode D1 is a BAS316 model diode, the transistor Q1 is an L8550HQLT1G model transistor, the transistor Q2 is an L8050QLT1G model transistor, and the other resistors and capacitors can be selected according to the actual situation, and will not be listed here.

[0098] Preferably, the bypass control circuit includes a bypass drive sub-circuit and a bypass relay sub-circuit;

[0099] The input terminal of the bypass driver sub-circuit is electrically connected to the control signal output terminal of the main control circuit and the output terminal of the holding signal circuit, respectively. The output terminal of the bypass driver sub-circuit is electrically connected to the input terminal of the bypass relay sub-circuit and the control signal input terminal of the main control circuit, respectively. The bypass relay sub-circuit is also electrically connected to the network circuit.

[0100] In the bypass control circuit described above, the bypass drive sub-circuit can simultaneously receive the control signal output from the control signal output terminal of the main control circuit and the holding drive signal output from the holding signal circuit. Depending on whether the holding drive signal is received, it determines whether to drive the bypass relay sub-circuit in conjunction with the control signal, thereby switching the switching state of the relay in the bypass relay sub-circuit. Since the bypass relay sub-circuit is also electrically connected to the network circuit, the connection state between the network circuit and the network signal terminal of the bypass control circuit can be controlled by switching the relay, thereby enabling the disabling and deactivation of the bypass function.

[0101] Preferably, such as Figure 4 As shown, the bypass driver sub-circuit includes transistor Q3, transistor Q4, diode D8, resistors R52, R53, R54, R55, R56 and capacitor C42.

[0102] The negative electrode of the diode D8 is electrically connected with the control signal output end of the master control circuit, the positive electrode of the diode D8 is electrically connected with the base of the triode Q3 through the resistor R53, the emitter of the triode Q3 is electrically connected with the circuit power supply end, and the collector of the triode Q3 is electrically connected with the input end of the bypass relay sub-circuit and the control signal input end of the master control circuit respectively; the first end of the resistor R52 and the first end of the resistor R54 are both connected on the common connection end between the resistor R53 and the base of the triode Q3, the second end of the resistor R52 is connected on the common connection end between the emitter of the triode Q3 and the circuit power supply end, and the second end of the resistor R54 is electrically connected with the collector of the triode Q4;

[0103] The base of the triode Q4 is electrically connected with the output end of the holding signal circuit through the resistor R55, the first end of the resistor R56 and the first end of the capacitor C42 are both connected on the common connection end between the base of the triode Q4 and the resistor R55, and the second end of the resistor R56, the second end of the capacitor C42 and the emitter of the triode Q4 are all grounded.

[0104] Through the bypass driving sub-circuit with the above structure, the accurate driving of the bypass relay sub-circuit in the rear stage can be realized, so as to realize the accurate switching of the switching state of the relay in the bypass relay sub-circuit. The output end of the bypass driving sub-circuit is the port NET_Relay_Con in Figures 5A-5D , which is electrically connected with the bypass relay sub-circuit to control the switching of the switching state of the relay in the bypass relay sub-circuit, and is also electrically connected with the control signal input end of the master control circuit to realize the signal feedback of the bypass driving sub-circuit.

[0105] Preferably, as shown in Figures 5A-5D , the bypass relay sub-circuit comprises a relay K1, a relay K2, a relay K3, a relay K4, a triode Q6, a triode Q7, a triode Q8, a triode Q9, a diode D9, a diode D10, a diode D11, a diode D12, a resistor R59, a resistor R60, a resistor R61, a resistor R62, a resistor R64, a resistor R65, a resistor R66, a resistor R67, a capacitor C45, a capacitor C46, a capacitor C47 and a capacitor C48; wherein the relay K1, the relay K2, the relay K3 and the relay K4 are all double-pole double-throw relays switched in two groups;

[0106] The base of the triode Q6 is electrically connected with the output end of the bypass drive sub-circuit through the resistor R59, the first end of the resistor R64 and the first end of the capacitor C45 are both connected on the common connection end between the base of the triode Q6 and the resistor R59, the second end of the resistor R64, the second end of the capacitor C45 and the emitter of the triode Q6 are all grounded; the collector of the triode Q6 is electrically connected with the +5V power supply end through the diode D9;

[0107] The first end of the coil of the relay K1 is connected on the common connection end between the collector of the triode Q6 and the diode D9, the second end of the coil of the relay K1 is connected on the common connection end between the diode D9 and the +5V power supply end; the first moving contact, the second moving contact, the first normally open static contact and the second normally open static contact of the relay K1 are all electrically connected with the network circuit, the first normally closed static contact of the relay K1 is electrically connected with the first normally closed static contact of the relay K3, the second normally closed static contact of the relay K1 is electrically connected with the second normally closed static contact of the relay K3;

[0108] The base of the triode Q7 is electrically connected with the output end of the bypass drive sub-circuit through the resistor R60, the first end of the resistor R65 and the first end of the capacitor C46 are both connected on the common connection end between the base of the triode Q7 and the resistor R60, the second end of the resistor R65, the second end of the capacitor C46 and the emitter of the triode Q7 are all grounded; the collector of the triode Q7 is electrically connected with the +5V power supply end through the diode D10;

[0109] The first end of the coil of the relay K2 is connected on the common connection end between the collector of the triode Q7 and the diode D10, the second end of the coil of the relay K2 is connected on the common connection end between the diode D10 and the +5V power supply end; the first moving contact, the second moving contact, the first normally open static contact and the second normally open static contact of the relay K2 are all electrically connected with the network circuit, the first normally closed static contact of the relay K2 is electrically connected with the first normally closed static contact of the relay K4, the second normally closed static contact of the relay K2 is electrically connected with the second normally closed static contact of the relay K4;

[0110] The base of the triode Q8 is electrically connected with the output end of the bypass drive sub-circuit through the resistor R61, the first end of the resistor R66 and the first end of the capacitor C47 are both connected on the common connection end between the base of the triode Q8 and the resistor R61, the second end of the resistor R66, the second end of the capacitor C47 and the emitter of the triode Q8 are all grounded; the collector of the triode Q8 is electrically connected with the +5V power supply end through the diode D11; the first end of the coil of the relay K3 is connected on the common connection end between the collector of the triode Q8 and the diode D11, the second end of the coil of the relay K3 is connected on the common connection end between the diode D11 and the +5V power supply end; the first moving contact, the second moving contact, the first normally open static contact and the second normally open static contact of the relay K3 are all electrically connected with the network circuit;

[0111] The base of the triode Q9 is electrically connected with the output end of the bypass drive sub-circuit through the resistor R62, the first end of the resistor R67 and the first end of the capacitor C48 are both connected on the common connection end between the base of the triode Q9 and the resistor R62, the second end of the resistor R67, the second end of the capacitor C48 and the emitter of the triode Q9 are all grounded; the collector of the triode Q9 is electrically connected with the +5V power supply end through the diode D12; the first end of the coil of the relay K4 is connected on the common connection end between the collector of the triode Q9 and the diode D12, the second end of the coil of the relay K4 is connected on the common connection end between the diode D12 and the +5V power supply end; the first moving contact, the second moving contact, the first normally open static contact and the second normally open static contact of the relay K4 are all electrically connected with the network circuit.

[0112] In the bypass relay subcircuit with the above structure, the switch circuit composed of four double-pole double-throw relays is included, each double-pole double-throw relay has two sets of switching mechanisms of switch states; the first normally closed static contact of the relay K1 is electrically connected with the first normally closed static contact of the relay K3, the second normally closed static contact of the relay K1 is electrically connected with the second normally closed static contact of the relay K3, and the first normally closed static contact of the relay K2 is electrically connected with the first normally closed static contact of the relay K4, the second normally closed static contact of the relay K2 is electrically connected with the second normally closed static contact of the relay K4, which can control the relays K1 and K3 to switch to the closed state when the bypass relay subcircuit receives the signal output by the bypass driving subcircuit (i.e. the embedded system starts the upgrading process), and then make the loop between the relays K1 and K3 closed, also control the relays K2 and K4 to switch to the closed state, and then make the loop between the relays K2 and K4 closed, so that the connection between the entire bypass control circuit and the network circuit is successful, the bypass function is disabled, and the network circuit is prevented from starting according to the bypass function, which causes the network between the network terminal device and the embedded system to be disconnected, and the upgrading process is interrupted; also can control the relays K1 and K3 to switch to the open state when the bypass relay subcircuit does not receive the signal output by the bypass driving subcircuit (i.e. the embedded system completes the upgrading process), and then make the loop between the relays K1 and K3 open, also control the relays K2 and K4 to switch to the open state, and then make the loop between the relays K2 and K4 open, so that the connection between the entire bypass control circuit and the network circuit is disconnected, and the bypass function is enabled.

[0113] Specifically, in the present embodiment, the relays K1, K2, K3 and K4 each have 8 contacts, including 2 sets of moving contacts (i.e. contacts 1 and 2 in Figures 5A-5D each relay), 2 sets of normally open static contacts (i.e. contacts 4 and 5 in Figures 5A-5D each relay), 2 sets of normally closed static contacts (i.e. contacts 2 and 7 in Figures 5A-5D each relay) and 2 coil contacts (i.e. contacts 3 and 6 in Figures 6A-6BThe contact 1 and the contact 8 of each relay); 2 sets of switching mechanisms of each relay, including two sets of conversion from normally open to normally closed, and two sets of conversion from normally closed to normally open, when the bypass relay subcircuit receives the signal output by the bypass driving subcircuit, 2 sets of moving contacts (i.e. the contact 3 and the contact 6) in each relay are connected with 2 sets of normally closed static contacts (i.e. the contact 2 and the contact 7) respectively, to realize the closing of the corresponding relay respectively; when the bypass relay subcircuit does not receive the signal output by the bypass driving subcircuit, 2 sets of moving contacts (i.e. the contact 3 and the contact 6) in each relay are switched from being connected with 2 sets of normally closed static contacts (i.e. the contact 2 and the contact 7) to being connected with 2 sets of normally open static contacts (i.e. the contact 4 and the contact 5) respectively, to realize the opening of the corresponding relay respectively.

[0114] Specifically, in the bypass driving subcircuit described above, the diode D8 is selected as a BAS316 type diode, the transistor Q3 is selected as an L8550HQLT1G type transistor, and the transistor Q4 is selected as an L8050QLT1G type transistor; in the bypass relay subcircuit described above, the relays K1, K2, K3 and K4 are all selected as G6K-2F-Y-TR type relays, the transistors Q6, Q7, Q8 and Q9 are all selected as L8050QLT1G type transistors, and the diodes D9, D10, D11 and D12 are all selected as 1N4148WS type diodes; the resistors and the capacitors can all be selected according to actual conditions, and appropriate specifications or types are not listed here.

[0115] Preferably, as shown in Figure 7 and Figure 7 , the network circuit includes an Ethernet switch chip, a network transformer chip U5, a network transformer chip U4, an Ethernet connector J2A, an Ethernet connector J2B, a common mode inductor L4, a common mode inductor L5, a common mode inductor L6, a common mode inductor L7, a resistor R31, a resistor R36, a resistor R37, a resistor R38, a resistor R39, a resistor R40, a resistor R41, a resistor R42, a resistor R43, a capacitor C29, a capacitor C30, a capacitor C31, a capacitor C32, a capacitor C33, a capacitor C34, a capacitor C35, a capacitor C36 and a capacitor C37; wherein the Ethernet connector J2A and the Ethernet connector J2B are both Ethernet connectors with 8 pins and 1 port;

[0116] The network signal input end and the network signal output end of the master control circuit are electrically connected with the Ethernet exchange chip, the sending data positive pole pin TD+, the sending data negative pole pin TD-, the receiving data positive pole pin RD+ and the receiving data negative pole pin RD- of the network transformer chip U5 are electrically connected with the Ethernet exchange chip; the neutral point pin TCT1 of the network transformer chip U5 is grounded through the capacitor C37, the reverse point pin RCT1 of the network transformer chip U5 is grounded through the capacitor C36;

[0117] The forward differential signal sending pin TX+ of the network transformer chip U5 is electrically connected with the same name end of the primary coil of the common mode inductor L4, the non-same name end of the primary coil of the common mode inductor L4 is electrically connected with the first normally open static contact of the relay K1; the reverse differential signal sending pin TX- of the network transformer chip U5 is electrically connected with the same name end of the secondary coil of the common mode inductor L4, the non-same name end of the secondary coil of the common mode inductor L4 is electrically connected with the second normally open static contact of the relay K1; the forward differential signal receiving pin RX+ of the network transformer chip U5 is electrically connected with the non-same name end of the primary coil of the common mode inductor L6, the same name end of the primary coil of the common mode inductor L6 is electrically connected with the first normally open static contact of the relay K2; the reverse differential signal receiving pin RX- of the network transformer chip U5 is electrically connected with the non-same name end of the secondary coil of the common mode inductor L6, the same name end of the secondary coil of the common mode inductor L6 is electrically connected with the second normally open static contact of the relay K2; the clock output pin CMT1 of the network transformer chip U5 is grounded in sequence through the resistor R41 and the capacitor C33, the clock input pin CMT2 of the network transformer chip U5 is connected between the resistor R41 and the capacitor C33 through the resistor R43;

[0118] The port of the Ethernet connector J2A is connected with the port of the Ethernet connector J2B and grounded, the first end of the resistor R31 and the first end of the capacitor C29 are both connected on the common connection end between the port of the Ethernet connector J2A and the port of the Ethernet connector J2B, the second end of the resistor R31 and the second end of the capacitor C29 are both grounded; the No.1 pin of the Ethernet connector J2A is electrically connected with the first moving contact of the relay K1, the No.2 pin of the Ethernet connector J2A is electrically connected with the second moving contact of the relay K1, the No.3 pin of the Ethernet connector J2A is electrically connected with the first moving contact of the relay K2, the No.6 pin of the Ethernet connector J2A is electrically connected with the second moving contact of the relay K2; the No.4 pin and the No.5 pin of the Ethernet connector J2A are connected together and grounded in sequence through the resistor R39 and the capacitor C31; the No.7 pin and the No.8 pin of the Ethernet connector J2A are connected together and connected on the common connection end between the resistor R39 and the capacitor C31 through the resistor R37;

[0119] The sending data positive pole pin TD+, the sending data negative pole pin TD-, the receiving data positive pole pin RD+ and the receiving data negative pole pin RD- of the network transformer chip U4 are all electrically connected with the Ethernet exchange chip; the neutral point pin TCT1 of the network transformer chip U4 is grounded through the capacitor C35, the reverse point pin RCT1 of the network transformer chip U4 is grounded through the capacitor C34;

[0120] The same name end of the primary coil of the common mode inductor L5 is electrically connected with the forward differential signal transmission pin TX+ of the network transformer chip U4, and the non-same name end of the primary coil of the common mode inductor L5 is electrically connected with the first normally open static contact of the relay K3; the same name end of the secondary coil of the common mode inductor L5 is electrically connected with the reverse differential signal transmission pin TX- of the network transformer chip U4, and the non-same name end of the secondary coil of the common mode inductor L5 is electrically connected with the second normally open static contact of the relay K3; the non-same name end of the primary coil of the common mode inductor L7 is electrically connected with the forward differential signal receiving pin RX+ of the network transformer chip U4, and the same name end of the primary coil of the common mode inductor L7 is electrically connected with the first normally open static contact of the relay K4; the non-same name end of the secondary coil of the common mode inductor L7 is electrically connected with the reverse differential signal receiving pin RX- of the network transformer chip U4, and the same name end of the secondary coil of the common mode inductor L7 is electrically connected with the second normally open static contact of the relay K4; the clock output pin CMT1 of the network transformer chip U4 is grounded through the resistor R40 and the capacitor C32 in sequence, and the clock input pin CMT2 of the network transformer chip U4 is connected between the resistor R40 and the capacitor C32 through the resistor R42.

[0121] The No. 1 pin of the Ethernet connector J2B is electrically connected with the first moving contact of the relay K3, the No. 2 pin of the Ethernet connector J2B is electrically connected with the second moving contact of the relay K3, the No. 3 pin of the Ethernet connector J2B is electrically connected with the first moving contact of the relay K4, and the No. 6 pin of the Ethernet connector J2B is electrically connected with the second moving contact of the relay K4; the No. 4 pin and the No. 5 pin of the Ethernet connector J2B are connected together and grounded through the resistor R38 and the capacitor C30 in sequence; the No. 7 pin and the No. 8 pin of the Ethernet connector J2B are connected together and connected between the resistor R38 and the capacitor C30 through the resistor R36.

[0122] In the above network circuit, the network transformer chip U4, the network transformer chip U5, and the Ethernet connector J2A and the Ethernet connector J2B constitute a double-port network, and data transmission and reception is performed between the double-port network and the master control circuit through an Ethernet exchange chip; wherein the network transformer chip U5 and the Ethernet connector J2A, in combination with the common mode inductors L4 and L6, constitute a first port network CH0 of the double-port network; and the network transformer chip U4 and the Ethernet connector J2B, in combination with the common mode inductors L5 and L7, constitute a second port network CH1 of the double-port network.

[0123] In each port network, the sending data positive electrode pin TD+, the sending data negative electrode pin TD-, the receiving data positive electrode pin RD+ and the receiving data negative electrode pin RD- of the network transformer chip are electrically connected with the Ethernet switch chip, and based on the Ethernet switch chip, data transmission and reception between the corresponding port network and the main control circuit is realized; the forward differential signal sending pin TX+ and the reverse differential signal sending pin TX- of the network transformer chip are connected with the 2 normally open static contacts of one of the relays based on one common mode inductor (for example, the forward differential signal sending pin TX+ and the reverse differential signal sending pin TX- of the network transformer chip U5 are connected with the 2 normally open static contacts of the relay K1 based on the common mode inductor L4), which can realize data transmission between the corresponding port network and the Bypass control circuit; similarly, the forward differential signal receiving pin RX+ and the reverse differential signal receiving pin RX- of the network transformer chip are connected with the 2 normally open static contacts of one of the relays based on one common mode inductor (for example, the forward differential signal receiving pin RX+ and the reverse differential signal receiving pin RX- of the network transformer chip U5 are connected with the 2 normally open static contacts of the relay K2 based on the common mode inductor L6), which can realize data reception between the corresponding port network and the Bypass control circuit.

[0124] In the first port network, the No. 1 pin of the Ethernet connector J2A is electrically connected with the first moving contact of the relay K1, the No. 2 pin is electrically connected with the second moving contact of the relay K1, the No. 3 pin is electrically connected with the first moving contact of the relay K2, and the No. 6 pin is electrically connected with the second moving contact of the relay K2, which can ensure the successful connection between the first port network and the relays K1 and K2 when the relays K1 and K2 are closed (i.e. the embedded system starts the upgrading process); similarly, in the second port network, the No. 1 pin of the Ethernet connector J2B is electrically connected with the first moving contact of the relay K3, the No. 2 pin is electrically connected with the second moving contact of the relay K3, the No. 3 pin is electrically connected with the first moving contact of the relay K4, and the No. 6 pin is electrically connected with the second moving contact of the relay K4, which can ensure the successful connection between the second port network and the relays K3 and K4 when the relays K3 and K4 are closed (i.e. the embedded system starts the upgrading process); further ensuring that based on the closure of the four relays, the connection between the entire network circuit and the entire Bypass control circuit is successful when the upgrading process is started, on the one hand, realizing the data transmission and reception between the network terminal device and the embedded system during the upgrading process, so that the embedded system can smoothly realize the remote software upgrading, and on the other hand, avoiding the network circuit starting according to the bypass function, which leads to the disconnection of the network between the network terminal device and the embedded system, interrupting the upgrading process.

[0125] In the first port network, based on the connection relationship of the pins of the Ethernet connector J2A, when the relays K1 and K2 are disconnected (i.e. the embedded system is upgraded), the connection between the first port network and the relays K1 and K2 is ensured to be disconnected. Similarly, in the second port network, based on the connection relationship of the pins of the Ethernet connector J2B, when the relays K3 and K4 are disconnected (i.e. the embedded system is upgraded), the connection between the second port network and the relays K3 and K4 is ensured to be disconnected. Then, based on the disconnection of the four relays, the connection between the entire network circuit and the entire bypass control circuit is ensured to be disconnected when the upgrade is completed, and the bypass function is started. Since the port of the Ethernet connector J2A is electrically connected to the port of the Ethernet connector J2B, when the bypass function is started, the two ports are directly connected. When the network terminal device connected to the embedded system fails, the network of the embedded system is connected to each other, so that the network is in a connected state, thereby meeting the data transmission requirements of the embedded system.

[0126] As shown in Figure 7 , the Ethernet switch chip PHY in the embodiment includes a plurality of network signal terminals, such as the TXP1-TXP4 ports, TXN1-TXN4 ports, RXP1-RXP4 ports, and RXN1-RXN4 ports in Figure 8 . The TXP1 and TXN1 ports are connected to the network transformer chip U5 in the first port network, and are used to transmit data in the Ethernet switch chip PHY to the first port network. The RXP1 and RXN1 ports are connected to the network transformer chip U5 in the first port network, and are used to receive data in the first port network by the Ethernet switch chip PHY. The TXP2 and TXN2 ports are connected to the network transformer chip U4 in the second port network, and are used to transmit data in the Ethernet switch chip PHY to the second port network. The RXP2 and RXN2 ports are connected to the network transformer chip U4 in the second port network, and are used to receive data in the second port network by the Ethernet switch chip PHY. The TXP3, TXN3, TXP4, and TXN4 ports are all connected to the main control circuit, and the RXP3, RXN3, RXP4, and RXN4 ports are also all connected to the main control circuit, and are used to realize data transmission between the Ethernet switch chip PHY and the main control circuit.

[0127] Specifically, in the network circuit of the embodiment, the Ethernet connectors J2A and J2B are both KH-56-8P8C-1X2-D type RJ45 connectors, the network transformer chips U4 and U5 are both HR641680E single-port network transformer modules, and the common-mode inductors L4-L7 are all SDCW2012U-2-900TF inductors. The Ethernet switching chip, the resistors and the capacitors can be selected according to actual conditions, and are not listed here.

[0128] Specifically, as shown in Figure 8 , the master control circuit includes a single-chip microcomputer (MCU) having a plurality of network signal input terminals, a plurality of network signal output terminals, a plurality of control signal input terminals and a plurality of control signal output terminals. In Figure 9 , the I / O1 pin is a control signal output terminal connected to the NET_Relay port in the bypass driving sub-circuit; the I / O2 pin is a control signal output terminal connected to the RE port in the holding function release circuit; the I / O / 3 pin is a control signal output terminal connected to the SET port in the holding function trigger circuit; the I / O5 pin is a control signal output terminal connected to the WDI pin of the watchdog chip U1 in the watchdog inhibit reset circuit; the I / O4 pin is a control signal input terminal connected to the collector of the transistor Q3 in the bypass driving sub-circuit; the RESET pin is a control signal input terminal connected to the anode of the diode D1 in the watchdog inhibit reset circuit; the TXP1-TXP2 pins, the TXN1-TXN2 pins, the RXP1-RXP2 pins and the RXN1-RXN2 pins are all connected to the Ethernet switching chip in the network circuit.

[0129] Embodiment Two

[0130] As shown in Figures 1 to 8 , a method for upgrading and maintaining an embedded system, using the upgrading and maintaining device of the embedded system of embodiment one to upgrade and maintain the embedded system, the method comprising:

[0131] S1: when the embedded system starts the upgrading process, using the master control circuit to send a holding function trigger signal to the holding function trigger circuit;

[0132] S2: using the holding function trigger circuit to receive the holding function trigger signal, and according to the holding function trigger signal, controlling the output channel of the holding signal circuit to be opened;

[0133] S3: when the output channel of the holding signal circuit is opened, using the holding signal circuit to generate a holding driving signal, and sending the holding driving signal to the bypass control circuit and the watchdog inhibit reset circuit, respectively;

[0134] S4: using the bypass control circuit, when receiving the holding driving signal, controlling the disable of the bypass function of the embedded system according to the holding driving signal, so that the connection between the network circuit and the network signal end of the bypass control circuit is successful; using the watchdog disable reset circuit, when receiving the holding driving signal, controlling the disable of the watchdog reset function of the embedded system according to the holding driving signal;

[0135] S5: when the embedded system completes the upgrading process, using the master control circuit, sending a holding function release signal to the holding function release circuit;

[0136] S6: using the holding function release circuit, receiving the holding function release signal, and controlling the output channel of the holding signal circuit to be closed according to the holding function release signal;

[0137] S7: using the bypass control circuit, when not receiving the holding driving signal, releasing the disable of the bypass function of the embedded system, so that the connection between the network circuit and the network signal end of the bypass control circuit is disconnected; using the watchdog disable reset circuit, when not receiving the holding driving signal, releasing the disable of the watchdog reset function of the embedded system.

[0138] The upgrading holding method of the embedded system of the embodiment can effectively ensure that the software upgrading process of the embedded system is not interrupted based on the disable of the bypass function and the failure of the watchdog reset function during the software upgrading process, realizes software upgrading holding, and ensures normal software upgrading of the embedded system; and after the software upgrading is completed, the bypass function and the watchdog reset function are restored.

[0139] The structure of the device used in the upgrading holding method of the embodiment is exactly the same as that of the upgrading holding device of the embedded system of Embodiment One, and therefore, the details of the embodiment are described in detail in Embodiment One and the specific description of ​ , and will not be described here again.

[0140] Although the embodiments of the present application are described in combination with the drawings, various modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. An upgrade retention apparatus for an embedded system, characterized by comprising: The device comprises a master control circuit, a network circuit, a bypass control circuit, a watchdog inhibition reset circuit, a holding function triggering circuit, a holding function releasing circuit and a holding signal circuit; The network signal input end and the network signal output end of the master control circuit are electrically connected with the network signal end of the bypass control circuit through the network circuit, the control signal output end of the master control circuit is electrically connected with the control signal end of the bypass control circuit, the input end of the watchdog inhibition reset circuit, the input end of the holding function triggering circuit and the input end of the holding function releasing circuit, the control signal input end of the master control circuit is electrically connected with the control signal end of the bypass control circuit and the output end of the watchdog inhibition reset circuit, the output end of the holding function triggering circuit and the output end of the holding function releasing circuit are electrically connected with the input end of the holding signal circuit, and the output end of the holding signal circuit is electrically connected with the control signal end of the bypass control circuit and the input end of the watchdog inhibition reset circuit; The master control circuit is configured to send a holding function triggering signal to the holding function triggering circuit when the embedded system starts an upgrading process; The holding function triggering circuit is configured to receive the holding function triggering signal and control the output channel of the holding signal circuit to be opened according to the holding function triggering signal; The holding signal circuit is configured to generate a holding driving signal when the output channel is opened and send the holding driving signal to the bypass control circuit and the watchdog inhibition reset circuit respectively; The bypass control circuit is configured to control the disabling of the bypass function of the embedded system according to the holding driving signal when the holding driving signal is received, so that the connection between the network circuit and the network signal end of the bypass control circuit is successful; The watchdog inhibition reset circuit is configured to control the disabling of the watchdog reset function of the embedded system according to the holding driving signal when the holding driving signal is received; The master control circuit is further configured to send a holding function releasing signal to the holding function releasing circuit when the embedded system completes the upgrading process; The holding function releasing circuit is configured to receive the holding function releasing signal and control the output channel of the holding signal circuit to be closed according to the holding function releasing signal; The bypass control circuit is further configured to release the disabling of the bypass function of the embedded system when the holding driving signal is not received, so that the connection between the network circuit and the network signal end of the bypass control circuit is disconnected; The watchdog inhibition reset circuit is further configured to release the disabling of the watchdog reset function of the embedded system when the holding driving signal is not received.

2. The apparatus for upgrade retention of an embedded system according to claim 1, wherein The holding signal circuit comprises a transistor Q10, a transistor Q11, a resistor R8, a resistor R78, a resistor R80, a resistor R81 and a resistor R93. The emitter of the triode Q10 is electrically connected with the circuit power supply end, the base of the triode Q10 is electrically connected with the output end of the holding function trigger circuit and the output end of the holding function release circuit through the resistor R81, the base of the triode Q10 is also electrically connected with the base of the triode Q11 through the resistor R81 and the resistor R93 in sequence, the collector of the triode Q10 is electrically connected with the control signal end of the bypass control circuit and the input end of the watchdog inhibition reset circuit, the first end of the resistor R78 is connected with the common connection end between the emitter of the triode Q10 and the circuit power supply end, the second end of the resistor R78 is connected with the common connection end between the base of the triode Q10 and the resistor R81; The emitter of the triode Q11 is electrically connected with the circuit power supply end, the first end of the resistor R80 is connected with the common connection end between the emitter of the triode Q11 and the circuit power supply end, the second end of the resistor R80 is connected with the common connection end between the base of the triode Q11 and the resistor R93; the collector of the triode Q11 is electrically connected with the output end of the holding function release circuit through the resistor R8.

3. The apparatus for upgrade preservation of an embedded system according to claim 2, wherein, The holding function trigger circuit comprises an operational amplifier U2, a diode D2, a triode Q12, resistors R7, R9, R11, R12, R15, R85, R90, capacitors C3, C4 and C53; The power supply pin of the operational amplifier U2 is electrically connected with the circuit power supply end, and the ground pin of the operational amplifier U2 is grounded; the positive input pin of the operational amplifier U2 is electrically connected with the control signal output end of the master control circuit through the resistor R12 and the capacitor C3 in sequence, the first end of the resistor R15 and the first end of the capacitor C4 are both connected on the common connection end between the positive input pin of the operational amplifier U2 and the resistor R12, the second end of the resistor R15 and the second end of the capacitor C4 are both grounded, the first end of the diode D2 is connected on the common connection end between the resistor R12 and the capacitor C3, and the second end of the diode D2 is grounded; the inverting input pin of the operational amplifier U2 is electrically connected with the circuit power supply end through the resistor R7, the first end of the resistor R9 is connected on the common connection end between the inverting input pin of the operational amplifier U2 and the resistor R7, and the second end of the resistor R9 is grounded; the output pin of the operational amplifier U2 is electrically connected with the base of the triode Q12 through the resistor R85, and the output pin of the operational amplifier U2 is also electrically connected with the circuit power supply end through the resistor R11; the first end of the resistor R90 and the first end of the capacitor C53 are both connected on the common connection end between the resistor R85 and the base of the triode Q12, the second end of the resistor R90 and the second end of the capacitor C53 are both grounded; the collector of the triode Q12 is connected on the common connection end between the resistor R81 and the resistor R93, and the emitter of the triode Q12 is grounded.

4. The apparatus for upgrade preservation of an embedded system according to claim 2, wherein, The holding function release circuit comprises an operational amplifier U3, a diode D3, a triode Q5, a triode Q16, a resistor R10, a resistor R13, a resistor R14, a resistor R16, a resistor R17, a resistor R18, a resistor R89, a resistor R94, a capacitor C5, a capacitor C6 and a capacitor C52. The power supply pin of the operational amplifier U3 is electrically connected with the circuit power supply end, and the ground pin of the operational amplifier U3 is grounded; the positive input pin of the operational amplifier U3 is electrically connected with the control signal output end of the master control circuit through the resistor R17 and the capacitor C5 in sequence, the first end of the resistor R18 and the first end of the capacitor C6 are both connected on the common connection end between the positive input pin of the operational amplifier U3 and the resistor R17, the second end of the resistor R18 and the second end of the capacitor C6 are both grounded, the first end of the diode D3 is connected on the common connection end between the resistor R17 and the capacitor C5, and the second end of the diode D3 is grounded; the inverting input pin of the operational amplifier U3 is electrically connected with the circuit power supply end through the resistor R10, and the first end of the resistor R13 is connected on the common connection end between the inverting input pin of the operational amplifier U3 and the resistor R10, and the second end of the resistor R13 is grounded; the output pin of the operational amplifier U3 is electrically connected with the base of the triode Q5, and the output pin of the operational amplifier U3 is also electrically connected with the circuit power supply end through the resistor R14; the first end of the resistor R16 is connected on the common connection end between the output pin of the operational amplifier U3 and the base of the triode Q5, and the second end of the resistor R16 is grounded; the emitter of the triode Q5 is grounded, the collector of the triode Q5 is electrically connected with the base of the triode Q16 through the resistor R94, and the resistor R8 in the holding signal circuit is connected on the common connection end between the collector of the triode Q5 and the resistor R94; the first end of the resistor R89 and the first end of the capacitor C52 are both connected on the common connection end between the resistor R94 and the base of the triode Q16, and the second end of the resistor R89 and the second end of the capacitor C52 are both grounded; the emitter of the triode Q16 is grounded, and the collector of the triode Q16 is connected on the common connection end between the resistor R81 and the resistor R93.

5. The apparatus for upgrade preservation of an embedded system of claim 1, wherein, The watchdog reset prevention circuit comprises a watchdog chip U1, a triode Q1, a triode Q2, a diode D1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a capacitor C1 and a capacitor C2; The power supply pin VDD of the watchdog chip U1 is electrically connected with the circuit power supply end, the first end of the capacitor C1 is connected on the common connection end between the power supply pin VDD of the watchdog chip U1 and the circuit power supply end, and the second end of the capacitor C1 is grounded; the watchdog chip U1 is electrically connected with the control signal output end of the master control circuit through the watchdog signal input pin WDI, the first end of the resistor R6 is connected on the common connection end between the watchdog signal input pin WDI of the watchdog chip U1 and the control signal output end of the master control circuit, and the second end of the resistor R6 is grounded; the ground pin GND of the watchdog chip U1 is grounded, the manual reset pin MR# of the watchdog chip U1 is suspended, the hardware reset pin RESET# of the watchdog chip U1 is electrically connected with the collector of the transistor Q1 through the resistor R3, the positive electrode of the diode D1 is electrically connected with the control signal input end of the master control circuit, and the negative electrode of the diode D1 is connected on the common connection end between the resistor R3 and the collector of the transistor Q1; The base of the transistor Q1 is electrically connected with the collector of the transistor Q2 through the resistor R2, the emitter of the transistor Q1 is electrically connected with the circuit power supply end, the first end of the resistor R1 is connected on the common connection end between the base of the transistor Q1 and the resistor R2, and the second end of the resistor R1 is connected on the common connection end between the emitter of the transistor Q1 and the circuit power supply end; the base of the transistor Q2 is electrically connected with the output end of the holding signal circuit through the resistor R4, the first end of the resistor R5 and the first end of the capacitor C2 are both connected on the common connection end between the base of the transistor Q2 and the resistor R4, and the second end of the resistor R5, the second end of the capacitor C2 and the emitter of the transistor Q2 are all grounded.

6. The apparatus for upgrade preservation of an embedded system of claim 1, wherein, The bypass control circuit comprises a bypass driving sub-circuit and a bypass relay sub-circuit; The input end of the bypass driving sub-circuit is electrically connected with the control signal output end of the master control circuit and the output end of the holding signal circuit respectively, the output end of the bypass driving sub-circuit is electrically connected with the input end of the bypass relay sub-circuit and the control signal input end of the master control circuit respectively, and the bypass relay sub-circuit is also electrically connected with the network circuit.

7. The apparatus for upgrade preservation of an embedded system according to claim 6, wherein, The bypass driving sub-circuit comprises a transistor Q3, a transistor Q4, a diode D8, a resistor R52, a resistor R53, a resistor R54, a resistor R55, a resistor R56 and a capacitor C42; The negative electrode of the diode D8 is electrically connected with the control signal output end of the main control circuit, the positive electrode of the diode D8 is electrically connected with the base of the triode Q3 through the resistor R53, the emitter of the triode Q3 is electrically connected with the circuit power supply end, and the collector of the triode Q3 is electrically connected with the input end of the bypass relay sub-circuit and the control signal input end of the main control circuit respectively; the first end of the resistor R52 and the first end of the resistor R54 are both connected on the common connection end between the resistor R53 and the base of the triode Q3, the second end of the resistor R52 is connected on the common connection end between the emitter of the triode Q3 and the circuit power supply end, and the second end of the resistor R54 is electrically connected with the collector of the triode Q4; The base of the triode Q4 is electrically connected with the output end of the holding signal circuit through the resistor R55, the first end of the resistor R56 and the first end of the capacitor C42 are both connected on the common connection end between the base of the triode Q4 and the resistor R55, and the second end of the resistor R56, the second end of the capacitor C42 and the emitter of the triode Q4 are all grounded.

8. The apparatus for upgrade preservation of an embedded system according to claim 6, wherein, The bypass relay sub-circuit comprises a relay K1, a relay K2, a relay K3, a relay K4, a triode Q6, a triode Q7, a triode Q8, a triode Q9, a diode D9, a diode D10, a diode D11, a diode D12, a resistor R59, a resistor R60, a resistor R61, a resistor R62, a resistor R64, a resistor R65, a resistor R66, a resistor R67, a capacitor C45, a capacitor C46, a capacitor C47 and a capacitor C48; wherein the relay K1, the relay K2, the relay K3 and the relay K4 are all double-pole double-throw relays of two groups of switches; The base of the triode Q6 is electrically connected with the output end of the bypass drive sub-circuit through the resistor R59, the first end of the resistor R64 and the first end of the capacitor C45 are both connected on the common connection end between the base of the triode Q6 and the resistor R59, the second end of the resistor R64, the second end of the capacitor C45 and the emitter of the triode Q6 are all grounded, and the collector of the triode Q6 is electrically connected with the +5V power supply end through the diode D9; The first end of the coil of the relay K1 is connected on the common connection end between the collector of the triode Q6 and the diode D9, and the second end of the coil of the relay K1 is connected on the common connection end between the diode D9 and the +5V power supply end; the first moving contact, the second moving contact, the first normally open static contact and the second normally open static contact of the relay K1 are all electrically connected with the network circuit, the first normally closed static contact of the relay K1 is electrically connected with the first normally closed static contact of the relay K3, and the second normally closed static contact of the relay K1 is electrically connected with the second normally closed static contact of the relay K3. The base of the triode Q7 is electrically connected with the output end of the bypass drive sub-circuit through the resistor R60, the first end of the resistor R65 and the first end of the capacitor C46 are both connected on the common connection end between the base of the triode Q7 and the resistor R60, the second end of the resistor R65, the second end of the capacitor C46 and the emitter of the triode Q7 are all grounded; the collector of the triode Q7 is electrically connected with the +5V power supply end through the diode D10; The first end of the coil of the relay K2 is connected on the common connection end between the collector of the triode Q7 and the diode D10, the second end of the coil of the relay K2 is connected on the common connection end between the diode D10 and the +5V power supply end; the first moving contact, the second moving contact, the first normally open static contact and the second normally open static contact of the relay K2 are all electrically connected with the network circuit, the first normally closed static contact of the relay K2 is electrically connected with the first normally closed static contact of the relay K4, the second normally closed static contact of the relay K2 is electrically connected with the second normally closed static contact of the relay K4; The base of the triode Q8 is electrically connected with the output end of the bypass drive sub-circuit through the resistor R61, the first end of the resistor R66 and the first end of the capacitor C47 are both connected on the common connection end between the base of the triode Q8 and the resistor R61, the second end of the resistor R66, the second end of the capacitor C47 and the emitter of the triode Q8 are all grounded; the collector of the triode Q8 is electrically connected with the +5V power supply end through the diode D11; the first end of the coil of the relay K3 is connected on the common connection end between the collector of the triode Q8 and the diode D11, the second end of the coil of the relay K3 is connected on the common connection end between the diode D11 and the +5V power supply end; the first moving contact, the second moving contact, the first normally open static contact and the second normally open static contact of the relay K3 are all electrically connected with the network circuit; The base of the triode Q9 is electrically connected with the output end of the bypass drive sub-circuit through the resistor R62, the first end of the resistor R67 and the first end of the capacitor C48 are both connected on the common connection end between the base of the triode Q9 and the resistor R62, the second end of the resistor R67, the second end of the capacitor C48 and the emitter of the triode Q9 are all grounded; the collector of the triode Q9 is electrically connected with the +5V power supply end through the diode D12; the first end of the coil of the relay K4 is connected on the common connection end between the collector of the triode Q9 and the diode D12, the second end of the coil of the relay K4 is connected on the common connection end between the diode D12 and the +5V power supply end; the first moving contact, the second moving contact, the first normally open static contact and the second normally open static contact of the relay K4 are all electrically connected with the network circuit.

9. The apparatus for upgrade preservation of an embedded system according to claim 8, wherein, The network circuit comprises an Ethernet switch chip, a network transformer chip U5, a network transformer chip U4, an Ethernet connector J2A, an Ethernet connector J2B, a common mode inductor L4, a common mode inductor L5, a common mode inductor L6, a common mode inductor L7, a resistor R31, a resistor R36, a resistor R37, a resistor R38, a resistor R39, a resistor R40, a resistor R41, a resistor R42, a resistor R43, a capacitor C29, a capacitor C30, a capacitor C31, a capacitor C32, a capacitor C33, a capacitor C34, a capacitor C35, a capacitor C36 and a capacitor C37; wherein the Ethernet connector J2A and the Ethernet connector J2B are both Ethernet connectors with 8 pins and 1 port; The network signal input end and the network signal output end of the main control circuit are electrically connected with the Ethernet switch chip, the sending data positive electrode pin TD+, the sending data negative electrode pin TD-, the receiving data positive electrode pin RD+ and the receiving data negative electrode pin RD- of the network transformer chip U5 are all electrically connected with the Ethernet switch chip; the neutral point pin TCT1 of the network transformer chip U5 is grounded through the capacitor C37, and the reverse point pin RCT1 of the network transformer chip U5 is grounded through the capacitor C36; The forward differential signal sending pin TX+ of the network transformer chip U5 is electrically connected with the same name end of the primary coil of the common mode inductor L4, and the non-same name end of the primary coil of the common mode inductor L4 is electrically connected with the first normally open static contact of the relay K1; the reverse differential signal sending pin TX- of the network transformer chip U5 is electrically connected with the same name end of the secondary coil of the common mode inductor L4, and the non-same name end of the secondary coil of the common mode inductor L4 is electrically connected with the second normally open static contact of the relay K1; the forward differential signal receiving pin RX+ of the network transformer chip U5 is electrically connected with the non-same name end of the primary coil of the common mode inductor L6, and the same name end of the primary coil of the common mode inductor L6 is electrically connected with the first normally open static contact of the relay K2; the reverse differential signal receiving pin RX- of the network transformer chip U5 is electrically connected with the non-same name end of the secondary coil of the common mode inductor L6, and the same name end of the secondary coil of the common mode inductor L6 is electrically connected with the second normally open static contact of the relay K2; the clock output pin CMT1 of the network transformer chip U5 is grounded in sequence through the resistor R41 and the capacitor C33, and the clock input pin CMT2 of the network transformer chip U5 is connected between the resistor R41 and the capacitor C33 through the resistor R43; The port of the Ethernet connector J2A is connected with the port of the Ethernet connector J2B and grounded, the first end of the resistor R31 and the first end of the capacitor C29 are both connected to the common connection end between the port of the Ethernet connector J2A and the port of the Ethernet connector J2B, the second end of the resistor R31 and the second end of the capacitor C29 are both grounded; the No.1 pin of the Ethernet connector J2A is electrically connected with the first moving contact of the relay K1, the No.2 pin of the Ethernet connector J2A is electrically connected with the second moving contact of the relay K1, the No.3 pin of the Ethernet connector J2A is electrically connected with the first moving contact of the relay K2, the No.6 pin of the Ethernet connector J2A is electrically connected with the second moving contact of the relay K2; the No.4 pin and the No.5 pin of the Ethernet connector J2A are connected together and grounded through the resistor R39 and the capacitor C31 in sequence; the No.7 pin and the No.8 pin of the Ethernet connector J2A are connected together and connected to the common connection end between the resistor R39 and the capacitor C31 through the resistor R37; The sending data positive pole pin TD+, the sending data negative pole pin TD-, the receiving data positive pole pin RD+ and the receiving data negative pole pin RD- of the network transformer chip U4 are all electrically connected with the Ethernet exchange chip; the neutral point pin TCT1 of the network transformer chip U4 is grounded through the capacitor C35, and the reverse point pin RCT1 of the network transformer chip U4 is grounded through the capacitor C34; The forward differential signal sending pin TX+ of the network transformer chip U4 is electrically connected with the same name end of the primary coil of the common mode inductor L5, and the non-same name end of the primary coil of the common mode inductor L5 is electrically connected with the first normally open static contact of the relay K3; the reverse differential signal sending pin TX- of the network transformer chip U4 is electrically connected with the same name end of the secondary coil of the common mode inductor L5, and the non-same name end of the secondary coil of the common mode inductor L5 is electrically connected with the second normally open static contact of the relay K3; the forward differential signal receiving pin RX+ of the network transformer chip U4 is electrically connected with the non-same name end of the primary coil of the common mode inductor L7, and the same name end of the primary coil of the common mode inductor L7 is electrically connected with the first normally open static contact of the relay K4; the reverse differential signal receiving pin RX- of the network transformer chip U4 is electrically connected with the non-same name end of the secondary coil of the common mode inductor L7, and the same name end of the secondary coil of the common mode inductor L7 is electrically connected with the second normally open static contact of the relay K4; the clock output pin CMT1 of the network transformer chip U4 is grounded through the resistor R40 and the capacitor C32 in sequence, and the clock input pin CMT2 of the network transformer chip U4 is connected to the common connection end between the resistor R40 and the capacitor C32 through the resistor R42; The No.1 pin of the Ethernet connector J2B is electrically connected with the first movable contact of the relay K3, the No.2 pin of the Ethernet connector J2B is electrically connected with the second movable contact of the relay K3, the No.3 pin of the Ethernet connector J2B is electrically connected with the first movable contact of the relay K4, the No.6 pin of the Ethernet connector J2B is electrically connected with the second movable contact of the relay K4; the No.4 pin and the No.5 pin of the Ethernet connector J2B are connected together, and are grounded in sequence through the resistor R38 and the capacitor C30; the No.7 pin and the No.8 pin of the Ethernet connector J2B are connected together, and are connected on the common connection end between the resistor R38 and the capacitor C30 through the resistor R36.

10. An upgrade retention method for an embedded system, characterized by, The method for upgrading and maintaining an embedded system using the upgrading and maintaining device for embedded system according to any one of claims 1 to 9 comprises: when the embedded system starts the upgrading process, sending a maintaining function triggering signal to the maintaining function triggering circuit by using the master control circuit; receiving the maintaining function triggering signal by using the maintaining function triggering circuit, and controlling the output channel of the maintaining signal circuit to be opened according to the maintaining function triggering signal; when the output channel of the maintaining signal circuit is opened, generating a maintaining driving signal by using the maintaining signal circuit, and sending the maintaining driving signal to the bypass control circuit and the watchdog inhibit reset circuit respectively; controlling the bypass function of the embedded system to be disabled according to the maintaining driving signal when the maintaining driving signal is received by using the bypass control circuit, so that the connection between the network circuit and the network signal end of the bypass control circuit is successful; controlling the watchdog reset function of the embedded system to be disabled according to the maintaining driving signal when the maintaining driving signal is received by using the watchdog inhibit reset circuit; when the embedded system completes the upgrading process, sending a maintaining function releasing signal to the maintaining function releasing circuit by using the master control circuit; receiving the maintaining function releasing signal by using the maintaining function releasing circuit, and controlling the output channel of the maintaining signal circuit to be closed according to the maintaining function releasing signal; controlling the bypass function of the embedded system to be released when the maintaining driving signal is not received by using the bypass control circuit, so that the connection between the network circuit and the network signal end of the bypass control circuit is disconnected; controlling the watchdog reset function of the embedded system to be released when the maintaining driving signal is not received by using the watchdog inhibit reset circuit.

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