A feed forward equalizer circuit using distributed taps
By employing a distributed tap structure in the feedforward equalizer circuit, and utilizing series connections and reducing the transconductance amplifier gain and transistor width, the problem of severe signal reflection in centralized taps is solved, resulting in a lower bit error rate and higher signal quality.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-15
- Publication Date
- 2026-04-10
AI Technical Summary
In a feedforward equalizer circuit with a centralized tap, the input parasitic capacitance of the transconductance amplifier is large, which causes severe reflection of the signal at discontinuities, increasing the bit error rate of the received signal.
A distributed tap structure is adopted, in which each tap circuit includes multiple transconductance amplifiers and delay units. By connecting them in series and reducing the gain and transistor width of each transconductance amplifier, parasitic capacitance is reduced and impedance discontinuity problems are alleviated.
It reduces signal reflection, decreases the bit error rate of the received signal, and improves the quality of signal transmission.
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Figure CN116866121B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of electronic technology, and more particularly to the field of high-speed interface integrated circuits, and relates to a feedforward equalizer circuit using distributed taps. Background Technology
[0002] A feedforward equalizer delays the input signal, distributes it across multiple taps, configures the gain of each tap, and then performs a weighted sum of the delayed signals to construct a specified frequency response. It is commonly used in transmitters and receivers of high-speed interface circuits.
[0003] Using a feedforward equalizer with centralized taps, such as Figure 1 As shown, the circuit includes a centralized tap circuit 101, an input resistor 105, and an output resistor 106. Each centralized tap circuit 101 includes a transconductance amplifier 102, an input signal delay unit 103, and an output signal delay unit 107. Delay units 103 and 107 can provide a delay of TD / 2 (TD stands for TimeDelay, representing unit delay). The transconductance amplifier 102 amplifies the delayed input signal VI1 with a specified gain to obtain the output VO1 of the tap circuit. After the delay, the outputs of all tap circuits are converged to the output port of the feedforward equalizer to obtain the output signal VO, thereby achieving weighted summation of the signals. Since each tap contains two delay units with a duration of TD / 2, ... Figure 1 Taking the two-tap feedforward equalizer shown as an example, it can provide a weighted sum of two types of delayed input signals: TD and 2TD.
[0004] However, in this centralized tap feedforward equalizer circuit, the input parasitic capacitance 104 of the transconductance amplifier is large, which generates significant impedance discontinuities after the delay unit 103. This causes severe signal reflections at these discontinuities, ultimately resulting in a high bit error rate of the received signal. Summary of the Invention
[0005] To reduce signal reflection caused by parasitic capacitance, this invention proposes a feedforward equalizer circuit using distributed taps.
[0006] The technical solution adopted in this invention is as follows:
[0007] A feed-forward equalizer circuit using distributed taps, comprising M distributed tap circuits, an input resistor and an output resistor; each distributed tap circuit comprising N transconductance amplifiers, N input signal delay units and N output signal delay units; M and N are integers greater than or equal to 2; an input signal VI enters from the input terminal of the first distributed tap circuit, and after passing through the first, second,..., Mth distributed tap circuit respectively, is connected to one end of the input resistor, and the other end of the input resistor is grounded; the output signals of each distributed tap circuit are connected together at one end of the output resistor to generate an output signal VO; the other end of the output resistor is connected to a power supply.
[0008] Further, in each distributed tap circuit, the N input signal delay units are connected in series, and the input signal of the distributed tap circuit enters from the input terminal of the first input signal delay unit; the output terminals of the first, second,..., N-1th input signal delay units are respectively connected to the input terminals of the second, third,..., Nth input signal delay units, and are respectively connected to the input terminals of the first, second,..., N-1th transconductance amplifiers; the output terminal of the Nth input signal delay unit is connected to the input terminal of the Nth transconductance amplifier; the N output signal delay units are connected in series, and the input terminals of the first, second,..., Nth output signal delay units are respectively connected to the output terminals of the first, second,..., Nth transconductance amplifiers; the output terminals of the first, second,..., N-1th output signal delay units are respectively connected to the input terminals of the second, third,..., Nth output signal delay units; the output of the Nth output signal delay unit is the output signal of the distributed tap circuit.
[0009] Further, in each distributed tap circuit, the tap input signal VI0 passes through the N input signal delay units to generate tap input signals VI1, VI2, VI3,..., VIN with delays of 1 / 2N*TD, 2 / 2N*TD, 3 / 2N*TD,..., N / 2N*TD respectively; these N signals are amplified by the N transconductance amplifiers with a gain A to obtain transconductance amplifier output signals VO0, VO1, VO2, VO3,..., VON-1 respectively, and pass through N, N-1, N-2,..., 1 output signal delay units to obtain delays of N / 2N*TD, N-1 / 2N*TD, N-2 / 2N*TD,..., 1 / 2N*TD respectively, and converge into a tap output signal VON.
[0010] Further, the signal delay of each trans-impedance amplifier is (N+1) / 2N*TD, the gain provided by the N trans-impedance amplifiers is equivalent to that of a trans-impedance amplifier with a gain of N*A formed by connecting the N trans-impedance amplifiers in parallel; the gain of each trans-impedance amplifier is reduced to 1 / N of that of the trans-impedance amplifier formed by connecting the N trans-impedance amplifiers in parallel, the width of the transistor inside the trans-impedance amplifier is also reduced to 1 / N, and the parasitic capacitance of the trans-impedance amplifier is also reduced to 1 / N.
[0011] Further, the input signal delay unit and the output signal delay unit are implemented as a transmission line, an inductance-capacitance-based delay line, or an amplifier-based delay unit.
[0012] Further, the delay values provided by each of the input signal delay unit and the output signal delay unit are arbitrary and do not need to be the same.
[0013] Further, one end of the input end resistance grounded can be connected to any voltage, and one end of the output end resistance connected to the power supply can be connected to any voltage.
[0014] Further, the trans-impedance amplifier is a common-source differential trans-impedance amplifier, which includes two NMOS transistors of controllable current source.
[0015] Further, the input signal delay unit and the output signal delay unit are microstrip line delay units.
[0016] Further, the feed-forward equalizer circuit using distributed taps is in the form of a single-ended circuit or a fully differential circuit.
[0017] The feed-forward equalizer circuit using distributed taps provided by the application reduces the parasitic capacitance of the trans-impedance amplifier, reduces the degree of signal reflection, and further reduces the bit error rate of the received signal. BRIEF DESCRIPTION OF DRAWINGS
[0018] Figure 1 The circuit diagram of the feed-forward equalizer circuit using centralized taps.
[0019] Figure 2 The circuit diagram of the feed-forward equalizer circuit using distributed taps provided by the application.
[0020] Figure 3 The feed-forward equalizer circuit using common-source differential trans-impedance amplifiers and microstrip line delay units is a preferred specific embodiment according to the application.
[0021] Figure 4 The comparison diagram of the input end return loss of the feed-forward equalizer using centralized taps and the feed-forward equalizer using distributed taps.
[0022] Explanation of main element symbols:
[0023] 100: feedforward equalizer circuit using centralized taps
[0024] 101: centralized tap circuit
[0025] 102, 202: transconductance amplifier
[0026] 103, 203, 312: input signal delay unit
[0027] 107, 207, 313: output signal delay unit
[0028] 104, 204, 304: capacitor
[0029] 105, 106, 205, 206, 305, 306: resistor
[0030] 200: feedforward equalizer circuit using distributed taps
[0031] 201, 301: distributed tap circuit
[0032] 300: feedforward equalizer circuit using common-source differential transconductance amplifier and microstrip delay unit
[0033] 302: common-source differential transconductance amplifier
[0034] 303: microstrip delay unit
[0035] 307: controllable current source
[0036] 308, 309: NMOS transistor
[0037] 310: ground plane
[0038] 311: signal line
[0039] VI: input voltage signal
[0040] VO: output voltage signal
[0041] VIP: positive end of input differential voltage signal
[0042] VIN: negative end of input differential voltage signal
[0043] IOP: positive end of output differential current signal
[0044] ION: negative end of output differential current signal DETAILED DESCRIPTION
[0045] The present application will be further described below with reference to the accompanying drawings.
[0046] The present application is a feed-forward equalizer circuit using distributed taps, comprising M distributed tap circuits, an input resistor and an output resistor. Each distributed tap circuit comprises N transconductance amplifiers, N input signal delay units and N output signal delay units, wherein M and N are integers greater than or equal to 2, i.e. at least 2.
[0047] The connection relationship among the distributed tap circuits, the input resistor and the output resistor is that the input signal VI enters the input end of the first distributed tap circuit, and is connected to one end of the input resistor after passing through the first, second, …, and Mth distributed tap circuits, and the other end of the input resistor is grounded. The output signals of each distributed tap circuit are connected together with one end of the output resistor to generate the output signal VO. The other end of the output resistor is connected to a power supply.
[0048] In each distributed tap circuit, the tap input signal VI0 passes through N input signal delay units to generate tap input signals VI1, VI2, VI3, …, and VIN with delays of 1 / 2N*TD, 2 / 2N*TD, 3 / 2N*TD, …, and N / 2N*TD, respectively. These N signals are amplified by N transconductance amplifiers with a gain A to obtain output signals VO0, VO1, VO2, VO3, …, and VON-1 of the transconductance amplifiers, respectively, and pass through N, N-1, N-2, …, and 1 output signal delay units to obtain delays of N / 2N*TD, N-1 / 2N*TD, N-2 / 2N*TD, …, and 1 / 2N*TD, respectively, and converge into the tap output signal VON. In this way, the signal delay through each transconductance amplifier is (N+1) / 2N*TD, and thus the gain provided by the N transconductance amplifiers is equivalent to that of a transconductance amplifier formed by connecting them in parallel with a gain of N*A. Since the gain of each transconductance amplifier is reduced to 1 / N times compared with the transconductance amplifier formed by connecting them in parallel, the width of the transistor inside the transconductance amplifier can also be reduced to 1 / N, and the parasitic capacitance of the transconductance amplifier is also reduced to 1 / N, so that the problem of impedance discontinuity after the delay unit is alleviated, the degree of signal reflection is reduced, and in turn the bit error rate is reduced.
[0049] In each distributed tap circuit, the connection relationship of the parts is as follows:
[0050] N input signal delay units are connected in series, and the input signal of the distributed tap circuit enters the input terminal of the first input signal delay unit. The output terminals of the first, second, …, (N-1)th input signal delay units are connected to the input terminals of the second, third, …, Nth input signal delay units, respectively, and are connected to the input terminals of the first, second, …, (N-1)th transconductance amplifiers, respectively. The output terminal of the Nth input signal delay unit is connected to the input terminal of the Nth transconductance amplifier. N output signal delay units are connected in series, and the input terminals of the first, second, …, Nth output signal delay units are connected to the output terminals of the first, second, …, Nth transconductance amplifiers, respectively. The output terminals of the first, second, …, (N-1)th output signal delay units are connected to the input terminals of the second, third, …, Nth output signal delay units, respectively. The output of the Nth output signal delay unit is taken as the output signal of the distributed tap circuit.
[0051] Further, the specific implementation of the input signal delay unit and the output signal delay unit can be a transmission line, an inductance-capacitance-based delay line, or an amplifier-based delay unit.
[0052] Further, the delay value provided by each delay unit can be equal to any time and does not need to be the same.
[0053] Further, one end of the input terminal resistor can be connected to any voltage in addition to ground.
[0054] Further, one end of the output terminal resistor can be connected to any voltage in addition to the power supply.
[0055] Further, the feedforward equalizer circuit using distributed taps proposed by the present application can be in the form of a single-ended circuit or in the form of a fully differential circuit.
[0056] Next, taking M=4 and N=4 as an example, a feedforward equalizer circuit using distributed taps 200 proposed by the present application is described as follows: Figure 2The input signal VI0 is inputted into the distributed tap circuit 201, the input resistance 205 and the output resistance 206. The distributed tap circuit 201 includes four transconductance amplifiers 202 with a gain of A, an input signal delay unit 203 and an output signal delay unit 207. The tap input signal VI0 is inputted into the four input signal delay units 203 to generate the tap input signals VI1, VI2, VI3 and VI4 with a delay of 1 / 8*TD, 2 / 8*TD, 3 / 8*TD and 4 / 8*TD respectively. The four signals are amplified by the four transconductance amplifiers 202 with a gain of A to generate the transconductance amplifier output signals VO0, VO1, VO2 and VO3 respectively. The four signals are then inputted into the output signal delay unit 207 to generate the tap output signal VO4 with a delay of 4 / 8*TD, 3 / 8*TD, 2 / 8*TD and 1 / 8*TD respectively. In this way, the signal delay of each transconductance amplifier 202 is 5 / 8*TD, and the four transconductance amplifiers 202 with a gain of A provide an amplification effect equivalent to a transconductance amplifier with a gain of 4*A formed by connecting the four transconductance amplifiers in parallel. The gain of each transconductance amplifier is reduced to 1 / 4, and the width of the transistor inside the transconductance amplifier is also reduced to 1 / 4, so that the parasitic capacitance of the transconductance amplifier is reduced to 1 / 4. The impedance discontinuity problem of the delay unit 203 is alleviated, the degree of signal reflection is reduced, and the bit error rate of the receiver is reduced.
[0057] Figure 3A preferred embodiment of the present application is a feed-forward equalizer circuit 300 using common-source differential trans-impedance amplifiers and microstrip line delay units. The feed-forward equalizer circuit 300 includes a distributed-tap circuit 301, an input resistor 305 and an output resistor 306. The distributed-tap circuit 301 includes four common-source differential trans-impedance amplifiers 302 with a gain of A, four input signal delay units 312 and four output signal delay units 313. The common-source differential trans-impedance amplifier 302 includes a controllable current source 307, NMOS transistors 308 and 309. The delay units 312 and 313 are microstrip line delay units 303, which include a signal line 311 with a width of 3 μm and a length of 190 μm, and a distance of 7 μm between the signal line 311 and a ground plane 310. A tapped input signal VI0 passes through the four input signal delay units 312 to produce tapped input signals VI1, VI2, VI3 and VI4 with delays of 1 / 8*TD, 2 / 8*TD, 3 / 8*TD and 4 / 8*TD, respectively. The four signals are amplified by the common-source differential trans-impedance amplifiers 302 with a specified gain to produce output signals VO0, VO1, VO2 and VO3, respectively, and then pass through delay units with delays of 4 / 8*TD, 3 / 8*TD, 2 / 8*TD and 1 / 8*TD, respectively, to produce a tapped output signal VO4. In this way, the signal delay through each common-source differential trans-impedance amplifier 302 is 5 / 8*TD, and thus the four common-source differential trans-impedance amplifiers 302 with a gain of A provide a gain equivalent to a trans-impedance amplifier with a gain of 4*A. Since the gain of each amplifier is reduced to 1 / 4, the width of the transistors in the trans-impedance amplifier can also be reduced to 1 / 4, which reduces the parasitic capacitance of the trans-impedance amplifier to 1 / 4, and thus alleviates the impedance discontinuity problem of the delay unit 303 and reduces the degree of signal reflection, thereby reducing the bit error rate.
[0058] Figure 4 A comparison of the input return loss of the feed-forward equalizer using centralized taps and the feed-forward equalizer using distributed taps. The curve 401 is the input return loss of the feed-forward equalizer 100 using centralized taps, and the curve 402 is the input return loss of the example 300. It can be seen that the return loss is significantly reduced, which indicates that the use of distributed taps can reduce the signal reflection of the feed-forward equalizer.
[0059] In the microstrip line delay unit 303, the width, length and distance of the signal line from the ground plane can be any value.
[0060] While the foregoing detailed description has set forth various specific embodiments of the application, it is to be understood that the disclosure is not to be limited to the details of construction or the arrangement of parts as set forth in the foregoing description. The foregoing detailed description is to be considered in all respects only as illustrative and not as restrictive.
Claims
1. A feed forward equalizer circuit using distributed taps, characterized by, The circuit comprises M distributed tap circuits, an input resistor and an output resistor; each distributed tap circuit comprises N transconductance amplifiers, N input signal delay units and N output signal delay units; M and N are integers greater than or equal to 2; an input signal VI enters from the input end of the first distributed tap circuit, and is connected to one end of the input resistor after passing through the first, second, …, and Mth distributed tap circuits; the other end of the input resistor is grounded; the output signals of the distributed tap circuits are connected together at one end of the output resistor to generate an output signal VO; the other end of the output resistor is connected to a power supply; in each distributed tap circuit, the N input signal delay units are connected in series; the input signal of the distributed tap circuit enters from the input end of the first input signal delay unit; the output ends of the first, second, …, and N-1th input signal delay units are connected to the input ends of the second, third, …, and Nth input signal delay units, respectively, and are connected to the input ends of the first, second, …, and N-1th transconductance amplifiers, respectively; the output end of the Nth input signal delay unit is connected to the input end of the Nth transconductance amplifier; the N output signal delay units are connected in series; the input ends of the first, second, …, and Nth output signal delay units are connected to the output ends of the first, second, …, and Nth transconductance amplifiers, respectively; the output ends of the first, second, …, and N-1th output signal delay units are connected to the input ends of the second, third, …, and Nth output signal delay units, respectively; the output of the Nth output signal delay unit is the output signal of the distributed tap circuit; in each distributed tap circuit, a tap input signal VI0 passes through the N input signal delay units to generate tap input signals VI1, VI2, VI3, …, and VIN with delays of 1 / 2N*TD, 2 / 2N*TD, 3 / 2N*TD, …, and N / 2N*TD, respectively; the N signals are amplified by the N transconductance amplifiers with a gain A to obtain output signals VO0, VO1, VO2, VO3, …, and VON-1 of the transconductance amplifiers, respectively, and pass through N, N-1, N-2, …, and 1 output signal delay units to obtain delays of N / 2N*TD, N-1 / 2N*TD, N-2 / 2N*TD, …, and 1 / 2N*TD, respectively, and converge into a tap output signal VON; the signal delay through each transconductance amplifier is (N+1) / 2N*TD, and the gain provided by the N transconductance amplifiers is equivalent to that of a transconductance amplifier formed by connecting the N transconductance amplifiers in parallel with a gain of N*A.
2. The feed-forward equalizer circuit using distributed taps of claim 1, wherein, The gain of each transconductance amplifier is reduced to 1 / N times that of the transconductance amplifier formed by connecting the N transconductance amplifiers in parallel, and the width of the transistor inside the transconductance amplifier is also reduced to 1 / N, so that the parasitic capacitance of the transconductance amplifier is also reduced to 1 / N.
3. The feed-forward equalizer circuit using distributed taps of claim 1, wherein, The input signal delay unit and the output signal delay unit are implemented in the form of a transmission line, an inductance-capacitance-based delay line or an amplifier-based delay unit.
4. The feed-forward equalizer circuit using distributed taps of claim 1, wherein, The delay value provided by each of the input signal delay unit and the output signal delay unit is arbitrary and need not be the same.
5. The feed-forward equalizer circuit using distributed taps of claim 1, wherein, The ground end of the input end resistor can be connected to any voltage; the power end of the output end resistor can be connected to any voltage.
6. The feed-forward equalizer circuit using distributed taps of claim 1, wherein, The transconductance amplifier is a common-source differential transconductance amplifier, and the common-source differential transconductance amplifier comprises two NMOS transistors of controllable current source.
7. The feed-forward equalizer circuit using distributed taps of claim 1, wherein, The input signal delay unit and the output signal delay unit are microstrip line delay units.
8. The feed-forward equalizer circuit using distributed taps of claim 1, wherein, The feedforward equalizer circuit using distributed taps is in the form of a single-ended circuit or in the form of a fully differential circuit.
Citation Information
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