Electronic devices, high electron mobility transistors, and methods of making the same
By forming through grooves and filling air gaps in high electron mobility transistors, the problem of high parasitic capacitance is solved, thereby improving the frequency performance and yield of transistors.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HATCHIP CO LTD
- Filing Date
- 2022-09-20
- Publication Date
- 2026-04-24
AI Technical Summary
Existing high electron mobility transistors (HEMTs) require further improvements to reduce parasitic capacitance.
By forming a first dielectric layer, a sacrificial layer, a second dielectric layer, and a protective layer in the gate region, forming a through groove and removing the sacrificial layer, filling the recess to form a fourth dielectric layer, and providing an air gap, the parasitic capacitance of the gate is reduced.
It reduces the parasitic capacitance of the gate, enhances the performance of high electron mobility transistors in millimeter-wave and terahertz frequency applications, and provides good support for miniaturized gate structures, thereby improving yield.
Smart Images
Figure CN115472501B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to an electronic device, a high electron mobility transistor, and a method for fabricating the same. Background Technology
[0002] Nitride semiconductor materials are widely used in high electron mobility transistors (HEMTs) due to their wider bandgap, higher breakdown electric field, higher electron density, and higher mobility compared to traditional semiconductor materials. However, existing HEMTs still require further improvement. Summary of the Invention
[0003] The purpose of this disclosure is to provide an electronic device, a high electron mobility transistor, and a method for fabricating the same, which can reduce parasitic capacitance.
[0004] According to one aspect of this disclosure, a method for fabricating a high electron mobility transistor is provided, comprising:
[0005] A heterojunction structure is formed on a substrate, the heterojunction structure including a source region, a drain region, and a gate region located between the source region and the drain region;
[0006] A first dielectric layer, a sacrificial layer, a second dielectric layer, and a protective layer are formed in the gate region. The first dielectric layer, the sacrificial layer, and the second dielectric layer are stacked. The first dielectric layer is located between the second dielectric layer and the substrate. The protective layer covers the sidewall of the sacrificial layer.
[0007] A groove is formed that penetrates the second dielectric layer and the sacrificial layer;
[0008] A third dielectric layer is formed, which conformally covers the groove;
[0009] A gate is formed on the third dielectric layer;
[0010] The sacrificial layer is removed, and the portion of the third dielectric layer located on the sidewall of the groove, the protective layer, and the first dielectric layer form a recess;
[0011] A fourth dielectric layer is formed to fill the recessed portion, and the portion of the fourth dielectric layer located within the recessed portion has an air gap.
[0012] Furthermore, forming a first dielectric layer, a sacrificial layer, a second dielectric layer, and a protective layer in the gate region includes:
[0013] A first dielectric layer, a sacrificial layer, and a second dielectric layer are formed in a stacked manner in the gate region;
[0014] A protective layer is formed covering the second dielectric layer and the heterojunction structure, the protective layer covering the sidewall of the sacrificial layer.
[0015] Furthermore, the heterojunction structure includes a channel layer and a barrier layer, and the fabrication method further includes:
[0016] A heavily doped structure is formed on the source region and the drain region, the heavily doped structure covering the sidewall of the protective layer facing away from the sacrificial layer, and the heavily doped structure has the same conductivity type as the barrier layer.
[0017] Furthermore, forming a groove penetrating the second dielectric layer and the sacrificial layer includes:
[0018] A passivation layer is formed covering the heavily doped structure and the second dielectric layer;
[0019] A groove is formed through the passivation layer, the second dielectric layer, and the sacrificial layer using a photolithography process.
[0020] Furthermore, a portion of the third dielectric layer is located outside the groove and is disposed on the passivation layer; forming a gate on the third dielectric layer includes:
[0021] A gate material layer is formed on the third dielectric layer;
[0022] A mask layer is formed on the gate material layer, and the gate material layer is etched using the mask layer as a mask to form the gate.
[0023] Before removing the sacrificial layer, the preparation method further includes:
[0024] The film layer covering the sacrificial layer is etched using the mask layer as a mask to expose the sacrificial layer.
[0025] Further, removing the sacrificial layer includes:
[0026] The sacrificial layer is removed by a wet etching process.
[0027] Furthermore, the material of the sacrificial layer includes polycrystalline silicon, and the etching solution used in the wet etching process includes tetramethylammonium hydroxide.
[0028] Furthermore, the material of the first dielectric layer includes silicon nitride or silicon oxide; and / or
[0029] The material of the second dielectric layer includes silicon nitride or silicon oxide.
[0030] Furthermore, the heterojunction structure includes a channel layer and a barrier layer, and the fabrication method further includes:
[0031] Remove the portion of the protective layer located in the drain region and the source region;
[0032] The portion of the barrier layer located in the source region and the drain region is thinned.
[0033] A heavily doped structure is formed in the source region and the drain region. The heavily doped structure covers the sidewall of the protective layer facing away from the sacrificial layer. The heavily doped structure has the same conductivity type as the barrier layer.
[0034] Furthermore, the cross-sectional area of the portion of the gate located within the groove is smaller than the cross-sectional area of the portion of the gate located outside the groove.
[0035] Furthermore, the preparation method further includes:
[0036] A source electrode is formed in the source region, and a drain electrode is formed in the drain region.
[0037] According to one aspect of this disclosure, a high electron mobility transistor is provided, comprising:
[0038] Substrate;
[0039] A heterojunction structure, the heterojunction structure including a source region, a drain region, and a gate region located between the source region and the drain region;
[0040] A first dielectric layer is disposed in the gate region;
[0041] The protective layer has a cylindrical structure and is disposed on the first dielectric layer;
[0042] A fourth dielectric layer fills the space enclosed by the protective layer and the first dielectric layer, and the fourth dielectric layer has a groove penetrating the fourth dielectric layer, and the portion of the fourth dielectric layer outside the groove has an air gap;
[0043] A third dielectric layer conformally covers the groove;
[0044] The gate is disposed on the third dielectric layer.
[0045] Furthermore, the heterojunction structure includes a channel layer and a barrier layer, and the high electron mobility transistor further includes:
[0046] A heavily doped structure is disposed on the source region and the drain region, the heavily doped structure covers the sidewall of the protective layer, and the heavily doped structure has the same conductivity type as the barrier layer; the fourth dielectric layer covers the heavily doped structure.
[0047] Furthermore, the cross-sectional area of the portion of the gate located within the groove is smaller than the cross-sectional area of the portion of the gate located outside the groove.
[0048] Furthermore, the high electron mobility transistor also includes:
[0049] A source electrode is disposed on the source electrode region;
[0050] The drain electrode is located in the drain region.
[0051] According to one aspect of this disclosure, an electronic device is provided, including the aforementioned high electron mobility transistor.
[0052] The electronic device, high electron mobility transistor, and fabrication method disclosed herein, by removing the sacrificial layer, such that the portion of the third dielectric layer located on the sidewall of the recess, the protective layer, and the first dielectric layer form a recess, and then a fourth dielectric layer is formed to fill the recess. Since the portion of the fourth dielectric layer located within the recess has an air gap, the parasitic capacitance of the gate is reduced, thereby enhancing the application performance of the high electron mobility transistor at millimeter-wave and terahertz frequencies. At the same time, this disclosure can also provide good structural support for miniaturized gates, improving yield. Attached Figure Description
[0053] Figure 1 This is a schematic diagram after the second dielectric layer is formed in an embodiment of this disclosure.
[0054] Figure 2 This is a schematic diagram showing the protective layer after it has been formed in the embodiments of this disclosure.
[0055] Figure 3 This is a schematic diagram of the barrier layer after thinning in the embodiments of this disclosure.
[0056] Figure 4 This is a schematic diagram of the heavily doped structure formed in the embodiments of this disclosure.
[0057] Figure 5 yes Figure 4 The diagram shows a cross-sectional view of the structure shown.
[0058] Figure 6 This is a schematic diagram after the passivation layer is formed in an embodiment of this disclosure.
[0059] Figure 7 This is a schematic diagram of the groove formed in an embodiment of this disclosure.
[0060] Figure 8 This is a schematic diagram after the gate material layer is formed in an embodiment of this disclosure.
[0061] Figure 9This is a schematic diagram of the mask after it has been formed in the embodiments of this disclosure.
[0062] Figure 10 This is a schematic diagram of the sacrificial layer after exposure in an embodiment of this disclosure.
[0063] Figure 11 This is a schematic diagram after removing the sacrificial layer in an embodiment of this disclosure.
[0064] Figure 12 This is a schematic diagram after the fourth dielectric layer is formed in an embodiment of this disclosure.
[0065] Figure 13 This is a schematic diagram showing the formation of the source and drain in the embodiments of this disclosure.
[0066] Explanation of reference numerals in the attached figures: 1. Substrate; 2. Heterojunction structure; 201. Channel layer; 202. Barrier layer; 3. First dielectric layer; 4. Sacrificial layer; 5. Second dielectric layer; 6. Protective layer; 7. Heavily doped structure; 8. Passivation layer; 9. Gate; 10. Air gap; 11. Gate material layer; 12. Mask layer; 13. Third dielectric layer; 14. Fourth dielectric layer; 15. Photoresist layer; 16. Trench; 17. Source; 18. Drain. Detailed Implementation
[0067] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses consistent with some aspects of this disclosure as detailed in the appended claims.
[0068] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. Unless otherwise defined, the technical or scientific terms used in this disclosure should be understood in their ordinary sense by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “a” or “one,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. “A plurality” or “several” indicates two or more. Unless otherwise stated, the terms “front,” “rear,” “lower,” and / or “upper,” and similar terms are for ease of description only and are not limited to a location or spatial orientation. The terms “comprising,” “including,” and similar terms mean that the elements or objects preceding “comprising,” encompass the elements or objects listed following “comprising,” and their equivalents, and do not exclude other elements or objects. The terms “connected,” “linked,” and similar terms are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. The singular forms “a” and “the” used in this disclosure and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.
[0069] This disclosure provides a method for fabricating a high electron mobility transistor. The method for fabricating the high electron mobility transistor may include steps 100-160, wherein:
[0070] Step 100, as follows Figure 1 As shown, a heterojunction structure 2 is formed on a substrate 1. The heterojunction structure 2 includes a source region, a drain region, and a gate region located between the source region and the drain region.
[0071] Step 110, as follows Figure 1 As shown, a first dielectric layer 3, a sacrificial layer 4, a second dielectric layer 5, and a protective layer 6 are formed in the gate region. The first dielectric layer 3, the sacrificial layer 4, and the second dielectric layer 5 are stacked. The first dielectric layer 3 is located between the second dielectric layer 5 and the substrate 1, and the protective layer 6 covers the sidewall of the sacrificial layer 4.
[0072] Step 120, as follows Figure 7 As shown, a groove 16 is formed that penetrates the second dielectric layer 5 and the sacrificial layer 4.
[0073] Step 130, as follows Figure 7 As shown, a third dielectric layer 13 is formed, which conformally covers the groove 16.
[0074] Step 140, as follows Figure 9 As shown, a gate 9 is formed on the third dielectric layer 13.
[0075] Step 150, as follows Figure 11 As shown, the recess is formed by removing the sacrificial layer 4, the portion of the third dielectric layer 13 located on the sidewall of the groove 16, the protective layer 6, and the first dielectric layer 3.
[0076] Step 160, as follows Figure 12 As shown, a fourth dielectric layer 14 is formed to fill the recess, and an air gap 10 is provided in the portion of the fourth dielectric layer 14 located in the recess.
[0077] The method for fabricating a high electron mobility transistor according to the present invention involves removing the sacrificial layer 4, such that the portion of the third dielectric layer 13 located on the sidewall of the recess 16, the protective layer 6, and the first dielectric layer 3 form a recess, and then forming a fourth dielectric layer 14 to fill the recess. Since the portion of the fourth dielectric layer 14 located in the recess has an air gap 10, the parasitic capacitance of the gate 9 is reduced.
[0078] The following is a detailed description of each step in the fabrication method of the high electron mobility transistor according to the present disclosure:
[0079] In step 100, as Figure 1 As shown, a heterojunction structure 2 is formed on a substrate 1. The heterojunction structure 2 includes a source region, a drain region, and a gate region located between the source region and the drain region.
[0080] The substrate 1 can be a silicon substrate or a silicon carbide substrate. Of course, the substrate 1 can also be a sapphire substrate, but the embodiments disclosed herein are not limited to this. The substrate 1 can also be silicon-on-insulator, etc.
[0081] The heterojunction structure 2 may include a channel layer 201 and a barrier layer 202. The channel layer 201 may be disposed between the barrier layer 202 and the substrate 1. The material of the channel layer 201 may be at least one of GaN, AlGaN, InGaN, and AlInGaN. The bandgap of the barrier layer 202 is greater than the bandgap of the channel layer 201. The material of the barrier layer 202 may be at least one of GaN, AlGaN, InGaN, and AlInGaN. The barrier layer 202 may be an n-type semiconductor, but this disclosure does not specifically limit it. The channel layer 201 and the barrier layer 202 may be fabricated by epitaxial growth. The gate region may be strip-shaped, but the embodiments of this disclosure are not limited to this. Furthermore, in a direction parallel to the substrate 1 and perpendicular to the strip-shaped gate region, the length of one end of the gate region is greater than the length of the other end of the gate region, that is, the gate region may be "T"-shaped. The arrangement direction of the source region, drain region, and gate region may be perpendicular to the extension direction of the strip-shaped gate region.
[0082] In step 110, as Figure 2 and Figure 3 As shown, a first dielectric layer 3, a sacrificial layer 4, a second dielectric layer 5, and a protective layer 6 are formed in the gate region. The first dielectric layer 3, the sacrificial layer 4, and the second dielectric layer 5 are stacked. The first dielectric layer 3 is located between the second dielectric layer 5 and the substrate 1, and the protective layer 6 covers the sidewall of the sacrificial layer 4.
[0083] The material of the first dielectric layer 3 may include nitrides, such as silicon nitride (SiN). x The material of the first dielectric layer 3 may also include oxides, such as silicon oxide (SiO2). The material of the sacrificial layer 4 may include polycrystalline silicon. The material of the second dielectric layer 5 may include oxides, such as silicon oxide (SiO2), and of course, the material of the second dielectric layer 5 may also include nitrides, such as silicon nitride (SiN). x The material of the protective layer 6 can also include oxides, such as silicon oxide (SiO2), etc. Of course, the material of the protective layer 6 can also include nitrides, such as silicon nitride (SiN). xThe material of the protective layer 6 can be the same as or different from that of the second dielectric layer 5. The thickness of the first dielectric layer 3 can be 10 nm. The thickness of the sacrificial layer 4 can be 200 nm. The thickness of the second dielectric layer 5 can be 100 nm. The thickness of the protective layer 6 can be 100 nm. The shapes of the first dielectric layer 3, the sacrificial layer 4, and the second dielectric layer 5 can be the same as the shape of the gate region. Taking a strip-shaped gate region as an example, the shapes of the first dielectric layer 3, the sacrificial layer 4, and the second dielectric layer 5 are all strip-shaped, and their extension lengths can be 0.5 μm to 0.6 μm. The protective layer 6 can have a cylindrical structure, the axis of which is perpendicular to the substrate 1, and the cylindrical structure can surround the sacrificial layer 4.
[0084] For example, step 110 may include steps 1101-1102, wherein:
[0085] Step 1101, as follows Figure 2 As shown, a first dielectric layer 3, a sacrificial layer 4, and a second dielectric layer 5 are stacked in the gate region.
[0086] Specifically, this disclosure can first form a first dielectric layer 3, a sacrificial layer 4, and a second dielectric layer 5 stacked on the heterojunction structure 2, and then remove the portions of the first dielectric layer 3, the sacrificial layer 4, and the second dielectric layer 5 located outside the gate region.
[0087] Step 1102, as follows Figure 2 As shown, a protective layer 6 is formed covering the second dielectric layer 5 and the heterojunction structure 2, and the protective layer 6 covers the sidewall of the sacrificial layer 4.
[0088] Of course, the protective layer 6 also covers the sidewall of the first dielectric layer 3, and the protective layer 6 also covers the sidewall of the second dielectric layer 5.
[0089] Following step 1102 above, step 110 may further include steps 1103-1105, wherein:
[0090] Step 1103, as follows Figure 3 As shown, the portion of the protective layer 6 located in the drain and source regions is removed.
[0091] Specifically, this disclosure may retain the portion of the protective layer 6 located on the sidewall of the first dielectric layer 3, the portion of the protective layer 6 located on the sidewall of the sacrificial layer 4, and the portion of the protective layer 6 located on the sidewall of the second dielectric layer 5, while removing the remaining portion of the protective layer 6. The retained protective layer 6 has a cylindrical structure.
[0092] Step 1104, as follows Figure 3 As shown, the portion of the barrier layer 202 located in the source and drain regions is thinned.
[0093] Specifically, this disclosure allows for the thinning of the portion of the barrier layer 202 located outside the gate region. This disclosure allows for the thinning of the barrier layer 202 using an etching process.
[0094] Step 1105, as follows Figure 4 and Figure 5 As shown, a heavily doped structure 7 is formed in the source and drain regions. The heavily doped structure 7 covers the sidewall of the protective layer 6 facing away from the sacrificial layer 4. The heavily doped structure 7 has the same conductivity type as the barrier layer 202.
[0095] Taking the barrier layer 202 as an n-type semiconductor as an example, the heavily doped structure 7 can also be an n-type semiconductor, and the doping concentration of the heavily doped structure 7 is greater than the doping concentration of the barrier layer 202. The thickness of the heavily doped structure 7 can be 200 nm.
[0096] In step 120, a groove 16 is formed that penetrates the second dielectric layer 5 and the sacrificial layer 4.
[0097] For example, step 120 may include: Figure 6 As shown, a passivation layer 8 is formed covering the heavily doped structure 7 and the second dielectric layer 5. The material of the passivation layer 8 may include nitrides, such as silicon nitride (SiN). x The passivation layer 8 can have a thickness of 100 nm; for example... Figure 7 As shown, a groove 16 is formed through the passivation layer 8, the second dielectric layer 5, and the sacrificial layer 4 using photolithography. Furthermore, the groove 16 can also penetrate the first dielectric layer 3, meaning the bottom of the groove 16 reaches the heterojunction structure 2. During the photolithography process, this disclosure can first form a patterned photoresist layer 15, and then use the patterned photoresist layer 15 as a mask to form the groove 16. Taking the second dielectric layer 5 as a strip shape as an example, the groove 16 can also be strip-shaped in the direction parallel to the substrate 1, and the extension direction of the groove 16 is the same as the extension direction of the second dielectric layer 5. The extension length of the groove 16 can be less than or equal to the extension length of the second dielectric layer 5. The width of the strip-shaped groove 16 can be less than or equal to 100 nm.
[0098] In step 130, as Figure 8 As shown, a third dielectric layer 13 is formed, which conformally covers the groove 16.
[0099] The third dielectric layer 13 can cover the passivation layer 8, meaning that a portion of the third dielectric layer 13 is located outside the groove 16 and is disposed on the passivation layer 8. The material of the third dielectric layer 13 can include oxides, such as silicon oxide (SiO2) or aluminum oxide (Al2O3). Alternatively, the material of the third dielectric layer 13 can also include nitrides, such as silicon nitride (SiN).x The thickness of the third dielectric layer 13 can be 20 nm.
[0100] In step 140, as Figure 8 and Figure 9 As shown, a gate 9 is formed on the third dielectric layer 13.
[0101] The cross-sectional area of the portion of the gate 9 located within the groove 16 is smaller than the cross-sectional area of the portion of the gate 9 located outside the groove 16; that is, the gate 9 is T-shaped. The cross-section of the gate 9 is the cross-section of the gate 9 in the direction parallel to the substrate 1. The gate 9 can be fabricated by a vapor deposition process. In the direction perpendicular to the substrate 1, the gate 9 can be a stacked structure, such as Ti / Al / Ti. Furthermore, taking the groove 16 as a strip shape as an example, the gate 9 can also be strip-shaped in the direction parallel to the substrate 1, and the extension direction of the gate 9 is the same as the extension direction of the groove 16. The orthographic projection of the gate 9 on the substrate 1 lies within the orthographic projection region of the sacrificial layer 4 on the substrate 1. Specifically, along the direction perpendicular to the extension direction of the groove 16, the sacrificial layer 4 includes a first region, a second region, and a third region distributed sequentially, with the second region located between the first and third regions. The orthographic projection of the gate 9 on the substrate 1 completely coincides with the orthographic projection of the second region of the sacrificial layer 4 on the substrate 1. Furthermore, in a direction perpendicular to the extending direction of the groove 16, the width of the portion of the gate 9 located outside the groove 16 can be 0.3μm-0.4μm.
[0102] For example, step 140 may include: Figure 8 As shown, a gate material layer 11 is formed on the third dielectric layer 13, and the thickness of the gate material layer can be 50nm-60nm; Figure 9 As shown, a mask layer 12 is formed on the gate material layer 11, and the gate material layer 11 is etched using the mask layer 12 as a mask to form the gate 9. The mask layer 12 can be a patterned photoresist layer, but this disclosure does not specifically limit it.
[0103] In step 150, as Figure 11 As shown, the recess is formed by removing the sacrificial layer 4, the portion of the third dielectric layer 13 located on the sidewall of the groove 16, the protective layer 6, and the first dielectric layer 3.
[0104] Before removing the sacrificial layer 4, the preparation method of this disclosure may further include: Figure 10As shown, the film layer covering the sacrificial layer 4 is etched using the aforementioned mask layer 12 as a mask to expose the sacrificial layer 4. Specifically, the first region and the third region of the sacrificial layer 4 can be exposed. The film layer covering the sacrificial layer 4 can be the aforementioned second dielectric layer 5, passivation layer 8, and third dielectric layer 13. Furthermore, during the etching process of the film layer covering the sacrificial layer 4, this disclosure can also etch away the passivation layer 8 and the third dielectric layer 13 covering the heavily doped structure 7.
[0105] This disclosure allows for the removal of the sacrificial layer 4 using a wet etching process. Taking polysilicon as an example, the etching solution used in this wet etching process may include tetramethylammonium hydroxide (TMAH), but this disclosure does not impose any special limitations on this method.
[0106] In step 160, as Figure 12 As shown, a fourth dielectric layer 14 is formed to fill the recess, and an air gap 10 is provided in the portion of the fourth dielectric layer 14 located in the recess.
[0107] The material of the fourth dielectric layer 14 may include oxides, such as silicon oxide (SiO2), aluminum oxide (Al2O3), etc. Of course, the material of the fourth dielectric layer 14 may also include nitrides, such as silicon nitride (SiN). x ), etc. After step 160, the preparation method of this disclosure may further include: such as Figure 13 As shown, a source electrode 17 is formed in the source region and a drain electrode 18 is formed in the drain region.
[0108] This disclosure also provides a high electron mobility transistor, which can be fabricated by the high electron mobility transistor fabrication method of any of the above embodiments. The high electron mobility transistor may include: a substrate 1; a heterojunction structure 2, the heterojunction structure 2 including a source region, a drain region, and a gate region located between the source region and the drain region; a first dielectric layer 3 disposed in the gate region; a protective layer 6, having a cylindrical structure and disposed on the first dielectric layer 3; a fourth dielectric layer 14 filling the space enclosed by the protective layer 6 and the first dielectric layer 3, and the fourth dielectric layer 14 having a groove 16 penetrating the fourth dielectric layer 14, and an air gap 10 located in the portion of the fourth dielectric layer 14 outside the groove 16; a third dielectric layer 13 conformally covering the groove 16; and a gate 9 disposed on the third dielectric layer 13.
[0109] The heterojunction structure 2 may include a channel layer 201 and a barrier layer 202. The high electron mobility transistor may also include a heavily doped structure 7. The heavily doped structure 7 is disposed on the source and drain regions, covers the sidewalls of the protective layer 6, and has the same conductivity type as the barrier layer 202. The fourth dielectric layer 14 covers the heavily doped structure 7.
[0110] The cross-sectional area of the portion of the gate 9 located within the groove 16 is smaller than the cross-sectional area of the portion of the gate 9 located outside the groove 16.
[0111] The high electron mobility transistor may further include a source 17 and a drain 18. The source 17 is disposed on the source region. The drain 18 is disposed on the drain region.
[0112] This disclosure also provides an electronic device. This electronic device may include a high electron mobility transistor.
[0113] The high electron mobility transistor fabrication method, high electron mobility transistor, and electronic device provided in this disclosure belong to the same inventive concept. Related details and beneficial effects can be referred to each other and will not be repeated here.
[0114] The above are merely preferred embodiments of this disclosure and are not intended to limit this disclosure in any way. Although this disclosure has been disclosed above with reference to preferred embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this disclosure. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this disclosure without departing from the content of the technical solution of this disclosure shall still fall within the scope of the technical solution of this disclosure.
Claims
1. A method for fabricating a high electron mobility transistor, characterized in that, include: A heterojunction structure is formed on a substrate, the heterojunction structure including a source region, a drain region, and a gate region located between the source region and the drain region; A first dielectric layer, a sacrificial layer, a second dielectric layer, and a protective layer are formed in the gate region. The first dielectric layer, the sacrificial layer, and the second dielectric layer are stacked. The first dielectric layer is located between the second dielectric layer and the substrate. The protective layer covers the sidewall of the sacrificial layer. A groove is formed that penetrates the second dielectric layer and the sacrificial layer; A third dielectric layer is formed, which conformally covers the groove; A gate is formed on the third dielectric layer; The sacrificial layer is removed, and the portion of the third dielectric layer located on the sidewall of the groove, the protective layer, and the first dielectric layer form a recess; A fourth dielectric layer is formed to fill the recessed portion, and the portion of the fourth dielectric layer located within the recessed portion has an air gap.
2. The method for fabricating a high electron mobility transistor according to claim 1, characterized in that, The formation of a first dielectric layer, a sacrificial layer, a second dielectric layer, and a protective layer in the gate region includes: A first dielectric layer, a sacrificial layer, and a second dielectric layer are formed in a stacked manner in the gate region; A protective layer is formed covering the second dielectric layer and the heterojunction structure, the protective layer covering the sidewall of the sacrificial layer.
3. The method for fabricating a high electron mobility transistor according to claim 1 or 2, characterized in that, The heterojunction structure includes a channel layer and a barrier layer, and the preparation method further includes: A heavily doped structure is formed on the source region and the drain region, the heavily doped structure covering the sidewall of the protective layer facing away from the sacrificial layer, and the heavily doped structure has the same conductivity type as the barrier layer.
4. The method for fabricating a high electron mobility transistor according to claim 3, characterized in that, Forming a groove penetrating the second dielectric layer and the sacrificial layer includes: A passivation layer is formed covering the heavily doped structure and the second dielectric layer; A groove is formed through the passivation layer, the second dielectric layer, and the sacrificial layer using a photolithography process.
5. The method for fabricating a high electron mobility transistor according to claim 4, characterized in that, A portion of the third dielectric layer is located outside the groove and is disposed on the passivation layer; Forming a gate on the third dielectric layer includes: A gate material layer is formed on the third dielectric layer; A mask layer is formed on the gate material layer, and the gate material layer is etched using the mask layer as a mask to form the gate. Before removing the sacrificial layer, the preparation method further includes: The film layer covering the sacrificial layer is etched using the mask layer as a mask to expose the sacrificial layer.
6. The method for fabricating a high electron mobility transistor according to claim 1 or 5, characterized in that, Removing the sacrificial layer includes: The sacrificial layer is removed by a wet etching process.
7. The method for fabricating a high electron mobility transistor according to claim 6, characterized in that, The sacrificial layer is made of polycrystalline silicon, and the etching solution used in the wet etching process includes tetramethylammonium hydroxide.
8. The method for fabricating a high electron mobility transistor according to claim 6, characterized in that, The material of the first dielectric layer includes silicon nitride or silicon oxide; and / or The material of the second dielectric layer includes silicon nitride or silicon oxide.
9. The method for fabricating a high electron mobility transistor according to claim 2, characterized in that, The heterojunction structure includes a channel layer and a barrier layer, and the preparation method further includes: Remove the portion of the protective layer located in the drain region and the source region; The portion of the barrier layer located in the source region and the drain region is thinned. A heavily doped structure is formed in the source region and the drain region. The heavily doped structure covers the sidewall of the protective layer facing away from the sacrificial layer. The heavily doped structure has the same conductivity type as the barrier layer.
10. The method for fabricating a high electron mobility transistor according to claim 1, characterized in that, The cross-sectional area of the portion of the gate located within the groove is smaller than the cross-sectional area of the portion of the gate located outside the groove.
11. The method for fabricating a high electron mobility transistor according to claim 1, characterized in that, The preparation method further includes: A source electrode is formed in the source region, and a drain electrode is formed in the drain region.
12. A high electron mobility transistor, characterized in that, include: Substrate; A heterojunction structure, the heterojunction structure including a source region, a drain region, and a gate region located between the source region and the drain region; A first dielectric layer is disposed in the gate region; The protective layer has a cylindrical structure and is disposed on the first dielectric layer; A fourth dielectric layer fills the space enclosed by the protective layer and the first dielectric layer, and the fourth dielectric layer has a groove penetrating the fourth dielectric layer, and the portion of the fourth dielectric layer outside the groove has an air gap; A third dielectric layer conformally covers the groove; A gate is disposed on the third dielectric layer; The fourth dielectric layer that fills the space also covers the surface of the gate away from the substrate, and the air gap is formed inside the fourth dielectric layer located between the protective layer and the third dielectric layer.
13. The high electron mobility transistor according to claim 12, characterized in that, The heterojunction structure includes a channel layer and a barrier layer, and the high electron mobility transistor further includes: A heavily doped structure is disposed on the source region and the drain region, the heavily doped structure covers the sidewall of the protective layer, and the heavily doped structure has the same conductivity type as the barrier layer; the fourth dielectric layer covers the heavily doped structure.
14. The high electron mobility transistor according to claim 12, characterized in that, The cross-sectional area of the portion of the gate located within the groove is smaller than the cross-sectional area of the portion of the gate located outside the groove.
15. The high electron mobility transistor according to claim 12, characterized in that, The high electron mobility transistor also includes: A source electrode is disposed on the source electrode region; The drain electrode is located in the drain region.
16. An electronic device, characterized in that, Includes the high electron mobility transistor according to any one of claims 12-15.
Citation Information
Patent Citations
Pseudomorphic high electron mobility transistor and manufacture method for improving frequency characteristic
CN103887335A