Chip assembly and packaging method thereof, and electronic device

Abstract

The present application relates to a chip assembly and a packaging method thereof, and an electronic device. The chip assembly includes: a packaging substrate, including a packaging area, wherein a first solder affinity layer forming a first solder area is arranged, and also includes a blocking structure; a chip die is arranged in the packaging area, and a second solder affinity layer is arranged on one side of the chip die, and the second solder affinity layer forms a second solder area; a solder layer includes a solder portion, which is sandwiched between the first solder affinity layer and the second solder affinity layer; in the direction from the blocking structure to the chip die, the sum of the effective areas of the second solder area exceeding the corresponding first solder area is S11, and the sum of the effective areas of the first solder area exceeding the corresponding second solder area is S21; in the opposite direction, the sum of the effective areas of the first solder area exceeding the corresponding second solder area is S12, and the sum of the effective areas of the second solder area exceeding the corresponding first solder area is S22, and S21+S22≤S11+S12. The chip assembly provided by the embodiment of the present application can improve production efficiency and yield.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chip component and a packaging method thereof, and an electronic device. Background Art

[0002] In the existing semiconductor chip processing flow, packaging is an indispensable post-processing technology, which is used to provide physical protection, signal interconnection, heat dissipation and fixation for the internal structure of the chip. On this basis, PLP (panel level Package) has obvious development advantages due to its low cost and high production efficiency. The PLP process uses a larger packaging substrate, which can package a large number of chips at one time, which is easy to reduce the position accuracy of the chip bare, hindering subsequent steps such as wafer reconstruction, resulting in a decrease in product yield and production efficiency.

[0003] Therefore, there is an urgent need for a chip assembly that can improve the position accuracy of the bare chip and improve the yield rate, as well as a corresponding packaging method and electronic device. Summary of the invention

[0004] The present application provides a chip component and a packaging method thereof, and an electronic device, wherein a packaging substrate can improve product yield and production efficiency.

[0005] In a first aspect, a chip assembly is proposed according to an embodiment of the present application, comprising: a packaging substrate, comprising at least one packaging area spaced apart from each other, each packaging area being provided with at least one first solder affinity layer, each first solder affinity layer forming a first solder area; the packaging substrate comprising at least one blocking structure corresponding to each packaging area, the blocking structure being provided close to an edge of the corresponding packaging area; at least one chip die being provided in the corresponding packaging area, at least one second solder affinity layer being provided on a side of the chip die facing the first solder affinity layer, each second solder affinity layer forming a second solder area; the solder layer comprising at least one solder A solder portion is sandwiched between each pair of corresponding first solder-affinity layers and second solder-affinity layers; in each pair of corresponding chip die and package areas, in the direction from the blocking structure to the chip die, the sum of the effective areas of each second solder area exceeding the corresponding first solder area is S11, and the sum of the effective areas of each first solder area exceeding the corresponding second solder area is S21; in the opposite direction, the sum of the effective areas of each first solder area exceeding the corresponding second solder area is S12, and the sum of the effective areas of each second solder area exceeding the corresponding first solder area is S22, S21+S22≤S11+S12.

[0006] According to one aspect of the embodiments of the present application, the blocking structure includes a first substructure extending along a first direction, and the chip die abuts against the first substructure in the corresponding blocking structure.

[0007] According to one aspect of the embodiment of the present application, the maximum distance between the edge of the first solder area and the first substructure is L1, the maximum distance between the second solder area and the first substructure is L2, and L2≥L1.

[0008] According to one aspect of the embodiment of the present application, the blocking structure further includes a second substructure extending along a second direction, the first direction intersects with the second direction, and the chip die abuts against the second substructure in the corresponding blocking structure.

[0009] According to one aspect of the embodiment of the present application, the maximum distance between the edge of the first solder area and the second substructure is L3, the maximum distance between the edge of the second solder area and the second substructure is L4, and L3≥L4.

[0010] According to one aspect of an embodiment of the present application, the packaging substrate includes a plurality of packaging grooves, the packaging areas are located in the packaging grooves and are arranged in a one-to-one correspondence with the packaging grooves, and the blocking structure includes at least a portion of the side walls of the packaging grooves.

[0011] According to one aspect of the embodiments of the present application, a first solder affinity layer is provided in each packaging region, and a second solder affinity layer is provided in each chip bare die.

[0012] According to one aspect of the embodiment of the present application, the first solder affinity layer and the second solder affinity layer are made of metal material.

[0013] According to one aspect of the embodiment of the present application, the first solder affinity layer and the second solder affinity layer include at least one of titanium, copper, tungsten, and nickel.

[0014] According to one aspect of the embodiment of the present application, the area of ​​the first solder region is S13, the area of ​​the second solder region is S23, and 0.5S23≤S13≤S23.

[0015] According to one aspect of the embodiment of the present application, the package substrate is provided with a solder-repelling layer, and the solder-repelling layer is at least partially provided around the first solder-affinity layer.

[0016] In a second aspect, a chip assembly is proposed according to an embodiment of the present application, comprising: a packaging substrate, comprising at least one packaging area spaced apart from each other, each packaging area being provided with at least one first solder affinity layer, each first solder affinity layer forming a first solder area; the packaging substrate comprising at least one blocking structure corresponding to each packaging area, the blocking structure being provided close to an edge of the corresponding packaging area; at least one chip die being provided in the corresponding packaging area, at least one second solder affinity layer being provided on a side of the chip die facing the first solder affinity layer, each second solder affinity layer forming a second solder area; the solder layer comprising at least one A solder portion is sandwiched between each pair of corresponding first solder-affinity layers and second solder-affinity layers; in the direction from the blocking structure to the chip bare die, each second solder area exceeds its corresponding first solder area by a length of L21, and in the opposite direction, each second solder area exceeds its corresponding first solder area by a length of L22, L22≤L21; or, in the direction from the blocking structure to the chip bare die, each first solder area exceeds its corresponding second solder area by a length of L11, and in the opposite direction, each first solder area exceeds its corresponding second solder area by a length of L12, L12≥L11.

[0017] In the third aspect, according to an embodiment of the present application, a chip component is proposed, comprising: a packaging substrate, comprising at least one packaging area spaced apart from each other, each packaging area being provided with at least one first solder affinity layer, each first solder affinity layer forming a first solder area; the packaging substrate comprising at least one blocking structure corresponding to the packaging area, the blocking structure being arranged close to the edge of the corresponding packaging area; at least one chip bare particle being arranged in the first solder area of ​​the corresponding packaging area, at least one second solder affinity layer being arranged on the side of the chip bare particle facing the first solder affinity layer, each second solder affinity layer forming a second solder area; the solder layer comprising at least one solder portion, a solder portion being sandwiched between each pair of corresponding first solder affinity layers and second solder affinity layers; the orthographic projection of the second solder area on the packaging substrate forms a projection pattern, and the distance between the centroid of the first solder area and the blocking structure is less than or equal to the distance between the centroid of the projection pattern and the blocking structure.

[0018] In a fourth aspect, a chip component packaging method is proposed according to an embodiment of the present application, comprising: providing a packaging substrate and a chip die, the packaging substrate comprising at least one packaging area, a blocking structure being arranged on the periphery of the packaging area, at least one first solder affinity layer being arranged in each packaging area, each first solder affinity layer forming a first solder area, at least one second solder affinity layer being arranged on one side surface of the chip die, each second solder affinity layer forming a second solder area; solder is arranged on at least one of the first solder area and the second solder area to form at least one solder portion; the chip die is placed in the packaging area, and the solder portion is located between the first solder affinity layer and the second solder affinity layer; the solder is heated to melt the solder to a liquid state, and the chip die is moved to a preset target position under the action of the solder; the solder is cooled to solidify the solder portion to form a solder layer, so as to complete the welding connection and fix the relative position between the packaging substrate and the chip die.

[0019] According to one aspect of an embodiment of the present application, the step of placing a chip die in a packaging area includes: for each pair of corresponding chip die and packaging area, in a direction from the blocking structure to the chip die, the sum of the effective areas of each second solder area exceeding the corresponding first solder area is S11, and the sum of the effective areas of each first solder area exceeding the corresponding second solder area is S21; in the opposite direction, the sum of the effective areas of each first solder area exceeding the corresponding second solder area is S12, and the sum of the effective areas of each second solder area exceeding the corresponding first solder area is S22, and the chip die is placed so that S21+S22<S11+S12;

[0020] Alternatively, the step of placing the chip die in the packaging area includes: in the direction from the blocking structure to the chip die, each second solder area exceeds the corresponding first solder area by a length of L1, and in the opposite direction, each second solder area exceeds the corresponding first solder area by a length of L2, and the chip die is placed so that L2 is less than L1; or, in the direction from the blocking structure to the chip die, each first solder area exceeds the corresponding second solder area by a length of L3, and in the opposite direction, each first solder area exceeds the corresponding second solder area by a length of L4, and the chip die is placed so that L4 is greater than L3;

[0021] Alternatively, the step of placing the chip die in the packaging area includes: forming a projection pattern by orthographic projection of the second solder area on the packaging substrate, and placing the chip die so that the distance between the centroid of the first solder area and the blocking structure is smaller than the distance between the centroid of the projection pattern and the blocking structure.

[0022] According to one aspect of an embodiment of the present application, the step of placing a chip die in a packaging area includes: placing the chip die, in a direction from the blocking structure to the chip die, the distance between the centroid of the first solder area and the blocking structure is L5, and the distance between the centroid of the second solder area and the blocking structure is L6, so that the absolute value of the difference between L5 and L6 is greater than the maximum distance between the chip die and the blocking structure.

[0023] According to one aspect of the embodiments of the present application, the step of heating the solder further includes: making the chip die moved to a preset target position abut against the blocking structure.

[0024] In a fifth aspect, an electronic device is proposed according to an embodiment of the present application, comprising at least part of the chip components in any one of the embodiments of the first, second and third aspects.

[0025] The chip assembly in the embodiment of the present application includes a packaging substrate and a plurality of chip dies. By welding the chip dies to the packaging substrate, the relative position between the chip dies and the packaging substrate can be stabilized to avoid chip movement during injection molding. At the same time, a blocking structure is provided on the packaging substrate and the chip dies are moved by the self-alignment effect of the solder during welding, thereby improving the position accuracy and production efficiency of each chip dies in the chip assembly. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The features, advantages and technical effects of exemplary embodiments of the present application will be described below with reference to the accompanying drawings.

[0027] Figure 1 is a schematic diagram of the structure of a chip assembly provided by an embodiment of the present application;

[0028] Figure 2 It is a schematic diagram of a top view of a bare chip in a chip assembly provided in one embodiment of the present application;

[0029] Figure 3 yes Figure 1 A cross-sectional view at A-A';

[0030] Figure 4 yes Figure 1 An enlarged view of the middle region Q;

[0031] Figure 5 yes Figure 1 Another cross-sectional view at A-A';

[0032] Figure 6 is a flow chart of a packaging method provided by an embodiment of the present application;

[0033] Figure 7 yes Figure 6 Schematic diagram of the structure corresponding to step S2;

[0034] Figure 8 yes Figure 6 Schematic diagram of the structure corresponding to step S3 in FIG.

[0035] in:

[0036] 100-chip assembly;

[0037] 10-Packaging substrate; 20-Bare chip; 30-Solder layer;

[0038] 11-packaging area; 12-barrier structure; 13-packaging groove; 21-second solder area; 31-solder portion; 41-first solder affinity layer; 42-second solder affinity layer;

[0039] 111 - first solder area; 121 - first substructure; 122 - second substructure; 131 - side wall;

[0040] X-first direction; Y-second direction; Z-thickness direction.

[0041] In the drawings, the same reference numerals are used for the same components. The drawings are not drawn to scale. DETAILED DESCRIPTION

[0042] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0043] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0044] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0045] The features and exemplary embodiments of various aspects of the present application will be described in detail below.In addition, the features, structures, or characteristics described below may be combined in any suitable manner in one or more embodiments.

[0046] In the existing semiconductor processing technology, chip packaging is usually an indispensable post-processing technology. By using plastic packaging materials to cover at least part of the chip area, it can provide physical protection, signal connection, heat dissipation, and fixation for the packaged chip bare die. When the chip is packaged using panel-level packaging, it is usually necessary to set the chip in the packaging groove of the packaging substrate and then package it with plastic packaging materials. In the process of panel-level packaging, the wafer reconstruction step usually has very high requirements on the position accuracy of the chip bare die, which is directly related to the yield of the final product.

[0047] On this basis, the applicant found that in the existing panel-level packaging process, in order to prevent the plastic packaging material from pushing the chip away from the target position during the injection process, it is usually necessary to set a DAF (Die Attach Film, chip bare die bonding layer) between the bare chip to be packaged and the packaging substrate, and keep the bare chip in the same position by bonding and fixing it so that it stays in the target position. However, the bonding and fixing method through the bonding layer has a low connection strength, and it is difficult to accurately position and connect, resulting in low overall production efficiency and yield of chip components.

[0048] In order to solve the above problems, a chip component and its packaging method and an electronic device are provided in an embodiment of the present application, wherein the chip component is provided with a solder affinity layer, and the chip bare particle and the packaging substrate are connected by welding, which can improve the production efficiency and yield of the chip component.

[0049] It is understandable that the following embodiments of the present application are only described by applying the corresponding structure to the chip components to be packaged, but the present application is not limited to this and can also be applied to other occasions where the chip bare needs to be positioned and protected.

[0050] In order to better understand this application, Figures 1 to 8 The chip assembly, packaging method thereof, and electronic device provided in the embodiments of the present application are described in detail.

[0051] Please also read Figure 1 , Figure 2 and Figure 3 , Figure 1 is a schematic diagram of the structure of a chip assembly provided by an embodiment of the present application, Figure 3 yes Figure 1 A cross-sectional view at A-A'.

[0052] In the first aspect, according to an embodiment of the present application, a chip component 100 is proposed, including a packaging substrate 10, a chip die 20, and a solder layer 30. The packaging substrate 10 includes at least one packaging area 11 spaced apart from each other, each packaging area 11 is provided with at least one first solder affinity layer 41, each first solder affinity layer 41 forms a first solder area 111, the packaging substrate 10 includes at least one blocking structure 12 corresponding to the packaging area 11, and the blocking structure 12 is arranged near the edge of the corresponding packaging area 11; at least one chip die 20 is arranged in the corresponding packaging area 11, and at least one second solder affinity layer 42 is arranged on the side of the chip die 20 facing the first solder affinity layer 41, and each second solder affinity layer 42 forms a second solder area 21; the solder layer 30 includes at least one solder portion 31, and a solder portion 31 is sandwiched between each pair of corresponding first solder affinity layers 41 and second solder affinity layers 42.

[0053] In each pair of corresponding chip die 20 and packaging area 11, in the direction from the blocking structure 12 to the chip die 20, the sum of the effective areas of each second solder area exceeding the corresponding first solder area is S11, and the sum of the effective areas of each first solder area exceeding the corresponding second solder area is S21. In the opposite direction, the sum of the effective areas of each first solder area exceeding the corresponding second solder area is S12, and the sum of the effective areas of each second solder area exceeding the corresponding first solder area is S22, and S21+S22≤S11+S12.

[0054] The embodiment of the present application provides a chip assembly 100, which may include a packaging substrate 10 and at least one chip die 20 respectively arranged on the packaging substrate 10, wherein the packaging substrate 10 is used to provide support and positioning for the chip die 20, and the packaging substrate 10 has at least one packaging area 11, these packaging areas 11 may have the same or similar shape and size and are arranged at intervals from each other, and the packaging area 11 is used to arrange the chip die 20 for packaging in subsequent process steps. Optionally, these packaging areas 11 may be arranged in an array with equal intervals to make the distribution of the chip die 20 uniform and facilitate cutting in subsequent processes.

[0055] The packaging substrate 10 in the embodiment of the present application can be made of materials such as silicon wafer, glass, ceramic or PI (Polyimide) so that it can be used to support and position the chip die 20. The present application does not make any specific limitation on this.

[0056] Specifically, the package substrate 10 includes a package area 11 and a blocking structure 12, wherein there is a certain step difference between the blocking structure 12 and the package area 11, that is, the blocking structure 12 is protruding from the plane where the package area 11 is located. At the same time, the blocking structure 12 is extended along the edge of the package area 11 to form a blocking wall that partially surrounds the package area 11. After the chip die 20 is set, the chip die 20 can be limited by the blocking structure 12. The package area 11 includes a first solder affinity layer 41, which can have better contact performance with the solder. Each first solder affinity layer 41 forms at least one first solder area 111, that is, the material used in the first solder area 111 has good bonding performance with the solder used for welding. When welding, the melted solder can smoothly wet the part of the solder affinity layer 40 and cover the first solder area 111.

[0057] It can be understood that the first and second solder areas should correspond to areas surrounded by the outer contour of the first solder affinity layer 41 and the outer contour of the second solder affinity layer 42 respectively.

[0058] Further, the multiple chip dies 20 in the chip assembly 100 and the multiple packaging areas 11 in the packaging substrate 10 can be arranged in a one-to-one correspondence, that is, each packaging area 11 is used to position and package a corresponding chip die 20. The second solder affinity layer 42 is provided on the surface of one side of these chip dies 20 close to the packaging substrate 10, and at least one second solder area 21 is formed in each second solder affinity layer 42, so that the second solder area 21 can be opposite to the first solder area 111 and form a weld between the two, and at this time, the first solder area 111 and the second solder area 21 are at least partially connected. It can be understood that the first solder area 111 and the second solder area 21 can be completely arranged in the corresponding solder affinity layer, and each solder affinity layer can be simultaneously provided with a plurality of mutually spaced solder areas.

[0059] Specifically, there is also a solder layer 30 between the packaging substrate 10 and the chip bare particle 20. The solder layer 30 can be formed by coating solder on the first solder area 111 and the second solder area 21 respectively. The solder layer 30 is composed of a plurality of solder portions 31 arranged in the same layer, and a solder portion 31 is sandwiched between each pair of relatively arranged first solder areas 111 and second solder areas 21.

[0060] On this basis, in the direction away from the blocking structure 12, the edges of the first solder area 111 and the second solder area 21 should be able to be flush with the first solder area 111 or at least partially exceed the first solder area 111, or the minimum spacing between the second solder area 21 and the blocking structure 12 should be greater than the minimum spacing between the first solder area 111 and the blocking structure 12. That is, overall, compared with the first solder area 111, the distance between the second solder area 21 and the blocking structure 12 can be farther, or the second solder area 21 can have a larger area, so that it can at least partially exceed the end away from the blocking structure 12.

[0061] Specifically, in the direction from the blocking structure 12 to the chip bare die 20, the sum of the effective areas of the first solder area 111 exceeding the second solder area 21 is recorded as S21, and the sum of the effective areas of the second solder area 21 exceeding the first solder area 111 is recorded as S11; in the opposite direction, the sum of the effective areas of the first solder area 111 exceeding the second solder area 21 is recorded as S12, and the sum of the effective areas of the second solder area 21 exceeding the first solder area 111 is recorded as S22, wherein S21+S22≤S11+S12.

[0062] It is understood that the aforementioned effective area refers to the area where the melted solder can exert a force on the chip die 20. Specifically, Figure 2 As shown, the aforementioned area parameters are illustrated by taking the relative positions of various first solder areas 111 and second solder areas 21 as examples. As shown by the two solder areas in the first row, at this time, the second solder area 21 is set beyond the corresponding first solder area 111 in the direction from the blocking structure 12 to the chip bare die 20, and the areas of the exceeding parts are respectively recorded as S111 and S112. In the opposite direction, the first solder area 111 is set beyond the corresponding second solder area 21, and the exceeding areas are respectively recorded as S121 and S122. In the figure, the solid line frame corresponds to the second solder area, and the dotted line frame corresponds to the first solder area.

[0063] In the solder area located at the lower left, in the direction from the blocking structure 12 to the chip die 20, the first solder area 111 is arranged beyond the second solder area 21, and the exceeding area is recorded as S211. In the opposite direction, the second solder area 21 is arranged beyond the first solder area 111, and the exceeding area is recorded as S221.

[0064] In the solder area at the lower right, the first solder area 111 is over-arranged in both directions. In the direction from the blocking structure 12 to the chip die 20, the over-area of ​​the first solder area 111 is recorded as S212, and the over-area in the opposite direction is recorded as S123.

[0065] On this basis, S11=S111+S112, S12=S121+S122+S123, S21=S211+S212, S22=S221, and S21+S22≤S11+S12. Limiting S21+S22≤S11+S12 can make the centers of the two solder areas offset from each other. After the solder portion 31 melts, the liquid solder can wet the first solder affinity layer 41 and the second solder affinity layer 42. The interfacial tension between the two and the repulsive force between the solder and the surrounding area with poor affinity can drive the chip die 20 to move. The magnitude of the aforementioned interfacial tension is positively correlated with the area of ​​the solder area. Therefore, by limiting the area difference between the two solder areas in different directions, it is possible to ensure that the chip die 20 moves to the preset target position through the self-alignment effect of the solder when it melts, thereby improving the position accuracy of the chip die 20 while soldering and fixing the chip die 20 so that it will not deviate during the packaging process.

[0066] It is understandable that during welding, the two layers of solder that are connected melt and polymerize. At this time, the solder is affected by its own surface tension and tends to polymerize toward the center. By virtue of the good bonding performance between the solder affinity layer 40 in the first solder area 111 and the second solder area 21 and the solder, and the light weight of the chip die 20 itself, the center of the second solder area 21 can be moved toward the center of the first solder area 111 through the self-alignment effect of the solder as described above. Then, by cooperating with the setting position of the blocking structure 12, the chip die 20 can be moved to the preset target position during the melting of the solder, thereby improving the position accuracy of the chip die 20. After the welding connection is formed, the connection is stable and reliable, and it is not easy to move when the plastic packaging material is injected, which can effectively improve the product yield and production efficiency.

[0067] See also Figure 4 , Figure 4 yes Figure 1 An enlarged view of the middle region Q. In some optional embodiments, the blocking structure 12 includes a first substructure 121 extending along the first direction X, and the chip die 20 abuts against the first substructure 121 in the corresponding blocking structure 12 .

[0068] The blocking structure 12 in the embodiment of the present application is used to limit the final stop position of the chip die 20 when the chip die 20 is moved by the molten solder, that is, the blocking structure 12 can be arranged in contact with the preset target position of the chip die 20. On this basis, the blocking structure 12 can include a first substructure 121 that is arranged on one side and extends along the first direction X, and the first substructure 121 can be a retaining wall structure protruding from the packaging area 11. At this time, the shape of a surface on the side of the chip die 20 can match the first substructure 121, and the side surface can finally move to abut against the first substructure 121, so as to further improve the position accuracy of the chip die 20.

[0069] In some optional embodiments, the maximum distance between the edge of the first solder region 111 and the first substructure 121 is L1, the maximum distance between the second solder region 21 and the first substructure 121 is L2, and L2≥L1.

[0070] As mentioned above, the blocking structure 12 in the embodiment of the present application can be a blocking wall extending along the first direction X, that is, the first substructure 121. On this basis, the chip die 20 can be limited by the first substructure 121. At this time, the maximum distance between the edge of the first solder area 111 and the first substructure 121, that is, the distance between the edge of one side of the first solder area 111 and the first substructure 121 and the first substructure 121 is recorded as L1. Correspondingly, the distance between the edge of one side of the second solder area 21 away from the first substructure 121 and the first substructure 121 is recorded as L2. L1 should be less than or equal to L2, that is, in the direction from the first substructure 121 to the chip die 20, the second solder area 21 should at least partially exceed the first solder area 111.

[0071] Setting the first solder area 111 closer to the first substructure 121 can ensure that the chip die 20 is abutted against the blocking structure 12 before the first solder area 111 and the second solder area 21 move to face each other, that is, after the chip die 20 moves into the preset target position, a certain distance is maintained between the centers of the first solder area 111 and the second solder area 21, thereby avoiding the problem that the solder force is insufficient and the chip die 20 cannot be pushed into the preset target position after the centers of the two solder areas are close to each other, thereby ensuring the product yield.

[0072] In some optional embodiments, the blocking structure 12 further includes a second substructure 122 extending along the second direction Y, the first direction X intersects the second direction Y, and the chip die 20 abuts against the second substructure 122 in the corresponding blocking structure 12 .

[0073] Similar to the first substructure 121, the blocking structure 12 may also include another blocking wall structure extending in a direction intersecting with the first substructure 121, that is, a second substructure 122 extending in the second direction Y. The first substructure 121 and the second substructure 122 may have the same thickness and height, and the two are arranged to intersect. Specifically, the first substructure 121 and the second substructure 122 may intersect to form an intersection line extending in a direction perpendicular to the packaging area 11. In the thickness direction Z, the extension dimensions of the two substructures may be equal to or slightly smaller than the extension dimension of the chip die 20 in this direction.

[0074] At this time, the first substructure 121 and the second substructure 122 intersect and form a certain angle, the size of which can match the size of the angle between the two side edges of the chip die 20 close to the blocking structure 12, and the preset target position of the chip die 20 can be set in the partial area connected to both the first substructure 121 and the second substructure 122, that is, the adjacent two side surfaces of the chip die 20 are respectively in contact with the first substructure 121 and the second substructure 122. By adding the second substructure 122, it can be further ensured that the chip die 20 enters the preset target position, thereby further improving the position accuracy of the chip die 20, thereby improving the product yield.

[0075] It is understandable that the first substructure 121 and the second substructure 122 in the embodiment of the present application can be continuously extended along their own extension direction to form a continuous retaining wall, or the two substructures can also have a certain spacing area in their own extension direction, that is, a plurality of retaining wall units extending in the same direction and spaced from each other are formed in the extension direction. The present application does not make a specific limitation on this, as long as it can form the required barrier and positioning for the chip bare die 20.

[0076] In some optional embodiments, the maximum distance between the edge of the first solder region 111 and the second substructure 122 is L3, the maximum distance between the edge of the second solder region 21 and the second substructure 122 is L4, and L3≥L4.

[0077] Similar to the position limitation related to the aforementioned first substructure 121, the first and second solder areas and the second substructure 122 should have a certain relative position relationship limitation, specifically, the outer edge of the first solder area 111 away from the second substructure 122 should not exceed the outer edge of the second solder area 21 away from the second substructure 122, so as to ensure that the center of the first solder area 111 can be set at a position closer to the blocking structure 12, thereby ensuring that the chip die 20 can move to abut against the blocking structure 12 during the welding process. Its working principle is the same as the principle of the position limitation related to the aforementioned first substructure 121, and this application will not repeat it here.

[0078] See also Figure 5 , Figure 5 yes Figure 1 In some optional embodiments, the packaging substrate 10 includes a plurality of packaging grooves 13 , the packaging regions 11 are located in the packaging grooves 13 and are arranged one-to-one with the packaging grooves 13 , and the blocking structure 12 includes at least a portion of the sidewalls 131 of the packaging grooves 13 .

[0079] Corresponding to the above-mentioned embodiment in which the blocking structure 12 is in the form of a retaining wall, the blocking structure 12 can also be provided in the form of a packaging groove 13. That is, the packaging substrate 10 can have a certain thickness, and a packaging groove 13 extending along the thickness direction Z is provided therein, and these packaging grooves 13 correspond to the packaging area 11 one by one and can have the same shape and size, that is, the bottom wall of each packaging groove 13 can be set as the packaging area 11, and the side wall 131 of the packaging groove 13 extends along the edge of the packaging area 11, so as to be used as the blocking structure 12.

[0080] Optionally, the extension dimension of each packaging groove 13 in the thickness direction Z can be equal to or slightly smaller than the extension dimension of the chip die 20 in this direction, thereby providing reliable support and limiting effects for the chip die 20, while avoiding obstacles to other processing techniques required for the chip die 20 after the packaging substrate 10.

[0081] In some optional embodiments, each packaging region 11 is provided with a first solder affinity layer 41 , and each chip die 20 is provided with a second solder affinity layer 42 .

[0082] The packaging area 11 in the embodiment of the present application and the first solder affinity layer 41 and the first solder area 111 can be arranged in a one-to-one correspondence. At the same time, the chip bare particle 20, the second solder affinity layer 42 and the second solder area 21 can be arranged in a one-to-one correspondence to facilitate processing and design of the shape, size and position of each solder area.

[0083] In some optional embodiments, the first solder affinity layer 41 and the second solder affinity layer 42 are made of metal material.

[0084] In the embodiment of the present application, the first solder area 111 and the second solder area 21 are respectively provided with a first solder affinity layer 41 and a second solder affinity layer 42, that is, a structure made of a material having good bonding performance with the solder, specifically, the material can be various metals or alloy materials. The solder in the chip assembly 100 is usually solder paste, which has poor bonding performance with the silicon-based material commonly used in the chip bare die 20, but has good bonding performance with metals, and metal materials are easy to process and manufacture, and the cost is low.

[0085] After solder is coated on the two solder affinity layers made of metal, the solder self-alignment function can be achieved through the good bonding performance between the solder and the first and second solder regions and the strong contact force, thereby moving the chip die 20.

[0086] In some optional embodiments, the first solder affinity layer 41 and the second solder affinity layer 42 include at least one of titanium, copper, tungsten, and nickel.

[0087] As mentioned above, the two solder affinity layers in the embodiment of the present application can be made of metal. On this basis, in order to reduce the impact on the chip bare particle 20 and simplify the processing steps, the two metal solder affinity layers can be prepared by physical vapor deposition. On this basis, target materials commonly used in physical vapor deposition technology and with mature process parameters can be used for preparation, such as titanium, copper, tungsten, nickel, etc., preferably at least one of titanium and copper, so that it is easier to process.

[0088] In some optional embodiments, the area of ​​the first solder region 111 is S13, the area of ​​the second solder region 21 is S23, and 0.5S23≤S13≤S23.

[0089] The first solder area 111, the second solder area 21 and the solder layer 30 therebetween in the embodiment of the present application are all used to assist in the positioning of the chip die 20. In order to ensure that the chip die 20 can be moved to the preset target position, the area of ​​the first solder area 111 in the embodiment of the present application can be smaller than the area of ​​the second solder area 21, so as to facilitate the adjustment of the position of the chip die 20 to abut against the blocking structure 12. At this time, the second solder area 21 on the chip die 20 can cover the side surface of the chip die 20 close to the packaging substrate 10, and the first solder area 111 can be connected to the blocking structure 12. Specifically, by adjusting the area size and relative position of the first solder area 111 and the second solder area 21, especially the distance between the geometric centers of the two solder areas, the center of the first solder area 111 can be made closer to the blocking structure 12, so that when the chip die 20 abuts against the blocking structure 12, there is still a certain distance between the center of the second solder area 21 and the center of the first solder area 111, that is, the chip die 20 reaches the preset target position before the first solder area 111 and the second solder area 21 are moved to be fully aligned, thereby further ensuring that the force provided by the solder can move the chip die 20 to the preset target position, thereby ensuring the yield and reliability of the product.

[0090] On this basis, the total area of ​​the first solder area 111 in each pair of corresponding packaging areas 11 and chip dies 20 is recorded as S13, and the total area of ​​the second solder area 21 is recorded as S23. S13 should be less than or equal to S23, and S13 should be kept greater than or equal to half of S23 to ensure that the first solder area 111 can carry a sufficient amount of solder, thereby ensuring that the self-alignment effect of the solder can generate sufficient force to move the chip die 20 to the preset target position.

[0091] In some optional embodiments, the package substrate 10 is provided with a solder-repelling layer, and the solder-repelling layer is at least partially provided around the first solder-affinity layer 41 .

[0092] In contrast to the first and second solder affinity layers, at least part of the packaging substrate 10 may be provided with a repelling solder layer, that is, a layer structure that cannot be well wetted by the solder and has poor contact performance between the two. The repelling solder layer can form a repelling and driving force in the corresponding direction on the solder. After the repelling solder layer is arranged around each solder area, the repulsive force is combined with the tension at the first and second solder affinity layers, which can further ensure the movement effect of the chip bare particle 20.

[0093] In the second aspect, according to an embodiment of the present application, a chip assembly 100 is proposed, including a packaging substrate 10, a chip die 20, and a solder layer 30. The packaging substrate 10 includes at least one packaging area 11 spaced apart from each other, each packaging area 11 is provided with at least one first solder affinity layer 41, each first solder affinity layer 41 forms a first solder area 111, and the packaging substrate 10 includes at least one blocking structure 12 corresponding to the packaging area 11, and the blocking structure 12 is arranged near the edge of the corresponding packaging area 11; at least one chip die 20 is arranged in the corresponding packaging area 11, and at least one second solder affinity layer 42 is arranged on the side of the chip die 20 facing the first solder affinity layer 41, and each second solder affinity layer 42 forms a second solder area 21 ; The solder layer 30 includes at least one solder portion 31, and a solder portion 31 is sandwiched between each pair of corresponding first solder-affinity layers 41 and second solder-affinity layers 42; in the direction from the blocking structure 12 to the chip die 20, each second solder area 21 exceeds its corresponding first solder area 111 by a length L21, and in the opposite direction, each second solder area 21 exceeds its corresponding first solder area 111 by a length L22, L22≤L21; or, in the direction from the blocking structure 12 to the chip die 20, each first solder area 111 exceeds its corresponding second solder area 21 by a length L11, and in the opposite direction, each first solder area 111 exceeds its corresponding second solder area 21 by a length L12, L12≥L11.

[0094] Similar to the nitrogen-sealed chip assembly 100 provided in any embodiment of the first aspect, the relative positions of the first solder area 111 and the second solder area 21 in the embodiment of the present application can be defined in another way, namely, the distance that the edges of the two solder areas exceed each other in the aforementioned two directions.

[0095] Specifically, in the direction away from the blocking structure 12, which can also be understood as the direction from the blocking structure 12 to the chip die 20, the edge of the second solder area 21 can be set beyond the edge of the first solder area 111, and the length of the excess is L21. At the same time, in the opposite direction, the length of the second solder area 21 exceeding the first solder area 111 can be L22. At this time, L22≤L21 should be made to ensure that the movable second solder area 21 can drive the chip die 20 to approach the location of the first solder area 111. Alternatively, it can also be limited by the lengths L11 and L12 that the first solder area 111 exceeds the second solder area 21 in the two opposite directions mentioned above. The specific effects and welding process of these two settings are the same as those of the chip assembly 100 in the first aspect, and the present application will not repeat them here.

[0096] In a third aspect, according to an embodiment of the present application, a chip assembly is proposed, including a packaging substrate 10, a chip die 20, and a solder layer 30. The packaging substrate 10 includes at least one packaging area 11 spaced apart from each other, each packaging area 11 is provided with at least one first solder affinity layer 41, each first solder affinity layer 41 forms a first solder area 111, and the packaging substrate 10 includes at least one blocking structure 12 corresponding to each packaging area 11, and the blocking structure 12 is arranged near the edge of the corresponding packaging area 11; at least one chip die 20 is arranged on the corresponding packaging area 11. In the region 11, at least one second solder affinity layer 42 is provided on the side of the chip bare particle 20 facing the first solder affinity layer 41, and each second solder affinity layer 42 forms a second solder area 21; the solder layer 30 includes at least one solder portion 31, and a solder portion 31 is sandwiched between each pair of corresponding first solder affinity layers 41 and second solder affinity layers 42; the orthographic projection of the second solder area 21 on the packaging substrate 10 forms a projection pattern, and the distance between the centroid of the first solder area 111 and the blocking structure 12 is less than or equal to the distance between the centroid of the projection pattern and the blocking structure 12.

[0097] Similar to the arrangement in the aforementioned second aspect, the chip assembly 100 in the embodiment of the present application can also define the relative position relationship and relative area size relationship between the first solder area 111 and the second solder area 21 by means of centroids.

[0098] Specifically, the centroid is the center of the area of ​​the geometric figure. The first solder area 111 and the second solder area 21 are arranged opposite to each other in the thickness direction Z, and the centroids of the two are staggered. That is, in the thickness direction Z, the positive projection of the second solder area 21 on the package substrate 10 forms a projection pattern. The first solder area 111 and the projection pattern can at least partially overlap each other, but the centroids of the two should be staggered. Compared with the projection pattern of the second solder area 21, the spacing between the first solder area 111 and the blocking structure 12 should be smaller, so as to adjust the chip bare die 20 to a preset position. The specific effect and welding process of this setting method are the same as those of the chip assembly 100 in the first aspect, and the present application will not repeat them here.

[0099] Please also read Figures 6 to 8 , Figure 6 is a flow chart of a packaging method provided by an embodiment of the present application, Figure 7 yes Figure 6 The structural diagram corresponding to step S2 in FIG. Figure 8 yes Figure 6 In a fourth aspect, according to an embodiment of the present application, a packaging method of a chip assembly 100 is proposed, comprising:

[0100] S1 and S2, providing a packaging substrate 10 and a chip bare die 20, the packaging substrate 10 includes at least one packaging area 11, a barrier structure 12 is arranged around the packaging area 11, at least one first solder affinity layer 41 is arranged in each packaging area 11, each first solder affinity layer 41 forms a first solder area 111, and at least one second solder affinity layer 42 is arranged on one side surface of the chip bare die 20, each second solder affinity layer 42 forms a second solder area 21; that is, the packaging substrate 10 includes at least one packaging area 11, a barrier structure 12 is arranged around the packaging area 11, each packaging area 11 is provided with at least one first solder affinity layer 41, each first solder affinity layer 41 forms a first solder area 111, and at least one second solder affinity layer 42 is arranged on one side surface of the chip bare die 20, each second solder affinity layer 42 forms a second solder area 21; Figure 6 There is no order of precedence between S1 and S2.

[0101] S3, disposing solder on at least one of the first solder region 111 and the second solder region 21 to form at least one solder portion 31;

[0102] S4, placing the bare chip 20 in the packaging area 11, and making the solder portion 31 located between the first solder affinity layer 41 and the second solder affinity layer 42;

[0103] S5, heating the solder to melt the solder into a liquid state, and causing the bare chip 20 to move to a preset target position under the action of the solder;

[0104] S6, cooling the solder to solidify the solder portion 31 to form a solder layer 30, so as to complete the solder connection and fix the relative position between the package substrate 10 and the chip die 20;

[0105] S7. After completing step S6, the chip assembly 100 may be packaged in a subsequent manner.

[0106] The embodiment of the present application also provides a packaging method for a chip assembly 100 , wherein the bare chip 20 is firstly disposed on the packaging substrate 10 , and then the two are welded to be connected to fix the position, and then the plastic packaging material can be injected for packaging.

[0107] Specifically, the method includes step S1, i.e., providing a package substrate 10 and a chip die 20, wherein the package substrate 10 includes a plurality of package regions 11, a barrier structure 12 is disposed around the package region 11, and the package region 11 includes a first solder region 111 formed by a first solder affinity layer 41 for easy soldering. Correspondingly, the chip die 20 may be provided with a second solder region 21 formed by a second solder affinity layer 42.

[0108] In step S2, solder is coated on at least one of the first and second solder areas to form at least one solder portion 31. In the embodiment where solder is coated on both the first and second solder areas, the two solder portions 31 can be made of the same material and have the same thickness, and the two solder portions 31 can respectively completely cover the corresponding solder areas, so that after the subsequent step of melting the solder portion 31, the chip bare particle 20 can be moved according to the size and position of the first and second solder areas.

[0109] Then in step S3, the chip die 20 can be placed in the packaging area 11. It can be understood that the first solder area 111 and the second solder area 21 are respectively located on the side surfaces of the packaging substrate 10 and the chip die 20 close to each other. Therefore, when applying solder and placing it, although it is not necessary to place it precisely at a certain position, the solders located on the packaging substrate 10 and the chip die 20 should still be able to at least partially overlap and contact each other to ensure that the solder can flow back to the center when it melts.

[0110] Subsequently, the chip assembly 100 can be soldered by reflow soldering, that is, the heating, soldering step S4 and cooling step S5 performed in sequence are all process steps in reflow soldering. Reflow soldering refers to the soldering that is connected and fixed between the two solder areas by remelting the solder pre-set in the first and second solder areas. Specifically, a circulating high-temperature airflow is used to make the gel-like flux physically react at this temperature to achieve SMD (surface-mount device) soldering.

[0111] Furthermore, reflow soldering is usually divided into four specific steps, namely heating, heat preservation, welding and cooling, wherein the heating step is used to soften the solder portion 31 so that it covers the two solder areas and isolates the air; the heat preservation step is used to fully preheat the chip component 100 to avoid the high temperature during welding from having adverse effects on the chip die 20; the welding step includes further heating the chip component 100 to melt the solder portion 31 applied in step S2, and drive the chip die 20 to a preset position through the self-alignment function of the solder located in the first and second solder areas respectively; the cooling step is to lower the temperature of the chip component 100 so that the aforementioned solder portion 31 is cooled and fixed to form a solder layer 30, thereby completing the connection between the packaging substrate 10 and the chip die 20.

[0112] The temperature of reflow soldering is easy to control, the cost is low, and the oxidation problem of metal parts such as pins can be avoided during the soldering process. The thermal shock to the chip assembly 100 is small, and damage to the chip die 20 caused by overheating can be avoided, and good soldering quality can be ensured.

[0113] After the aforementioned welding step is completed, packaging can be performed by injecting the plastic molding compound into the chip assembly 100. At this time, the chip die 20 has been fixed at the preset target position through the aforementioned welding connection, and no displacement will occur when injecting the plastic molding compound. Therefore, the position accuracy of the chip die 20 and the product yield obtained after packaging can be effectively improved.

[0114] In some optional embodiments, the step S3 of placing the chip die 20 in the packaging area 11 includes:

[0115] In each pair of corresponding chip dies 20 and packaging areas 11, in the direction from the blocking structure 12 to the chip dies 20, the sum of the effective areas of each second solder area 21 exceeding the corresponding first solder area 111 is S11, and the sum of the effective areas of each first solder area 111 exceeding the corresponding second solder area 21 is S21; in the opposite direction, the sum of the effective areas of each first solder area 111 exceeding the corresponding second solder area 21 is S12, and the sum of the effective areas of each second solder area 21 exceeding the corresponding first solder area 111 is S22. The chip dies 20 are placed so that S21+S22<S11+S12.

[0116] Alternatively, the step S3 of placing the bare chip 20 in the packaging area 11 includes:

[0117] In the direction from the blocking structure 12 to the chip die 20, each second solder region 21 exceeds the corresponding first solder region 111 by a length L21, and in the opposite direction, each second solder region 21 exceeds the corresponding first solder region 111 by a length L22, and the chip die 20 is placed so that L22 < L21; or, in the direction from the blocking structure 12 to the chip die 20, each first solder region 111 exceeds the corresponding second solder region 21 by a length L11, and in the opposite direction, each first solder region 111 exceeds the corresponding second solder region 21 by a length L12, and the chip die 20 is placed so that L12 > L11;

[0118] Alternatively, the step S3 of placing the bare chip 20 in the packaging area 11 includes:

[0119] The orthographic projection of the second solder region 21 on the package substrate 10 forms a projection pattern, and the chip die 20 is placed so that the distance between the centroid of the first solder region 111 and the blocking structure 12 is smaller than the distance between the centroid of the projection pattern and the blocking structure 12 .

[0120] Corresponding to the chip component 100 provided in any one of the embodiments of the first aspect, the second aspect and the third aspect, when placing the chip die 20, the same position limitation method as the chip component 100 in the aforementioned three aspects can be adopted, that is, at least one of the effective area, the excess length and the centroid distance is used for limitation, to ensure that when the chip die 20 is placed in the packaging area 11, the first solder area 111 and the second solder area 21 can be offset from each other, and the first solder area 111 is arranged closer to the blocking structure 12 to ensure that it can move the chip die 20 to the preset target position through the tension of the solder.

[0121] The principles and effects of each position limiting method are the same as those of the setting method of the chip assembly 100 in the above-mentioned corresponding embodiment, and the present application will not repeat them here. It can be understood that in the above-mentioned placement methods using different limiting methods, the equal conditions in the limiting conditions can be removed so that the chip bare die 20 can produce a position correction effect due to misalignment.

[0122] In some optional embodiments, the step S4 of heating the solder further includes:

[0123] S41 , making the bare chip 20 moved to the preset target position abut against the blocking structure 12 .

[0124] The package substrate 10 in the embodiment of the present application has a blocking structure 12. When the chip die 20 is moved by the surface tension of the solder, the chip die 20 can be accurately positioned at the target position by the aforementioned limitation of the position of the chip die 20 after placement and the assistance of the blocking structure 12. Specifically, during the heating step, a certain temperature should be maintained so that the surface of the chip die 20 close to the blocking structure 12 abuts against the blocking structure 12.

[0125] In a fifth aspect, an electronic device is proposed according to an embodiment of the present application, comprising at least part of the chip assembly 100 in any one of the embodiments of the first, second, and third aspects.

[0126] The embodiment of the present application also provides an electronic device, which includes at least part of the aforementioned chip component 100. It can be understood that the chip component 100 in the embodiment of the present application includes a plurality of chip dies 20, which can be correspondingly formed into a plurality of chips after packaging is completed, and can be split into a plurality of independent chip structures by laser cutting or other methods in subsequent process steps.

[0127] On this basis, the electronic device provided in the embodiment of the present application adopts the complete chip structure obtained by packaging and cutting the chip assembly 100 as described above. The electronic device provided in the embodiment of the present application has all the beneficial effects of the chip assembly 100 provided in the embodiment of the present application, and the specific description of the chip assembly 100 in the above embodiments can be referred to, and this embodiment will not be repeated here.

[0128] It is to be understood that the above description and detailed description are only exemplary and explanatory and do not constitute a limitation on the present application. Those skilled in the art may make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A chip assembly, characterized in that: include: A packaging substrate, comprising at least one packaging area spaced apart from each other, each of the packaging areas being provided with at least one first solder affinity layer, each of the first solder affinity layers forming a first solder area, the packaging substrate comprising at least one blocking structure corresponding to each of the packaging areas, the blocking structure being arranged close to an edge of the corresponding packaging area; At least one bare chip is disposed in the corresponding packaging area, and at least one second solder affinity layer is disposed on the side of the bare chip facing the first solder affinity layer, and each of the second solder affinity layers forms a second solder area; The solder layer comprises at least one solder portion, wherein the solder portion is sandwiched between each pair of corresponding first solder affinity layers and second solder affinity layers; For each pair of corresponding chip die and package area, in the direction from the blocking structure to the chip die, the sum of the effective areas of each second solder area exceeding the corresponding first solder area is S11, and the sum of the effective areas of each first solder area exceeding the corresponding second solder area is S21; In the opposite direction, the sum of the effective areas of the first solder areas exceeding the corresponding second solder areas is S12, the sum of the effective areas of the second solder areas exceeding the corresponding first solder areas is S22, and S21+S22≤S11+S12.

2. The chip assembly according to claim 1, characterized in that: The blocking structure includes a first substructure extending along a first direction, and the chip die abuts against the first substructure in the corresponding blocking structure.

3. The chip assembly according to claim 2, characterized in that: The maximum distance between the edge of the first solder area and the first substructure is L1, and the maximum distance between the second solder area and the first substructure is L2, where L2≥L1.

4. The chip assembly according to claim 2, characterized in that: The blocking structure further includes a second substructure extending along a second direction, the first direction intersects with the second direction, and the chip die abuts against the corresponding second substructure in the blocking structure.

5. The chip assembly according to claim 4, characterized in that: The maximum distance between the edge of the first solder area and the second substructure is L3, the maximum distance between the edge of the second solder area and the second substructure is L4, and L3≥L4.

6. The chip assembly according to claim 1, characterized in that: The packaging substrate includes a plurality of packaging grooves, the packaging regions are located in the packaging grooves and are arranged in a one-to-one correspondence with the packaging grooves, and the blocking structure includes at least a portion of the side walls of the packaging grooves.

7. The chip assembly according to claim 6, characterized in that: Each of the packaging regions is provided with a first solder affinity layer, and each of the chip bare die is provided with a second solder affinity layer.

8. The chip assembly according to claim 1, characterized in that: The first solder affinity layer and the second solder affinity layer are made of metal material.

9. The chip assembly according to claim 8, characterized in that: The first solder affinity layer and the second solder affinity layer include at least one of titanium, copper, tungsten, and nickel.

10. The chip assembly according to claim 1, characterized in that: The area of ​​the first solder region is S13, the area of ​​the second solder region is S23, and 0.5S23≤S13≤S23.

11. The chip assembly according to claim 1, characterized in that: The package substrate is provided with a solder-repelling layer, and the solder-repelling layer is at least partially provided around the first solder-affinity layer.

12. A chip assembly, characterized in that: include: The packaging substrate comprises at least one packaging area spaced apart from each other, each of the packaging areas is provided with a first solder affinity layer, and the first solder affinity layer forms a first solder area; the packaging substrate comprises at least one blocking structure corresponding to each of the packaging areas, and the blocking structure is arranged close to the edge of the corresponding packaging area; At least one bare chip is disposed in the corresponding packaging area, a second solder affinity layer is disposed on a side of the bare chip facing the first solder affinity layer, and the second solder affinity layer forms a second solder area; The solder layer comprises at least one solder portion, wherein the solder portion is sandwiched between each pair of corresponding first solder affinity layers and second solder affinity layers; In each pair of corresponding chip die and package areas, in the direction from the blocking structure to the chip die, each second solder area exceeds the corresponding first solder area by a length of L21, and in the opposite direction, each second solder area exceeds the corresponding first solder area by a length of L22, where L22≤L21; or, in the direction from the blocking structure to the chip die, each first solder area exceeds the corresponding second solder area by a length of L11, and in the opposite direction, each first solder area exceeds the corresponding second solder area by a length of L12, where L12≥L11.

13. A chip assembly, characterized in that: include: The packaging substrate comprises at least one packaging area spaced apart from each other, each of the packaging areas is provided with at least one first solder affinity layer, and each of the first solder affinity layers forms a first solder area; the packaging substrate comprises at least one blocking structure corresponding to each of the packaging areas, and the blocking structure is arranged close to the edge of the corresponding packaging area; At least one bare chip is disposed in the first solder area in the corresponding packaging area, and at least one second solder layer is disposed on the side of the bare chip facing the first solder layer, and each of the second solder layers forms a second solder area; The solder layer comprises at least one solder portion, wherein the solder portion is sandwiched between each pair of corresponding first solder affinity layers and second solder affinity layers; In each pair of corresponding chip bare die and package areas, the orthographic projection of the second solder area on the package substrate forms a projection pattern, and the distance between the centroid of the first solder area and the blocking structure is less than or equal to the distance between the centroid of the projection pattern and the blocking structure.

14. A chip assembly packaging method, characterized in that: include: A packaging substrate and a chip die are provided, wherein the packaging substrate comprises at least one packaging area, a barrier structure is arranged around the packaging area, at least one first solder affinity layer is arranged in each packaging area, each of the first solder affinity layers forms a first solder area, and at least one second solder affinity layer is arranged on a side surface of the chip die, each of the second solder affinity layers forms a second solder area; Disposing solder on at least one of the first solder area and the second solder area to form at least one solder portion; Placing the bare chip in the packaging area, and making the solder portion located between the first solder affinity layer and the second solder affinity layer; Heating the solder to melt the solder into a liquid state, and causing the chip die to move toward a preset target position under the action of the solder; The solder is cooled to solidify the solder portion to form a solder layer, so as to complete the solder connection and fix the relative position between the package substrate and the chip die.

15. The packaging method according to claim 14, characterized in that: The step of placing the bare chip in the packaging area comprises: For each pair of corresponding die and package area, in the direction from the blocking structure to the die, the sum of the effective areas of the second solder areas exceeding the corresponding first solder areas is S11, and the sum of the effective areas of the first solder areas exceeding the corresponding second solder areas is S21; in the opposite direction, the sum of the effective areas of the first solder areas exceeding the corresponding second solder areas is S12, and the sum of the effective areas of the second solder areas exceeding the corresponding first solder areas is S22, and the die is placed so that S21+S22<S11+S12; Alternatively, the step of placing the bare chip in the packaging area includes: In the direction from the blocking structure to the chip die, each second solder area exceeds the corresponding first solder area by a length of L21, and in the opposite direction, each second solder area exceeds the corresponding first solder area by a length of L22, and the chip die is placed so that L22 < L21; or, in the direction from the blocking structure to the chip die, each first solder area exceeds the corresponding second solder area by a length of L11, and in the opposite direction, each first solder area exceeds the corresponding second solder area by a length of L12, and the chip die is placed so that L12 > L11; Alternatively, the step of placing the bare chip in the packaging area includes: The orthographic projection of the second solder area on the package substrate forms a projection pattern, and the chip die is placed so that the distance between the centroid of the first solder area and the blocking structure is smaller than the distance between the centroid of the projection pattern and the blocking structure.

16. The packaging method according to claim 15, characterized in that: The step of placing the bare chip in the packaging area comprises: The chip die is placed so that in the direction from the blocking structure to the chip die, the distance between the centroid of the first solder area and the blocking structure is L5, and the distance between the centroid of the second solder area and the blocking structure is L6, so that the absolute value of the difference between L5 and L6 is greater than the maximum distance between the chip die and the blocking structure.

17. The packaging method according to claim 14, characterized in that: The step of heating the solder further comprises: The bare chip moved to the preset target position is brought into contact with the blocking structure.

18. An electronic device, characterized in that: Comprising at least part of the chip assembly as described in any one of claims 1 to 13.

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