A receiving-end equalization circuit with pre-determination for a high-speed serial interface chip

Abstract

The present application relates to the field of communication technology, and discloses a receiving-end equalization circuit with pre-determination for a high-speed serial interface chip, comprising a plurality of forward nodes, a main node, and a plurality of backward nodes connected in sequence, with delay units connected between adjacent nodes, wherein the forward node farthest from the main node receives the output value of the analog-to-digital converter; a plurality of multipliers, each multiplier connected to each of the main node, the plurality of forward nodes, and the plurality of backward nodes; one or more backward pre-determiners, each backward pre-determiner connected between each of the plurality of backward nodes far from the main node and the corresponding multiplier; and a first adder, the first adder being connected to the output ends of the plurality of multipliers. The present application reduces the area and power consumption requirements of the forward feedback equalizer implementation while ensuring that the performance meets the requirements through a forward feedback equalizer implementation method using a pre-determiner.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and more specifically to a receiving-end equalization circuit with pre-determination. Background Art

[0002] This section is intended to provide a background or context to the embodiments of the present application as recited in the claims. No admission is made that the description herein is prior art as disclosed by virtue of its inclusion in this section.

[0003] In high-speed serial interface chips, intersymbol interference (ISI) caused by channel insertion loss can affect signal transmission quality and cause bit errors. Therefore, equalization technology is needed to compensate for channel insertion loss and mitigate the effects of ISI. In serializer / deserializer (SerDes) receiver solutions based on analog-to-digital converters (ADCs) and digital signal processing (DSPs), the feedforward equalizer (FFE) is a commonly used linear digital equalizer. However, in a typical SerDes receiver implementation, the FFE typically accounts for the largest portion of power consumption, a key metric for evaluating SerDes performance.

[0004] In an adaptive equalization scheme for receiving end of a serial deserializer used in analog-to-digital converter and digital signal processing, such as Figure 1 As shown in Figure 1, the FFE multiplies the data at each node by the coefficient of the corresponding node, then adds the results from all nodes and quantizes them for output. Simulations and tests show that the multiplier consumes the majority of the power in the FFE circuit.

[0005] The disadvantage of the prior art is that the area and power consumption occupied by the multiplier during implementation are positively correlated with the input bit width of the multiplier. At the same time, in the implementation of FFE, the bit width of the data and coefficient is also positively correlated with the performance of FFE. In other words, the larger the bit width of the data and coefficient of each FFE input node, the larger the area and power consumption occupied during implementation, and the better the performance achieved. In the existing FFE implementation, the data and coefficient bit width of the node are the same, but the contribution of each node to the final FFE performance is different. The nodes at the edge (the nodes farther away from the center node) contribute less to the final performance of FFE. Therefore, using multipliers of the same size for nodes with different performance contributions will cause a waste of area and power consumption. Summary of the Invention

[0006] The purpose of this application is to provide a high-speed serial interface chip with a pre-determined receiving end equalization circuit, through an FFE implementation method using a pre-determinator, to reduce the area and power consumption requirements during FFE implementation while ensuring that the performance meets the requirements.

[0007] The present application discloses a receiving-end equalization circuit with pre-determination for a high-speed serial interface chip, comprising:

[0008] A plurality of forward nodes, a main node, and a plurality of backward nodes are sequentially connected, with delay units connected between adjacent nodes, wherein the main node receives an output value of the analog-to-digital converter;

[0009] a plurality of multipliers, each multiplier being connected to each of the master node, the plurality of forward nodes, and the plurality of backward nodes;

[0010] One or more backward pre-determiners, each backward pre-determiner being connected between each of several backward nodes far from the main node among the plurality of backward nodes and a corresponding multiplier; and

[0011] A first adder is connected to output terminals of the plurality of multipliers.

[0012] In a preferred example, it further includes: one or more forward pre-determiners, each forward pre-determiner is connected between each forward node of several forward nodes far away from the main node among the multiple forward nodes and the corresponding multiplier.

[0013] In a preferred embodiment, the number of the backward pre-determiners is twice the number of the forward pre-determiners.

[0014] In a preferred example, the receiving end equalization circuit includes: 9 forward nodes and 22 backward nodes, wherein the number of the backward pre-determiners is 6 and the number of the forward pre-determiners is 3.

[0015] In a preferred example, the bit width of the data output by the backward pre-determinator and the forward pre-determinator is smaller than the bit width of the output value of the analog-to-digital converter.

[0016] In a preferred example, the bit width of the output value of the analog-to-digital converter is 8 bits, the data bit width output by the backward pre-determinator and the forward pre-determinator is 3 bits or 4 bits or 5 bits, the coefficient bit width of the multiplier is 9 bits, and the bit width of the first adder is 22 bits.

[0017] In a preferred embodiment, the number of the backward pre-determiners and the number of the forward pre-determiners are determined by simulation testing of their relationship with the bit error rate.

[0018] In a preferred example, the receiving end equalization circuit includes: 6 forward nodes and 25 backward nodes, wherein the number of the backward pre-determiners is 8.

[0019] In a preferred embodiment, it also includes:

[0020] an output decider, wherein an input end of the output decider is connected to an output end of the first adder and decides data output by the first adder;

[0021] a second adder, wherein an input terminal of the second adder is connected to an output terminal of the decision maker and calculates an error value between the data output by the decision maker and an ideal value; and

[0022] An adaptive algorithm module receives the output value of the analog-to-digital converter and the error value output by the second adder respectively and calculates and outputs coefficients of each node.

[0023] In a preferred embodiment, the calculation formula of the output value of the first adder is as follows:

[0024]

[0025] Wherein, y(n) is the output value of the first adder at the nth moment, h(n,j) is the coefficient of the multiplier corresponding to the jth node at the nth moment, and x”(n,j) is the input value of the multiplier corresponding to the jth node at the nth moment, wherein, -N≤j≤M, N is the number of the forward nodes, and M is the number of the backward nodes;

[0026] The calculation formula for the input value x″(n,j) of the multiplier corresponding to the jth node at the nth time is as follows:

[0027]

[0028] Among them, x′(n,j) is the output value of the backward pre-determinator corresponding to the j-th node at the n-th time, x(n,j) is the output value of the analog-to-digital converter corresponding to the j-th node at the n-th time, and Q is the number of the backward pre-determinators, where 0<Q<M.

[0029] Compared with the prior art, the main differences and effects of the embodiments of this application are:

[0030] The present invention can optimize the area and power consumption of the entire FFE circuit without causing critical impact on performance.

[0031] Furthermore, under different pre-determination schemes, different degrees of area and power consumption optimization can be achieved.

[0032] The specification of this application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features of this application (i.e., technical solutions) are to be listed, the specification will be too lengthy. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of this application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions should all be deemed to have been recorded in this specification), unless such a combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed. Features C and D are equivalent technical means that play the same role. Technically, only one of them can be used, and it is impossible to use them at the same time. Feature E can be technically combined with feature C. Then, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, while the solution of A+B+C+E should be deemed to have been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0034] Figure 1 It is a schematic diagram of a receiving end equalization circuit in the prior art.

[0035] Figure 2 This is a schematic diagram of a receiving-end equalization circuit with pre-determination according to the first embodiment of the present application.

[0036] Figure 3 This is a schematic diagram of the relationship between the total number of forward pre-determiners and backward pre-determiners and the bit error rate in Example 1 of the present application.

[0037] Figure 4 This is a schematic diagram of a receiving-end equalization circuit with pre-determination according to the second embodiment of the present application.

[0038] Figure 5 This is a schematic diagram of the relationship between the number of backward pre-determiners and the bit error rate in Example 2 of the present application.

[0039] In the accompanying drawings, the following are marked:

[0040] 1- Delay unit;

[0041] 2-Backward pre-decision device;

[0042] 3-Multiplier;

[0043] 4-Adder;

[0044] 5-Forward predictor. DETAILED DESCRIPTION

[0045] In the following description, many technical details are provided to help readers better understand this application. However, those skilled in the art will understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can be implemented.

[0046] Description of some concepts:

[0047] High-speed serial interface: A serial interface standard. This technology also involves a serial deserializer (SerDes). This technology converts multiple low-speed parallel signals at the transmitting end into high-speed serial signals, which are then transmitted over the media (fiber optic cable or copper wire) and then reconverted back into low-speed parallel signals at the receiving end.

[0048] Feedforward Equalizer (FFE) is a linear equalization technology that modifies the amplitude of the current bit based on the weighted values ​​of the voltage amplitudes of adjacent bits. The weighting coefficient of each adjacent bit is directly related to the impulse response of the channel.

[0049] Decision Feedback Equalizer (DFE): It is a nonlinear equalization technology that corrects the decision threshold of the current bit by using the decision levels of adjacent bits.

[0050] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0051] The present application discloses a receiving-end equalizer circuit with pre-determination for a high-speed serial interface chip, comprising: a plurality of forward nodes, a master node, and a plurality of backward nodes connected in sequence, with delay units connected between adjacent nodes, wherein the master node receives the output value of an analog-to-digital converter. The receiving-end equalizer circuit also includes a plurality of multipliers, one or more backward pre-determiners, and a first adder. Each multiplier is connected to the master node, each of the plurality of forward nodes, and each of the plurality of backward nodes. Each backward pre-determiner is connected between each of the plurality of backward nodes that are remote from the master node and a corresponding multiplier. The first adder is connected to the output ends of the plurality of multipliers.

[0052] The present invention can optimize the area and power consumption of the entire receiving-end equalization circuit without causing critical impact on performance.

[0053] Example 1

[0054] Figure 2 A schematic diagram of a receiving-end equalizer circuit with pre-determination for a high-speed serial interface chip in one embodiment is shown. The circuit includes: a plurality of forward nodes x(n,-9 to x(n,-1), a main node x(n,0), and a plurality of backward nodes x(n,1 to x(n,22) connected in sequence, with a delay unit 1 connected between adjacent nodes. The forward node x(n,-9), which is farthest from the main node, receives the output value of an analog-to-digital converter (not shown in the figure). The receiving-end equalizer circuit also includes a plurality of multipliers 3, one or more backward pre-determiners 2, a first adder 4, and one or more forward pre-determiners 5. Each multiplier 3 is connected to each of the main node x(n,0), the plurality of forward nodes x(n,-9 to x(n,-1), and the plurality of backward nodes x(n,1 to x(n,22. The first adder 4 is connected to the output ends of the plurality of multipliers 3.

[0055] Each backward pre-determinator 2 is connected between each of the plurality of backward nodes that are remote from the master node and the corresponding multiplier 3. In one embodiment, the bit width of the data output by the backward pre-determinator 2 is smaller than the bit width of the output value of the analog-to-digital converter. For example, the bit width of the output value of the analog-to-digital converter is 8 bits, while the bit width of the data output by the backward pre-determinator 2 can be 3 bits, 4 bits, or 5 bits.

[0056] Each forward pre-determinator 5 is connected between each of the plurality of forward nodes that are remote from the main node and the corresponding multiplier 3. In one embodiment, the data bit width output by the forward pre-determinator 5 is smaller than the bit width of the output value of the analog-to-digital converter. For example, the data bit width output by the forward pre-determinator 2 can be 3 bits, 4 bits, or 5 bits.

[0057] Figure 2 In the example, a receiving-end equalization circuit including 32 nodes is used for illustration. The receiving-end equalization circuit includes: 1 master node, 9 forward nodes, and 22 backward nodes. In other embodiments of the present application, the total number of nodes may also be 24, 16, etc., and the present application is not limited thereto.

[0058] In this embodiment, the number of backward pre-determiners 2 is twice the number of forward pre-determiners 5. The number of backward pre-determiners 2 and the number of forward pre-determiners 5 are determined by simulation test and their relationship with bit error rate, as shown in FIG. Figure 3As shown, when the bit error rate is lower than 1E-6, it is considered acceptable. At this time, the maximum number of nodes introducing the pre-determinator is 9. In this embodiment, the receiving end equalization circuit includes: 9 forward nodes and 22 backward nodes, of which the number of backward pre-determinators 2 is 6 and the number of forward pre-determinators 5 is 3. In other words, the forward pre-determinators are connected between the 3 nodes of the forward node far away from the main node (i.e., the nodes x(n,-9 to x(n,-7) and the corresponding multipliers), and the backward pre-determinators are connected between the 6 nodes of the backward node far away from the main node (i.e., the nodes x(n,17 to x(n,22) and the corresponding multipliers).

[0059] It should be understood that the number of backward pre-determiners 2 does not need to be twice the number of forward pre-determiners 5. For example, other numerical relationships are possible. For example, the number of backward pre-determiners 2 is 7 and the number of forward pre-determiners 5 is 2, or the number of backward pre-determiners 2 is 5 and the number of forward pre-determiners 5 is 4. In addition, the maximum number of nodes introducing pre-determiners can also be 10, where the number of backward pre-determiners 2 is 7 and the number of forward pre-determiners 5 is 3.

[0060] In one embodiment, Figure 2 As shown, the bit width of the output value of the analog-to-digital converter is 8 bits. For the convenience of description, the backward pre-determiner 2 and the forward pre-determiner 5 are collectively referred to as pre-determiners, the backward node with the backward pre-determiner 2 is called the backward node of pre-determination, and the forward node with the forward pre-determiner 5 is called the forward node of pre-determination.

[0061] In one embodiment, the data bit width output by the predeterminator is 3 bits, 4 bits, or 5 bits. The nodes farther from the central node use predeterminators with lower bit widths, which can achieve better power consumption optimization. The coefficient bit width of multiplier 3 is 9 bits. At the node connected to the predeterminator, the data bit width of multiplier 3 is the data bit width output by the corresponding predeterminator. At the node not connected to the predeterminator, the data bit width of multiplier 3 is the bit width of the output value of the analog-to-digital converter. In other words, the data bit width of the multiplier corresponding to the node connected to the predeterminator is smaller than the data bit width of the multiplier corresponding to the node not connected to the predeterminator.

[0062] That is, in this embodiment, when the data bit width output by the pre-determinator is all 3 bits, 32 8*9 multipliers 3 with a bit width of 8 are required without the pre-determinator. With the pre-determinator, 23 8*9 multipliers 3, 9 3*9 multipliers 3, and 9 3-bit pre-determiners are required. The area and power consumption of the pre-determinator are much smaller than those of the multiplier 3. Under this implementation scheme, the overall power consumption of FFE is approximately 10%.

[0063] Because the bit width of first adder 4 depends on the bit width of the input signal, sufficient bit width must be reserved to prevent overflow. The data input of each node is 8 or 9 bits, and the bit width of the output data of multiplier 3 is 17 bits. There are 32 17-bit bits for 32 nodes, so the bit width of first adder 4 is 22 bits.

[0064] In one embodiment, the calculation formula of the output value of the first adder is as follows:

[0065]

[0066] Where y(n) is the output value of the first adder at the nth moment, h(n,j) is the coefficient of the multiplier corresponding to the jth node at the nth moment, and x”(n,j) is the input value of the multiplier corresponding to the jth node at the nth moment, where -N≤j≤M, N is the number of forward nodes, and M is the number of backward nodes.

[0067] The calculation formula for the input value x″(n,j) of the multiplier corresponding to the jth node at the nth time is as follows:

[0068]

[0069] Among them, x′(n,j) is the output value of the pre-determinator corresponding to the j-th node at the n-th time, x(n,j) is the output value of the analog-to-digital converter corresponding to the j-th node at the n-th time, P is the number of forward pre-determinators, and Q is the number of backward pre-determinators, where 0<P<N, 0<Q<M.

[0070] Example 2

[0071] Figure 4 A schematic diagram of a receiver-side equalization circuit with pre-determination for a high-speed serial interface chip in one embodiment is shown. The circuit includes: a plurality of sequentially connected forward nodes x(n, -6) to x(n, -1), a master node x(n, 0), and a plurality of backward nodes x(n, 1) to x(n, 22). Delay units 1 are connected between adjacent nodes. The forward node x(n, -6), farthest from the master node, receives the output value of an analog-to-digital converter (not shown). The receiver-side equalization circuit also includes a plurality of multipliers 3, one or more backward pre-determiners 2, and a first adder 4. Each multiplier 3 is connected to the master node x(n, 0) and each of the plurality of backward nodes x(n, 1) to x(n, 22).

[0072] Each backward pre-determinator 2 is connected between each of several backward nodes away from the main node among the multiple backward nodes and the corresponding multiplier 3. In one embodiment, the data bit width output by the backward pre-determinator 2 is smaller than the bit width of the output value of the analog-to-digital converter.

[0073] In one embodiment, the number of backward pre-determiners 2 is determined by simulation test of the relationship between the number of backward pre-determiners 2 and the bit error rate. Figure 5 As shown, in this embodiment, the number of backward pre-determiners 2 is a multiple of 2. When the bit error rate is lower than 1E-6, it is acceptable. At this time, the maximum number of nodes introducing pre-determiners is 8. Figure 4 As shown, the receiving-end equalization circuit includes one master node, six forward nodes, and 25 backward nodes, with eight backward pre-determinators 2. Under this implementation, the overall FFE power consumption benefit is approximately 7.6%. Furthermore, the maximum number of nodes incorporating pre-determinators can be increased to nine, with nine backward pre-determinators 2.

[0074] In another embodiment, the receiving-end equalization circuit optionally further includes: an output determiner, a second adder, and an adaptive algorithm module. The input of the output determiner is connected to the output of the first adder 4 and determines the data output by the first adder 4. The input of the second adder is connected to the output of the determiner and calculates the error between the data output by the determiner and the ideal value. The adaptive algorithm module receives the output value of the analog-to-digital converter and the error value output by the second adder, respectively, and calculates and outputs the coefficients of each node.

[0075] In one embodiment, the calculation formula of the output value of the first adder is as follows:

[0076]

[0077] Where y(n) is the output value of the first adder at the nth moment, h(n,j) is the coefficient of the multiplier corresponding to the jth node at the nth moment, and x”(n,j) is the input value of the multiplier corresponding to the jth node at the nth moment, where -N≤j≤M, N is the number of forward nodes, and M is the number of backward nodes.

[0078] The calculation formula for the input value x″(n,j) of the multiplier corresponding to the jth node at the nth time is as follows:

[0079]

[0080] Among them, x′(n,j) is the output value of the backward pre-determinator corresponding to the j-th node at the n-th time, x(n,j) is the output value of the analog-to-digital converter corresponding to the j-th node at the n-th time, and Q is the number of the backward pre-determinators, where 0<Q<M.

[0081] The key point of the present invention is to introduce the decider originally used for DFE into the data path of FFE as a pre-determiner. The ADC sampling data sent to multiplier 3 is first judged once and then sent to the multiplier 3 of FFE for multiplication. Finally, the calculation results of each operation node of FFE are added and finally sent to DFE as the output decider for secondary judgment, thereby achieving area and power consumption optimization of the entire FFE circuit.

[0082] It should be noted that in the claims and description of this patent, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "including a" does not exclude the presence of other identical elements in the process, method, article or device that includes the element.

[0083] All documents mentioned in this application are incorporated herein by reference, just as if each document were incorporated herein by reference individually. It should also be understood that after reading the above teachings of this application, those skilled in the art may make various changes or modifications to this application, and that such equivalents also fall within the scope of the claims appended hereto.

Claims

1. A receiving-end equalization circuit with pre-determination for a high-speed serial interface chip, characterized in that: include: A plurality of forward nodes, a main node, and a plurality of backward nodes are sequentially connected, with delay units connected between adjacent nodes, wherein the forward node farthest from the main node receives the output value of the analog-to-digital converter; a plurality of multipliers, each multiplier being connected to each of the master node, the plurality of forward nodes, and the plurality of backward nodes; One or more backward pre-determiners, each backward pre-determiner being connected between each of several backward nodes far from the main node among the plurality of backward nodes and a corresponding multiplier; and A first adder is connected to output terminals of the plurality of multipliers.

2. The receiving end equalization circuit according to claim 1, characterized in that: Also includes: One or more forward pre-determiners, each forward pre-determiner is connected between each forward node of several forward nodes far away from the main node among the plurality of forward nodes and a corresponding multiplier.

3. The receiving end equalization circuit according to claim 2, characterized in that: The number of the backward pre-determiners is twice the number of the forward pre-determiners.

4. The receiving end equalization circuit according to claim 3, characterized in that: The receiving end equalization circuit includes: 9 forward nodes and 22 backward nodes, wherein the number of the backward pre-determiners is 6 and the number of the forward pre-determiners is 3.

5. The receiving end equalization circuit according to claim 2, characterized in that: The bit width of the data output by the backward pre-determinator and the forward pre-determinator is smaller than the bit width of the output value of the analog-to-digital converter.

6. The receiving end equalization circuit according to claim 5, characterized in that: The bit width of the output value of the analog-to-digital converter is 8 bits, the data bit width output by the backward pre-determinator and the forward pre-determinator is 3 bits, 4 bits or 5 bits, the coefficient bit width of the multiplier is 9 bits, and the bit width of the first adder is 22 bits.

7. The receiving-end equalizing circuit according to claim 2, wherein: The number of the backward pre-determiners and the number of the forward pre-determiners are determined by simulation testing of the relationship between them and the bit error rate.

8. The receiving end equalization circuit according to claim 1, characterized in that: The receiving end equalization circuit includes: 6 forward nodes and 25 backward nodes, wherein the number of the backward pre-determiners is 8.

9. The receiving end equalization circuit according to claim 1, characterized in that: Also includes: an output decider, wherein an input end of the output decider is connected to an output end of the first adder and decides data output by the first adder; a second adder, wherein an input terminal of the second adder is connected to an output terminal of the decision device and calculates an error value between the data output by the decision device and an ideal value; as well as An adaptive algorithm module receives the output value of the analog-to-digital converter and the error value output by the second adder respectively and calculates and outputs coefficients of each node.

10. The receiving end equalization circuit according to claim 1, characterized in that: The calculation formula of the output value of the first adder is as follows: in, The first adder The output value at time For the Moment The coefficient of the multiplier corresponding to each node, For the Moment The input value of the multiplier corresponding to the node, where , N is the number of the forward nodes, M is the number of the backward nodes; No. Moment The input value of the multiplier corresponding to the node The calculation formula is as follows: in, For the Moment The output value of the backward pre-determiner corresponding to the node, For the Moment The output value of the analog-to-digital converter corresponding to the node, Q is the number of the backward pre-determiners, where .

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