Trim control circuit for current integrating ramp DAC stabilization auxiliary circuit

Abstract

This application relates to trim control circuitry for current integrating ramp DAC stabilization auxiliary circuitry. A ramp generator includes an operational amplifier having an output for generating a ramp signal. An integrating current source is coupled to a first input of the operational amplifier, and a reference voltage is coupled to a second input of the operational amplifier. A feedback capacitor is coupled between the first input and the output of the operational amplifier. Monitoring circuitry is coupled to the first and second inputs of the operational amplifier to generate an output flag in response to a comparison of the first and second inputs. Trim control circuitry is configured to generate a trim signal in response to the output flag. An auxiliary current source is configured to conduct an auxiliary current from the output of the operational amplifier to ground in response to the trim signal generated by the trim control circuitry.

Description

Technical Field

[0001] This disclosure generally relates to image sensors, and specifically, but not exclusively, to a ramp generator in an image sensor. Background Technology

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, surveillance cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is expected that their functionality and performance metrics will be enhanced in as many ways as possible (e.g., resolution, power consumption, dynamic range) through device architecture design and image acquisition and processing. The technologies used to manufacture image sensors continue to advance rapidly. For example, the demand for higher resolution and lower power consumption has encouraged further miniaturization and integration of these devices.

[0003] A typical complementary metal-oxide-semiconductor (CMOS) image sensor operates in response to image light from an external scene incident on the sensor. The image sensor comprises an array of pixels having portions that absorb the incident image light and generate image charge upon absorption. The image charge generated by the pixel light can be measured as an analog output image signal on the bit lines that varies according to the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out as an analog signal from the bit lines and converted into a digital value to produce a digital image (i.e., image data) representing the external scene.

[0004] Analog-to-digital converters (ADCs) are commonly used in CMOS image sensors (CIS) to convert electrical charges into a digital representation of the charges. An ADC generates a digital representation of the charges based on a comparison between an image charge signal and a reference voltage signal. The reference voltage signal is typically a ramp signal provided by a ramp generator, and the comparison is usually performed by a comparator that provides an output that can be used with a counter to generate a digital representation of the image charges.

[0005] It should be understood that the ramp settling time or delay of the ramp signal generated by the ramp generator and received by the comparator can limit the maximum frame rate of the image sensor. Therefore, reducing the ramp settling time of the ramp signal received by the comparator can increase the maximum frame rate and thus the performance of the image sensor. Summary of the Invention

[0006] One aspect of this disclosure provides a ramp generator comprising: an operational amplifier having a first input, a second input, and an output for generating a ramp signal; an integrating current source coupled to the first input of the operational amplifier; a reference voltage coupled to the second input of the operational amplifier; a feedback capacitor coupled between the first input and the output of the operational amplifier; an auxiliary current source coupled between the output of the operational amplifier and ground; a monitoring circuit coupled to the first and second inputs of the operational amplifier, wherein the monitoring circuit is configured to generate an output mark in response to a comparison of the first and second inputs of the operational amplifier; and a trimming control circuit coupled to the auxiliary current source, wherein the trimming control circuit is configured to generate a trimming signal in response to the output mark generated by the monitoring circuit, wherein the auxiliary current source is configured to conduct auxiliary current from the output of the operational amplifier to ground in response to the trimming signal generated by the trimming control circuit.

[0007] Another aspect of this disclosure provides an imaging system comprising: a pixel array for receiving image light and generating an image charge voltage signal in response; and a readout circuit coupled to receive the image charge voltage signal from the pixel array and providing a digital representation of the image charge voltage signal in response, the readout circuit including a comparator for receiving the image charge voltage signal, comparing the image charge voltage signal with a ramp signal from a ramp generator, and providing the digital representation of the image charge voltage signal in response, wherein the ramp generator includes: an operational amplifier having a first input, a second input, and an output for generating the ramp signal; an integrating current source coupled to the first input of the operational amplifier; and a reference voltage coupled to the... The operational amplifier includes: a second input; a feedback capacitor coupled between the first input and the output of the operational amplifier; an auxiliary current source coupled between the output of the operational amplifier and ground; a monitoring circuit coupled to the first and second inputs of the operational amplifier, wherein the monitoring circuit is configured to generate an output mark in response to a comparison of the first and second inputs of the operational amplifier; and a trimming control circuit coupled to the auxiliary current source, wherein the trimming control circuit is configured to generate a trimming signal in response to the output mark generated by the monitoring circuit, wherein the auxiliary current source is configured to conduct auxiliary current from the output of the operational amplifier to ground in response to the trimming signal generated by the trimming control circuit. Attached Figure Description

[0008] The following figures illustrate non-limiting and non-exhaustive embodiments of the invention, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0009] Figure 1 An example of an imaging system comprising a readout circuit containing a ramp generator according to the teachings of the present invention is described, wherein the ramp generator has a ramp stabilization auxiliary circuit having a trimming control circuit.

[0010] Figure 2 An example of a schematic diagram of a current integration ramp generator with a low-power ramp stabilization auxiliary circuit according to the teachings of the present invention is shown.

[0011] Figure 3 This is a timing diagram illustrating a signal comprising a ramp signal generated by an example current integral ramp generator having a low-power ramp stabilization auxiliary circuit, according to the teachings of the present invention.

[0012] Figure 4 An example of a current integral ramp generator, illustrating a low-power ramp stabilization auxiliary circuit with a trimming control circuit, is shown in the present invention.

[0013] Figure 5 This is a timing diagram illustrating the signal containing the ramp signal generated by the instance current integral ramp generator, which includes a low-power ramp stabilization auxiliary circuit with instance trimming control circuitry.

[0014] Figure 6 An example of a schematic diagram of a current integral ramp generator, which includes another example of a low-power ramp stabilization auxiliary circuit with a trimming control circuit, according to the teachings of the present invention.

[0015] Figure 7 This is a timing diagram illustrating, in more detail, an example of a ramp signal generated by an example current integral ramp generator comprising an example current current integral ramp generator having an example trimming control circuit, according to the teachings of the present invention.

[0016] Figure 8 This is a flowchart illustrating an example of a process for modifying an example low-power ramp stabilization auxiliary circuit included in an example current integral ramp generator, according to the teachings of the present invention.

[0017] Throughout the various views illustrated, corresponding reference numerals indicate the corresponding components. Those skilled in the art will understand that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be enlarged relative to other elements to aid in understanding the various embodiments of the invention. Furthermore, common but well-known elements that are useful or necessary in commercially viable embodiments are generally not depicted to facilitate a more intuitive understanding of these various embodiments of the invention. Detailed Implementation

[0018] This document describes an example of an imaging system comprising a readout circuit with a current integral ramp generator having a low-power ramp stabilization auxiliary circuit with trimming control circuitry. In the following description, numerous specific details are set forth to provide a thorough understanding of the example. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more of these specific details or with other methods, components, materials, etc. In other examples, well-known structures, materials, or operations have not been shown or described in detail to avoid ambiguity regarding certain aspects.

[0019] Throughout this specification, the reference to "an example" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one embodiment of the invention. Therefore, the phrases "in one example" or "in one embodiment" appearing in various places throughout this specification do not necessarily refer to the same example. Furthermore, a particular feature, structure, or characteristic may be combined in one or more examples in any suitable manner.

[0020] For ease of description, spatially relative terms such as “below,” “under,” “above,” “under,” “above,” “top,” “bottom,” “left,” “right,” “center,” “middle,” etc., may be used herein to describe the relationship of one element or feature to another element(s), as illustrated in the figures. It will be understood that, in addition to the orientations depicted in the figures, the spatially relative terms are intended to also cover different orientations of the device during use or operation. For example, if the device in the figures is rotated or flipped, then an element described as “below,” “under,” or “below other elements or features” will be oriented “above other elements or features.” Thus, the exemplary terms “below” and “under” can cover both above and below orientations. The device may be oriented in other ways (rotated ninety degrees or otherwise) and the spatially relative descriptive terms used herein will be interpreted accordingly. Furthermore, it will be understood that when an element is referred to as “between two other elements,” it may be the only element between the two other elements, or there may be one or more intervening elements.

[0021] Throughout this specification, certain terms used refer to the field. These terms have their general meaning in the field of origin, unless specifically defined herein or otherwise clearly indicated by the context of their use. It should be noted that component names and symbols (e.g., Si for silicon) may be used interchangeably throughout this document; however, they have the same meaning.

[0022] As will be discussed, various examples of imaging systems incorporating readout circuitry with a current-integrating ramp generator having a low-power ramp-stabilizing auxiliary circuit with trimming control circuitry are described. In various examples, the ramp generator is a current-integrating ramp generator comprising an operational amplifier configured as an integrator with a feedback capacitor coupled between the input and output of the operational amplifier. An integrating current source is also coupled to the input of the operational amplifier. In one example, the low-power ramp-stabilizing auxiliary circuit includes an auxiliary current source coupled between the output of the current-integrating ramp generator and ground. In another example, the low-power ramp-stabilizing auxiliary circuit provides an auxiliary current from the output of the ramp generator to ground, the auxiliary current being turned on during a ramp event or ramp phase of the output ramp signal of the ramp generator. For the purposes of this disclosure, it should be understood that a ramp event of the output ramp signal is the time during which the ramp signal continuously decreases. In another example, it should be understood that a ramp event of the output ramp signal can also be considered as the time during which the ramp signal continuously increases. The output capacitor coupled to the output of the ramp generator discharges through an auxiliary current, which thus reduces the ramp settling time of the ramp signal caused by the load on the output of the ramp generator, thereby improving the maximum frame rate and image sensor performance. In various instances, the low-power stabilization auxiliary circuit is trimmed with a trimming control circuit, which can therefore adjust the auxiliary current provided by the low-power stabilization auxiliary circuit to accommodate changes in pressure, volume, temperature (PVT), and / or process variations according to the teachings of the invention.

[0023] To illustrate, Figure 1 An example of an imaging system 100 according to the teachings of the present invention, comprising readout circuitry with a ramp generator having ramp stabilization auxiliary circuitry having trimming control circuitry, is shown. As shown in the illustrated example, the imaging system 100 includes a pixel array 102, control circuitry 110, readout circuitry 106, and functional logic 108. In one example, the pixel array 102 is a two-dimensional (2D) array comprising a plurality of pixel circuits 104 (e.g., P1, P2, ..., Pn) arranged in rows (e.g., R1 to Ry) and columns (e.g., C1 to Cx) to acquire image data of people, places, objects, etc., which can then be used to render images of people, places, objects, etc.

[0024] In various embodiments, each pixel circuit 104 may include one or more photodiodes configured to generate image charge in response to incident light. The image charge generated in each photodiode is transferred to a floating diffuser included in each pixel circuit 104, the image charge is converted into an image signal, and then read out from each pixel circuit 104 by readout circuit 106 via column line 112. In various embodiments, readout circuit 106 may read out one line of image data at a time along readout column line 112 (illustrated), or may use various other techniques (not illustrated) to read out image data, such as simultaneous serial or fully parallel readout of all pixel circuits 104.

[0025] In various examples, the readout circuit 106 may include an amplifier, an analog-to-digital converter (ADC), or something else. In the depicted example, the ADC 118 includes a comparator circuit 116 coupled to receive an image signal from the pixel array 102 via the column bit line 112. In one example, the comparator circuit 116 may include a plurality of comparators coupled to receive the image signal via the bit line 112. In one example, each comparator included in the comparator circuit 116 is also coupled to receive a ramp signal 140 from the ramp generator 114, as shown. In one example, each comparator included in the comparator circuit 116 can be used to determine a digital representation of the image signal based on a comparison of the ramp signal 140 with the voltage level of the image signal received via the bit line 112 using a counter. As will be discussed in further detail below, in various examples, the ramp generator 114 is a current-integrating ramp generator. In various instances, the ramp settling time or delay of the ramp signal 140 generated by ramp generator 114 and received by comparator circuit 116 is reduced using a low-power stabilization auxiliary circuit to increase the maximum frame rate and thus improve the performance of imaging system 100. In various instances, the low-power stabilization auxiliary circuit is calibrated using a trimming control circuit, which can therefore adjust the auxiliary current provided by the low-power stabilization auxiliary circuit to adapt to changes in pressure, volume, temperature (PVT), and / or other conditions according to the teachings of the present invention.

[0026] In this example, the digital image data values ​​generated by the ADC 118 can then be received by the functional logic 108. The functional logic 108 can simply store the digital image data or even manipulate the digital image data by applying post-image effects (e.g., cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, or others).

[0027] In one example, control circuitry 104 is coupled to pixel array 102 to control the operation of multiple photodiodes within pixel array 102. For example, control circuitry 104 may generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal used to simultaneously activate all pixel circuits 104 within pixel array 102 to simultaneously capture their respective image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal, causing each row, column, or group of pixels to be sequentially activated during consecutive acquisition windows. In yet another example, image acquisition is synchronized with an illumination effect (e.g., flash).

[0028] In one example, the imaging system 100 may be included in a digital camera, mobile phone, laptop computer, or the like. Additionally, the imaging system 100 may be coupled to other hardware components, such as a processor (general purpose or other), memory elements, outputs (USB port, wireless transmitter, HDMI port, etc.), illumination / flash, electrical inputs (keyboard, touchscreen, touchpad, mouse, microphone, etc.), and / or a display. These other hardware components can deliver instructions to the imaging system 100, retrieve image data from the imaging system 100, or manipulate image data supplied by the imaging system 100.

[0029] Figure 2 An example of a schematic diagram of a current integration ramp generator with a low-power ramp stabilization auxiliary circuit according to the teachings of the present invention is shown. It should be understood that... Figure 2 The current integrating ramp generator with low-power ramp stabilization auxiliary circuit shown in the article can provide... Figure 1 The example of ramp generator 114 described above, and similarly named and numbered elements described above are similarly coupled and operated below.

[0030] like Figure 2 As shown, the current integrating ramp generator includes an operational amplifier 224. A first input (e.g., an inverting input) of the operational amplifier 224 is coupled to an integrating current source 230 to receive the integrating current I. INT 232. The second input (e.g., the non-inverting input) of operational amplifier 224 is coupled to receive a reference voltage V. REF 234. In the depicted example, the switch and capacitor 236 can be coupled to the non-inverting input of the operational amplifier 224 to adjust the reference voltage V at the non-inverting input of the operational amplifier 224. REF 224 is sampled and held. In the depicted example, the feedback capacitor C F 226 is coupled to the output of operational amplifier 224 and the inverting input of operational amplifier 224. Reset switch 228 is also coupled between the output of operational amplifier 224 and the inverting input of operational amplifier 224. Figure 2The example depicted shows the output capacitor C. OUT 238 is coupled between the output of operational amplifier 224 and ground. As shown in the illustrated example, auxiliary current source 240 is coupled between the output of operational amplifier 224 and ground. In the example, ramp switch 244 is coupled to auxiliary current source 240, such that ramp switch 244 and auxiliary current source 240 are coupled between the output of operational amplifier 224 and ground.

[0031] In operation, the auxiliary current source 240 is configured to supply auxiliary current I in response to the reset switch 228 being turned off. ASSIST 246 is conducted from the output of operational amplifier 224 to ground, which corresponds to the ramp voltage V. RAMP The ramp event that occurred in 220. In the described example, it is due to the ramp voltage V. RAMP During a ramp event occurring in 220, ramp switch 244 is also activated to transfer auxiliary current I during the ramp event. ASSIST 246 is conducted from the output of operational amplifier 224 to ground. Current I C 242 indicates that the output capacitor C OUT The discharge current of 238, and the current I IN 240 indicates that the value is attributed to the output capacitor C. OUT The discharge of 238 will be absorbed by the output of operational amplifier 224 without the auxiliary current source 240.

[0032] Specifically, the auxiliary current I ASSIST 246 is configured to operate at ramp voltage V RAMP During the ramp event in 220, the magnitude is approximately equal to that of the output capacitor C. OUT 238 discharge current I C 242. Therefore, according to the teachings of the present invention, the input current I that would normally be absorbed by the output of operational amplifier 224 is... IN 240 remains substantially zero, and operational amplifier 224 does not require restabilization. Therefore, according to the teachings of the present invention, the ramp voltage V... RAMP 220 is closer to an ideal ramp signal, with virtually no ramp settling time delay and a sharper bend at the onset of a ramp event.

[0033] Figure 3 This is a timing diagram illustrating a signal comprising a ramp signal generated by an example current integral ramp generator with a low-power ramp stabilization auxiliary circuit, according to the teachings of the present invention. It should be understood that... Figure 3 The signals illustrated in the timing diagram can be in Figure 2Examples of signals found in a current integrating ramp generator are depicted below, and similarly named and numbered components described above are similarly coupled and operated below. Specifically, the depicted examples show the ramp signal RAMP 344, the reset signal RESET 328, and the ramp voltage signal V. RAMP 320. Input current I IN 340. Capacitor current I C 342. Auxiliary current I ASSIST 346 and power line current I AVDD 348.

[0034] like Figure 3 The example depicted shows that the ramp voltage signal V is generated at a time T0 prior to the ramp event. RAMP 320 is initialized to voltage V CVDN At time T1, the ramp event begins, which is manifested as the ramp signal RAMP 344 transitioning high (e.g., "1") and the reset signal RESET 328 transitioning low (e.g., "0"). In this example, the ramp signal RAMP 344 transitioning high (e.g., "1") turns on the ramp switch 244, and the reset signal RESET 328 transitioning low (e.g., "0") turns off the reset switch 228. Figure 2 This is illustrated in the example described. Therefore, the ramp event occurs at time T1 in the ramp voltage signal V. RAMP Starting at 320, where the voltage slope is as shown. As will be discussed, in the auxiliary current I... ASSIST 346 is configured to be approximately equal to the capacitor current I. C 342 to make the output capacitor C OUT Under the condition of 238 discharge, the ramp voltage signal V RAMP 320 has a sharp bend at time T1 and begins a linear descent with virtually no ramp-up time delay, as indicated by an ideal ramp signal 384. It should be understood that without an auxiliary current I... ASSIST In the case of auxiliary current source 240 of 346, the current will be attributed to output capacitor C. OUT The discharge of 238 resulted in a non-ideal ramp signal 386.

[0035] Specifically, at time T1, when the ramp event or ramp phase occurs in the ramp voltage signal V RAMP At the beginning of 320, the integrating current I INT 332 via feedback capacitor C F 326, and the ramp voltage signal V RAMP The slope begins to drop from 320. At this point, the output capacitor C... OUT 338 requires capacitor current I C342 Discharge. This provides a current approximately equal to the capacitor current I. C The auxiliary current I with a value of 342 ASSIST In the case of auxiliary current source 240 of 246, the input current I absorbed by the output of operational amplifier 224 IN 340 remains substantially zero, which achieves the ideal ramp signal 384 at time T1, as shown. Therefore, it should be understood that at time T1, the auxiliary current I... ASSIST 346. Input current I IN 340 and ramp voltage signal V RAMP 320 can be expressed by the following equation:

[0036]

[0037] I IN (t)=0, (4)

[0038]

[0039] Regarding the auxiliary current I described in equation (3) ASSIST 346. Note that the output capacitor C... OUT The capacitance value of 338 may include the capacitance provided by the polysilicon capacitor and the gate-to-source capacitance of the source follower transistor coupled to the output of operational amplifier 224. Additionally, the feedback capacitor C... F The capacitance value of 226 may include the capacitance provided by the metal-oxide-semiconductor capacitor coupled between the inverting input and output of operational amplifier 224. Therefore, it should be understood that potential process variations should also be considered when adjusting the auxiliary current source 240.

[0040] In operation, it should be further understood that when the ramp signal RAMP 344 is configured to turn off during non-ramp events (e.g., at time T0) or before a ramp event at time T1, the auxiliary current I... ASSIST The additional power consumption of 346 is saved because ramp switch 244 is turned off during non-ramp events (e.g., at time T0). Furthermore, as... Figure 3 In addition to the above, it should also be understood that the power line current I... AVDD 348 remains substantially constant or unchanged during non-ramp events (e.g., at time T0) and during ramp events (e.g., at time T1) because the auxiliary current source is coupled between the output of operational amplifier 224 and ground, rather than between the power supply line (e.g., AVDD) and the output of operational amplifier 224.

[0041] Figure 4This illustration shows an example of a current integral ramp generator comprising a low-power ramp stabilization auxiliary circuit with a trimming control circuit, according to the teachings of the present invention. It should be understood that... Figure 4 The current integrating ramp generator with low-power ramp stabilization auxiliary circuit shown in the article can provide... Figure 1 This is another example of the ramp generator 114 described above, and similarly named and numbered elements described above are similarly coupled and operate below. It should be further understood that... Figure 4 The current integration ramp generator with low-power ramp stabilization auxiliary circuitry shown in the image is... Figure 2 The current integration ramp generators with low-power ramp stabilization auxiliary circuits shown in the article share many similarities.

[0042] For example, such as Figure 4 As shown, the current integrating ramp generator includes an operational amplifier 424. The first input (e.g., an inverting input) of the operational amplifier 424 is coupled to an integrating current source 430 to receive the integrating current I. INT 432. The second input (e.g., the non-inverting input) of operational amplifier 424 is coupled to receive a reference voltage V. REF 434. In the depicted example, the switch and capacitor 436 can be coupled to the non-inverting input of the operational amplifier 424 to adjust the reference voltage V at the non-inverting input of the operational amplifier 424. REF 424 performs sampling and holding. In the depicted example, the feedback capacitor C F 426 is coupled to the output of operational amplifier 424 and the inverting input of operational amplifier 424. Reset switch 428 is also coupled between the output of operational amplifier 424 and the inverting input of operational amplifier 424. Figure 4 The example depicted shows the output capacitor C. OUT 438 is coupled between the output of operational amplifier 424 and ground. As shown in the illustrated example, auxiliary current source 440 is coupled between the output of operational amplifier 424 and ground. In the example, ramp switch 444 is coupled to auxiliary current source 440, such that ramp switch 444 and auxiliary current source 440 are coupled between the output of operational amplifier 424 and ground.

[0043] In operation, the auxiliary current source 440 is configured to supply auxiliary current I in response to the reset switch 428 being turned off. ASSIST 446 is conducted from the output of operational amplifier 424 to ground, which corresponds to the ramp voltage V. RAMP The ramp event that occurred in 420. In the described example, it is due to the ramp voltage V. RAMP During a ramp event occurring in 420, ramp switch 444 is also activated to transfer auxiliary current I during the ramp event.ASSIST 446 is conducted from the output of operational amplifier 424 to ground. Current I C 442 indicates that the output capacitor C OUT The discharge current of 438, and the current I IN 440 indicates that the value is attributed to the output capacitor C. OUT The discharge of 438 will be absorbed by the output of operational amplifier 424 without the auxiliary current source 440.

[0044] Figure 4 The current integration ramp generator with low-power ramp stabilization auxiliary circuitry shown in the image is... Figure 2 Some differences between the current integration ramp generators with low-power ramp stabilization auxiliary circuits shown in the article are: Figure 4 The current integrating ramp generator with low-power ramp stabilization auxiliary circuitry shown also includes a monitoring circuit 450 and a trimming control circuit 460. Figure 4 In the example depicted, the auxiliary current source 440 is coupled to perform trimming in response to a trimming signal 462 received by the monitoring circuit 450 from the trimming control circuit 460, so as to adjust the ramp voltage V. RAMP During the ramp event in 420, the auxiliary current I will be... ASSIST 446 was adjusted to be roughly equal in value to the output capacitor C. OUT 438 discharge current I C 442. Therefore, according to the teachings of the present invention, the input current I that would normally be absorbed by the output of operational amplifier 424 is... IN 440 remains substantially zero, and operational amplifier 424 does not require restabilization. Therefore, according to the teachings of the present invention, the ramp voltage V... RAMP 420 is closer to an ideal ramp signal, which has virtually no settling time delay and a sharper bend at the start of a ramp event.

[0045] like Figure 4As shown in the example depicted, monitoring circuitry 450 is coupled to both the inverting and non-inverting inputs of operational amplifier 424. In this example, monitoring circuitry 450 includes comparator 452, which is configured to generate an output flag FLAG 454 in response to a comparison of the inverting and non-inverting inputs of operational amplifier 424. Trimming control circuitry 460 is coupled to monitoring circuitry 450 and auxiliary current source 440. In one example, comparator 452 is coupled to the inverting and non-inverting inputs of operational amplifier 424 via a first switch sw0 456 and a second switch sw1 458, as shown. In operation, trimming control circuitry 460 is configured to generate a trimming signal 462 in response to the output flag FLAG 454 generated by monitoring circuitry 450, the output flag FLAG 454 being generated by comparator 452 in response to a comparison of the inverting and non-inverting inputs of operational amplifier 424. Therefore, the auxiliary current source 440 is configured to adjust or regulate the auxiliary current I conducted from the output of the operational amplifier 424 to ground in response to the adjustment signal 462 generated by the adjustment control circuit 460. ASSIST 446.

[0046] like Figure 4 As shown in the example depicted, the trimming control circuit 460 includes a latch or flip-flop 464 having a clock input coupled to receive an output marker FLAG 454 from the monitoring circuit 450. In this example, the flip-flop 464 has a D input coupled to the Q bar (Qb) output of the flip-flop 464. In this example, the Qb output of the flip-flop 464 is a latch enable signal latch_en 466, which is coupled to be received at the write enable signal WR_EN input of the trimming memory 468 of the trimming control circuit 460.

[0047] In one example, the trimming memory of the trimming control circuit 460 may be implemented using a trimming register configured to store trimming code 470. In one example, trimming code 470 may be initialized to a preset code, which may then be incremented (e.g., "+1"), as shown, until the latch enable signal latch_en 466 toggles (e.g., 0 to 1 or 1 to 0) in response to an output flag FLAG 454 received from comparator 452 of monitoring circuit 450. In another example, it should be understood that the logic of the trimming circuit may be inverted such that trimming code 470 is decremented (e.g., "-1") or otherwise adjusted until the latch enable signal latch_en 466 toggles (e.g., 0 to 1 or 1 to 0) in response to a comparison of the inverting and non-inverting inputs of operational amplifier 424, receiving an output flag FLAG 454 from comparator 452 of monitoring circuit 450.

[0048] According to the teachings of the present invention, once the latch enable signal latch_en 466 has toggled (e.g., 0 to 1 or 1 to 0) in response to the toggling (e.g., 0 to 1 or 1 to 0) of the output flag FLAG 454 of comparator 452, trimming code 470 is set, and then said trimming code 470 is stored in trimming memory 468 and used to generate auxiliary current I. ASSIST At time 446, the auxiliary current source 440 is controlled or adjusted via adjustment signal 462.

[0049] Figure 5 This is a timing diagram illustrating a signal comprising a ramp signal generated by an instance current integral ramp generator including an instance current oscillation ramp generator having an instance trimming control circuit, according to the teachings of the present invention. It should be understood that... Figure 5 The signals illustrated in the timing diagram can be in Figure 4 Examples of signals found in the current integrating ramp generator are depicted below, and similarly named and numbered components described above are similarly coupled and operated below. Specifically, the depicted examples show the ramp signal RAMP 544, the reset signal RESET 528, the ramp voltage signal VRAMP 520, and the output flag signal FLAG 554.

[0050] like Figure 5 The example depicted shows that the ramp voltage signal V is generated at a time T0 prior to the ramp event. RAMP 520 is initialized to voltage V CVDN At time T1, the ramp event begins, which is manifested as the ramp signal RAMP 544 transitioning high (e.g., "1") and the reset signal RESET 528 transitioning low (e.g., "0"). In this example, the ramp signal RAMP 544 transitioning high (e.g., "1") turns on the ramp switch 444, and the reset signal RESET 528 transitioning low (e.g., "0") turns off the reset switch 428. Figure 4 This is illustrated in the example described. Therefore, the ramp event occurs at time T1 in the ramp voltage signal V. RAMP Starting from 520, the voltage slope is as shown.

[0051] In one example, when the ramp signal RAMP transitions to a high level (e.g., "1"), the first switch sw0 456 and the second switch sw1 458 are also turned on at time T1. Therefore, the monitoring circuit 450 begins monitoring the inverting and non-inverting inputs of the operational amplifier 424. At this time, assuming the write enable input WR_EN of the trimming memory 468 is enabled at time T1, the trimming code 470 increments from its initial value until the output flag FLAG 554 toggles from low to high (e.g., 0 to 1) at time T2. At time T2, the trimming code 470 is recorded or stored in the trimming memory 468. In various examples, according to the teachings of the invention, the recorded or stored trimming code 470 can be written back to the trimming memory 468 as a default value at a subsequent or different time.

[0052] Figure 6 This illustration shows an example of a current integral ramp generator comprising another example of a low-power ramp stabilization auxiliary circuit with a trimming control circuit, according to the teachings of the present invention. It should be understood that... Figure 6 The current integrating ramp generator with low-power ramp stabilization auxiliary circuit shown in the article can provide... Figure 1 This is another example of the ramp generator 114 described above, and similarly named and numbered elements described above are similarly coupled and operate below. It should be further understood that... Figure 6 The current integration ramp generator with low-power ramp stabilization auxiliary circuitry shown in the image is... Figure 4 The current integration ramp generators with low-power ramp stabilization auxiliary circuits shown in the article share many similarities.

[0053] For example, such as Figure 6 As shown, the current integrating ramp generator includes an operational amplifier 624. The first input (e.g., an inverting input) of the operational amplifier 624 is coupled to an integrating current source 630 to receive the integrating current I. INT 632. The second input (e.g., the non-inverting input) of operational amplifier 624 is coupled to receive a reference voltage V. REF 634. In the depicted example, the switch and capacitor 636 can be coupled to the non-inverting input of the operational amplifier 624 to adjust the reference voltage V at the non-inverting input of the operational amplifier 624. REF 624 performs sampling and holding. In the depicted example, the feedback capacitor C F 626 is coupled to the output of operational amplifier 624 and the inverting input of operational amplifier 624. Reset switch 628 is also coupled between the output of operational amplifier 624 and the inverting input of operational amplifier 624. Figure 6 The example depicted shows the output capacitor C. OUT638 is coupled between the output of operational amplifier 624 and ground. As shown in the illustrated example, auxiliary current source 640 is coupled between the output of operational amplifier 624 and ground. In the example, ramp switch 644 is coupled to auxiliary current source 640, such that ramp switch 644 and auxiliary current source 640 are coupled between the output of operational amplifier 624 and ground.

[0054] In operation, the auxiliary current source 640 is configured to supply auxiliary current I in response to the reset switch 628 being turned off. ASSIST 646 is conducted from the output of operational amplifier 624 to ground, which corresponds to the ramp voltage V. RAMP The ramp event that occurred in 620. In the described example, it is related to the ramp voltage V. RAMP During a ramp event occurring in 620, ramp switch 644 is also activated to transfer auxiliary current I during the ramp event. ASSIST The current I is conducted from the output of operational amplifier 624 to ground. C 642 indicates that the output capacitor C OUT The discharge current of 638, and the current I IN 640 indicates that the value is attributed to the output capacitor C. OUT The discharge of 438 will be absorbed by the output of operational amplifier 624 without the auxiliary current source 640.

[0055] Similar to Figure 4 The current integration ramp generator with low-power ramp stabilization auxiliary circuitry is shown in the image. Figure 6 The current integrating ramp generator with low-power ramp stabilization auxiliary circuitry shown also includes monitoring circuitry 650 coupled to the inverting and non-inverting inputs of operational amplifier 624. In one example, monitoring circuitry 650 includes comparator 652 configured to generate an output flag FLAG 654 in response to a comparison of the inverting and non-inverting inputs of operational amplifier 624. In one example, comparator 452 is coupled to the inverting and non-inverting inputs of operational amplifier 424 via a first switch sw0 456 and a second switch sw1 458, as shown. In various examples, the output flag FLAG 654 generated by monitoring circuitry 650 can be adjusted by a trimming control circuit (e.g., for example, ...). Figure 4 The trim control circuit 460 shown in the image receives and generates trim codes.

[0056] Figure 6 The current integration ramp generator with low-power ramp stabilization auxiliary circuitry shown in the image is... Figure 4 One of the differences between the current integration ramp generators with low-power ramp stabilization auxiliary circuits shown in the article is that... Figure 6The trimming control circuit 660 shown includes a trimming memory 668 configured to store or preload predetermined trimming code 670. In one example, trimming code 670 may be trimming code 470 previously generated by trimming control circuit 460 in response to output flag FLAG 454 generated by monitoring circuit 450. Thus, in various examples, trimming control circuit 660 may be implemented as a one-time programmable memory per die, comprising one or more current integral ramp generators with low-power ramp stabilization auxiliary circuitry, such as... Figure 6 As shown in the diagram. In various instances, the trimming control circuitry 660 may be internal or external to the die. In one instance, the trimming code 670 may therefore be integrated into the trimming memory 668 of the trimming control circuitry 660.

[0057] Figure 7 This is a timing diagram illustrating, in more detail, an example of a ramp signal generated by an example current integral ramp generator comprising an example current current integral ramp generator with an example trimming control circuit, according to the teachings of the present invention. It should be understood that... Figure 7 The example of ramp signal 720 illustrated in the timing diagram can be similar to that in Figure 4 An example or illustration of the ramp signal 420 found in the current integral ramp generator depicted in the figure. Figure 5 Examples of more detailed ramp signal 520 described above, and similarly named and numbered elements described above are similarly coupled and operated below.

[0058] like Figure 7 As illustrated in the example, before the ramp event begins at time T1, the ramp signal 720 is initialized at a certain voltage (e.g., approximately 2.1 volts). At time T1, the ramp event begins and the ramp signal 720 begins to ramp down, as shown. The ramp signal 786 after time T1 represents the ramp signal 720 during ramp events with no trimming or minimal trimming, provided by the auxiliary current source 440. Therefore, the ramp signal 786 is non-ideal, where the degradation is attributed to the current from the output capacitor C. OUT The capacitor current I of 438 C The discharge current of 442 is determined by current I. IN The ramp settling time delay caused by 440 is absorbed by the output of operational amplifier 224. It should be understood that when a non-ideal ramp signal 786 is present during a ramp event, output flag FLAG 454 has not yet toggled (e.g., FLAG = 0). When trimming circuit 460 increments trimming code 470 (e.g., "+1"), ramp signal 720... Figure 7 The improvement in the trim direction shown in the diagram continues until the output marker FLAG 454 flips (e.g., FLAG=0 to FLAG=1), as shown by the ideal ramp signal 784 during the ramp event shown. Figure 7The examples depicted also illustrate instances of ramp signal 720 during ramp events where the output flag FLAG 454 does not flip, resulting in over-trimming of ramp signal 720.

[0059] Figure 8 This is a flowchart illustrating an example of a process for modifying an example low-power ramp stabilization auxiliary circuit for an example current integral ramp generator according to the teachings of the present invention. It should be understood that... Figure 8 The process described in the example for adjusting the low-power ramp stabilization auxiliary circuit can illustrate... Figure 4 The current integration ramp generator described above is a trimming process, and similarly named and numbered components described above are similarly coupled and operated below.

[0060] like Figure 8 As shown in the example depicted, the process begins at processing block 872, where the trimming code is initialized (e.g., trim_code = 0x00) and the latch enable signal is initialized to a high value (e.g., latch_en = 1) to set the write enable input for the trimmed memory. In decision block 874, it is determined whether the output flag of the monitoring circuit has been toggled (e.g., is Flag = 1?).

[0061] If decision box 874 determines that the flag has been flipped, or Flag = 1, then in processing box 880 the trim code is latched or stored in the trim memory. Next, in processing box 882, the latch enable signal latch_en is set to 0, which disables write-enabled inputs to the trim memory, and processing ends.

[0062] In another instance, it should be understood that processing from processing box 882 may instead continue in processing box 876. In this instance, the trimming code is latched or stored in the trimming memory only the first time Flag=1 appears.

[0063] Return to reference Figure 8 In the example depicted, if decision box 874 determines that the flag has not been flipped, or Flag = 0, then in processing box 876 the trim code is incremented (e.g., trim_code = trim_code + 1). Next, in decision box 878, it is determined whether the trim code has been incremented to the maximum value (e.g., trim_code = 0xFF?).

[0064] If decision box 878 determines that the trim code has been incremented to the maximum value (e.g., trim_code = 0xFF), then the processing ends. If decision box 878 determines that the trim code has not yet been incremented to the maximum value (e.g., trim_code < 0xFF), then the processing loop returns to decision box 874.

[0065] It is not intended that the foregoing description of the illustrative examples of the invention (including the content described in the abstract) be exhaustive or limit the invention to the precise forms disclosed. Although specific examples of the invention have been described herein for illustrative purposes, those skilled in the art will recognize that various modifications are possible within the scope of the invention.

[0066] These modifications can be made to the invention based on the detailed description above. The terminology used in the appended claims should not be construed as limiting the invention to the specific instances disclosed in this specification. Rather, the scope of the invention is to be fully defined by the appended claims, which should be interpreted according to established principles of claim interpretation.

Claims

1. A ramp generator, comprising: An operational amplifier having a first input, a second input, and an output for generating a ramp signal; An integrating current source coupled to the first input of the operational amplifier; A reference voltage, which is coupled to the second input of the operational amplifier; A feedback capacitor is coupled between the first input and the output of the operational amplifier; An auxiliary current source is coupled between the output of the operational amplifier and ground. A monitoring circuit coupled to the first and second inputs of the operational amplifier, wherein the monitoring circuit is configured to generate an output flag in response to a comparison of the first and second inputs of the operational amplifier; and A trimming control circuit coupled to the auxiliary current source, wherein the trimming control circuit is configured to generate a trimming signal in response to the output flag generated by the monitoring circuit, wherein the auxiliary current source is configured to conduct auxiliary current from the output of the operational amplifier to ground in response to the trimming signal generated by the trimming control circuit.

2. The ramp generator of claim 1, wherein the trimming signal generated by the trimming control circuit includes trimming code configured to control the auxiliary current generated by the auxiliary current source.

3. The ramp generator of claim 2, wherein the trimming control circuitry includes a trimming memory configured to store the trimming code, wherein the trimming control circuitry is configured to generate the trimming signal in response to the trimming code stored in the trimming memory.

4. The ramp generator of claim 3, wherein the trimming control circuit is configured to adjust the trimming code stored in the trimming memory in response to the output flag generated by the monitoring circuit having a first value, wherein the trimming control circuit is configured not to further adjust the trimming code stored in the trimming memory in response to the output flag generated by the monitoring circuit having a second value.

5. The ramp generator of claim 4, wherein the trimming control circuitry further comprises a flip-flop having a clock input coupled to receive the output flag generated by the monitoring circuitry, wherein the output of the flip-flop is configured to generate a latch enable flag coupled to be received by the trimming memory, wherein the trimming control circuitry is configured to respond to the latch enable flag generated by the flip-flop without further adjusting the trimming code stored in the trimming memory.

6. The ramp generator of claim 3, wherein the trimming code stored in the trimming memory is a previously generated trimming code determined in response to the output flag generated by the monitoring circuit.

7. The ramp generator of claim 1, further comprising a reset switch coupled between the first input and the output of the operational amplifier, wherein the reset switch is configured to turn on to reset the ramp generator, wherein a ramp event is configured to generate in the ramp signal at the output of the operational amplifier in response to the reset switch being turned off, wherein the auxiliary current source is configured to conduct the auxiliary current from the output of the operational amplifier to ground in response to the reset switch being turned off.

8. The ramp generator of claim 1, further comprising a reference capacitor coupled between the second input of the operational amplifier and ground.

9. The ramp generator of claim 7, further comprising an output capacitor coupled between the output of the operational amplifier and ground.

10. The ramp generator of claim 9, wherein the auxiliary current is substantially equal to the integral current conducted through the integral current source multiplied by the ratio of the capacitance of the output capacitor to the capacitance of the feedback capacitor.

11. The ramp generator of claim 9, wherein the auxiliary current conducted through the auxiliary current source is substantially equal to the discharge current from the output capacitor during the ramp event generated in the ramp signal at the output of the operational amplifier in response to the reset switch being turned off.

12. The ramp generator of claim 7, wherein the auxiliary current is zero when the reset switch is configured to turn on to reset the ramp generator.

13. The ramp generator of claim 12, further comprising an auxiliary current switch coupled to the auxiliary current source, wherein the auxiliary current switch is configured to be turned off when the reset switch is configured to be turned on, and wherein the auxiliary current switch is configured to be turned on when the reset switch is configured to be turned off.

14. An imaging system comprising: A pixel array that receives image light and generates an image charge voltage signal in response; and A readout circuit, coupled to receive the image charge voltage signal from the pixel array and providing a digital representation of the image charge voltage signal in response, the readout circuit including a comparator to receive the image charge voltage signal, compare the image charge voltage signal with a ramp signal from a ramp generator, and provide the digital representation of the image charge voltage signal in response, wherein the ramp generator includes: An operational amplifier having a first input, a second input, and an output for generating a ramp signal; An integrating current source coupled to the first input of the operational amplifier; A reference voltage, which is coupled to the second input of the operational amplifier; A feedback capacitor is coupled between the first input and the output of the operational amplifier; An auxiliary current source is coupled between the output of the operational amplifier and ground. A monitoring circuit coupled to the first and second inputs of the operational amplifier, wherein the monitoring circuit is configured to generate an output flag in response to a comparison of the first and second inputs of the operational amplifier; and A trimming control circuit coupled to the auxiliary current source, wherein the trimming control circuit is configured to generate a trimming signal in response to the output flag generated by the monitoring circuit, wherein the auxiliary current source is configured to conduct auxiliary current from the output of the operational amplifier to ground in response to the trimming signal generated by the trimming control circuit.

15. The imaging system of claim 14, wherein the trimming signal generated by the trimming control circuit includes trimming code configured to control the auxiliary current generated by the auxiliary current source.

16. The imaging system of claim 15, wherein the trimming control circuitry includes a trimming memory configured to store the trimming code, wherein the trimming control circuitry is configured to generate the trimming signal in response to the trimming code stored in the trimming memory.

17. The imaging system of claim 16, wherein the trimming control circuit is configured to adjust the trimming code stored in the trimming memory in response to the output marker generated by the monitoring circuit having a first value, wherein the trimming control circuit is configured not to further adjust the trimming code stored in the trimming memory in response to the output marker generated by the monitoring circuit having a second value.

18. The imaging system of claim 17, wherein the trimming control circuitry further comprises a flip-flop having a clock input coupled to receive the output flag generated by the monitoring circuitry, wherein the output of the flip-flop is configured to generate a latch enable flag coupled to be received by the trimming memory, wherein the trimming control circuitry is configured to respond to the latch enable flag generated by the flip-flop without further adjusting the trimming code stored in the trimming memory.

19. The imaging system of claim 16, wherein the trimming code stored in the trimming memory is a previously generated trimming code determined in response to the output flag generated by the monitoring circuit.

20. The imaging system of claim 14, wherein the ramp generator further includes a reset switch coupled between the first input and the output of the operational amplifier, wherein the reset switch is configured to turn on to reset the ramp generator, wherein a ramp event is configured to generate in the ramp signal at the output of the operational amplifier in response to the reset switch being turned off, wherein the auxiliary current source is configured to conduct the auxiliary current from the output of the operational amplifier to ground in response to the reset switch being turned off.

21. The imaging system of claim 14, wherein the ramp generator further comprises a reference capacitor coupled between the second input of the operational amplifier and ground.

22. The imaging system of claim 20, wherein the ramp generator further comprises an output capacitor coupled between the output of the operational amplifier and ground.

23. The imaging system of claim 22, wherein the auxiliary current is substantially equal to the integral current conducted through the integral current source multiplied by the ratio of the capacitance of the output capacitor to the capacitance of the feedback capacitor.

24. The imaging system of claim 22, wherein the auxiliary current conducted through the auxiliary current source is substantially equal to the discharge current from the output capacitor during the ramp event generated in the ramp signal at the output of the operational amplifier in response to the reset switch being turned off.

25. The imaging system of claim 20, wherein the auxiliary current is zero when the reset switch is configured to turn on to reset the ramp generator.

26. The imaging system of claim 25, wherein the ramp generator further includes an auxiliary current switch coupled to the auxiliary current source, wherein the auxiliary current switch is configured to be turned off when the reset switch is configured to be turned on, and wherein the auxiliary current switch is configured to be turned on when the reset switch is configured to be turned off.

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