Hall chip calibration structure, method, system, device and hall chip

Abstract

This invention provides a Hall chip calibration structure, method, system, apparatus, and Hall chip, belonging to the field of chip technology. The Hall chip calibration structure includes: at least one calibration Hall disk, the shape of which is identical to the Hall disk used for functional implementation in the Hall chip to be calibrated; the calibration Hall disk is provided with an input terminal and an output terminal, the input terminal of which is connected to the output terminal of an external excitation, and the output terminal of which is used to output a Hall voltage. Compared with the prior art that uses circuits or modules for calibration, this significantly reduces calibration errors and improves the accuracy of calibration results.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and more specifically to a Hall chip calibration structure, a Hall chip calibration method, a Hall chip calibration device, a Hall chip calibration system, a Hall chip, a machine-readable storage medium, and a processor. Background Technology

[0002] Hall effect chips utilize Hall effect semiconductors. The Hall effect refers to the physical phenomenon of the transverse potential difference when a magnetic field is applied to charge carriers in a current-carrying semiconductor and a metallic conductor. Common Hall effect chips include Hall current sensors.

[0003] When calibrating existing Hall effect sensors, most calibration devices are built outside the Hall effect sensor. For example, the calibration device includes a calibration winding, a zero-detection coil, a calibration current source, and an excitation current detector. The two ends of the excitation current detector are connected to the excitation current detector so that the excitation current detector can measure the current of the excitation current detector. The excitation current detector adjusts the output current of the calibration current source according to the measured current of the excitation current detector, which can perform online zero-point calibration of the Hall current sensor.

[0004] This method of calibration by building a calibration device outside the Hall chip is prone to errors because the calibration device is generally composed of circuits or modules, resulting in inaccurate calibration. Summary of the Invention

[0005] The purpose of this invention is to provide a Hall chip calibration structure, a Hall chip calibration method, a Hall chip calibration device, a Hall chip calibration system, a Hall chip, a machine-readable storage medium, and a processor. This Hall chip calibration structure can reduce calibration errors and improve the accuracy of calibration results.

[0006] To achieve the above objectives, a first aspect of this application provides a Hall chip calibration structure, comprising: at least one calibration Hall disk, the shape of which is the same as that of the Hall disk used for functional implementation in the Hall chip to be calibrated; the calibration Hall disk is provided with an input terminal and an output terminal, the input terminal of which is connected to the output terminal of an external excitation, and the output terminal of which is used to output a Hall voltage.

[0007] In this embodiment, the Hall chip calibration structure is disposed inside the Hall chip to be calibrated.

[0008] In this embodiment of the application, the verification Hall disk is connected to multiple PADs, which serve as the input and output terminals of the verification Hall disk, respectively.

[0009] In the embodiments of this application, the shape of the verification Hall disk includes rectangle, square, cross, and octagon.

[0010] In this embodiment, there is a proportional relationship between the size of the calibration Hall disk and the size of the Hall disk used for functional implementation in the Hall chip to be calibrated.

[0011] In the embodiments of this application, there are multiple verification Hall disks, and the dimensions of each verification Hall disk may be the same or different.

[0012] In this embodiment of the application, the shape of the verification Hall disk and the shape of the Hall disk used for functional implementation in the Hall chip to be calibrated are both rectangular; wherein, the width of the verification Hall disk and the width of the Hall disk used for functional implementation in the Hall chip to be calibrated are the same, and the length of the verification Hall disk and the length of the Hall disk used for functional implementation in the Hall chip to be calibrated are proportional.

[0013] In this embodiment of the application, there are multiple verification Hall disks, and each verification Hall disk has a different length.

[0014] A second aspect of this application provides a Hall effect chip, including a Hall disk chip, wherein the Hall disk chip includes a Hall disk structure for functional implementation and the aforementioned Hall effect chip calibration structure.

[0015] In this embodiment, a conditioning circuit chip is also included, the input terminal of which is connected to the output terminal of the Hall disk chip.

[0016] A third aspect of this application provides a Hall chip calibration system, characterized in that it includes a conditioning circuit chip and the aforementioned Hall chip, wherein the output terminal of the Hall chip is connected to the input terminal of the conditioning circuit chip, and the input terminal of the Hall chip is connected to the output terminal of an external excitation.

[0017] A fourth aspect of this application provides a Hall chip calibration method applied to the aforementioned Hall chip calibration structure, comprising:

[0018] When an excitation is applied to the Hall chip to be calibrated and the Hall chip calibration structure, the voltage values ​​of the Hall chip to be calibrated and the Hall chip calibration structure are obtained respectively.

[0019] The calibration value is obtained based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure.

[0020] In this embodiment, the calibration value includes a zero bias calibration value; the applied excitation is an applied electrical excitation.

[0021] The process of obtaining the calibration value based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure includes:

[0022] The zero bias is calculated based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure to obtain the zero bias calibration value.

[0023] In this embodiment of the application, the calibration value includes a temperature drift calibration value;

[0024] The process of obtaining the calibration value based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure includes:

[0025] Obtain the zero bias calibration value;

[0026] The ideal Hall voltage output ratio is determined based on the shape of the Hall disk in the Hall chip calibration structure and the shape of the Hall disk in the Hall chip to be calibrated.

[0027] Based on the ideal Hall voltage output ratio, the voltage value of the Hall chip to be calibrated, the voltage value of the Hall chip calibration structure, and the zero bias calibration value, the temperature drift calibration value is determined.

[0028] The fifth aspect of this application provides a Hall chip calibration device, characterized in that, applied to the aforementioned Hall chip calibration structure, it comprises:

[0029] The acquisition module is used to acquire the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure respectively when an excitation is applied to the Hall chip to be calibrated and the Hall chip calibration structure.

[0030] The calibration module is used to obtain a calibration value based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure.

[0031] In this embodiment, the calibration value includes a zero bias calibration value; the applied excitation is an applied electrical excitation.

[0032] The calibration module includes:

[0033] The zero-bias calibration unit is used to calculate the zero bias based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure, and obtain the zero-bias calibration value.

[0034] In this embodiment of the application, the calibration value includes a temperature drift calibration value;

[0035] The calibration module includes:

[0036] Zero bias acquisition unit, used to acquire zero bias calibration value;

[0037] The ratio determination unit is used to determine the ideal Hall voltage output ratio of each verification Hall disk based on the shape of the verification Hall disk in the Hall chip calibration structure and the shape of the Hall disk in the Hall chip to be calibrated.

[0038] The calculation unit is used to determine the temperature drift calibration value based on the ideal Hall voltage output ratio of each calibration Hall disk, the voltage value of the Hall chip to be calibrated, the voltage value of the Hall chip calibration structure, and the zero bias calibration value.

[0039] The sixth aspect of this application provides a processor configured to perform the Hall chip calibration method described above.

[0040] A seventh aspect of this application provides a machine-readable storage medium storing instructions that, when executed by a processor, configure the processor to perform the Hall chip calibration method described above.

[0041] The above technical solution, by setting a calibration Hall disk, since the shape of the calibration Hall disk is the same as that of the Hall disk used for function implementation in the Hall chip to be calibrated, the principle of calibration using the calibration Hall disk is the same as the principle of operation of the Hall chip to be calibrated. Both are based on the Hall effect to obtain the output result. Compared with the existing technology of using circuits or modules for calibration, this greatly reduces calibration error and improves the accuracy of calibration results.

[0042] Other features and advantages of the embodiments of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0043] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:

[0044] Figure 1 A schematic diagram of a Hall chip calibration structure according to an embodiment of this application is shown.

[0045] Figure 2 A schematic diagram of a Hall disk design including calibration according to an embodiment of this application is shown.

[0046] Figure 3 A schematic diagram illustrating the composition of a Hall chip according to an embodiment of this application is shown.

[0047] Figure 4 A schematic diagram of the Hall effect according to an embodiment of this application is shown;

[0048] Figure 5 A schematic diagram of a Hall chip calibration system according to an embodiment of this application is shown.

[0049] Figure 6 The illustration shows a schematic flowchart of a Hall chip calibration method according to an embodiment of this application;

[0050] Figure 7 This schematic diagram illustrates a structural block diagram of a Hall chip calibration device according to an embodiment of this application;

[0051] Figure 8 The diagram illustrates the internal structure of a computer device according to an embodiment of this application.

[0052] Explanation of reference numerals in the attached figures

[0053] 1-Hall disk calibration; 2-PAD; 410-Acquisition module; 420-Calibration module; A01-Processor; A02-Network interface; A03-Internal memory; A04-Display screen; A05-Input device; A06-Non-volatile storage medium; B01-Operating system; B02-Computer program. Detailed Implementation

[0054] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the scope of the present invention.

[0055] Please refer to Figure 1 and Figure 2 , Figure 1 A schematic diagram of a Hall chip calibration structure according to an embodiment of this application is shown. Please refer to... Figure 2 , Figure 2 A schematic diagram of a Hall disk design including calibration according to an embodiment of this application is shown. This embodiment provides a Hall chip calibration structure, including: at least one calibration Hall disk 1, the shape of which is the same as the shape of the Hall disk used for functional implementation in the Hall chip to be calibrated; the calibration Hall disk 1 is provided with an input terminal and an output terminal, the input terminal of the calibration Hall disk 1 is connected to the output terminal of an external excitation, and the output terminal of the calibration Hall disk 1 is used to output a Hall voltage. The external excitation can be a voltage / current excitation.

[0056] Please refer to Figure 4 , Figure 4 A schematic diagram of the Hall effect according to an embodiment of this application is shown, where I represents current, B represents magnetic field, and U represents magnetic field. H The Hall effect is based on the Hall effect principle. When a magnetic field is applied to a current-carrying semiconductor material, a voltage is generated at the other two poles of the semiconductor material due to the different Lorentz forces exerted by the magnetic field on electrons and holes in the semiconductor. This voltage is called the Hall voltage. Since the electromotive force is proportional to the input current and the magnitude of the applied magnetic field, the input current or the applied magnetic field can be measured by measuring the electromotive force.

[0057] In this embodiment, during calibration, external excitation is simultaneously input to both the calibration Hall disk 1 and the Hall chip to be calibrated. The calibration result is obtained based on the outputs of the calibration Hall disk 1 and the Hall chip to be calibrated. The aforementioned calibration Hall disk 1 constitutes the calibration region, and the calibration Hall disk 1 within this calibration region is the Hall effect region. This region is used for calibration, and the Hall effect region of the calibration region can be an array of different numbers, such as 1, 2, 3, etc. The Hall effect region can be made of various semiconductor materials; for example, the Hall effect region can be lightly doped with boron ions.

[0058] In the above implementation process, since the shape of the verification Hall disk 1 is the same as that of the Hall disk used for function implementation in the Hall chip to be calibrated, the principle of using the verification Hall disk 1 for calibration is the same as the principle of the Hall chip to be calibrated when it works. Both are based on the Hall effect to obtain the output result. Compared with the existing technology of using circuits or modules for calibration, this greatly reduces the calibration error and improves the accuracy of the calibration result.

[0059] It should be noted that the Hall chip calibration structure described above can be located inside the Hall chip to be calibrated or outside the Hall chip to be calibrated.

[0060] In some embodiments, to further improve the accuracy of the calibration results, the Hall chip calibration structure is disposed inside the Hall chip to be calibrated.

[0061] In this embodiment, the Hall chip calibration structure can be manufactured inside the Hall disk when the Hall chip to be calibrated is manufactured for functional implementation. This allows the Hall chip calibration structure to be built in advance, enabling the creation of a calibration region structure inside the Hall disk chip for Hall voltage calibration.

[0062] In the above implementation process, by setting a Hall chip calibration structure inside the Hall chip to be calibrated, calibration can be performed inside the Hall chip, including zero bias and temperature drift calibration. This reduces the complexity of the calibration device, enhances the performance of the Hall chip, and further improves the accuracy of the calibration results. Simultaneously, it significantly reduces the need for calibration devices, simplifies calibration, and lowers the cost of chip design.

[0063] In some embodiments, in order to facilitate the verification of the connection between the Hall disk 1 and the external excitation and the output voltage, the verification Hall disk 1 is connected to a plurality of terminals (PADs), and the plurality of PADs 2 serve as the input and output terminals of the verification Hall disk 1, respectively.

[0064] In this embodiment, the verification Hall disk 1 is connected to each PAD2 via leads. Multiple PAD2s can be used for output, and the specific number can be configured according to actual needs. The PAD2s also include grounding PAD2s. For example, for a rectangular verification Hall disk 1, one PAD2 is connected to the wider side of the rectangle as an input terminal, connected to the external excitation; another PAD2 is connected to the wider side of the other side of the rectangle as a ground terminal; and two PAD2s are connected to the longer sides of the rectangle as output terminals. By setting multiple PAD2s, it is convenient to connect the verification Hall disk 1 to the external excitation and to control the output voltage.

[0065] In some embodiments, there is a proportional relationship between the size of the calibration Hall disk 1 and the size of the Hall disk used for functional implementation in the Hall chip to be calibrated.

[0066] In this embodiment, for example, the shape of the Hall disk 1 for verification and the shape of the Hall disk in the Hall chip to be calibrated are both rectangular, with a size ratio of 1:2.

[0067] By setting a proportional relationship between the sizes of the Hall effect sensors, the output voltage under ideal conditions is also proportional, which facilitates the rapid calculation of calibration results.

[0068] In some embodiments, there are multiple verification Hall disks 1, each with a different size. The multiple verification Hall disks form a Hall effect array in the calibration region, and the geometric dimensions of the verification Hall disks 1 in the calibration region are related to each other, including but not limited to equal widths and halved lengths.

[0069] By setting different sizes of calibration Hall plates 1, the output voltage under various conditions can be collected to obtain more accurate calibration results and further improve the accuracy of calibration.

[0070] In some embodiments, the shape of the verification Hall disk 1 includes rectangle, square, cross, octagon, etc.

[0071] In this embodiment, the shape of the calibration Hall disk 1 is the same as that of the Hall disk in the Hall chip to be calibrated. It can be rectangular, square, cross-shaped, octagonal, etc., to suit different chips.

[0072] In some embodiments, there are multiple calibration Hall disks, and the dimensions of each calibration Hall disk may be the same or different. By setting multiple calibration Hall disks, multiple output Hall voltages can be obtained during calibration, thereby providing multiple data references for the calibration results and facilitating the obtaining of more accurate calibration results.

[0073] In some embodiments, the shape of the verification Hall disk 1 and the shape of the Hall disk used for functional implementation in the Hall chip to be calibrated are both rectangular; wherein, the width of the verification Hall disk 1 and the width of the Hall disk used for functional implementation in the Hall chip to be calibrated are the same, and the length of the verification Hall disk 1 and the length of the Hall disk used for functional implementation in the Hall chip to be calibrated are proportional.

[0074] There are multiple verification Hall disks 1, and each verification Hall disk 1 has a different length.

[0075] In this embodiment, for Hall effect disks with a rectangular shape, the width can be set to be the same, but the lengths can be different, which facilitates calculation. When there are multiple verification Hall effect disks 1, the lengths of each verification Hall effect disk 1 are different. For example, if there are two verification Hall effect disks 1, both rectangular in shape and with the same width, the length of one verification Hall effect disk 1 is half the length of the other. The length of each verification Hall effect disk 1 includes, but is not limited to, being greater than or less than the length of the Hall effect region in the Hall effect chip to be calibrated.

[0076] By keeping the width of the rectangular calibration Hall disk 1 constant and only changing its length, the calibration results can be calculated quickly.

[0077] For example, taking the Hall chip to be calibrated as a Hall sensor, such as... Figure 1 As shown, this chip is mainly divided into two parts: a conventional sensing area and a calibration area obtained using the Hall chip calibration structure in this embodiment. The Hall effect area of ​​the Hall sensor is rectangular and lightly doped with boron ions. The left PAD2 of the Hall effect area is connected to an external voltage / current excitation, the right PAD2 is grounded, and the upper and lower PAD2s output Hall voltages. Correspondingly, the Hall effect area of ​​the calibration area is also rectangular. In this example, two calibration Hall disks 1 are set, meaning the two Hall effect areas of the calibration area are connected to the voltage / current excitation at the top, grounded at the bottom, and the left and right PAD2s output Hall voltages. The width w of the three Hall effect areas in this example must be consistent, while the lengths of the Hall effect areas are different: the length of the Hall effect area in the Hall sensing area is L, while the lengths of the Hall effect areas in the calibration areas are L / 2 and L / 4, respectively.

[0078] Please refer to Figure 3 , Figure 3 A schematic diagram illustrating the composition of a Hall chip according to an embodiment of this application is provided. This embodiment also provides a Hall chip, including a Hall disk chip, which comprises a Hall disk structure for functional implementation and the aforementioned Hall chip calibration structure. The Hall chip calibration structure is used to verify the aforementioned Hall disk structure, including zero-bias verification and temperature drift verification.

[0079] In this embodiment, a Hall disk chip refers to a chip containing a Hall disk, such as a Hall sensor. By setting a Hall chip calibration structure in the Hall chip, calibration can be performed inside the Hall disk chip, thereby enhancing the chip's performance.

[0080] In some embodiments, a conditioning circuit chip is further included, the input terminal of which is connected to the output terminal of the Hall disk chip. In this embodiment, the conditioning circuit chip can be an application-specific integrated circuit (ASIC) chip, and the Hall output voltage of the calibration area is connected to the ASIC chip for processing to obtain the calibration result, thereby realizing the calibration function.

[0081] By setting a conditioning circuit chip in the Hall chip, during calibration, the Hall disk outputs the Hall voltage to the conditioning circuit chip for calculation, so that the calibration calculation process is carried out inside the chip. This allows for automatic calibration within the Hall chip, making it convenient and quick to obtain calibration results.

[0082] Please refer to Figure 5 , Figure 5 A schematic diagram of a Hall chip calibration system according to an embodiment of this application is shown. This embodiment also provides a Hall chip calibration system, including a conditioning circuit chip and the Hall chip, wherein the output terminal of the Hall chip is connected to the input terminal of the conditioning circuit chip, and the input terminal of the Hall chip is connected to the output terminal of an external excitation.

[0083] In this embodiment, the conditioning circuit chip is used to calculate the calibration result based on the Hall output voltage. The Hall chip includes only a Hall disk chip, that is, only the Hall disk structure for functional implementation and the aforementioned Hall chip calibration structure. To automatically calculate the calibration result, the output terminal of the Hall chip can be connected to the conditioning circuit chip. This Hall chip calibration system only requires connecting a conditioning circuit chip outside the Hall chip, making the calibration system simpler and easier to set up. Simultaneously, the Hall chip calibration structure within the Hall disk chip can reduce calibration errors and improve the accuracy of the calibration results.

[0084] This embodiment also provides a Hall chip calibration method, please refer to... Figure 6 , Figure 6 The schematic diagram illustrates a flow chart of a Hall chip calibration method according to an embodiment of this application. This Hall chip calibration method is applied to the aforementioned Hall chip calibration structure and includes the following steps:

[0085] Step 210: While applying excitation to the Hall chip to be calibrated and the Hall chip calibration structure, obtain the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure, respectively.

[0086] Step 220: Obtain the calibration value based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure.

[0087] In this embodiment, during Hall chip calibration, excitation is applied simultaneously to both the Hall chip to be calibrated and the Hall chip calibration structure. Specifically, electrical excitation, magnetic field, etc., can be applied as needed. Different excitations can be applied for different types of calibration, including calibration of zero bias and calibration of temperature drift. Based on the output voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure, the corresponding calibration value can be calculated. Since the shape of the verification Hall disk 1 is the same as the shape of the Hall disk used for functional implementation in the Hall chip to be calibrated, the principle of calibration using the verification Hall disk 1 is the same as the principle of operation of the Hall chip to be calibrated, both based on the Hall effect to obtain the output result. Therefore, calculating the calibration value based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure can greatly reduce calibration errors and improve the accuracy of the calibration results.

[0088] In some embodiments, the calibration value includes a zero-bias calibration value; the applied excitation is an applied electrical excitation;

[0089] The step of obtaining a calibration value based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure includes: calculating zero bias based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure to obtain a zero bias calibration value.

[0090] In this embodiment, zero bias calibration is performed when the external magnetic field bias is zero and only electrical excitation is applied. Ideally, the output Hall voltage should be zero. However, in actual use, factors such as process technology, external packaging, and external temperature environment can cause the Hall chip output to be non-zero. In this case, the zero bias calibration value can be calculated by referring to the zero bias voltage of the calibration structure and combining it with the zero bias voltage of the Hall chip to be calibrated. For example, for a Hall sensor, the zero bias of the Hall sensor can be calculated by referring to the zero bias voltage output of the calibration structure and combining it with the zero bias voltage of the sensing area through the ASIC conditioning circuit. Since the shape of the calibration Hall disk 1 is the same as the shape of the Hall disk used for functional implementation in the Hall chip to be calibrated, the principle of calibration using the calibration Hall disk 1 is the same as the principle of the Hall chip to be calibrated during operation. Both are based on the Hall effect to obtain the output result. Therefore, the obtained zero bias calibration value is more accurate.

[0091] In some embodiments, the calibration value includes a temperature drift calibration value;

[0092] The process of obtaining a calibration value based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure includes the following steps:

[0093] First, obtain the zero bias calibration value;

[0094] Then, based on the shape of the calibration Hall disk 1 in the Hall chip calibration structure and the shape of the Hall disk in the Hall chip to be calibrated, the ideal Hall voltage output ratio is determined.

[0095] Finally, based on the ideal Hall voltage output ratio, the voltage value of the Hall chip to be calibrated, the voltage value of the Hall chip calibration structure, and the zero bias calibration value, the temperature drift calibration value is determined.

[0096] In this embodiment, the zero-bias calibration value can be obtained in advance or through the aforementioned zero-bias calibration process. Since the temperature drift of the Hall chip mainly originates from the temperature effects of the materials and devices themselves under external temperature conditions, the Hall voltage temperature drift of the Hall chip to be calibrated can be corrected based on the Hall voltage output within the calibration area as a reference. Specifically:

[0097] Taking a Hall chip as a Hall current sensor as an example, when under constant voltage bias, the output Hall voltage is proportional to the aspect ratio of the Hall effect region, which can be expressed by the following formula. In the formula V h Hall voltage, μ n Let G be the mobility, G be the geometric factor, and B be the mobility. z V represents the applied magnetic field, V represents the applied voltage, w represents the width of the Hall effect region, and l represents the length of the Hall effect region. Since the calibration region and the sensing region have different aspect ratios, different Hall voltage values ​​will be output in the Hall effect regions of the calibration region and the sensing region. At different temperatures, the total voltage output of the sensing region can be defined as V1(T) (length L), and the total voltage output of the calibration region can be defined as V2(T) (length L / 2) and V3(T) (length L / 4), respectively. The ideal Hall voltage outputs are Vh_1 (sensing region, length L), Vh_2 (calibration region, length L / 2), and Vh_3 (calibration region, length L / 3), respectively; V0(T) is the zero-bias voltage, i.e., the zero-bias calibration value, and V(T) is the temperature drift output voltage, i.e., the temperature drift calibration value.

[0098] Taking the Hall effect region as a rectangle as an example, the relationship between the total voltage, zero bias voltage, and ideal Hall voltage can be expressed by the following set of equations:

[0099] V1(T)=Vh_1+V0(T)+V(T);

[0100] V2(T)=Vh_2+V0(T)+V(T);

[0101] V3(T)=Vh_3+V0(T)+V(T);

[0102] Vh_1:Vh_2:Vh_3=1:m:n. In the example above, w is equal. Based on the lengths of the various Hall effect regions, we can obtain: m=2, n=4.

[0103] Solving the above system of equations yields the temperature drift output voltage:

[0104] V(T)=Average((n*V1(T)-V3(T)-(n-1)*V0(T)) / (n-1), n / m*V1(T)-V2(T)-V0(T));

[0105] The temperature drift output voltage can be used to correct the temperature drift characteristics of the Hall current sensor.

[0106] It should be noted that the above explanation is based on the Hall effect region being rectangular. When the Hall effect region is of other shapes, the same process can be used to calculate the temperature drift output voltage, which will not be elaborated here.

[0107] In the above implementation process, by verifying the shape of Hall disk 1 and the shape of Hall disk in the Hall chip to be calibrated, as well as the voltage value of the Hall chip to be calibrated, the voltage value of the Hall chip calibration structure, and the zero bias calibration value, the temperature drift output voltage can be calculated. Since the shape of the verification Hall disk 1 is the same as the shape of the Hall disk used for functional implementation in the Hall chip to be calibrated, the principle of using the verification Hall disk 1 for calibration is the same as the principle of the Hall chip to be calibrated when it is working. Both are based on the Hall effect to obtain the output result, thereby making the obtained temperature drift output voltage more accurate, greatly reducing calibration error, and improving the accuracy of calibration results.

[0108] Figure 6 This is a flowchart illustrating a Hall chip calibration method in one embodiment. It should be understood that, although... Figure 6 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 6 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0109] This embodiment provides a Hall effect chip calibration device; please refer to [link / reference]. Figure 7 The Hall chip calibration structure described above includes an acquisition module 410 and a calibration module 420, wherein:

[0110] The acquisition module 410 is used to acquire the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure respectively when an excitation is applied to the Hall chip to be calibrated and the Hall chip calibration structure.

[0111] The calibration module 420 is used to obtain a calibration value based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure.

[0112] Wherein, the calibration value includes a zero bias calibration value; the applied excitation is an applied electrical excitation;

[0113] The calibration module 420 includes:

[0114] The zero-bias calibration unit is used to calculate the zero bias based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure, and obtain the zero-bias calibration value.

[0115] The calibration values ​​include temperature drift calibration values;

[0116] The calibration module 420 includes:

[0117] Zero bias acquisition unit, used to acquire zero bias calibration value;

[0118] The ratio determination unit is used to determine the ideal Hall voltage output ratio of each verification Hall disk 1 based on the shape of the verification Hall disk 1 in the Hall chip calibration structure and the shape of the Hall disk in the Hall chip to be calibrated.

[0119] The calculation unit is used to determine the temperature drift calibration value based on the ideal Hall voltage output ratio of each of the calibration Hall disks 1, the voltage value of the Hall chip to be calibrated, the voltage value of the Hall chip calibration structure, and the zero bias calibration value.

[0120] The Hall chip calibration device includes a processor A01 and a memory. The acquisition module 410 and calibration module 420 are stored in the memory as program units. The processor A01 executes the program units stored in the memory to realize the corresponding functions.

[0121] The processor A01 contains a core, which retrieves the corresponding program unit from memory. One or more cores can be configured; adjusting core parameters can reduce calibration errors and improve the accuracy of calibration results.

[0122] The memory may include non-permanent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0123] This invention provides a machine-readable storage medium storing a program that, when executed by processor A01, implements the Hall chip calibration method.

[0124] This invention provides a processor A01 for running a program, wherein the program executes the Hall chip calibration method during runtime.

[0125] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 8 As shown, the computer device includes a processor A01, a network interface A02, a display screen A04, an input device A05, and a memory (not shown) connected via a system bus. The processor A01 provides computing and control capabilities. The memory includes internal memory A03 and a non-volatile storage medium A06. The non-volatile storage medium A06 stores an operating system B01 and a computer program B02. The internal memory A03 provides an environment for the operation of the operating system B01 and the computer program B02 stored in the non-volatile storage medium A06. The network interface A02 is used for communication with external terminals via a network connection. When the processor A01 executes the computer program B02, it implements a Hall chip calibration method. The display screen A04 can be a liquid crystal display screen A04 or an electronic ink display screen A04. The input device A05 can be a touch layer covering the display screen A04, or buttons, a trackball, or a touchpad mounted on the computer device casing, or an external keyboard, touchpad, or mouse, etc.

[0126] Those skilled in the art will understand that Figure 8 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0127] In one embodiment, the Hall chip calibration device provided in this application can be implemented as a computer program BO2, which can be configured as follows: Figure 8 The computer device shown is running the program. The computer device's memory can store the various program modules that make up the Hall chip calibration device, for example... Figure 7 The acquisition module 410 and calibration module 420 are shown. The computer program B02, composed of the various program modules, causes the processor A01 to execute the steps in the file system invocation methods of the various embodiments of this application described in this specification.

[0128] Figure 8 The computer device shown can be used as follows Figure 7 The acquisition module 410 in the Hall chip calibration device shown executes step 210, and the calibration module 420 executes step 220.

[0129] This application provides a device including a processor A01, a memory, and a program stored in the memory and executable on the processor A01. When the processor A01 executes the program, it performs the following steps: applied to the aforementioned Hall chip calibration structure, including:

[0130] When an excitation is applied to the Hall chip to be calibrated and the Hall chip calibration structure, the voltage values ​​of the Hall chip to be calibrated and the Hall chip calibration structure are obtained respectively.

[0131] The calibration value is obtained based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure.

[0132] In one embodiment, the calibration value includes a zero-bias calibration value; the applied excitation is an applied electrical excitation;

[0133] The process of obtaining the calibration value based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure includes:

[0134] The zero bias is calculated based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure to obtain the zero bias calibration value.

[0135] In one embodiment, the calibration value includes a temperature drift calibration value;

[0136] The process of obtaining the calibration value based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure includes:

[0137] Obtain the zero bias calibration value;

[0138] Based on the shape of the calibration Hall disk 1 in the Hall chip calibration structure and the shape of the Hall disk in the Hall chip to be calibrated, the ideal Hall voltage output ratio is determined.

[0139] Based on the ideal Hall voltage output ratio, the voltage value of the Hall chip to be calibrated, the voltage value of the Hall chip calibration structure, and the zero bias calibration value, the temperature drift calibration value is determined.

[0140] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program BO2 products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program BO2 product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0141] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program B02 products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program B02 instructions. These computer program B02 instructions can be provided to a processor A01 of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor A01 of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0142] These computer program B02 instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0143] These computer program B02 instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0144] In a typical configuration, a computing device includes one or more processors A01 (CPU), input / output interfaces, network interfaces A02, and memory.

[0145] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0146] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0147] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0148] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A Hall chip calibration structure, characterized in that, include: At least one calibration Hall disk, the shape of which is the same as that of the Hall disk used for functional implementation in the Hall chip to be calibrated; the calibration Hall disk is provided with an input terminal and an output terminal, the input terminal of which is connected to the output terminal of an external excitation, and the output terminal of which is used to output a Hall voltage; The Hall chip calibration structure is located inside the Hall chip to be calibrated. The calibration Hall disk forms a calibration region, which is the Hall effect region used for calibration. During calibration, external excitation is simultaneously input to both the calibration Hall disk and the Hall chip to be calibrated. Under constant voltage bias, the output Hall voltage is proportional to the aspect ratio of the Hall effect region. Zero bias is calculated based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure to obtain the zero bias calibration value. The ideal Hall voltage output ratio is determined based on the shape of the calibration Hall disk in the Hall chip calibration structure and the shape of the Hall disk in the Hall chip to be calibrated. The temperature drift calibration value is determined based on the ideal Hall voltage output ratio, the voltage value of the Hall chip to be calibrated, the voltage value of the Hall chip calibration structure, and the zero bias calibration value.

2. The Hall chip calibration structure according to claim 1, characterized in that, The verification Hall disk is connected to multiple PADs, which serve as the input and output terminals of the verification Hall disk, respectively.

3. The Hall chip calibration structure according to claim 1, characterized in that, The shape of the calibration Hall disk includes rectangular, square, cross-shaped, and octagonal.

4. The Hall chip calibration structure according to claim 1, characterized in that, There is a proportional relationship between the size of the calibration Hall disk and the size of the Hall disk used for functional implementation in the Hall chip to be calibrated.

5. The Hall chip calibration structure according to claim 1, characterized in that, There are multiple verification Hall disks, and the dimensions of each verification Hall disk may be the same or different.

6. The Hall chip calibration structure according to claim 1, characterized in that, The shape of the verification Hall disk and the shape of the Hall disk used for functional implementation in the Hall chip to be calibrated are both rectangular; wherein, the width of the verification Hall disk and the width of the Hall disk used for functional implementation in the Hall chip to be calibrated are the same, and the length of the verification Hall disk and the length of the Hall disk used for functional implementation in the Hall chip to be calibrated are proportional.

7. The Hall chip calibration structure according to claim 6, characterized in that, There are multiple verification Hall effect disks, each with a different length.

8. A Hall effect chip, characterized in that, It includes a Hall disk chip, which comprises a Hall disk structure for functional implementation and a Hall chip calibration structure according to any one of claims 1-7.

9. The Hall chip according to claim 8, characterized in that, It also includes a conditioning circuit chip, the input of which is connected to the output of the Hall effect disk chip.

10. A Hall effect chip calibration system, characterized in that, It includes a conditioning circuit chip and the Hall chip of claim 8, wherein the output terminal of the Hall chip is connected to the input terminal of the conditioning circuit chip, and the input terminal of the Hall chip is connected to the output terminal of an external excitation.

11. A Hall chip calibration method, characterized in that, The Hall chip calibration structure applied to any one of claims 1-7 comprises: When an excitation is applied to the Hall chip to be calibrated and the Hall chip calibration structure, the voltage values ​​of the Hall chip to be calibrated and the Hall chip calibration structure are obtained respectively. The calibration value is obtained based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure; The calibration values ​​include temperature drift calibration values ​​and zero bias calibration values; The process of obtaining the calibration value based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure includes: The zero bias is calculated based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure to obtain the zero bias calibration value. Obtain the zero bias calibration value; The ideal Hall voltage output ratio is determined based on the shape of the Hall disk in the Hall chip calibration structure and the shape of the Hall disk in the Hall chip to be calibrated. Based on the ideal Hall voltage output ratio, the voltage value of the Hall chip to be calibrated, the voltage value of the Hall chip calibration structure, and the zero bias calibration value, the temperature drift calibration value is determined.

12. A Hall effect chip calibration device, characterized in that, The Hall chip calibration structure applied to any one of claims 1-8 comprises: The acquisition module is used to acquire the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure respectively when an excitation is applied to the Hall chip to be calibrated and the Hall chip calibration structure. The calibration module is used to obtain a calibration value based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure; The calibration values ​​include temperature drift calibration values ​​and zero bias calibration values; The calibration module includes: The zero-bias calibration unit is used to calculate the zero bias based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure, and obtain the zero-bias calibration value. Zero bias acquisition unit, used to acquire zero bias calibration value; The ratio determination unit is used to determine the ideal Hall voltage output ratio of each verification Hall disk based on the shape of the verification Hall disk in the Hall chip calibration structure and the shape of the Hall disk in the Hall chip to be calibrated. The calculation unit is used to determine the temperature drift calibration value based on the ideal Hall voltage output ratio of each calibration Hall disk, the voltage value of the Hall chip to be calibrated, the voltage value of the Hall chip calibration structure, and the zero bias calibration value.

13. A processor, characterized in that, It is configured to perform the Hall chip calibration method as described in claim 11.

14. A machine-readable storage medium storing instructions thereon, characterized in that, When executed by the processor, this instruction causes the processor to be configured to perform the Hall chip calibration method as described in claim 11.

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