Method for manufacturing a semiconductor device and semiconductor device
By forming spaced pre-top electrodes on the substrate and removing them vertically, combined with self-alignment and chemical mechanical planarization techniques, the problem of memory cell size being limited by process limitations was solved, enabling the fabrication of smaller top electrodes and meeting the development needs of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CETHIK GRP
- Filing Date
- 2022-04-07
- Publication Date
- 2026-05-12
AI Technical Summary
In existing technologies, the size of memory cells cannot meet future development needs due to manufacturing process limitations. In particular, during the miniaturization of MRAM, the dimensional accuracy of photolithography and etching, as well as the problem of metal material filling, have become bottlenecks.
By forming multiple spaced pre-top electrodes on the substrate, removing part of the top electrode layer along a direction perpendicular to the substrate thickness to form multiple block-shaped top electrodes, and using the top electrodes as masks to etch the storage material layer, the removal area is adjusted to control critical dimensions by combining self-aligned processes and chemical mechanical planarization technology.
This enables the fabrication of smaller top electrodes with large linewidths, reduces the equipment requirements of the process, ensures that the size of semiconductor devices meets development needs, and improves the controllability of the process.
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Figure CN116936362B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductors, and more specifically, to a method for manufacturing a semiconductor device and the semiconductor device itself. Background Technology
[0002] Currently, the storage structure of memory cells is such that the storage cells are connected to two layers of metal wires through upper and lower electrodes. As future products increasingly require lower write current, reducing the size of the storage cells has become an inevitable trend.
[0003] Currently, MRAM (Magnetic Random Access Memory) sizes are around 70nm, and existing processes can still meet the requirements. However, as the size of memory cells continues to shrink, the supporting processes will be limited, such as the dimensional accuracy of photolithography and etching, the accuracy of nesting alignment, and the problem of filling metal materials in smaller critical dimensions (CD). Therefore, a manufacturing process is needed to ensure that the size of memory cells meets the development needs.
[0004] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention
[0005] The main objective of this application is to provide a method for manufacturing a semiconductor device and a semiconductor device in order to solve the problem that the size of memory cells in the prior art cannot meet development needs due to limitations in manufacturing processes.
[0006] According to one aspect of this application, a method for fabricating a semiconductor device is provided, comprising: providing a substrate, the substrate including a substrate, a bottom electrode layer, a storage material layer, a first dielectric layer, and a top electrode layer, wherein the substrate, the bottom electrode layer, the storage material layer, and the first dielectric layer are stacked sequentially, the first dielectric layer including a first opening, the first opening exposing a portion of the storage material layer, and the top electrode layer being located within the first opening; removing a portion of the top electrode layer along a first direction, the remaining top electrode layer forming a plurality of spaced-apart pre-top electrodes, the first direction being perpendicular to the thickness direction of the substrate; removing a portion of the pre-top electrodes along a second direction, such that each pre-top electrode forms a plurality of spaced-apart top electrodes, the second direction being perpendicular to the thickness direction of the substrate and perpendicular to the first direction; using the top electrode as a mask, etching the storage material layer, such that a portion of the bottom electrode layer is exposed, and the remaining storage material layer forming a storage layer.
[0007] Optionally, after etching the storage material layer using the top electrode as a mask, the method further includes: depositing a second pre-dielectric layer on the exposed surface of the top electrode and the side surface of the storage layer; etching the bottom electrode layer and the second pre-dielectric layer such that a portion of the substrate is exposed and the top electrode and the storage layer are not exposed, the remaining second pre-dielectric layer forms a second dielectric layer, and the remaining bottom electrode layer forms a bottom electrode; forming a third dielectric layer on the exposed surface of the second dielectric layer and the side surface of the bottom electrode; removing a portion of the second dielectric layer and a portion of the third dielectric layer, the remaining second dielectric layer forming a second dielectric portion, and the remaining third dielectric layer forming a third dielectric portion; forming a first metal line on the second dielectric portion and the third dielectric portion, the first metal line contacting the top electrode.
[0008] Optionally, etching the bottom electrode layer and the second preparatory dielectric layer includes etching the bottom electrode layer and the second preparatory dielectric layer using a self-aligned process.
[0009] Optionally, a substrate is provided, comprising: providing a substrate; sequentially depositing the bottom electrode layer, the storage material layer, and the first preparatory dielectric layer on the substrate; etching the first preparatory dielectric layer to form the first opening, the remaining first preparatory dielectric layer forming the first dielectric layer; and filling the first opening with electrode material to form the top electrode layer.
[0010] Optionally, a substrate is provided; a fourth dielectric layer is deposited on the substrate; the fourth dielectric layer is etched to expose a portion of the substrate, forming a second opening, and the remaining fourth dielectric layer forms a fourth dielectric portion; an electrode material is filled into the second opening to form the bottom electrode layer; the storage material layer and the first preparative dielectric layer are sequentially deposited on the exposed surfaces of the fourth dielectric portion and the bottom electrode layer; the first preparative dielectric layer is etched to form the first opening, and the remaining first preparative dielectric layer forms the first dielectric layer; an electrode material is filled into the first opening to form the top electrode layer.
[0011] Optionally, a substrate is provided, comprising: providing a pre-substrate, the pre-substrate including a plurality of third openings; filling the third openings with a metallic material to obtain a second metal line, thereby forming the substrate.
[0012] Optionally, the material of the first dielectric layer includes at least one of SiN, SiO2, and SiON.
[0013] Optionally, etching the bottom electrode layer and the second preparatory dielectric layer includes etching the bottom electrode layer and the second preparatory dielectric layer, and cleaning the side surfaces of the bottom electrode layer and the exposed surfaces of the second preparatory dielectric layer.
[0014] Optionally, removing a portion of the top electrode layer along the first direction includes: removing a portion of the top electrode layer along the first direction by photolithography and etching processes; removing a portion of the prepared top electrode along the second direction includes: removing a portion of the prepared top electrode along the second direction by photolithography and etching processes.
[0015] According to another aspect of this application, a semiconductor device is provided, said semiconductor device being fabricated using the method described above.
[0016] In an embodiment of the present invention, the method for fabricating a semiconductor device firstly provides a substrate comprising a substrate, a bottom electrode layer, a storage material layer, a first dielectric layer, and a top electrode layer, wherein the substrate, the bottom electrode layer, the storage material layer, and the first dielectric layer are stacked sequentially, the first dielectric layer includes a first opening that exposes a portion of the storage material layer, and the top electrode layer is located within the first opening; then, a portion of the top electrode layer is removed along a first direction, the remaining top electrode layer forming a plurality of spaced-apart pre-top electrodes, the first direction being perpendicular to the thickness direction of the substrate; subsequently, a portion of the pre-top electrodes is removed along a second direction, such that each pre-top electrode forms a plurality of spaced-apart top electrodes, the second direction being perpendicular to the thickness direction of the substrate and the first direction; finally, using the top electrode as a mask, the storage material layer is etched, exposing a portion of the bottom electrode layer, the remaining storage material layer forming a storage layer. Compared to existing technologies where the size of memory cells cannot meet development needs due to manufacturing process limitations, the semiconductor device fabrication method of this application removes a portion of the top electrode layer along the first direction to form multiple strip-shaped pre-top electrodes, and then removes a portion of the pre-top electrodes along the second direction perpendicular to the first direction to form multiple block-shaped top electrodes. The larger the area of the removed top electrode layer, the smaller the size of the remaining pre-top electrodes. Since larger critical dimensions are easier to control and have lower equipment requirements, the semiconductor device fabrication method changes the removal area under large linewidths to ensure that the size of the remaining top electrodes meets actual needs, enabling the fabrication of smaller top electrodes and ensuring that the size of the semiconductor device meets development requirements. Attached Figure Description
[0017] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:
[0018] Figure 1 A schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this application is shown;
[0019] Figures 2 to 14 The diagrams show the structural schematics obtained after each process step in a method for fabricating a semiconductor device according to an embodiment of this application.
[0020] Figures 15 to 28 The diagrams show the structural schematics obtained after each process step of a method for fabricating a semiconductor device according to another embodiment of this application.
[0021] Figures 29 to 31 The diagram shows a top view of the semiconductor device fabrication method according to an embodiment of the present application, after each process step.
[0022] Figures 32 to 37 The diagrams show the structural schematics obtained after each process step of a method for fabricating a semiconductor device according to another embodiment of this application.
[0023] The above figures include the following reference numerals:
[0024] 10. Substrate; 20. Bottom electrode layer; 30. Storage material layer; 40. First dielectric layer; 50. Top electrode layer; 60. Second pre-dielectric layer; 70. Third dielectric layer; 80. First metal line; 90. Fourth dielectric layer; 100. Second metal line; 101. Pre-substrate; 102. Third opening; 110. First photoresist layer; 120. Second photoresist layer; 130. Third photoresist layer; 140. Fourth photoresist layer; 150. Fifth dielectric layer; 151. Fifth dielectric section; 201. Bottom electrode; 202. Pre-bottom electrode; 203. Bottom electrode section; 301. Storage layer; 401. First opening; 402. First pre-dielectric layer; 501. Pre-top electrode; 502. Top electrode; 601. Second dielectric layer; 602. Second dielectric section; 701. Third dielectric section; 901. Second opening; 902. Fourth dielectric section; 903. Sub-dielectric section. Detailed Implementation
[0025] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.
[0026] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.
[0027] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.
[0028] As described in the background section, the size of existing memory cells cannot meet development needs due to manufacturing process limitations. To address this issue, in a typical embodiment of this application, a method for manufacturing a semiconductor device and a semiconductor device are provided.
[0029] According to an embodiment of this application, a method for fabricating a semiconductor device is provided.
[0030] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application. For example... Figure 1 As shown, the method includes the following steps:
[0031] Step S101, as follows Figure 5 , Figure 6 as well as Figure 19 as well as Figure 20 As shown, a substrate is provided, the substrate including a substrate 10, a bottom electrode layer 20, a storage material layer 30, a first dielectric layer 40 and a top electrode layer 50, wherein the substrate 10, the bottom electrode layer 20, the storage material layer 30 and the first dielectric layer 40 are stacked sequentially, the first dielectric layer 40 includes a first opening 401, the first opening 401 exposes a portion of the storage material layer 30, and the top electrode layer 50 is located within the first opening 401;
[0032] Step S102, as follows Figure 8 as well as Figure 22 As shown, a portion of the top electrode layer 50 is removed along a first direction, and the remaining top electrode layer 50 forms a plurality of spaced pre-top electrodes 501. The first direction is perpendicular to the thickness of the substrate.
[0033] Step S103, as follows Figure 10 as well as Figure 24 As shown, a portion of the prepared top electrode 501 is removed along the second direction, such that each of the prepared top electrodes 501 forms a plurality of spaced top electrodes 502. The second direction is perpendicular to the direction of the substrate thickness and the second direction is perpendicular to the first direction.
[0034] Step S104, as follows Figure 11 as well as Figure 25 As shown, the top electrode 502 is used as a mask to etch the storage material layer 30, exposing part of the bottom electrode layer 20, and the remaining storage material layer 30 forms the storage layer 301.
[0035] In the above-described method for fabricating a semiconductor device, firstly, a substrate including a substrate, a bottom electrode layer, a storage material layer, a first dielectric layer, and a top electrode layer is provided. The substrate, bottom electrode layer, storage material layer, and first dielectric layer are sequentially stacked. The first dielectric layer includes a first opening that exposes a portion of the storage material layer. The top electrode layer is located within the first opening. Then, a portion of the top electrode layer is removed along a first direction, leaving a plurality of spaced-apart pre-top electrodes. The first direction is perpendicular to the thickness direction of the substrate. Next, a portion of the pre-top electrodes is removed along a second direction, leaving a plurality of spaced-apart top electrodes for each pre-top electrode. The second direction is perpendicular to both the thickness direction of the substrate and the first direction. Finally, using the top electrode as a mask, the storage material layer is etched, exposing a portion of the bottom electrode layer. The remaining storage material layer forms a storage layer. Compared to the problem in existing technologies where the size of memory cells cannot meet development needs due to manufacturing process limitations, the semiconductor device manufacturing method of this application removes a portion of the top electrode layer along the first direction to form multiple strip-shaped pre-top electrodes, and then removes a portion of the pre-top electrodes along the second direction perpendicular to the first direction to form multiple block-shaped top electrodes. The larger the area of the removed top electrode layer, the smaller the size of the remaining pre-top electrodes. Since larger critical dimensions are easier to control and have lower equipment requirements, the semiconductor device manufacturing method changes the removal area under large linewidths to ensure that the size of the remaining top electrodes meets actual needs, enabling the fabrication of smaller top electrodes and ensuring that the size of the semiconductor device meets development needs.
[0036] Specifically, such as Figure 7 as well as Figure 21As shown, before removing a portion of the top electrode layer 50 along the first direction, a first photoresist layer 110 needs to be formed. This first photoresist layer 110 can form a covered layer with a fixed pattern on the top electrode layer 50, ensuring that the subsequent removal of the portion of the top electrode layer 50 can be carried out according to the set pattern. Figure 9 as well as Figure 23 As shown, before removing a portion of the pre-top electrode 501 along the second direction, the second photoresist layer 120 needs to be formed first. The second photoresist layer 120 can form a covered layer with a fixed pattern on the pre-top electrode 501, ensuring that the subsequent removal of the portion of the pre-top electrode 501 can be carried out according to the set pattern.
[0037] In one specific embodiment, such as Figure 29 As shown, the top electrode layer 50 is located within the first opening of the first dielectric layer 40, as... Figure 29 as well as Figure 30 As shown, a first photolithographic patterning is performed along the first direction to remove a portion of the top electrode layer 50, forming a plurality of spaced-apart pre-top electrodes 501, and exposing a portion of the storage material layer 30, such as... Figure 30 as well as Figure 31 As shown, a second photolithographic patterning is performed along the second direction perpendicular to the first direction to remove a portion of the pre-existing top electrode 501, forming multiple spaced top electrodes 502. The shape of the top electrodes can be changed according to actual needs. To ensure accurate pattern transfer during the first and second photolithographic patterning processes, the etched pattern needs to be trimmed during the photolithography process.
[0038] According to a specific embodiment of this application, after etching the storage material layer using the top electrode as a mask, the method further includes: as follows: Figure 11 as well as Figure 25 As shown, a second preparative dielectric layer 60 is deposited on the exposed surface of the top electrode 502 and on the side surface of the storage layer 301; as Figure 11 as well as Figure 12 or Figure 25 as well as Figure 26 As shown, the bottom electrode layer 20 and the second preparatory dielectric layer 60 are etched to expose a portion of the substrate while the top electrode 502 and the storage layer 301 are not exposed. The remaining portion of the second preparatory dielectric layer 60 forms the second dielectric layer 601, and the remaining portion of the bottom electrode layer 20 forms the bottom electrode 201. Figure 26 As shown, the remaining fourth dielectric portion 902 forms a sub-dielectric portion 903; as Figure 13 as well as Figure 27As shown, a third dielectric layer 70 is formed on the exposed surface of the second dielectric layer 601 and on the side surface of the bottom electrode 201, wherein, Figure 27 In this process, the third dielectric layer 70 also covers the side surface of the sub-dielectric section 903; as... Figure 13 as well as Figure 14 ,or Figure 27 as well as Figure 28 As shown, a portion of the second dielectric layer 601 and a portion of the third dielectric layer 70 are removed, leaving the second dielectric layer 601 to form the second dielectric portion 602 and the remaining third dielectric layer 70 to form the third dielectric portion 701. A first metal line 80 is formed on the second dielectric portion 602 and the third dielectric portion 701, and the first metal line 80 contacts the top electrode 502. By depositing a second preparatory dielectric layer on the exposed surface of the top electrode and the side surface of the storage layer, it is ensured that the top electrode and the storage layer will not be damaged during the subsequent etching of the bottom electrode layer. Furthermore, by forming the third dielectric layer, it is ensured that the first metal line can be formed in the third dielectric layer. Finally, the contact between the formed first metal line and the top electrode ensures that the performance of the semiconductor device can be achieved.
[0039] Specifically, a portion of the second and third dielectric layers are removed via chemical mechanical planarization, followed by the formation of the first metal line using a damascus process. In one specific embodiment, by adjusting the photolithography process, the above method can form a 20nm memory cell.
[0040] According to another specific embodiment of this application, etching the bottom electrode layer and the second preparatory dielectric layer includes: etching the bottom electrode layer and the second preparatory dielectric layer using a self-aligned process. Etching the bottom electrode layer and the second preparatory dielectric layer using a self-aligned process ensures that the bottom electrode, the top electrode, and the memory layer are aligned on a single line, preventing OVL (Over Lay) misalignment.
[0041] In one specific embodiment, in order to ensure that the storage material layer is not etched during the removal of part of the top electrode layer along the first direction, a predetermined element in the top electrode layer can be monitored during the etching process. When the predetermined element in the top electrode layer is not detected, the etching process is stopped. Similarly, during the etching of the preparatory top electrode along the second direction, the etching stop position is controlled by monitoring the predetermined element in the preparatory top electrode. During the etching of the bottom electrode layer using a self-aligned process, the etching stop position is controlled by monitoring the predetermined element in the bottom electrode layer.
[0042] According to another specific embodiment of this application, a substrate is provided, comprising: as Figure 3 As shown, a substrate 10 is provided; as Figure 4 As shown, the bottom electrode layer 20, the storage material layer 30, and the first pre-dielectric layer 402 are sequentially deposited on the substrate 10; as Figure 5 As shown, the first preparatory dielectric layer 402 is etched to form the first opening 401, and the remaining first preparatory dielectric layer 402 forms the first dielectric layer 40; as Figure 6 As shown, electrode material is filled into the first opening 401 to form the top electrode layer 50. By filling the first opening, which is relatively large, with electrode material to form the top electrode layer, the problem of limited filling capacity during direct metal deposition is avoided.
[0043] In one specific embodiment, the first preparative dielectric layer is patterned using photolithography, with pitch-CD as the linewidth and pitch+CD as the spacing, wherein, as shown... Figure 31 As shown, Pitch is the distance between the centers of two adjacent top electrodes 502, CD is the width of the top electrode 502, the resulting pattern is a through hole shape, forming the first opening, and after filling the first opening with electrode material, chemical mechanical polishing is performed.
[0044] Specifically, after filling the first opening with electrode material, the top electrode layer is formed by chemical mechanical planarization.
[0045] We can also form the bottom electrode layer using the same method as the top electrode layer described above. According to a specific embodiment of this application, a substrate is provided, comprising: Figure 15 As shown, a substrate 10 is provided; a fourth dielectric layer 90 is deposited on the substrate 10; as Figure 16 As shown, the fourth dielectric layer 90 is etched to expose a portion of the substrate 10, forming a second opening 901, and the remaining fourth dielectric layer 90 forms a fourth dielectric portion 902; as Figure 17 As shown, electrode material is filled into the second opening 901 to form the bottom electrode layer 20; as Figure 18 As shown, the storage material layer 30 and the first preparative dielectric layer 402 are sequentially deposited on the exposed surfaces of the fourth dielectric portion 902 and the bottom electrode layer 20; as Figure 19 As shown, the first preparatory dielectric layer 402 is etched to form the first opening 401, and the remaining first preparatory dielectric layer 402 forms the first dielectric layer 40; as Figure 20As shown, electrode material is filled into the first opening 401 to form the top electrode layer 50. By filling the second opening with electrode material to form the bottom electrode layer, and then filling the larger first opening with electrode material to form the top electrode layer, the problem of limited filling capacity during direct metal deposition is avoided for both the bottom and top electrode layers.
[0046] Specifically, after filling the first opening and the second opening with electrode material, the top electrode layer and the bottom electrode layer are formed by chemical mechanical planarization.
[0047] In one specific embodiment, the height of the top electrode layer can be adjusted according to actual needs, and the first metal line can directly contact the top electrode, thus avoiding the through-holes in the array region in the prior art.
[0048] According to another specific embodiment of this application, after filling the second opening with electrode material to form the bottom electrode layer, the method further includes: as follows: Figure 32 As shown, a third photoresist layer 130 is formed, and the third photoresist layer 130 is a covered layer with a fixed pattern formed on the bottom electrode layer 20; as Figure 33 As shown, a portion of the bottom electrode layer 20 is removed along the first direction, and the remaining bottom electrode layer 20 forms a plurality of spaced pre-bottom electrodes 202; as Figure 34 As shown, a fourth photoresist layer 140 is formed, which is a cover layer with a fixed pattern formed on the pre-ground electrode 202; as Figure 35 As shown, a portion of the prepared bottom electrode 202 is removed along the second direction, such that each prepared bottom electrode 202 forms a plurality of spaced bottom electrode portions 203; as Figure 36 As shown, a fifth dielectric layer 150 is formed on the surface of the bottom electrode portion 203 and the surface of the substrate 10; as Figure 37 As shown, the fifth dielectric layer 150 is chemically mechanically ground until a portion of the bottom electrode portion 203 is exposed, and the remaining fifth dielectric layer 150 forms the fifth dielectric portion 151.
[0049] According to another specific embodiment of this application, a substrate is provided, comprising: as Figure 2 As shown, a pre-substrate 101 is provided, the pre-substrate including a plurality of third openings 102; as Figure 3 As shown, metal material is filled into the third opening 102 to obtain a second metal line 100, forming the substrate 10. The second metal line ensures that the performance of the semiconductor device can be achieved.
[0050] Specifically, after filling the third opening with metallic material, the second metal wire is obtained through chemical mechanical planarization.
[0051] According to one specific embodiment of this application, the first dielectric layer material includes at least one of SiN, SiO2, and SiON.
[0052] In one specific embodiment, the materials of the first dielectric layer, the second dielectric layer, the third dielectric layer, the fourth dielectric layer, and the fifth dielectric layer include at least one of SiN, SiO2, and SiON. Of course, other materials can also be used according to actual needs.
[0053] According to another specific embodiment of this application, etching the bottom electrode layer and the second preparatory dielectric layer includes: etching the bottom electrode layer and the second preparatory dielectric layer, and cleaning the side surface of the bottom electrode layer and the exposed surface of the second preparatory dielectric layer.
[0054] Specifically, etching the bottom electrode layer and the second preparative dielectric layer, while cleaning the sidewalls of the bottom electrode layer and the exposed surfaces of the second preparative dielectric layer, can reduce backsplashing on the sidewalls of the bottom electrode and ensure better performance of the semiconductor device.
[0055] According to another specific embodiment of this application, removing a portion of the top electrode layer along a first direction includes: removing a portion of the top electrode layer along the first direction by photolithography and etching processes; removing a portion of the prepared top electrode along a second direction includes: removing a portion of the prepared top electrode along the second direction by photolithography and etching processes.
[0056] According to an embodiment of this application, a semiconductor device is also provided, which is manufactured using the method described above.
[0057] The aforementioned semiconductor device is manufactured using any of the methods described above. Compared to the problem in the prior art where the size of the memory cell cannot meet development needs due to manufacturing process limitations, the semiconductor device of this application, by removing a portion of the top electrode layer along the first direction to form multiple strip-shaped pre-top electrodes, and then removing a portion of the pre-top electrodes along the second direction perpendicular to the first direction to form multiple block-shaped top electrodes, allows for the larger the area of the removed top electrode layer to be, resulting in a smaller size of the remaining pre-top electrodes. Since a larger critical dimension makes the process easier to control and reduces equipment requirements, the manufacturing method of the aforementioned semiconductor device, by changing the removal area under a large linewidth, allows the size of the remaining top electrodes to meet actual needs, enabling the fabrication of smaller top electrodes and ensuring that the size of the aforementioned semiconductor device meets development needs.
[0058] Example 1
[0059] Step 1: Deposit the fourth dielectric layer on the substrate surface where the second metal line is located;
[0060] Step 2: Perform photolithography on the fourth dielectric layer to form a through-hole shape, thus forming the second opening. The remaining fourth dielectric layer forms the fourth dielectric portion.
[0061] Step 3: Backfill the second opening with metal material and perform chemical mechanical polishing to form the bottom electrode layer.
[0062] Step 4: Sequentially deposit the storage material layer and the first preparative dielectric layer on the surfaces of the bottom electrode layer and the fourth dielectric portion;
[0063] Step 5: Perform photolithography on the first preparatory dielectric layer to form a through-hole shape, thereby forming the first opening. The remaining first preparatory dielectric layer forms the first dielectric layer.
[0064] Step 6: Backfill the first opening with metal material and perform chemical mechanical polishing to form the top electrode layer.
[0065] Step 7: Perform a first one-dimensional photolithography patterning on the top electrode layer in the first direction to form multiple strip-shaped pre-top electrodes;
[0066] Step 8: Perform a second photolithography patterning in the second direction above the one-dimensional patterning orthogonal direction to form the top electrode in the final metal hard mask module shape;
[0067] Step 9: High selectivity etching After removing the first dielectric layer, using the top electrode as a hard mask, the storage material layer is etched to form the storage layer, and the second preparatory dielectric layer is then added.
[0068] Step 10: Etch the bottom electrode layer using a self-aligned process;
[0069] Step 11: Backfill the aforementioned third dielectric layer;
[0070] Step 12: Form the first metal line above. Generally, the circuit trace above is generated using the damascus process.
[0071] Example 2
[0072] The main difference between Example 2 and Example 1 is that in Example 2, a small-sized bottom electrode is formed directly before Example 1.
[0073] Step 1: Deposit the fourth dielectric layer on the substrate surface where the second metal line is located;
[0074] Step 2: Perform photolithography on the fourth dielectric layer to form a through-hole shape, thus forming the second opening. The remaining fourth dielectric layer forms the fourth dielectric portion.
[0075] Step 3: Backfill the second opening with metal material and perform chemical mechanical polishing to form the bottom electrode layer.
[0076] Step 4: Perform a first one-dimensional photolithography patterning on the bottom electrode layer in the first direction to form multiple strip-shaped pre-bottom electrodes;
[0077] Step 5: Perform a second photolithography patterning in the second direction of the above-mentioned one-dimensional patterning orthogonal direction to form the bottom electrode portion in the final metal hard mask module shape;
[0078] Step 6: After removing the fourth dielectric layer by high-selectivity etching, deposit the fifth dielectric layer.
[0079] Step 7: Chemical mechanical polishing exposes the bottom electrode portion, forming a conductive connection.
[0080] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0081] As can be seen from the above description, the embodiments of this application achieve the following technical effects:
[0082] 1) In the semiconductor device fabrication method described above in this application, firstly, a substrate including a substrate, a bottom electrode layer, a storage material layer, a first dielectric layer, and a top electrode layer is provided, wherein the substrate, the bottom electrode layer, the storage material layer, and the first dielectric layer are stacked sequentially, the first dielectric layer includes a first opening, the first opening exposing a portion of the storage material layer, and the top electrode layer is located within the first opening; then, a portion of the top electrode layer is removed along a first direction, the remaining top electrode layer forming a plurality of spaced-apart pre-top electrodes, the first direction being perpendicular to the thickness direction of the substrate; subsequently, a portion of the pre-top electrodes is removed along a second direction, such that each pre-top electrode forms a plurality of spaced-apart top electrodes, the second direction being perpendicular to the thickness direction of the substrate and perpendicular to the first direction; finally, using the top electrode as a mask, the storage material layer is etched, exposing a portion of the bottom electrode layer, and the remaining storage material layer forming a storage layer. Compared to the problem in existing technologies where the size of memory cells cannot meet development needs due to manufacturing process limitations, the semiconductor device manufacturing method of this application removes a portion of the top electrode layer along the first direction to form multiple strip-shaped pre-top electrodes, and then removes a portion of the pre-top electrodes along the second direction perpendicular to the first direction to form multiple block-shaped top electrodes. The larger the area of the removed top electrode layer, the smaller the size of the remaining pre-top electrodes. Since larger critical dimensions are easier to control and have lower equipment requirements, the semiconductor device manufacturing method changes the removal area under large linewidths to ensure that the size of the remaining top electrodes meets actual needs, enabling the fabrication of smaller top electrodes and ensuring that the size of the semiconductor device meets development needs.
[0083] 2) The semiconductor device described in this application is manufactured using any of the above methods. Compared with the problem in the prior art where the size of the memory cell cannot meet development needs due to manufacturing process limitations, the semiconductor device described in this application forms multiple strip-shaped pre-top electrodes by removing part of the top electrode layer along the first direction, and then removing part of the pre-top electrodes along the second direction perpendicular to the first direction to form multiple block-shaped top electrodes. The larger the area of the removed top electrode layer, the smaller the size of the remaining pre-top electrodes. Since the larger the critical size, the easier the process is to control, and the lower the requirements for equipment, the semiconductor device manufacturing method changes the removal area under a large linewidth so that the size of the remaining top electrodes meets the actual needs. It can realize the manufacturing of smaller top electrodes and ensure that the size of the semiconductor device meets development needs.
[0084] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate including a substrate, a bottom electrode layer, a storage material layer, a first dielectric layer and a top electrode layer, wherein the substrate, the bottom electrode layer, the storage material layer and the first dielectric layer are stacked sequentially, the first dielectric layer includes a first opening, the first opening exposing a portion of the storage material layer, and the top electrode layer is located within the first opening; A portion of the top electrode layer is removed along a first direction, and the remaining top electrode layer forms a plurality of spaced-apart pre-top electrodes, wherein the first direction is perpendicular to the thickness of the substrate. A portion of the prepared top electrode is removed along a second direction, such that each prepared top electrode forms a plurality of spaced top electrodes, the second direction being perpendicular to the substrate thickness direction and the second direction being perpendicular to the first direction; Using the top electrode as a mask, the storage material layer is etched to expose part of the bottom electrode layer, and the remaining storage material layer forms the storage layer.
2. The method according to claim 1, characterized in that, After etching the storage material layer using the top electrode as a mask, the method further includes: A second pre-dielectric layer is deposited on the exposed surface of the top electrode and on the side surface of the storage layer; The bottom electrode layer and the second preparative dielectric layer are etched to expose a portion of the substrate while the top electrode and the storage layer are not exposed. The remaining second preparative dielectric layer forms the second dielectric layer, and the remaining bottom electrode layer forms the bottom electrode. A third dielectric layer is formed on the exposed surface of the second dielectric layer and on the side of the bottom electrode; A portion of the second dielectric layer and a portion of the third dielectric layer are removed, leaving the remaining second dielectric layer to form a second dielectric portion and the remaining third dielectric layer to form a third dielectric portion. A first metal line is formed on the second dielectric portion and the third dielectric portion, and the first metal line is in contact with the top electrode.
3. The method according to claim 2, characterized in that, Etching of the bottom electrode layer and the second pre-dielectric layer includes: The bottom electrode layer and the second preparative dielectric layer are etched using a self-aligned process.
4. The method according to claim 1, characterized in that, Provide a substrate, including: Provide substrate; The bottom electrode layer, the storage material layer, and the first pre-dielectric layer are sequentially deposited on the substrate; The first preparatory dielectric layer is etched to form the first opening, and the remaining first preparatory dielectric layer forms the first dielectric layer; Electrode material is filled into the first opening to form the top electrode layer.
5. The method according to claim 4, characterized in that, Provide a substrate, including: Provide substrate; A fourth dielectric layer is deposited on the substrate; The fourth dielectric layer is etched to expose a portion of the substrate, forming a second opening, and the remaining fourth dielectric layer forms a fourth dielectric portion; Electrode material is filled into the second opening to form the bottom electrode layer; The storage material layer and the first pre-dielectric layer are sequentially deposited on the exposed surfaces of the fourth dielectric portion and the bottom electrode layer; The first preparatory dielectric layer is etched to form the first opening, and the remaining first preparatory dielectric layer forms the first dielectric layer; Electrode material is filled into the first opening to form the top electrode layer.
6. The method according to claim 4, characterized in that, Provide a substrate, including: A pre-substrate is provided, the pre-substrate including a plurality of third openings; Metal material is filled into the third opening to obtain a second metal wire, which forms the substrate.
7. The method according to any one of claims 1 to 6, characterized in that, The material of the first dielectric layer includes at least one of SiN, SiO2, and SiON.
8. The method according to claim 2, characterized in that, Etching of the bottom electrode layer and the second pre-dielectric layer includes: The bottom electrode layer and the second preparative dielectric layer are etched, and the sides of the bottom electrode layer and the exposed surfaces of the second preparative dielectric layer are cleaned.
9. The method according to claim 1, characterized in that, Removing a portion of the top electrode layer along a first direction includes: Part of the top electrode layer is removed along the first direction by photolithography and etching processes; Removing a portion of the prepared top electrode along the second direction includes: Part of the prepared top electrode is removed along the second direction by photolithography and etching processes.
10. A semiconductor device, characterized in that, The semiconductor device is manufactured using the method described in any one of claims 1 to 9.