Amplifier circuit, integrated circuit chip, and electronic device

Abstract

The application relates to an amplifier circuit, an integrated circuit chip and an electronic device. The amplifier circuit comprises a transistor having a first end, a second end and a third end, wherein a signal to be amplified is input from the first end, an inverted amplified signal is generated at the second end after the signal to be amplified is amplified by the transistor, and a follow-up amplified signal is generated at the third end; a first output impedance matching circuit, a first end of the first output impedance matching circuit being connected to the second end of the transistor, wherein the inverted amplified signal is output as a first amplified signal at a second end of the first output impedance matching circuit after passing through the first output impedance matching circuit; and a second output impedance matching circuit, a first end of the second output impedance matching circuit being connected to the third end of the transistor, wherein the follow-up amplified signal is output as a second amplified signal at a second end of the second output impedance matching circuit after passing through the second output impedance matching circuit. According to the application, the power consumption of the circuit can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, in particular to an amplifier circuit, an integrated circuit chip and an electronic device. BACKGROUND

[0002] An amplifier is used for amplifying a signal, and is a commonly used device in the field of radio frequency technology, especially in the field of wireless communication and satellite communication. The power consumption and gain of an amplifier are important indicators for measuring the performance of the amplifier. Generally, it is expected that a power amplifier can have low power consumption. With the development of communication technology, the number of amplifiers required in communication equipment is increasing, and it is expected to provide high-performance amplifiers with low power consumption. SUMMARY

[0003] The embodiments of the present application provide an amplifier circuit, an integrated circuit chip and an electronic device to provide an amplifier circuit with reduced power consumption.

[0004] According to an aspect of the present application, an amplifier circuit is provided, which comprises:

[0005] a transistor having a first end, a second end and a third end, wherein a signal to be amplified is connected to the first end of the transistor, and after being amplified by the transistor, an inverted amplified signal is generated at the second end of the transistor and a following amplified signal is generated at the third end of the transistor;

[0006] a first output impedance matching circuit for matching the output impedance of the second end of the transistor to a first target impedance, the first target impedance being the output impedance of the second end of the first output impedance matching circuit, the first end of the first output impedance matching circuit being connected to the second end of the transistor, wherein the inverted amplified signal is output as a first amplified signal at the second end of the first output impedance matching circuit after passing through the first output impedance matching circuit; and

[0007] a second output impedance matching circuit for matching the output impedance of the third end of the transistor to a second target impedance, the second target impedance being the output impedance of the second end of the second output impedance matching circuit, the first end of the second output impedance matching circuit being connected to the third end of the transistor, wherein the following amplified signal is output as a second amplified signal at the second end of the second output impedance matching circuit after passing through the second output impedance matching circuit.

[0008] According to another aspect of the present application, an integrated circuit chip is provided, which comprises a substrate, and an amplifier circuit as described above located on the substrate.

[0009] According to still another aspect of the present application, an electronic device is provided, which comprises an integrated circuit chip as described above.

[0010] The technical solutions provided by the embodiments of the present application can include the following beneficial effects:

[0011] In the amplifier circuit, integrated circuit chip and electronic device of the embodiments of the present application, the transistor and the first output impedance matching circuit and the second output impedance matching circuit located at two ends of the transistor form two amplification links respectively, and the input signal to be amplified is amplified respectively, and two amplified signals are output. That is, one transistor is used to realize two amplifications, so that the power consumption of the circuit is greatly reduced.

[0012] It should be understood that the above general description and the following description are only exemplary and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0013] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0014] Figure 1 Fig. 1 shows a structural schematic diagram of an amplifier circuit according to an embodiment of the present application;

[0015] Figure 2A and 2B Fig. 2 shows a principle schematic diagram of an amplifier circuit according to an embodiment of the present application;

[0016] Figure 3 Fig. 3 shows a structural schematic diagram of an amplifier circuit according to an embodiment of the present application, wherein the amplifier circuit 100 further includes a first bias circuit 124, a second bias circuit 134, an input impedance matching circuit 141 and a third bias circuit 142;

[0017] Figure 4A and 4B Fig. 4 shows a structural schematic diagram of an amplifier circuit according to other embodiments of the present application;

[0018] Figure 5A Fig. 5 shows a schematic diagram of the phase difference of the first amplified signal and the second amplified signal before and after passing through the first and second output impedance matching circuits;

[0019] Figure 5B Fig. 6 shows a waveform schematic diagram of the first amplified signal and the second amplified signal after superposition;

[0020] Figure 6 Fig. 7 shows a structural schematic diagram of an amplifier circuit according to an embodiment of the present application, wherein an example of the composition of the first and second output impedance matching circuits and the input impedance matching circuit is specifically shown;

[0021] Figure 7A structural schematic of an amplifier circuit according to an embodiment of the application is shown, in which an example of the composition of the first and second biasing circuits is specifically shown;

[0022] Figure 8 A structural schematic of an amplifier circuit according to an embodiment of the application is shown, in which another example of the composition of the second biasing circuit is specifically shown;

[0023] Figure 9 A structural schematic of an amplifier circuit according to an embodiment of the application is shown, in which still another example of the composition of the second biasing circuit is specifically shown;

[0024] Figure 10 A structural schematic of an amplifier circuit according to an embodiment of the application is shown, in which an example of the composition of the third biasing circuit is specifically shown;

[0025] Figure 11 A structural schematic of an amplifier circuit according to an embodiment of the application is shown, in which another example of the composition of the third biasing circuit is specifically shown;

[0026] Figure 12 A schematic diagram of an integrated circuit chip according to an embodiment of the application is shown;

[0027] Figure 13 A schematic diagram of an electronic device according to an embodiment of the application is shown.

[0028] Figure 14 A schematic diagram of an arrangement of inductors according to an embodiment of the application is shown. DETAILED DESCRIPTION

[0029] The exemplary embodiments will now be described in detail with reference to the accompanying drawings. If described with reference to the drawings, the same numbers on different drawings represent the same or similar elements. The following detailed description is provided to explain the exemplary embodiments in the best way. The following detailed description includes specific examples to assist in providing a thorough understanding of various inventive concepts. However, one skilled in the relevant art will recognize that the following

[0030] Numerous specific details, such as examples of particular components, circuits, and processes, are set forth in the following description to provide a thorough understanding of this disclosure. As used herein, the term "connection" means a direct connection or a connection via one or more intermediate components or circuits, or a connection in a coupled manner. Furthermore, specific nomenclature is set forth in the following description and for purposes of explanation to provide a thorough understanding of embodiments of this application. However, it will be understood by those skilled in the art that these specific details may not be necessary for implementing embodiments of this application. In some embodiments, well-known circuits and devices are illustrated in block diagram form to avoid obscuring the scope of this disclosure. Additionally, interconnections between circuit elements or software blocks may be shown as buses or single signal lines. Each bus may alternatively be a single signal line, and each single signal line may alternatively be a bus, and a single line or bus may represent any one or more of a large number of physical or logical mechanisms for communication between components.

[0031] Figure 1 This is a schematic diagram of an amplifier circuit 100 according to an embodiment of this application. Figure 1 As shown, in this embodiment, the amplifier circuit 100 includes a transistor 110, a first output impedance matching circuit 123, and a second output impedance matching circuit 133. The transistor 110 is used to amplify the signal to be amplified and has a first terminal 111, a second terminal 112, and a third terminal 113. The signal to be amplified is input from the first terminal 111, and after being amplified by the transistor 110, an inverting amplified signal is generated at the second terminal 112 of the transistor 110, and a follower amplified signal is generated at the third terminal 113 of the transistor 110.

[0032] The first output impedance matching circuit 123 and the second output impedance matching circuit 133 are respectively connected to the second terminal 112 and the third terminal 113 of the transistor 110. The first output impedance matching circuit 123 is used to match the output impedance of the second terminal 112 of the transistor 110 to a first target impedance, which is the output impedance of the second terminal 112 of the first output impedance matching circuit 123. The first terminal 121 of the first output impedance matching circuit 123 is connected to the second terminal 112 of the transistor 110. The inverting amplified signal generated at the second terminal 112 of the transistor 110 is output as a first amplified signal after passing through the first output impedance matching circuit 123 and being output as a first amplified signal at the second terminal 122 of the first output impedance matching circuit 123.

[0033] The second output impedance matching circuit 133 is configured to match the output impedance of the third terminal 113 of the transistor 110 to a second target impedance, which is the output impedance of the second terminal 132 of the second output impedance matching circuit 133, and the first terminal 131 of the second output impedance matching circuit 133 is connected to the third terminal 113 of the transistor 110. The follow-up amplified signal generated at the third terminal 113 of the transistor 110 is output as a second amplified signal at the second terminal 132 of the second output impedance matching circuit 133 after passing through the second output impedance matching circuit 133.

[0034] In one example, the to-be-amplified signal and the two amplified signals can be radio frequency signals.

[0035] In the embodiments of the present application, the transistor 110 and the first output impedance matching circuit 123 form a first signal amplification link, and the transistor 110 and the second output impedance matching circuit 133 form a second signal amplification link, i.e., the to-be-amplified signal is amplified by the amplifier circuit 100 into two amplified signals: a first amplified signal and a second amplified signal. The amplifier circuit 100 uses a single transistor 110 to form two amplification links to amplify the to-be-amplified signal. Both of the two amplification links use the transistor 110 as a device for amplifying the signal.

[0036] Generally, the power consumption of an amplifier mainly depends on the power consumption of the transistor as an amplification device. Usually, two corresponding transistors are needed to amplify the to-be-amplified signal to generate two amplified signals, but in the embodiments of the present application, a single transistor is used to generate two amplified signals, which reduces the number of transistors used, thereby greatly reducing the power consumption of the amplifier circuit.

[0037] Figure 2A and 2B The principle schematic diagram of the amplifier circuit 100 is shown, wherein Figure 2A The working principle schematic diagram of generating the first amplified signal is shown, Figure 2B The working principle schematic diagram of generating the second amplified signal is shown. In the embodiments of the present application, the working principle of amplifying the to-be-amplified signal based on the transistor 100 can be equivalent to Figure 1 The amplifier circuit 100 shown in the figure can be equivalent to two radio frequency signal amplifiers, as Figure 2A and 2B shown.

[0038] The "transistor" described herein is a transistor that can amplify a signal, for example, it can be a field effect transistor, a triode, etc. Although the transistor 100 is shown as a field effect transistor in the drawings herein, this is only one example of the transistor used in the amplifier of the present application, and the present application is not limited thereto.

[0039] In the case that the transistor 110 is a field effect transistor, the first terminal 111 of the transistor 110 is a gate, the second terminal 112 of the transistor 110 is a drain, and the third terminal 113 of the transistor 110 is a source, then the amplifier circuit 100 can be equivalently decomposed into a common source amplifier and a source follower amplifier, as shown in Figure 2A and 2B respectively. In the case that the transistor 110 is a triode, the first terminal 111 of the transistor 110 is a base, the second terminal 112 of the transistor 110 is a collector, and the third terminal 113 of the transistor 110 is an emitter, then the amplifier circuit 100 can be equivalently decomposed into a common emitter amplifier and an emitter follower amplifier, as shown in Figure 2A and 2B respectively.

[0040] As shown in Figure 2A , the transistor 110, the first output impedance matching circuit 123, and the source / emitter equivalent impedance Z1 form an equivalent common source / emitter amplifier, where the equivalent impedance Z1 is the equivalent impedance of the first terminal 131 of the second output impedance matching circuit 133. In the example of Figure 2A , a first bias power signal is applied to the third terminal 125 of the first output impedance matching circuit 123 to provide normal working voltage / current for the transistor 110 of the common source / emitter amplifier. The to-be-amplified signal is input from the first terminal 111 of the transistor 110, becomes an inverted amplified signal after passing through the equivalent common source amplifier / emitter amplifier, and is output as a first amplified signal at the second terminal 122 of the first output impedance matching circuit 123.

[0041] As shown in Figure 2B , the transistor 110, the second output impedance matching circuit 133, and the drain / collector equivalent impedance Z2 form an equivalent source / emitter follower amplifier, where the equivalent impedance Z2 is the equivalent impedance of the first terminal 121 of the first output impedance matching circuit 123. In the example of Figure 2B , a second bias power signal is applied to the third terminal 135 of the second output impedance matching circuit 133 to provide normal working voltage / current for the transistor 110 of the source / emitter follower amplifier. The to-be-amplified signal input from the first terminal 111 of the transistor 110 becomes a follow-up amplified signal after passing through the equivalent source / emitter follower amplifier, and is output as a second amplified signal at the second terminal 132 of the second output impedance matching circuit 133.

[0042] In one example, the first and second bias supply signals can be appropriate voltage or current signals to provide appropriate DC operating currents for the transistor 110, so that both the second and third terminals 112 and 113 of the transistor 110 can operate in amplification. The "applying the first / second bias supply signal" as described herein can refer to providing a positive voltage signal, a negative voltage signal, or a ground signal, and can also refer to providing a current signal. For example, the first bias supply signal can be a positive voltage signal, and the second bias supply signal can be another different positive voltage signal, or the first bias supply signal can be a positive voltage signal, and the second bias supply signal can be a negative voltage signal or a ground. In another example, a third bias supply signal can also be connected to the first terminal 111 of the transistor 110 to provide a bias supply (voltage or current) for the first terminal 111, and the magnitudes (voltage or current values) of the first, second, and third bias supply signals can be adjusted so that the transistor 110 has appropriate second-terminal-to-first-terminal voltage and second-terminal-to-third-terminal voltage, and thus the transistor 110 is in a normal operating state.

[0043] Figure 3 A structure diagram of an amplifier circuit according to an embodiment of the present application is shown, wherein the amplifier circuit 100 further comprises a first bias circuit 124 and a second bias circuit 134. The first terminal 126 of the first bias circuit 124 is connected to the third terminal 125 of the first output impedance matching circuit 123 and is connected to a first bias supply signal. The first bias circuit 124 is configured to provide a bias supply (e.g., bias voltage / current) for the second terminal 112 of the transistor 110, and can also provide a radio frequency signal ground for the third terminal 125 of the first output impedance matching circuit 123.

[0044] The first terminal 136 of the second bias circuit 134 is connected to the third terminal 135 of the second output impedance matching circuit 133 and is connected to a second bias supply signal. The second bias circuit 134 is configured to provide a bias supply (e.g., bias voltage / current) for the third terminal 113 of the transistor 110, and can also provide a radio frequency signal ground for the third terminal 135 of the second output impedance matching circuit 133.

[0045] In Figure 3In the example shown in FIG. 1, the amplifier circuit 100 can further include an input impedance matching circuit 141 and a third bias circuit 142 connected at the first end 111 of the transistor 110. The first end 143 of the input impedance matching circuit 141 is connected to the input of the signal to be amplified, and the second end 144 of the input impedance matching circuit 141 is connected to the first end 111 of the transistor 110. The first end 146 of the third bias circuit 142 is connected to the third end 145 of the input impedance matching circuit 141. The input impedance matching circuit 141 is used to achieve input impedance matching for the amplifier circuit 100. The third bias circuit 142 is used to provide a bias source (e.g., bias voltage / current) for the first end 111 of the transistor 110, and can also provide a radio frequency signal ground for the third end 145 of the input impedance matching circuit 141.

[0046] In the above-described embodiments, two amplified signals, a first amplified signal and a second amplified signal, can be obtained by the amplifier circuit 100. The two amplified signals can be used separately or in combination. Figure 4A An example of using the first amplified signal and the second amplified signal in combination is shown. As shown in FIG. 1, the amplifier circuit 100 includes a combined output end 103 for outputting a combined signal of the first amplified signal and the second amplified signal. Figure 4A As shown in FIG. 1, the amplifier circuit 100 includes a combined output end 103 for outputting a combined signal of the first amplified signal and the second amplified signal. Figure 4A In the example shown in FIG. 1, the amplifier circuit 100 further includes an output impedance transforming circuit 150 connected at one end to the combined signal of the first amplified signal and the second amplified signal, and connected at the other end to the combined output end 103 for output impedance transforming of the combined signal. The output impedance transforming circuit 150 has a function of isolating direct current, and can be a λ / 4 impedance transformer or any other impedance transformer that can meet the requirements of the amplifier circuit according to the embodiments.

[0047] In the example shown in FIG. 1, the amplifier circuit 100 further includes an output impedance transforming circuit 150 connected at one end to the combined signal of the first amplified signal and the second amplified signal, and connected at the other end to the combined output end 103 for output impedance transforming of the combined signal. The output impedance transforming circuit 150 has a function of isolating direct current, and can be a λ / 4 impedance transformer or any other impedance transformer that can meet the requirements of the amplifier circuit according to the embodiments. Figure 4A In the example shown in FIG. 1, the amplifier circuit 100 further includes an output impedance transforming circuit 150 connected at one end to the combined signal of the first amplified signal and the second amplified signal, and connected at the other end to the combined output end 103 for output impedance transforming of the combined signal. The output impedance transforming circuit 150 has a function of isolating direct current, and can be a λ / 4 impedance transformer or any other impedance transformer that can meet the requirements of the amplifier circuit according to the embodiments. Figure 4B Another example of using the first amplified signal and the second amplified signal in combination is shown. Figure 4B The example shown in FIG. 2 is different from the example shown in FIG. 1 in that the second end 122 of the first output impedance matching circuit 123 and the second end 132 of the second output impedance matching circuit 133 are not directly connected, but are both connected to a signal combining device 151, i.e., the first amplified signal and the second amplified signal are input to the signal combining device 151, and the signal combining device 151 combines the first amplified signal and the second amplified signal. Figure 4A The example shown in FIG. 2 is different from the example shown in FIG. 1 in that the second end 122 of the first output impedance matching circuit 123 and the second end 132 of the second output impedance matching circuit 133 are not directly connected, but are both connected to a signal combining device 151, i.e., the first amplified signal and the second amplified signal are input to the signal combining device 151, and the signal combining device 151 combines the first amplified signal and the second amplified signal.

[0048] In the case of amplitude amplification of the signal, in order to achieve the best gain when the first amplified signal and the second amplified signal are combined for use, the phase difference between the crests of the first amplified signal and the second amplified signal needs to be 2nπ, where n is an integer. In an embodiment of the present application, the first output impedance matching circuit 123 and the second output impedance matching circuit 133 can be configured to make the phase difference between the crests of the first amplified signal and the second amplified signal 2nπ, where n is an integer.

[0049] In the case of amplitude amplification of the signal, in order to achieve the best noise or the best power or the best efficiency when the first amplified signal and the second amplified signal are combined for use, the circuit parameters of the first output impedance matching circuit 123 and the second output impedance matching circuit 133 can be adjusted, at which time the phase difference between the crests of the first amplified signal and the second amplified signal will be adjusted according to the performance optimization direction, but the phase difference is close to 2nπ, where n is an integer.

[0050] Here, the first amplified signal that has not yet passed through the first output impedance matching circuit 123, i.e., the inverted amplified signal input to the first end 121 of the first output impedance matching circuit 123 after being amplified through the second end 112 of the transistor 110, is referred to as S1', the second amplified signal that has not yet passed through the second output impedance matching circuit 133, i.e., the follow-up amplified signal input to the first end 131 of the second output impedance matching circuit 133 after being amplified through the third end 113 of the transistor 110, is referred to as S2', and the first amplified signal and the second amplified signal output from the second end 122 of the first output impedance matching circuit 123 and the second end 132 of the second output impedance matching circuit 133 are referred to as S1 and S2, respectively.

[0051] Figure 5A A schematic diagram showing the phase difference between the crests of the amplified signals S1', S2' that have not passed through the first output impedance matching circuit 123 and the second output impedance matching circuit 133 and the first amplified signal S1 and the second amplified signal S2 that have passed through the first output impedance matching circuit 123 and the second output impedance matching circuit 133 is shown. As Figure 5A shown, if the first output impedance matching circuit 123 and the second output impedance matching circuit 133 do not exist, or if the amplified signals do not pass through them, the phase difference between the inverted amplified signal S1' and the follow-up amplified signal S2' is π. If such two signals S1' and S2' are combined together, their crests and troughs are superimposed, resulting in a decrease or 0 in the amplitude of the combined signal, so that the gain is 0 or very small.

[0052] The embodiment of the present application changes this effect through the first output impedance matching circuit 123 and the second output impedance matching circuit 133. The inverted amplified signal S1' becomes the first amplified signal S1 after passing through the first output impedance matching circuit 123, and the following amplified signal S2' becomes the second amplified signal S2 after passing through the second output impedance matching circuit 133. The first output impedance matching circuit 123 changes the phase of the signal passing therethrough, assuming that the phase is changed by ΔΦ1, i.e., as shown in FIG. 6, the phase difference between S1' and S1 is ΔΦ1. Similarly, the second output impedance matching circuit 133 also changes the phase of the signal passing therethrough, assuming that the phase is changed by ΔΦ2, i.e., as shown in FIG. 7, the phase difference between S2' and S2 is ΔΦ2. In order to make the phase difference between the crests of S1 and S2 be 2nπ so that the combined signal thereof achieves the best gain, the values of ΔΦ1 and ΔΦ2 can be changed by adjusting the circuit parameters of the first output impedance matching circuit 123 and the second output impedance matching circuit 133 (for example, a series inductive device causes phase lag, a series capacitor causes phase lead, etc.), so that the absolute value of the difference between ΔΦ1 and ΔΦ2 is (2n-1)π, n being an integer, and after adding the initial phase difference π between S1' and S2', the phase difference between the crests of S1 and S2 is 2nπ. Figure 5A Figure 5A Figure 5B The effect schematic diagram of the combined signal of the amplified signals S1 and S2 with the phase difference of 2nπ is shown. As shown in FIG. 8, after the two amplified signals are combined, the crests of the signals are superimposed, and the troughs of the signals are superimposed, thereby achieving the best gain. Ideally, the gain is twice the amplification gain of the second end or the third end of the single transistor. In the embodiment, the gain is doubled using a single transistor, and the power consumption does not increase (still the power consumption of a single transistor), thereby improving the gain to power consumption ratio of the amplifier. Figure 5B

[0053] Figure 5A 5B Only one period of the signal is shown, and it can be understood that the signal to be amplified is a continuous signal including multiple periods, and therefore the signals S1', S1, S2', and S2 are also continuous signals including multiple periods.

[0054] Figure 6 The structural schematic diagram of the amplifier circuit 100 is shown, in which an example of the composition of the first output impedance matching circuit 123, the second output impedance matching circuit 133, and the input impedance matching circuit 141 is specifically shown.

[0055] In Figure 6 ​​​​In the example, the first output impedance matching circuit 123 includes a first inductive device L1, a second inductive device L2, and a third inductive device L3. The first end of the first inductive device L1 serves as the first end 121 of the first output impedance matching circuit 123. The second end of the first inductive device L1 is connected to the first end of the second inductive device L2. The second end of the second inductive device L2 serves as the third end 125 of the first output impedance matching circuit 123. The first end of the third inductive device L3 is connected to the second end of the first inductive device L1 and the first end of the second inductive device L2. The second end of the third inductive device L3 serves as the second end 122 of the first output impedance matching circuit 123.

[0056] The second output impedance matching circuit 133 includes a fourth inductive device L4, a fifth inductive device L5, and a first capacitor C1. The first end of the fourth inductive device L4 serves as the first end 131 of the second output impedance matching circuit 133. The second end of the fourth inductive device L4 is connected to the first end of the fifth inductive device L5. The second end of the fifth inductive device L5 serves as the third end 135 of the second output impedance matching circuit 133. The first end of the first capacitor C1 is connected to the second end of the fourth inductive device L4 and the first end of the fifth inductive device L5. The second end of the first capacitor C1 serves as the second end 132 of the second output impedance matching circuit 133.

[0057] like Figure 6 As shown, the input impedance matching circuit 141 includes a sixth sensing device L6, a seventh sensing device L7, and a second capacitor C2. The first terminal of the sixth sensing device L6 serves as the second terminal 144 of the input impedance matching circuit 141. The second terminal of the sixth sensing device L6 is connected to the first terminal of the seventh sensing device L7 and the second terminal of the second capacitor C2. The first terminal of the second capacitor C2 serves as the first terminal 143 of the input impedance matching circuit 141, and the second terminal of the seventh sensing device serves as the third terminal 145 of the input impedance matching circuit 141.

[0058] In this document, "inductive device" refers to any one of a microstrip line, an inductor, or a combination thereof. Each inductive device in the embodiments of this application can be any one of a microstrip line, an inductor, or a combination thereof.

[0059] In one example, the first inductive device L1 and the second inductive device L2 can be configured as an inductor pair with opposite directions of the induced magnetic field. In another example, the fourth inductive device L4 and the fifth inductive device L5 can be configured as an inductor pair with opposite directions of the induced magnetic field. In yet another example, the sixth inductive device L6 and the seventh inductive device L7 can be configured as an inductor pair with opposite directions of the induced magnetic field.

[0060] The inductance pair with opposite directions of the induced magnetic field can be referred to as a "low-coupling inductance pair". The inductances in the low-coupling inductance pair can be single-layer wiring spiral inductances or multi-layer wiring spiral inductances. In some examples, some or all of the inductance pairs L1 and L2, L4 and L5, and L6 and L7 can be arranged as low-coupling inductance pairs. In other examples, none of the inductance pairs can be arranged as low-coupling inductance pairs.

[0061] When the inductances are excited by signals, induced magnetic fields are generated, which generate induced electric fields, and the induced electric fields generate induced eddy currents in the substrate of the chip, resulting in energy loss. Therefore, the inductances L1 and L2 also have induced magnetic fields, and the induced electric fields generated by the induced magnetic fields generate induced eddy currents in the substrate of the chip, resulting in energy loss. The directions of the induced magnetic fields of the two inductances of the low-coupling inductance pair are configured to be opposite, so that the directions of the induced electric fields generated by the induced magnetic fields are also opposite, and the directions of the induced eddy currents generated by the two opposite induced electric fields are also opposite. The induced eddy currents with opposite directions can partially or completely cancel each other out, so that the induced eddy currents are reduced or eliminated, the energy loss is reduced, and the energy loss of the circuit is reduced.

[0062] In addition, since the eddy currents generated by the two inductances of the low-coupling inductance pair can cancel each other out, the two inductances can be arranged to be adjacent or closer to each other, so that the circuit structure is more compact, the size is reduced, and the cost is reduced.

[0063] In one example, the two inductances of the inductance pair can be configured to be adjacent and have opposite directions of the induced magnetic fields generated by the two inductances.

[0064] In one example, the two inductances of the inductance pair are both spiral inductances, and they can be arranged in the circuit with opposite spiral directions. For example, the spiral direction of one inductance is clockwise, and the spiral direction of the other inductance is counterclockwise.

[0065] In one example, the two inductances are arranged in the circuit to be mirror images of each other.

[0066] Figure 14 A schematic diagram of the arrangement of an inductance pair in an amplifier circuit according to an embodiment of the present application is shown. Figure 14 A schematic diagram of the inductance pair of the amplifier circuit is shown from the direction perpendicular to the wiring layer of the amplifier circuit. In one example, the amplifier circuit can be an integrated circuit chip.

[0067] As Figure 14As shown, the inductor pair 1400 includes two inductors, each of which is formed by a first microstrip line 1410 and a second microstrip line 1420, and the first microstrip line 1410 is wound into a first spiral pattern S1 and the second microstrip line 1420 is wound into a second spiral pattern S2. The first end 1401 and the second end 1402 of the first microstrip line 1410 are respectively the first end and the second end of the first inductor. The first end 1403 and the second end 1402 of the second microstrip line 1420 are respectively the first end and the second end of the second inductor. The second end 1402 of the first microstrip line 1410 and the second end 1402 of the second microstrip line 1420 are connected together to form a common end 1402 of the first inductor and the second inductor, and the first microstrip line 1410 and the second microstrip line 1420 form a combined microstrip line. The first end 1401 of the first inductor, the first end 1403 of the second inductor, and the second end 1402 of the first inductor and the second inductor are respectively connected to other parts of the radio frequency switch circuit through connection lines.

[0068] The combined microstrip line (first / second microstrip line) of the embodiment of the present application can be composed of single-layer or multi-layer metal materials. In one example, the combined microstrip line is composed of multi-layer metal materials, each of which is located in a different wiring layer of the radio frequency switch circuit. The multi-layer metal materials located in different wiring layers are superimposed together to form the combined microstrip line, and are connected through interlayer vias between the layers. In another example, the combined microstrip line is composed of single-layer metal materials, which can be located in the same or different wiring layers of the radio frequency switch circuit. For example, part of the single-layer metal materials is located in a wiring layer, and the other part is located in one or more different wiring layers. Similarly, the single-layer metal materials located in different wiring layers are connected through vias.

[0069] In Figure 14 In the example shown, both spiral patterns S1 and S2 include multiple turns, but it can be understood that they can also each include one turn, or one includes multiple turns and the other includes multiple turns.

[0070] As an example, the first microstrip line 1410 and the second microstrip line 1420 can be wound in opposite directions, so that the spiral directions of the first spiral pattern S1 and the second spiral pattern S2 are opposite, so that when the inductor pair is in operation, the directions of the induced magnetic fields caused by the currents in the microstrip lines forming the two spiral patterns S1 and S2 are opposite. For example, the spiral direction of one of S1 and S2 is counterclockwise, and the spiral direction of the other is clockwise. Here, the direction from the first end of the first or second inductor to the common end can be referred to as the spiral direction, or the direction from the common end to the first end of the first or second inductor can also be referred to as the spiral direction.

[0071] In Figure 14In this embodiment, the first microstrip line 1410 is wound from the first end 1401 to the common end 1402 in a counterclockwise direction, forming a first spiral pattern S1, from the inside out (inner turns first, then outer turns). Similarly, the second microstrip line 1420 is wound from the first end 1403 to the common end 1402 in a clockwise direction, forming a second spiral pattern S2, from the inside out (inner turns first, then outer turns). It is understood that one can be wound from the inside out and the other from the outside in (outer turns first, then inner turns), or both can be wound from the outside in. It is also understood that when winding the microstrip lines into spiral patterns S1 or S2, it is not necessary to always follow the inside-out or outside-in direction; the direction can be changed once or multiple times. For example, it can start from the inside out and then change to the outside-in direction midway, or vice versa.

[0072] In summary, each spiral pattern in S1 and S2 can wind the microstrip line from its respective first end to the common end in one of the following ways:

[0073] From the inside out;

[0074] From the outside in;

[0075] The combination of the two above.

[0076] exist Figure 14 In one embodiment, the two spiral patterns S1 and S2 do not overlap and are adjacent but spaced a certain distance D in a direction parallel to the wiring layer of the RF switch circuit. In this embodiment, as described above, due to the low mutual coupling between the two inductors, the two spiral patterns S1 and S2 can be arranged as close as possible (but without overlapping), thereby reducing circuit size and cost. In one example, the spacing between the two spiral patterns S1 and S2 (e.g., ...) is... Figure 14 The distance D shown can be as small as approximately 3 micrometers. The "spacing between two spiral patterns" mentioned here refers to the distance between the closest microstrip lines of the two spiral patterns. For example... Figure 14 As shown, distance D is the distance between the outermost adjacent turns of S1 and S2. In practice, the minimum spacing between the two spiral patterns is determined by the chip manufacturing process.

[0077] exist Figure 14 In the example, the first microstrip line 1410 and the second microstrip line 1420 are of equal length. That is, the common terminal 1402 is located at the midpoint of the merged microstrip line. It is understood that the common terminal 1402 may not be located at the midpoint of the merged microstrip line, but at other locations, such as closer to S1 or S2.

[0078] like Figure 14As shown, in this embodiment, the spiral patterns S1 and S2 are arranged in mirror image, both are mirror image patterns, in Figure 14 which are arranged in axial symmetry. That is, the spiral patterns S1 and S2 have the same configuration, for example, have the same number of turns, microstrip line width and spacing between adjacent turns, etc., except that their patterns are opposite (the winding way is opposite), both are in a symmetric / mirror image relationship about a plane perpendicular to the wiring layer located in the middle of the two. S1 and S2 can also be arranged in mirror image, for example, S1 and S2 have different configurations, for example, S1 and S2 have different number of turns, microstrip line width or spacing between adjacent turns, etc., as long as the induced magnetic field direction of the spiral pattern S1 and S2 wound is opposite.

[0079] It can be understood that, Figure 14 the arrangement of the first spiral pattern S1 and the second spiral pattern S2 in

[0080] In the inductor pair according to the above-mentioned embodiments of the present application, the microstrip lines of the two inductors have a common end and are arranged as two spiral patterns with opposite spiral directions, so that in the working state when an excitation signal is applied to the inductor pair, the directions of the induced magnetic fields generated by the currents in the two spirals are opposite, thereby at least partially reducing the mutual coupling / mutual inductance between the two inductors.

[0081] In the above-mentioned inductor pair embodiments, as shown in Figure 14 , the inductor pair is arranged in an integrated circuit chip to have three ends: a common end 1402, a head end 1401 as a first branch end of the inductor pair, and a tail end 1403 as a second branch end of the inductor pair. As mentioned before, the three ends of the inductor pair can be connected to an excitation signal or other circuit parts through leads. For example, a radio frequency excitation signal can be accessed from the common end 1402 of the inductor pair, and the radio frequency excitation signal is split into the first microstrip line (first inductor) and the second microstrip line (second inductor) at the common end 1402. The radio frequency excitation signal is generally a periodically varying signal, for example, a sinusoidal signal. Assuming that the excitation signal accessed at the common end 1402 is i com = I com ·sinωt. The excitation signal is split into two branches at the common end 1402, one branch flows through the first spiral pattern S1 of the common end 1402 to the first branch end (head end) 1401, and the other branch flows through the second spiral pattern S2 of the common end 1402 to the second branch end (tail end) 1403. Assuming that the excitation signal in the first spiral pattern S1 is i1(t), and the excitation signal in the second spiral pattern S2 is i2(t), if there is no reflection, then i1(t)+i2(t)=I com ·sinωt. If the common end is located at the midpoint of the merged microstrip line, and S1 and S2 are arranged in axial symmetry, then at any time, the excitation signals in S1 and S2 are exactly the same, that is, The excitation signals i1(t) and i2(t) in the inductive pair are periodic signals, the current magnitude of which changes periodically and unevenly, thus the induced magnetic field generated is also periodically and unevenly changed; the changed magnetic field in turn generates electric field, thus electromagnetic wave is generated. In the case that the excitation signals in S1 and S2 are completely the same, since the spiral directions of S1 and S2 are opposite, the induced magnetic field generated by S1 at any time is of the same magnitude and opposite direction to the induced magnetic field generated by S2, and the corresponding induced electric field is also of opposite direction and changes direction periodically. Therefore, the induced magnetic fields generated by S1 and S2 will almost completely cancel out in many areas, and will partially cancel out in some areas, thus the corresponding electric field or electromagnetic wave caused by the induced magnetic field will also be partially cancelled out, thereby reducing the loss of the inductive pair.

[0082] If the common end is not located at the midpoint of the merged microstrip line, or S1 and S2 are patterns with different configurations, it is possible that the excitation signals in S1 and S2 are not completely the same, thus the degree of mutual cancellation of the induced magnetic fields of S1 and S2 is weakened compared with the case that the excitation signals in S1 and S2 are completely the same, but the induced magnetic fields generated by S1 and S2 will still partially cancel out each other at any time, weaken the electromagnetic radiation intensity, and thus reduce the loss of the inductive pair to a certain extent.

[0083] It should be noted that, theoretically, the inductive pair with three ports (the common end, the first end of the merged microstrip line as the first branch end, and the tail end of the merged microstrip line as the second branch end) as described above is a passive lossless network, since the passive network has reciprocity, the loss and transmission characteristics of the inductive pair are reciprocal regardless of which port the excitation signal is input from.

[0084] The above description of the inductive pair applies to all inductive pairs L1 and L2, L4 and L5, L6 and L7 in the present application.

[0085] In the above embodiments, the first output impedance matching circuit 123 includes three inductive devices, and the second output impedance matching circuit 133 includes two inductive devices and one capacitor. Alternatively, the first output impedance matching circuit 123 can include two inductive devices and one capacitor, and the second output impedance matching circuit 133 can include three inductive devices, i.e. the third inductive device L3 is interchanged with the first capacitor C1, without affecting the normal operation of the amplifier circuit embodiments of the present application.

[0086] It can be understood that the above embodiments are only examples of the composition of the first output impedance matching circuit 123, the second output impedance matching circuit 133, and the input impedance matching circuit 141, and those skilled in the art can construct other variant embodiments on the basis of these examples without creative labor, which are also applicable to the embodiments of the present application and fall within the protection scope of the present application.

[0087] Figure 14 The structural schematic diagram of the amplifier circuit 100 is shown, in which an example of the composition of the first bias circuit 124 and the second bias circuit 134 is specifically shown.

[0088] As shown in Figure 7 , in this example, the first bias circuit 124 includes a sixth capacitor C6, a first end of the sixth capacitor C6 is taken as a first end 126 of the first bias circuit 124, i.e., connected to (accessed) a first bias power supply signal (such as the first bias power supply V1 shown in Figure 7 , and a second end of the sixth capacitor C6 is grounded. The first end of the sixth capacitor C6 is also connected to the second inductive device L2.

[0089] In an example, the resonance point frequency of the sixth capacitor C6 is close to or the same as the center frequency of the working frequency band of the amplifier circuit 100, for realizing the isolation of the amplifier circuit 100 from the radio frequency alternating current signal of the first bias power supply V1, while providing the radio frequency signal ground for the second end 125 of the second inductive device L2.

[0090] Figure 7 An example of the composition of the second bias circuit 134 is also shown. In this example, the second bias circuit 134 includes a fourth capacitor C4, a first end of the fourth capacitor C4 is connected to a second bias power supply signal (such as the second bias power supply V2 shown in Figure 7 , and taken as a first end 136 of the second bias circuit 134, connected to the second end 135 of the fifth inductive device L5, and a second end of the fourth capacitor C4 is grounded. In an example, the resonance point frequency of the fourth capacitor C4 is close to or the same as the center frequency of the working frequency band of the amplifier circuit 100, for realizing the isolation of the amplifier circuit 100 from the radio frequency alternating current signal of the second bias power supply V2, while providing the radio frequency signal ground for the second end 135 of the fifth inductive device L5.

[0091] In Figure 7 the embodiment shown, the values of the first bias power supply V1 and the second bias power supply V2 can be adjusted to make the transistor 110 work in a normal state, so that the second end 112 and the third end 113 of the transistor 110 can both amplify signals. For example, in Figure 7 , the second bias power supply V2 can be directly a ground signal.

[0092] Figure 8 and Figure 8 Two other examples of the composition of the second bias circuit 134 are shown.

[0093] In the example of Figure 9 , the second bias circuit 134 is ground (ground node), that is, the second end 135 of the fifth inductive device L5 is directly grounded. In this way, when the first bias power supply VI is a proper positive voltage, a proper direct current working current can be maintained between the second end 112 and the third end 113 of the transistor 110, so that the transistor 110 is in a normal working state.

[0094] In the example of Figure 8 , the second bias circuit 134 includes a fifth capacitor C5 and a first resistor R1, wherein the first end of the fifth capacitor C5 is connected with the first end of the first resistor R1 and serves as the first end 136 of the second bias circuit 134, and the second end of the fifth capacitor C5 and the second end of the first resistor R1 are grounded. In this example, the fifth capacitor C5 is used to couple the signal output by the third end 113 of the transistor 110 and after passing through the inductive devices L4 and L5 to the ground, to provide a radio frequency signal ground for the second end 135 of the fifth inductive device L5, and to reduce the energy loss of the second bias circuit 134. In addition, the first resistor R1 is used to raise the potential of the third end 113 of the transistor 110, so that the voltage of the first end 111 to the third end 113 of the transistor 110 is negative, to maintain the normal working of the amplifier circuit 100.

[0095] Figure 9 and 11 Two examples of the composition of the third bias circuit 142 are shown respectively.

[0096] In the example of Figure 10 , the third bias circuit 142 includes a third capacitor C3, the first end of the third capacitor C3 is connected to a third bias power supply signal (for example, a third bias power supply V3 as shown in Figure 10 ), and serves as the first end 146 of the third bias circuit 142 and is connected to the second end 145 of the seventh inductive device L7, and the second end of the third capacitor C3 is grounded. In this example, the resonance point frequency of the third capacitor C3 is close to or the same as the center frequency of the working frequency band of the amplifier circuit 100, which is used to realize the isolation of the amplifier circuit 100 and the radio frequency alternating current signal of the third bias power supply V3, and to provide a radio frequency signal ground for the second end 145 of the seventh inductive device L7.

[0097] In the example of Figure 10 , the third bias circuit 142 is ground (ground node), that is, the second end 145 of the seventh inductive device L7 is directly grounded.

[0098] In Figure 11 In the examples of the first biasing circuit 124, three example compositions of the second biasing circuit 134, and two example compositions of the third biasing circuit 142 are provided. Each example composition of the second biasing circuit 134 can be used in combination with any example composition of the third biasing circuit 142.

[0099] In addition, it can be understood that the above only shows example compositions of the first biasing circuit 124, the second biasing circuit 134, and the third biasing circuit 142, and a person of ordinary skill in the art can construct other variant embodiments on the basis of these examples without creative labor, which are also applicable to the embodiments of the present application, and fall within the protection scope of the present application.

[0100] In the above embodiments, three biasing power sources are involved: the first biasing power source V1 located at the second end 112 of the transistor 110, the second biasing power source V2 located at the third end 113 of the transistor 110, and the third biasing power source V3 located at the first end 111 of the transistor 110. In some embodiments of the present application, the power biasing mode of the amplifier circuit 100 can include single power self-biasing, double power biasing, and triple power biasing. For example, single power self-biasing can mean that only the first biasing power source V1 is provided by the outside world; double power biasing can mean that the first biasing power source V1 and the third biasing power source V3 are provided by the outside world; and triple power biasing can mean that the first biasing power source V1, the second biasing power source V2, and the third biasing power source V3 are provided by the outside world. Single power self-biasing is simple in power supply, double power biasing can achieve better power performance, and triple power biasing is conducive to energy saving. The power biasing mode can be configured according to actual application.

[0101] It should be understood that any control signal / voltage mentioned herein can be a separate control signal / voltage, or can be a shared / common control signal / voltage in any combination. It should be understood that any electrical ground mentioned herein can be a separate ground connection / node, or can be a shared / common ground node in any combination (ground can also refer to a relative ground, a floating ground, or some desired potential difference).

[0102] The embodiments of the present application also provide an integrated circuit chip comprising the amplifier circuit as described above, and an electronic device comprising such an integrated circuit chip. Figures 7-11 and Figure 12 are respectively shown in their schematic diagrams. As Figure 13As shown, the integrated circuit chip 300 can include the substrate 200 and an amplifier circuit 100 on the substrate 200, where the amplifier circuit 100 can be any embodiment of the amplifier circuit as described above. One amplifier circuit 100 can be used alone, or multiple amplifier circuits 100 can be used in cascade. In an example, the integrated circuit chip 300 can include one or more amplifier circuits 100, and the multiple amplifier circuits 100 can be multiple amplifier circuits used alone or multiple amplifier circuits used in cascade. The integrated circuit chip 300 can also be a multi-function or system chip in which the amplifier circuit 100 is integrated with other circuits.

[0103] An integrated circuit chip including an embodiment of the amplifier circuit of the present application can be used in an electronic device. As shown, the electronic device 400 includes the integrated circuit chip 300 as shown in Figure 12 Figure 13 Figure 12 The electronic device 400 can be a wireless device or any other electronic device that can use an amplifier circuit.

[0104] For example, a wireless device can be a user equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a base station, etc. A wireless device can also be a cellular phone, a smartphone, a tablet, a wireless modem, a personal digital assistant (PDA), a handheld device, a laptop computer, a smartbook, a netbook, a cordless phone, a wireless local loop (WLL) station, a Bluetooth device, etc. A wireless device can be capable of communicating with a wireless communication system, and can be capable of receiving signals from a broadcast station, from one or more satellites, etc. A wireless device can support one or more wireless communication technologies (e.g., 5G, LTE, CDMA2000, WCDMA, TD-SCDMA, GSM, 802.11, millimeter wave, etc.).

[0105] ​Those skilled in the art will appreciate that information and signals can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. It should be noted that the types of transistors and technologies can be substituted, rearranged, or otherwise modified to achieve the same results. For example, circuits shown as utilizing PMOS transistors can be modified to use NMOS transistors, and vice versa. As such, the amplifiers disclosed herein can be implemented using a variety of transistor types and technologies, and are not limited to those shown in the figures. For example, transistor types such as Si BJT, GaAs pHEMT or HBT, Si MOSFET, SiGe HBT or BiCMOS, GaN HEMT, InP HBT or pHEMT, or any other transistor technology can be used.

[0106] As used herein, the phrase “at least one of a list of items refers to any combination of those items (including single members). For example, “at least one of a, b, or c” is intended to cover a, b, c, a-b, a-c, b-c, and a-b-c, as well as any of the same elements taken in any combination (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c).

[0107] It is to be noted that, in the present document, relational terms such as “first” and “second”, and the like, can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

[0108] Unless the context clearly indicates otherwise, throughout the description and the claims, the words “comprise”, “comprising”, and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to”. Conditional language such as, among others, “can”, “could”, “might”, “may”, “e.g.”, and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that a discussed feature, element, structure, or act might be included or instrumental in some embodiments, but not in others. Furthermore, the words “herein”, “above”, “below”, and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions thereof. Where the context permits, words in the above DETAILED DESCRIPTION using the singular or plural number can also include the plural or singular number respectively.

[0109] It is to be understood that the application is not limited to the precise construction herein described and as shown in the drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. An amplifier circuit, characterized by The amplifier circuit comprises: a transistor having a first terminal, a second terminal and a third terminal, wherein a signal to be amplified is input from the first terminal of the transistor, and an inverted amplified signal is generated at the second terminal of the transistor and a following amplified signal is generated at the third terminal of the transistor after amplification by the transistor; a first output impedance matching circuit for matching the output impedance of the second terminal of the transistor to a first target impedance, the first target impedance being the output impedance of the second terminal of the first output impedance matching circuit, the first terminal of the first output impedance matching circuit being connected to the second terminal of the transistor, wherein the inverted amplified signal is output as a first amplified signal at the second terminal of the first output impedance matching circuit after passing through the first output impedance matching circuit; and a second output impedance matching circuit for matching the output impedance of the third terminal of the transistor to a second target impedance, the second target impedance being the output impedance of the second terminal of the second output impedance matching circuit, the first terminal of the second output impedance matching circuit being connected to the third terminal of the transistor, wherein the following amplified signal is output as a second amplified signal at the second terminal of the second output impedance matching circuit after passing through the second output impedance matching circuit; the transistor, the first output impedance matching circuit and the equivalent impedance of the drain or collector of the transistor form an equivalent common source amplifier or common emitter amplifier, wherein the equivalent impedance is the equivalent impedance of the first terminal of the second output impedance matching circuit.

2. The amplifier circuit of claim 1, wherein, The amplifier circuit further comprises a first biasing circuit, the first terminal of the first biasing circuit being connected to the third terminal of the first output impedance matching circuit.

3. The amplifier circuit of claim 2, wherein, The third terminal of the first output impedance matching circuit and the first terminal of the first biasing circuit are connected to a first biasing power supply signal.

4. The amplifier circuit of claim 1, wherein, The amplifier circuit further comprises a second biasing circuit, the first terminal of the second biasing circuit being connected to the third terminal of the second output impedance matching circuit.

5. The amplifier circuit of claim 4, wherein, The third terminal of the second output impedance matching circuit and the first terminal of the second biasing circuit are connected to a second biasing power supply signal.

6. The amplifier circuit according to claim 1, wherein: the transistor is a field effect transistor, the first terminal of the transistor is a gate, the second terminal of the transistor is a drain and the third terminal of the transistor is a source; or the transistor is a triode, the first terminal of the transistor is a base, the second terminal of the transistor is a collector and the third terminal of the transistor is an emitter.

7. The amplifier circuit of claim 1, wherein The amplifier circuit further comprises a synthetic output terminal for outputting a synthetic signal of the first amplified signal and the second amplified signal.

8. The amplifier circuit of claim 1, wherein, The first output impedance matching circuit and the second output impedance matching circuit are configured such that the phase difference between the wave crests of the first amplified signal and the second amplified signal is 2nπ, wherein n is an integer.

9. The amplifier circuit of claim 1, wherein, The first output impedance matching circuit comprises a first inductive device, a second inductive device and a third inductive device, wherein a first end of the first inductive device is a first end of the first output impedance matching circuit, a second end of the first inductive device is connected to a first end of the second inductive device, a second end of the second inductive device is a third end of the first output impedance matching circuit, a first end of the third inductive device is connected to the second end of the first inductive device and the first end of the second inductive device, and a second end of the third inductive device is a second end of the first output impedance matching circuit.

10. The amplifier circuit of claim 1, wherein, The second output impedance matching circuit comprises a fourth inductive device, a fifth inductive device and a first capacitor, wherein a first end of the fourth inductive device is a first end of the second output impedance matching circuit, a second end of the fourth inductive device is connected to a first end of the fifth inductive device, a second end of the fifth inductive device is a third end of the second output impedance matching circuit, a first end of the first capacitor is connected to the second end of the fourth inductive device and the first end of the fifth inductive device, and a second end of the first capacitor is a second end of the second output impedance matching circuit.

11. The amplifier circuit of claim 9, wherein, The first inductive device and the second inductive device are configured as an inductive pair with opposite directions of induced magnetic field.

12. The amplifier circuit of claim 10, wherein, The fourth inductive device and the fifth inductive device are configured as an inductive pair with opposite directions of induced magnetic field.

13. The amplifier circuit of claim 1, wherein, An input impedance matching circuit connected at the first end of the transistor is further included, wherein the signal to be amplified is connected from a first end of the input impedance matching circuit, and a second end of the input impedance matching circuit is connected to the first end of the transistor.

14. The amplifier circuit of claim 13, wherein, A third biasing circuit connected at the first end of the transistor is further included, and a first end of the third biasing circuit is connected to a third end of the input impedance matching circuit.

15. The amplifier circuit of claim 13, wherein, The input impedance matching circuit comprises a sixth inductive device, a seventh inductive device and a second capacitor, wherein a first end of the sixth inductive device is a second end of the input impedance matching circuit, a second end of the sixth inductive device is connected to a first end of the seventh inductive device and a second end of the second capacitor, a first end of the second capacitor is a first end of the input impedance matching circuit, and a second end of the seventh inductive device is a third end of the input impedance matching circuit.

16. The amplifier circuit of claim 15, wherein, The sixth inductive device and the seventh inductive device are configured as an inductive pair with opposite directions of induced magnetic field.

17. The amplifier circuit of claim 14, wherein The third biasing circuit is one of the following structures: a third capacitor, a first end of the third capacitor is connected to a third biasing power signal and is a first end of the third biasing circuit, and a second end of the third capacitor is grounded; or ground.

18. The amplifier circuit of claim 4, wherein, The second biasing circuit is one of the following structures: a fourth capacitor, a first end of the fourth capacitor is connected to a second biasing power signal and is a first end of the second biasing circuit, and a second end of the fourth capacitor is grounded; a fifth capacitor and a first resistor, a first end of the fifth capacitor is connected to a first end of the first resistor and is a first end of the second biasing circuit, and a second end of the fifth capacitor and a second end of the first resistor are grounded; or ground.

19. The amplifier circuit of claim 2, wherein, The first biasing circuit includes a sixth capacitor, a first end of the sixth capacitor being a first end of the first biasing circuit, and a second end of the sixth capacitor being grounded.

20. The amplifier circuit of claim 9, 10 or 15, wherein, The inductive device is any one of a microstrip line, an inductor, or a combination thereof.

21. An integrated circuit chip, characterized by An amplifier circuit as claimed in any one of claims 1-20, on a substrate.

22. An electronic device, comprising: An integrated circuit chip as claimed in claim 21.

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