Data correction and phase optimization in high speed receivers

Abstract

This application relates to data correction and phase optimization in high-speed receivers. In some implementations, a system for performing data correction includes an analog-to-digital converter (ADC) configured to receive differential data from a continuous-time linear equalizer (CTLE) and generate a bitstream including a plurality of data bits and a corresponding plurality of data symbol bits, a decision feedback equalization (DFE) block configured to receive the bitstream from the ADC and provide data to a clock and data recovery (CDR) block, and data correction circuitry. In some implementations, the data correction circuitry is configured to receive the bitstream from the ADC, determine whether to correct a data symbol bit, flip the data symbol bit in response to determining that the data symbol bit is to be corrected, and provide the plurality of data symbol bits including the flipped data symbol bit to the DFE.

Description

Technical Field

[0001] This application relates to data correction and phase optimization in high-speed receivers. Background Technology

[0002] A serializer / deserializer (SerDes) device can receive or capture incoming data at high speed. This high-speed data can then be processed through a high-loss channel. Therefore, errors or inaccuracies may exist in the received and / or processed data. However, it may be difficult to correct the received data, especially due to the relatively high speed of transmitting and / or receiving data. Summary of the Invention

[0003] This document discloses methods and systems for performing data correction and phase optimization in high-speed receivers.

[0004] According to some embodiments, a system for performing data correction includes: an analog-to-digital converter (ADC) configured to receive differential data from a continuous-time linear equalizer (CTLE) and generate a bit stream as output comprising a plurality of data bits and corresponding plurality of data symbol bits; a decision feedback equalizer (DFE) block configured to receive the bit stream from the ADC and provide the data to a clock and data recovery (CDR) block; and a data correction circuit system. The data correction circuit system may be configured to: receive the bit stream from the ADC; determine whether to correct the data symbol bits among the plurality of data symbol bits; in response to determining that the data symbol bits are to be corrected, toggle the data symbol bits; and provide the plurality of data symbol bits, including the toggled data symbol bits, to the DFE.

[0005] In some instances, to determine whether to correct the data sign bits, the data correction circuitry is configured to identify patterns in the values ​​of the plurality of data bits in the bit stream. In some instances, the patterns in the plurality of data bits include an increase and / or a decrease in the values ​​of the plurality of data bits relative to a threshold voltage. In some instances, the patterns include identifying more than a predetermined number of consecutive data sign bits among the plurality of data sign bits having the same value.

[0006] In some instances, to determine whether to correct the data sign bit, the data correction circuitry is configured to determine whether the value of the data bit associated with the data sign bit is within a predetermined threshold voltage. In some instances, the threshold voltage includes an intermediate value from the range of values ​​that the ADC is configured to output.

[0007] According to some embodiments, a method for performing data correction includes: receiving a bit stream from an analog-to-digital converter (ADC), the bit stream being generated as an output by the ADC based on differential data received from a continuous-time linear equalizer (CTLE), wherein the bit stream includes a plurality of data bits and corresponding plurality of data symbol bits; determining whether to correct a data symbol bit among the plurality of data symbol bits; in response to determining that the data symbol bit is to be corrected, flipping the data symbol bit; and providing the plurality of data symbol bits, including the flipped data symbol bit, to a decision feedback equalizer (DFE) block, the DFE block being configured to provide data to a clock and data recovery (CDR) block.

[0008] In some instances, determining whether to correct the data sign bits includes identifying a pattern among the values ​​of the plurality of data bits in the bit stream. In some instances, the pattern among the plurality of data bits includes an increase and / or decrease in the values ​​of the plurality of data bits relative to a threshold voltage. Identifying the pattern includes identifying more than a predetermined number of consecutive data sign bits among the plurality of data sign bits having the same value.

[0009] In some instances, determining whether to correct the data sign bit includes determining whether the value of the data bit associated with the data sign bit is within a predetermined threshold of the threshold voltage.

[0010] According to some embodiments, a system for performing phase optimization includes: an analog-to-digital converter (ADC) configured to receive differential data from a continuous-time linear equalizer (CTLE) and generate a bit stream as output comprising a plurality of data bits and corresponding plurality of data symbol bits; a decision feedback equalizer (DFE) block configured to receive the bit stream from the ADC and provide the data to a clock and data recovery (CDR) block; and a data correction circuit system. The data correction circuit system may be configured to: receive the bit stream from the ADC; determine a current error value associated with the bit stream; determine, based on the current error value, whether to perform phase adjustment of a sampling clock; in response to determining that phase adjustment will be performed, determine a phase offset to be applied to the sampling clock; and provide the determined phase offset to the CDR block, wherein providing the determined phase offset to the CDR block moves the edge of the sampling clock toward alignment with the center of the data bit waveform associated with the plurality of data bits.

[0011] In some instances, in order to determine the current error value, the data correction circuitry is configured to determine the number of values ​​of the data bits among the plurality of data bits within a predetermined range of the threshold voltage.

[0012] In some instances, the phase offset will be applied by the CDR block in conjunction with Mueller-Muller techniques to adjust the sampling clock.

[0013] In some instances, in order to determine whether to perform the phase adjustment, the data correction circuitry is configured to determine whether the current error value exceeds an error threshold.

[0014] In some instances, in order to determine the phase offset, the data correction circuitry is configured to: determine whether phase adjustment was previously applied; and in response to determining that phase adjustment was not previously applied, set the phase offset to have a value in a first direction.

[0015] In some instances, to determine the phase offset, the data correction circuitry is configured to: determine whether a phase adjustment was previously applied; in response to determining that a phase adjustment was previously applied, compare the current error value with a previous error value associated with the previous phase adjustment to generate a comparison; and set the phase offset to have a value and direction based on the comparison. In some instances, in response to the comparison indicating that the current error value is less than the previous error value, the phase offset is set to have the same direction as the direction associated with the previous phase adjustment. In some instances, in response to the comparison indicating that the current value is greater than the previous error value, the phase offset is set to have the opposite direction to the direction associated with the previous phase adjustment.

[0016] According to some implementations, a method for performing phase optimization includes: receiving a bit stream from an analog-to-digital converter (ADC), wherein the ADC generates the bit stream based on differential data received from a continuous-time linear equalizer (CTLE), and wherein the bit stream includes a plurality of data bits and corresponding plurality of data sign bits; determining a current error value associated with the bit stream; determining, based on the current error value, whether to perform phase adjustment of a sampling clock; in response to determining that phase adjustment will be performed, determining a phase offset to be applied to the sampling clock; and providing the determined phase offset to a clock and data recovery (CDR) block, wherein providing the determined phase offset to the CDR block causes the edge of the sampling clock to be moved toward alignment with the center of the data bit waveform associated with the data bits among the plurality of data bits.

[0017] In some instances, determining the current error value includes determining the number of values ​​of the data bits among the plurality of data bits within a predetermined range of the threshold voltage.

[0018] In some instances, determining the phase offset includes: determining whether a phase adjustment was previously applied; in response to determining that a phase adjustment was previously applied, comparing the current error value with a previous error value associated with the previous phase adjustment to generate a comparison; and setting the phase offset to have a value and direction based on the comparison. In some instances, in response to the comparison indicating that the current error value is less than the previous error value, setting the phase offset to have the same direction as the direction associated with the previous phase adjustment. In some instances, in response to the comparison indicating that the current value is greater than the previous error value, setting the phase offset to have a direction opposite to the direction associated with the previous phase adjustment.

[0019] A further understanding of the nature and advantages of the various embodiments can be achieved by referring to the remainder of the instruction manual and accompanying drawings. Attached Figure Description

[0020] Figure 1 This is a block diagram depicting an example of a receiver device 100 according to some implementation schemes.

[0021] Figure 2 This section describes examples of analog-to-digital converters (ADCs) based on some implementation schemes of digital filters and the data sign bits generated based on the ADC output.

[0022] Figure 3 This section illustrates examples of data correction based on some implementation schemes.

[0023] Figure 4 This is a flowchart of an example process for data correction based on some implementation schemes.

[0024] Figure 5 This is a diagram illustrating the leading and lagging clocks according to some implementation schemes.

[0025] Figure 6 This is a flowchart of an example process for phase optimization based on some implementation schemes. Detailed Implementation

[0026] Reference will now be made in detail to specific embodiments. Examples of these embodiments are illustrated in the accompanying drawings. It should be noted that these examples are described for illustrative purposes and are not intended to limit the scope of this disclosure. Rather, alternatives, modifications, and equivalents of the described embodiments are included within the scope of this disclosure as defined by the appended claims. Specific details are provided to facilitate a thorough understanding of the described embodiments. Some embodiments within the scope of this disclosure may be practiced without some or all of these details. Furthermore, well-known features may not have been described in detail for clarity.

[0027] A serializer / deserializer (SerDes) device can receive or capture incoming data at high speed. This high-speed data can then be processed through a high-loss channel. Therefore, errors or inaccuracies may exist in the received and / or processed data. However, it may be difficult to correct the received data, especially given the relatively high speeds of transmitting and / or receiving data.

[0028] This document describes techniques for data correction and phase optimization, which can be implemented on receiver devices (e.g., receiver devices in a SerDes system), as described below. Figure 1 As shown and described herein. In some implementations, a data sign bit may be assigned corresponding to the data bit value. For example, in response to a data bit value being greater than or equal to a threshold voltage (generally referred to herein as V). threshold The data sign bit can be assigned a 1, and can be set to 0 in response to a data bit value being less than a threshold voltage. Since the data sign bit is used to adjust the phase of the sampling clock used by the analog-to-digital converter (ADC) of the receiver device, the accuracy of the data sign bit is important. However, the data sign bit can be inaccurate, especially when the data bit value is close to the threshold voltage. Below (for example, in conjunction with...) Figures 2 to 4 This describes systems, methods, and techniques for performing data correction on data sign bits.

[0029] In some embodiments, phase optimization can be performed to substantially align the sampling clock edge (e.g., used by the ADC) with the center of the data bit waveform. By aligning the sampling clock edge with the center of the data bit waveform, data bit values ​​close to a threshold voltage (e.g., within a predetermined range of the threshold voltage) can be avoided, thereby improving overall data accuracy. In some embodiments, phase optimization can be performed by determining a phase offset for adjusting the phase of the sampling clock. For example, the phase offset can be provided as an offset using a Mueller-Muller technique to adjust the phase of the sampling clock. In some embodiments, the phase offset can be determined as an iterative process that minimizes an error metric, as described below. Figure 5 and 6 What is shown and described.

[0030] Figure 1 This is a block diagram depicting an example of receiver device 100. Receiver device 100 is primarily implemented in the digital domain using a combination of circuit components described herein. Receiver device 100 may include components for communication with upstream or downstream devices (…). Figure 1 (Not shown in the diagram) Connected Tx and Rx ports. Differential signaling can be used for Tx and / or Rx ports; however, single-ended implementations are also possible.

[0031] exist Figure 1In this circuit, a continuous-time linear equalizer (CTLE) 120 can be incorporated to process the received signal and equalize frequency-dependent losses experienced in the signal, for example, in a communication channel. The output of the CTLE 120 is coupled to the input of an ADC 124, which converts the equalized signal from the CTLE 120 into a digital data signal. For example, the ADC 124 can be implemented as a 5-bit time-interleaved ADC. The ADC 124 has an output that is coupled to pass the digital data signal to the input of a CDR 128 via a decision feedback equalizer (DFE) 132. The DFE 132 can be used as a nonlinear equalizer to suppress inter-symbol interference (ISI) caused by channel defects such as high-frequency losses and notch filters.

[0032] exist Figure 1 In this configuration, CDR 128 is a digital type, specifically a phase interpolator-based CDR, configured to communicate with a phase interpolator (PI), unlike conventional analog-type CDRs that typically communicate with analog circuit systems such as phase-locked loops (PLLs). Receiver device 100 further includes PI 148, which may include an adjustable current source to update the phase output of the sampling clock provided as an output clock signal to ADC 124. PI 148 may receive PI control from CDR 128 and the output of PLL 156.

[0033] exist Figure 1 In some embodiments, PLL 156 may be located external to receiver device 100, but in this example it is illustrated as part of receiver device 100 for ease of understanding. Illustrated, PLL 156 may be implemented as an all-digital PLL (ADPLL). PLL 156 outputs a fundamental clock signal to two PIs 148. A phase control signal delivered from CDR 128 to PIs 148 controls PIs 148 to change the phase of the fundamental clock signal. PIs 148 accordingly generate a corresponding output clock signal. PIs 148 provide the output clock signal to ADC 124.

[0034] In operation, the CDR 128 tracks the incoming bitstream of the digital data signal mentioned above and extracts both the embedded clock signal and the data components from the bitstream. In this example, the CDR 128 does this by checking the phase information of the data sampled from the ADC 124 and continuously updating the phase control signal to the PI 148. If the CDR 128 detects that the sampled data is ahead of the output clock signal provided from the PI 148 to the ADC 124, then the CDR 128 updates the phase control signal to increase the clock frequency accordingly, and vice versa. The goal is to align the base clock signal generated by the PLL 156 with the embedded clock signal and sample the data at optimal timing.

[0035] exist Figure 1 In this example, to illustrate, ADC 124 can be implemented as a 5-bit flash ADC with 2-bit interpolation. For example, ADC 124 can comprise four time-interleaved ADCs with an input bandwidth exceeding 10 GHz. As an example, the sampling clock of ADC 124 can operate at 5 GHz with an effective number of bits (ENOB) exceeding 4.5 bits. In such an implementation, DFE 132 can receive the output data from the four time-interleaved ADCs and process / optimize the DFE coefficients accordingly. CDR 128 can apply techniques or processes to adjust lead / lag sampling based on the output clock signal from PI 148.

[0036] Internal digital logic, state machines, and / or microcontrollers can be used to control and otherwise manage components of receiver device 100, including CTLE 120, ADC 124, CDR 128, FIFO 140, digital filter 152, and first and second PIs 144 and 148. The internal digital logic, state machines, and / or microcontrollers can also manage the auto-adjustment of CTLE 120 and DFE 132, and implement protocol link training and state updates.

[0037] refer to Figure 1 The ADC 124 can generate data bits, which can be the result of a series of comparators. For example, in the case where the ADC 124 is a 5-bit ADC, the ADC 124 can generate 5 data bits, which can produce values ​​from 0 to 31 as the result of 31 comparators. Based on the data bits generated by the ADC 124, a data sign bit indicating the sign of the data bits relative to a threshold voltage can be determined. Note that the threshold voltage is typically referred to as V in this document. threshold .

[0038] Figure 2 This illustrates an example of how data sign bits are generated according to some implementation schemes. For example, Figure 2 This describes the 5-bit ADC224. The ADC244 generates data bits corresponding to values ​​between 0 and 31. For example... Figure 2 As explained in the text, V threshold In the example where V=16, the DFE can set the data sign bit to 0 in response to data bit values ​​ranging from 0 to 15 (inclusive). Conversely, the DFE can set the data sign bit to 1 in response to data bit values ​​greater than or equal to 16. Note that, as described in this article, V... threshold The value is merely illustrative, and V threshold Other values ​​are possible.

[0039] Return to reference Figure 1The data symbol bits generated by ADC 124 are used by CDR 128 and DFE 132 to generate information for inter-symbol interference (ISI) compensation and phase control. Data correction and phase optimization block 160 corrects the data symbol bits to allow DFE 132 to perform correct compensation and improve the phase alignment performed by CDR 128. More detailed techniques for performing data correction (e.g., performed by data correction and phase optimization block 160) are described below. Figure 3 and 4 Show and describe.

[0040] Furthermore, the data correction and phase optimization block 160 can provide phase optimization information to the CDR 128, allowing the CDR 128 to adjust the phase compensation information. Specifically, as described below... Figure 5 and 6 As described, the data correction and phase optimization block 160 can provide phase optimization information to the CDR 128, which allows the sampling clock to be aligned with the center of the data bit waveform, thereby allowing the data correction technique described herein to be synchronized with the phase compensation.

[0041] In some implementations, this can be targeted at voltages with a threshold voltage (V) threshold The data sign bit is corrected for the corresponding data bits of a value within a predetermined range (e.g., + / -1, + / -2, etc.). In some embodiments, the data sign bit may be corrected in response to determining that the corresponding data bit is within the predetermined range and in response to determining that a specific pattern (e.g., a set of candidate patterns) exists before and / or after the data bits within the predetermined range.

[0042] Figure 3 This section describes two examples of data sign bits that have been corrected based on corresponding patterns in the data bits, according to some implementation schemes. Referring to the first example 310, a set of data bits 314 is received (e.g., from an ADC). Figure 3 In the example shown, the data bits of data bit group 314 are in the range of 0 to 31, and V threshold It is 16. In example 310, data bit group 314 has values ​​27, 28, 22, 16, and 24. This is because the data sign bit has a value greater than or equal to 16 in the corresponding data bit (i.e., V). threshold In the case of ), it is set to 1, so the pre-correction data sign bit group 312 is 1, 1, 1, 1, 1, because all values ​​of data bit group 314 are greater than 16 (i.e., V). threshold However, because the fourth value of the data bits in data bit group 314 (which has a value of 16) may be incorrect due to the lossy channel, the corresponding data symbol bit that is 1 in pre-corrected data symbol bit group 312 may also be incorrect. Therefore, the fourth data symbol bit can be corrected (e.g., by...). Figure 1The data correction and phase optimization block 160) is 0, as shown in the corrected data sign bit 316. The fourth data sign bit can be based on the fourth value of the data bit in V. threshold The correction is performed within a predetermined range and based on a pattern of values ​​associated with data bit group 314. For example, note that the values ​​of the data bits in the data bit group decrease above the second, third, and fourth values ​​(i.e., values ​​of 28, 22, and 16). In some embodiments, a decrease (or conversely, an increase) above a previous number (e.g., the first two, three, four, etc. data bits) can be identified as a pattern leading to the correction of the data sign bit. As another example, note that the values ​​of the data bits in data bit group 314 are non-monotonic above the second through fifth values. In other words, the fourth data bit value is 16, which decreases from the third data bit value of 22, and the fifth data bit value is 24, which increases from the fourth data bit value of 16. In some embodiments, non-monotonicity above a predetermined number of data bits (e.g., three data bits, four data bits, and five data bits, etc.) without a corresponding change in the data sign bit can be identified as a pattern leading to the correction of the data sign bit.

[0043] Referring to the second example 320, a set of data bits 324 is received (e.g., from an ADC), wherein the data bit set 324 has values ​​3, 2, 3, 15, and 6. Because all values ​​associated with the data bit set 324 are less than V... threshold Therefore, the pre-correction data sign bit group 322 has values ​​0, 0, 0, 0, and 0. However, in some embodiments, in response to determining the corresponding fourth data bit value (i.e., 15) in V threshold Within a predetermined range (e.g., + / -1, + / -2, etc.), the fourth data sign bit can be corrected to have a value of 1. Furthermore, note that there is an increase above the values ​​of the second, third, and fourth data bits (i.e., above values ​​2, 3, and 15). As described above, in some embodiments, an increase (or conversely, a decrease) above a previous number (e.g., the first two, three, four, etc. data bits) can be identified as a pattern leading to the correction of the data sign bit. As another example, note that the values ​​of the data bits in data bit group 324 are non-monotonic above the second to fifth values. As described above, in some embodiments, non-monotonicity above a predetermined number of data bits (e.g., three, four, and five data bits, etc.) without a corresponding change in the data sign bit can be identified as a pattern leading to the correction of the data sign bit.

[0044] Go to Figure 4 Examples of a process 400 for performing data correction are described below, based on some embodiments. In some implementations, the block of process 400 may consist of a data correction and phase optimization block of the receiver device (e.g., as described above in conjunction with...). Figure 1The data correction and phase optimization block 160 shown and described is executed. In some embodiments, the blocks of process 400 may differ from those shown and described. Figure 4 The process is executed in the order shown. In some implementations, two or more blocks of process 400 may be executed substantially in parallel. In some implementations, one or more blocks of process 400 may be omitted.

[0045] Process 400 can begin at 402 by receiving a bit stream output from the ADC, where the output contains data bits and a data sign bit. The data bits can have corresponding values ​​determined by the number of bits associated with the ADC. For example, in the case where the ADC is a 5-bit ADC, the data bits can have values ​​in the range of 0 to 31. The corresponding data bit values ​​can be determined relative to a threshold voltage V. threshold The comparison is used to assign a specific data sign bit. For example, for values ​​less than V... threshold The corresponding data value, the data sign bit can be set to 0, and for values ​​greater than or equal to V threshold The corresponding data value, the data sign bit can be set to 1.

[0046] At 404, process 400 may determine whether to perform data sign bit correction for a specific data sign bit contained in the bit stream. In some embodiments, process 400 may respond to determining the corresponding data bit value at a threshold voltage V. threshold Within a predetermined range (e.g., within + / -1, within + / -2, etc.), the data sign bit to be corrected is determined. As another example, process 400 may determine the data sign bit to be corrected in response to a specific pattern identified in the data bit values ​​associated with the bit stream received at block 402. Examples of specific patterns include increases or decreases over a predetermined number of data bit values ​​without variation in the data sign bit value and / or non-monotonicity over a predetermined number of data bit values ​​within a variation in the data sign bit value. In some embodiments, process 400 may determine a specific data sign bit to be corrected in response to the data sign bit being within a predetermined range of a threshold voltage and / or one or more patterns identified in the data bit values ​​of the bit stream.

[0047] If at 404, process 400 determines that the data sign bits of the bit stream are not corrected ("No" at 404), then process 400 can continue to block 408 and can provide the data bits and data sign bits received from the ADC to the DFE.

[0048] Conversely, if at 404, process 400 determines that one or more of the data sign bits in the bit stream will be corrected ("Yes" at 404), then process 400 may proceed to block 406 and may toggle the identified one or more data sign bits. For example, in an example where the pre-corrected data sign bit is 0, process 400 may toggle the data sign bit to 1, or vice versa. Note that in some embodiments, any suitable number of data sign bits (e.g., one, two, ten, etc.) may be toggled at block 406. Subsequently, process 400 may proceed to block 408 and provide the data bits and data sign bits (including the corrected data sign bits) to the DFE.

[0049] In some implementations, a phase adjustment offset is determined and provided to the CDR to allow the CDR to perform phase adjustment using the phase adjustment offset. Phase adjustment can be performed to adjust the PI phase to avoid the ADC sampling data bits close to a threshold voltage. Specifically, the phase of the sampling clock used by the ADC can be adjusted so that the clock edges are substantially aligned with the center of the data bit sample. In some embodiments, the CDR performs phase adjustment using a Mueller-Mueller technique. In some such embodiments, the phase adjustment offset is an offset applied to the Mueller-Mueller technique.

[0050] In some embodiments, where the sampling clock edge is designated as "leading," the phase offset can be negative, resulting in an increased phase. Conversely, where the sampling clock edge is designated as "lagging," the phase offset can be positive, resulting in a decreased phase. Applying the offset can help the CDR improve the phase alignment of a particular data pattern that is poorly aligned when the CDR is initially locked. Figure 5 Describe the instance waveform h(t) sampled using lead, lag, and optimal (or "locked") sampling clocks. For example... Figure 5 As explained in the text, with the sampling period T s Sample h(t). Sampling point 510a (at time τ) k -T s ), 510b (at time T) s (at) and 510c (at time τ) k +T s The location 520a corresponds to the sample obtained using a lead sampling clock. Sampling point 520a (at time τ) corresponds to the sample obtained using a lead sampling clock. k -T s ), 520b (at time T) s (at) and 520c (at time τ) k +T s The sampling point 530a corresponds to the sample obtained using a locked sampling clock. k -T s ), 530b (at time T)s (at) and 530c (at time τ) k +T s The position (t) corresponds to the sample obtained using a delayed sampling clock. As explained, in the case of a locked (i.e., optimal) sampling clock, due to the symmetry of the waveform h(t), h(τ) k -T s )=h(τ k +T s In the case of a leading sampling clock, since the sampling is shifted from the center of the data bit waveform, h(τ) k -T s ) <h(τ k +T s In the case of a delayed sampling clock, since the sampling is shifted in the opposite direction to the center of the data bits, h(τ) k -T s )>h(τ k +T s ).

[0051] Because the goal of phase compensation is to shift the sampling clock used by the ADC to be substantially aligned with the center of the data bit waveform (associated with the data pattern determined by potentially generating incorrect data sign bits), and thus minimize the number of sampled values ​​within a predetermined range of the threshold voltage, the phase offset can be determined by determining the number of data values ​​within the predetermined range of the threshold voltage in the bit stream of data values. The number of data values ​​within the predetermined range of the threshold voltage can be referred to as the error value. The phase offset that reduces the error value can then be determined. In other words, a phase offset that, when applied to the sampling clock, causes the ADC to sample in a manner that reduces the number of data values ​​within the predetermined range of the threshold voltage. In some embodiments, the phase offset can be iteratively adjusted until a phase offset that minimizes the error value is identified. For example, in response to determining that the error value exceeds a predetermined error threshold, a phase offset (e.g., phase increase or phase decrease) can be applied in a predetermined phase correction direction. Continuing this example, the phase offset applied in the predetermined phase correction direction can be used to determine an updated error value. In response to determining that the updated error value is less than the original error value (i.e., the applied phase offset is in the correct direction), the phase offset can continue to be applied in the same direction. For example, the phase offset can be further increased (where the initially applied phase correction was a phase increase), or the phase offset can be further decreased (where the initially applied phase correction was a phase decrease). Conversely, in response to determining that the updated error value is greater than the original error value (i.e., the applied phase offset is in the wrong direction), a modified phase offset can be applied in the opposite direction to the original phase offset. This process can be repeated until the error value is less than an error threshold, thereby allowing the phase of the sampling clock to be iteratively modified until it is substantially aligned with the center of the data bit waveform.

[0052] Figure 6 This is a flowchart illustrating an example process 600, according to some embodiments, for determining a phase adjustment offset to be applied to phase adjustment calculations to shift the sampling clock used by the ADC toward the center of the data bit waveform. In some embodiments, the phase offset may be applied to phase adjustment calculations using a Mueller-Mueller technique. In some embodiments, the blocks of process 600 may be defined by a data correction and phase optimization block of the receiver device (e.g., ...). Figure 1 The data correction and phase optimization block 160) is executed. In some embodiments, the blocks of process 600 may differ from those of the data correction and phase optimization block 160. Figure 6 The process is executed in the order shown. In some embodiments, two or more blocks of process 600 may be executed substantially in parallel. In some embodiments, one or more blocks of process 600 may be omitted.

[0053] Process 600 can begin at 602 by receiving a bit stream output from the ADC, where the output contains a series of data bit values ​​and corresponding data sign bits. Similar to the above combination... Figure 1 , 2 As described in section 4, the data bit values ​​can be within a range corresponding to the number of bits associated with the ADC. For example, for a 5-bit ADC, the data bit values ​​can be in the range of 0 to 31. Similar to the above... Figure 2 and 4 The described content can be based on data bit values ​​and threshold voltage (V). threshold The sign bit is set to correspond to a specific data bit value through a comparison. For example, in response to a data bit value greater than or equal to V... threshold The data sign bit can be set to 1. Conversely, in response to a data bit value less than V... threshold The data sign bit can be set to 0.

[0054] At 604, process 600 can determine a current error value corresponding to the number of data bit values ​​within a predetermined range of the threshold voltage. The predetermined range can be + / -1 of the threshold voltage, within + / -2 of the threshold voltage, etc. In some embodiments, process 600 can determine the current error value by identifying the number of data bit values ​​received at block 602 that are outside the predetermined range of the threshold voltage. For example, where the bit stream contains data bit values ​​24, 22, 16, 15, 8, 25, 30, and where the threshold voltage (V... threshold In the example where the value is 16 and the predetermined range is + / - 2 of the threshold voltage, the current error value can be determined to be 2 because there exists a value in V. threshold -2 to V threshold Two data bit values ​​(i.e., 16 and 15) within the range of +2 (i.e., within the range of 14 to 18).

[0055] At 606, process 600 may determine whether to perform phase adjustment. For example, process 600 may determine whether to perform phase adjustment based on the current error value determined at block 604. As a more specific example, process 600 may compare the current error value with an error threshold and may determine to perform phase adjustment in response to determining that the current error value meets or exceeds the error threshold. Conversely, process 600 may determine not to perform phase adjustment in response to determining that the current error value is less than the error threshold. In some embodiments, the error threshold may be a fixed error threshold. In some embodiments, the error threshold may depend on parameters associated with the bit stream, such as size, bit rate, etc. The error threshold may be a user-configurable or design-specific value.

[0056] If at 606, process 600 determines that phase adjustment will not be performed ("No" at 606), then process 600 can loop back to block 602 and can receive additional bit stream output from the ADC.

[0057] Conversely, if at 606, process 600 determines that a phase adjustment will be performed ("Yes" at 606), then process 600 may continue to block 608 and may determine whether a phase adjustment was previously performed, for example, in a previous iteration of process 600. In other words, at block 606, process 600 may determine whether the current iteration or cycle of process 600 is the first iteration of process 600 or a subsequent iteration of process 600. In some embodiments, process 600 may determine whether a phase adjustment will be performed based on a cycle counter indicating whether the current iteration of process 600 is the first iteration or a subsequent (e.g., second, third, fourth, etc.) iteration of process 600.

[0058] If at block 608, process 600 determines that phase adjustment has not been performed previously ("No" at block 608), then at block 610, process 600 may apply a phase offset in a predetermined initial direction. The predetermined initial direction may be phase increasing or phase decreasing. For example, in some embodiments, all initial phase offsets may be in the phase increasing direction. As another example, in some embodiments, all initial phase offsets may be in the phase decreasing direction. In some embodiments, process 600 may set the initial phase offset to an initial offset value (e.g., 2, 3, 4, 10, etc.). Process 600 may then loop back to block 602 and receive additional bitstream data.

[0059] Conversely, if at box 608, process 600 determines that a phase adjustment has been previously performed ("Yes" at box 608), then at 612, process 600 may determine whether the current error value (e.g., determined at box 604) is less than the previous error value associated with the previously performed phase adjustment.

[0060] If, at box 612, process 600 determines that the current error value is less than the previous error value associated with the previously performed phase adjustment, then at 614, process 600 can determine the phase offset in the same direction as the previous phase offset. In other words, since the current error value is less than the previous error value associated with the previously performed phase adjustment, the previously performed phase adjustment was in the correct direction. Therefore, process 600 can determine the phase offset in the same direction as the previously performed phase adjustment. For example, in an example where the previously performed phase adjustment corresponds to a phase increase, process 600 can determine the phase offset as also corresponding to a phase increase. Conversely, in an example where the previously performed phase adjustment corresponds to a phase decrease, process 600 can determine the phase offset as also corresponding to a phase decrease.

[0061] In some embodiments, process 600 may increase the amount of the phase offset relative to a previously applied phase offset. For example, in an example where the previously applied phase offset is +4 (e.g., corresponding to a phase increase), process 600 may set the phase offset to +6, +8, +10, or any other suitable value.

[0062] Conversely, if at block 612, process 600 determines that the current error value is greater than the previous error value associated with the previously performed phase adjustment, then at 616, process 600 can determine a phase offset opposite to the previous phase offset direction. In other words, since the current error value is greater than the previous error value associated with the previously performed phase adjustment, the previously performed phase adjustment was in the wrong direction. Therefore, process 600 can determine a phase offset in the opposite direction to the previously performed phase adjustment. For example, in an example where the previously performed phase adjustment corresponds to a phase increase, process 600 can determine that the phase offset corresponds to a phase decrease. Conversely, in an example where the previously performed phase adjustment corresponds to a phase decrease, process 600 can determine that the phase offset corresponds to a phase increase.

[0063] In some embodiments, process 600 may increase the amount of the phase offset relative to a previously applied phase offset. For example, in an example where the previously applied phase offset is +4 (e.g., corresponding to a phase increase), process 600 may set the phase offset to -6, -8, -10, or any other suitable value with the opposite phase adjustment direction. Alternatively, in some embodiments, process 600 may maintain the amount of the previously applied phase offset and switch the direction of the phase adjustment. For example, in an example where the previously applied phase offset is +4 (e.g., corresponding to a phase increase), process 600 may set the phase offset to -4.

[0064] Regardless of whether the phase adjustment direction is maintained (e.g., at block 614) or reversed (e.g., at block 616), process 600 can loop back to block 602 and receive additional bitstream data. The phase offset can then be applied to the additional bitstream data and further adjusted based on subsequent iterations of process 500. This process can be repeated until the current error value is less than an error threshold, at which point it can be determined that the sampling clock is properly aligned with the center of the data bit waveform.

[0065] It should be noted that the phase shift, whether initially determined (e.g., at box 610), a phase shift in the same direction as the previously applied phase shift (e.g., at box 614), or a phase shift in the opposite direction to the previously applied phase shift (e.g., at box 616), can be applied as an offset constant in the Mueller-Mueller technique. For example, as described above... Figure 5 As described, given h(τ) k -T s ), h(τ) k ) and h(τ k +T s ) continuous data waveform samples, in a sampling time period of T s In this case, the optimal or locked state is represented as h(τ) k -T s )=h(τ k +T s The leading clock condition is represented as h(τ). k -T s ) <h(τ k +T s ), and the lag clock condition is represented by h(τ) k -T s ) <h(τ k +T s Given that:

[0066] h(τ k -T s ) = X k-1 *A k

[0067] h(τ k +T s ) = X k *A k-1

[0068] Given the above, the leading clock condition can be represented as:

[0069] X k *A k-1 -X k-1 *A k >0

[0070] In such examples, a phase shift, denoted as α, can be used to shift the leading clock condition toward the locked clock condition by subtracting the phase shift as follows (i.e., by making the left side of the above equation closer to 0):

[0071] X k *A k-1 -X k-1 *A k -α

[0072] Conversely, the lag clock condition can be represented as:

[0073] X k *A k-1 -X k-1 *A k <0

[0074] In such cases, a phase shift α can be added as follows to shift the lag clock condition toward the lock clock condition (i.e., by making the left side of the above equation closer to 0):

[0075] X k *A k-1 -X k-1 *A k +α

[0076] Those skilled in the art will understand that changes may be made to the form and details of the embodiments described herein without departing from the scope of this disclosure. Furthermore, although various advantages, aspects, and objectives have been described with reference to various embodiments, the scope of this disclosure should not be limited by reference to these advantages, aspects, and objectives. Rather, the scope of this disclosure should be determined by reference to the appended claims.

Claims

1. A system for performing data correction, comprising: An analog-to-digital converter (ADC) configured to receive differential data from a continuous-time linear equalizer (CTLE) and generate a bit stream as output, including multiple data bits and corresponding multiple data sign bits. A decision feedback equalizer (DFE) block, configured to receive the bit stream from the ADC and provide the data to a clock and data recovery (CDR) block; and The data correction circuit system is configured to: Receive the bit stream from the ADC. Determine whether to correct the data sign bit among the plurality of data sign bits. In response to determining that the data sign bit needs to be corrected, the data sign bit is flipped, and The plurality of data sign bits, including the inverted data sign bit, are provided to the DFE.

2. The system of claim 1, wherein, in order to determine whether to correct the data sign bit, the data correction circuit system is configured to identify a pattern among the values ​​of the plurality of data bits of the bit stream.

3. The system of claim 2, wherein the pattern of the plurality of data bits includes an increase and / or a decrease in the value of the plurality of data bits relative to a threshold voltage.

4. The system of claim 2, wherein the mode includes identifying more than a predetermined number of consecutive data symbol bits among the plurality of data symbol bits having the same value.

5. The system of claim 1, wherein, in order to determine whether to correct the data sign bit, the data correction circuit system is configured to determine whether the value of the data bit associated with the data sign bit is within a predetermined threshold of a threshold voltage.

6. The system of claim 5, wherein the threshold voltage includes an intermediate value of the range of values ​​that the ADC is configured to output.

7. A method for performing data correction, comprising: A bit stream is received from an analog-to-digital converter (ADC), the bit stream being generated by the ADC as an output based on differential data received from a continuous-time linear equalizer (CTLE), wherein the bit stream includes multiple data bits and corresponding multiple data sign bits; Determine whether to correct the data sign bit among the plurality of data sign bits; In response to determining that the data sign bit needs to be corrected, the data sign bit is toggled; and The plurality of data sign bits, including the inverted data sign bits, are provided to the Decision Feedback Equalization (DFE) block, which is configured to provide data to the Clock and Data Recovery (CDR) block.

8. The method of claim 7, wherein determining whether to correct the data symbol bit includes identifying a pattern among the values ​​of the plurality of data bits of the bit stream.

9. The method of claim 8, wherein the pattern of the plurality of data bits includes an increase and / or a decrease in the value of the plurality of data bits relative to a threshold voltage.

10. The method of claim 8, wherein identifying the pattern comprises identifying more than a predetermined number of consecutive data sign bits among the plurality of data sign bits having the same value.

11. The method of claim 7, wherein determining whether to correct the data sign bit includes determining whether the value of the data bit associated with the data sign bit is within a predetermined threshold of the threshold voltage.

12. A system for performing phase optimization, comprising: An analog-to-digital converter (ADC) configured to receive differential data from a continuous-time linear equalizer (CTLE) and generate a bit stream as output, including multiple data bits and corresponding multiple data sign bits. A decision feedback equalizer (DFE) block, configured to receive the bit stream from the ADC and provide the data to a clock and data recovery (CDR) block; and The data correction circuit system is configured to: Receive the bit stream from the ADC. Determine the current error value associated with the bit stream. Based on the current error value, determine whether to perform phase adjustment of the sampling clock. In response to determining that a phase adjustment will be performed, the phase offset to be applied to the sampling clock is determined, and The determined phase offset is provided to the CDR block, wherein providing the determined phase offset to the CDR block causes the edge of the sampling clock to move toward the center of the data bit waveform associated with the data bits in the plurality of data bits.

13. The system of claim 12, wherein, in order to determine the current error value, the data correction circuit system is configured to determine the number of values ​​of the data bits among the plurality of data bits within a predetermined range of a threshold voltage.

14. The system of claim 12, wherein the phase offset is to be applied by the CDR block in conjunction with Mueller-Mueller technology to adjust the sampling clock.

15. The system of claim 12, wherein, in order to determine whether to perform the phase adjustment, the data correction circuitry is configured to determine whether the current error value exceeds an error threshold.

16. The system of claim 12, wherein, in order to determine the phase offset, the data correction circuit system is configured to: Determine whether phase adjustment was previously applied; and In response to determining that phase adjustment has not been previously applied, the phase offset is set to have a value in the first direction.

17. The system of claim 12, wherein, in order to determine the phase offset, the data correction circuit system is configured to: Determine whether phase adjustment was previously applied; In response to determining that a previous phase adjustment was applied, the current error value is compared with a previous error value associated with the previous phase adjustment to generate a comparison; and The phase offset is set to have a value and direction based on the comparison.

18. The system of claim 17, wherein in response to the comparison indicating that the current error value is less than the previous error value, the phase offset is set to have the same direction as the direction associated with the previous phase adjustment.

19. The system of claim 18, wherein in response to the comparison indicating that the current value is greater than the previous error value, the phase offset is set to have a direction opposite to the direction associated with the previous phase adjustment.

20. A method for performing phase optimization, comprising: A bit stream is received from an analog-to-digital converter (ADC), wherein the ADC generates the bit stream based on differential data received from a continuous-time linear equalizer (CTLE), and wherein the bit stream includes a plurality of data bits and a corresponding plurality of data sign bits. Determine the current error value associated with the bit stream; Based on the current error value, determine whether to perform phase adjustment of the sampling clock; In response to determining that a phase adjustment will be performed, a phase offset to be applied to the sampling clock is determined; and The determined phase offset is provided to the clock and data recovery (CDR) block, wherein providing the determined phase offset to the CDR block causes the edge of the sampling clock to move toward the center of the data bit waveform associated with the data bits in the plurality of data bits.

21. The method of claim 20, wherein determining the current error value comprises determining the number of values ​​of the data bits among the plurality of data bits within a predetermined range of the threshold voltage.

22. The method of claim 20, wherein determining the phase offset comprises: Determine whether phase adjustment was previously applied; In response to determining that a previous phase adjustment was applied, the current error value is compared with a previous error value associated with the previous phase adjustment to generate a comparison; and The phase offset is set to have a value and direction based on the comparison.

23. The method of claim 22, wherein in response to the comparison indicating that the current error value is less than the previous error value, the phase offset is set to have the same direction as the direction associated with the previous phase adjustment.

24. The method of claim 22, wherein in response to the comparison indicating that the current value is greater than the previous error value, the phase offset is set to have a direction opposite to the direction associated with the previous phase adjustment.

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