DC-dc voltage control architecture with smooth switching pulse frequency modulation and load line compensation

Abstract

DC-DC power converters with closed loop error compensation can operate in pulse width modulation (PWM) mode and pulse frequency modulation (PFM) mode. The DC-DC power converter includes type III compensation, which can operate in PWM mode and PFM mode. The use of a bypass switch on the output inductance of the power converter can increase the stability of the loop including type III compensation.

Description

Technical Field

[0001] This invention relates to power management of semiconductor devices, and more particularly to pulse frequency modulation and / or load line operation of power converters that use Type III compensators in their power conversion control feedback loop. Background Technology

[0002] Integrated circuits typically require power to operate under specific parameter conditions. This process involves many complexities. For example, different components within a semiconductor chip may require power at the same or different times, different components may require different power parameters, and some components may use different power levels at different times. This is especially true for chips that integrate multiple components; such chips are considered systems-on-a-chip (SoCs).

[0003] In many applications, it is necessary to minimize power supply for various reasons, such as reducing component heat generation and / or reducing unnecessary depletion of available battery power. In some applications, it may also be necessary to supply power in a manner that prevents discrete variations in the power required by the circuit from causing transients that would degrade circuit performance, or to avoid providing excessive power to the circuit. Summary of the Invention

[0004] This invention provides a DC-DC power converter with closed-loop error compensation, which can operate in both pulse width modulation (PWM) and pulse frequency modulation (PFM) modes. The invention also provides a modification to the DC-DC power converter with Type III compensation for operation in PWM mode, providing operation in PFM mode. Furthermore, the invention provides the use of a bypass switch for the output inductor of the power converter, which can increase the stability of the loop, including Type III compensation.

[0005] This invention provides a DC-DC power converter having a power regulation feedback loop (including a Type III compensation circuit) and a freewheeling feedback loop (including a power stage replication), either of which is selectively activated according to output power requirements. The power regulation feedback loop is used to implement the power converter in PWM mode. The freewheeling feedback loop is sometimes used to implement the power converter in PFM mode. The freewheeling feedback loop is used to operate the power converter in PWM mode under certain conditions. The freewheeling feedback loop includes a load line replication, which can be used to clamp the duty cycle of the PWM mode. The duty cycle of the PWM mode is clamped under high load conditions. A state machine is used to determine whether the power converter uses the power regulation feedback loop or the freewheeling feedback loop. The state machine is also used to determine whether the converter operates in load line mode (which can be considered an adaptive voltage positioning mode in this invention). The state machine is used to determine whether the converter uses load line replication to clamp the duty cycle of the PWM mode. The state machine is used to determine whether the power converter operates in PWM mode or PFM mode. The power converter has a buck configuration.

[0006] This invention provides a DC-DC power converter, comprising: a power stage and an output inductor and an output capacitor for coupling to a load; a first feedback loop including a Type III compensator for determining the duty cycle of the power stage based on the output voltage supplied to the load; a second feedback loop including a replica power stage, a replica output inductor, and a replica output capacitor for determining the duty cycle of the power stage; and configuration logic circuitry for selecting the use of the first feedback loop in a first operating mode and the second feedback loop in a second operating mode. It also provides a third operating mode in which a replica load is selectively coupled to the second feedback loop, and the logic circuitry also configures the selection of the replica load to be coupled to the second feedback loop. The first operating mode is a voltage regulation operating mode, the second operating mode is a pulse frequency modulation (PFM) freewheeling operating mode, and the third operating mode is a load line operating mode. The power stage switches operate in pulse width modulation (PWM) mode during the first operating mode.

[0007] This invention provides a DC-DC power converter, comprising: a power stage and an output inductor and an output capacitor for coupling to a load; a first feedback loop including a Type III compensator for determining the duty cycle of the power stage based on the output voltage supplied to the load; a second feedback loop including a replica power stage, a replica output inductor, and a replica output capacitor for determining the duty cycle of the power stage; and configuration logic circuitry for selecting the first feedback loop to be used in a first operating mode and a second feedback loop in a second operating mode. It also provides a third operating mode in which a replica load is selectively coupled to the second feedback loop, and the logic circuitry also configures the selection of the replica load to be coupled to the second feedback loop. The first operating mode is a voltage-regulated operating mode, the second operating mode is a pulse-frequency modulation (PFM) freewheeling operating mode, and the third operating mode is a load-line operating mode. The voltage-regulated operating mode is a pulse-width modulation (PWM) operating mode. If the output voltage supplied to the load is greater than a first voltage, and a signal indicating the duty cycle indicates lower power usage of the load, the logic circuitry is configured to transition from selecting the PWM operating mode to the PFM freewheeling operating mode. When the logic circuit is configured to transition from PFM freewheeling mode to PWM mode when the output voltage supplied to the load is less than a second voltage, the logic circuit is also configured to transition from PWM mode to load-line mode when the output voltage supplied to the load is less than a second voltage. When the logic circuit is configured to transition from load-line mode to PWM mode when the output voltage supplied to the load is greater than a first voltage, the logic circuit is configured to transition from load-line mode to PWM mode. The power stage includes a high-side switch and a low-side switch coupled in series between a higher voltage source and a lower voltage source. A first terminal of an output inductor is coupled to a node between the high-side and low-side switches, and a second terminal of the output inductor is coupled to ground via an output capacitor. Some embodiments also include a bypass switch coupling the first and second terminals of the output inductor. The power stage controller controls the operation of the high-side switch, the low-side switch, and the bypass switch. A replica power stage includes a replica high-side switch and a replica low-side switch coupled in series between a higher voltage source and a lower voltage source. A first terminal of a resistor is coupled to a node between the replica high-side and replica low-side switches, and a second terminal of the resistor is coupled to ground via a replica output capacitor.

[0008] This invention provides a DC-DC power converter, comprising: a buck power converter; a power regulation feedback loop including a type III compensation circuit selectively coupled to the buck power converter; a freewheeling feedback loop including a replica power stage selectively coupled to the buck power converter; and a state machine configured to generate a signal to control the coupling of the power regulation feedback loop to the buck power converter, or to control the coupling of the freewheeling feedback loop to the buck power converter, based on the output voltage of the buck power converter and / or the duty cycle of the buck power converter. In some embodiments, the power regulation feedback loop is configured to operate the buck power converter in pulse width modulation (PWM) mode. The freewheeling feedback loop is configured to operate the buck power converter in pulse frequency modulation (PFM) mode. The freewheeling feedback loop includes a replica load line selectively coupled to the replica power stage, and the freewheeling feedback loop is configured to operate the buck power converter in pulse width modulation (PWM) mode with a clamping duty cycle, the replica load line being selectively coupled to the replica power stage. In some embodiments, the state machine is also configured to generate a signal for controlling the coupling of the replica load line to the replica power stage based on the buck power converter's operating duty cycle.

[0009] The details of this invention are more fully covered in the examination disclosure. Attached Figure Description

[0010] Figure 1 This is a semi-modular block diagram and semi-schematic diagram of a DC-DC power converter, based on part of the present invention.

[0011] Figure 2 This is an example state diagram of a state machine in operation, such as a state machine. Figure 1 According to part of the present invention.

[0012] Figure 3 This is a semi-modular block diagram; the semi-schematic diagram is for a DC-DC power converter. Figure 1 It has a voltage regulation feedback loop during operation.

[0013] Figure 4 This is a semi-modular block diagram; the semi-schematic diagram is for a DC-DC power converter. Figure 1 It operates in PFM mode in conjunction with the freewheeling feedback loop.

[0014] Figure 5 This is a semi-modular block diagram; the semi-schematic diagram is for a DC-DC power converter. Figure 1 The operation uses a freewheeling feedback loop and employs load line operation.

[0015] Figure 6 The diagram shows the power stage and output components of a DC-DC power converter, as well as the related logic elements used to determine the switching state of the power stage switches.

[0016] Figure 7A and 7B The diagram shows a complementary curve representing the duty cycle versus the reciprocal of the load current.

[0017] Figure 8 It is a graph illustrating the load line adjustment curve under the background of voltage and load regulation.

[0018] Figure 9 Transient response damping achieved by using a bypass switch is shown. Detailed Implementation

[0019] Figure 1 This is a half-module block diagram and half-schematic representation of a DC-DC power converter according to a portion of the present invention. The DC-DC power converter can be considered to provide a voltage control mode with seamless PFM and load line operation. The power converter includes a power stage, an output inductor, and an output capacitor in a buck configuration. For power stage 111, a high-side switch 113a and a low-side switch 113b are coupled in series between a higher voltage source (e.g., Pvdd) and a lower voltage source (e.g., ground). In operation, the high-side switch may be in the open state while the low-side switch is in the off state, the low-side switch may be in the open state while the high-side switch is in the off state, or both switches may be in the off state. A first terminal of the output inductor 115 is coupled to a node between the high-side and low-side switches. A second terminal of the inductor is coupled to ground via an output capacitor 117. A bypass switch 121, optional in some embodiments, couples the first and second terminals of the inductor. The node between the second terminal of the inductor and the output capacitor provides the converter's output. The load 119, connected in parallel with the output capacitor, receives power from the output of the converter.

[0020] The power stage controller 112 controls the operation of the high-side and low-side switches, as well as the bypass switch (if present). In some embodiments, the controller controls the operation of the high-side and low-side switches based on the content of what can be considered a pulse width modulation (PWM) signal. As described herein, the PWM signal can be used to operate the switches in PWM mode, or in pulse frequency modulation (PFM) mode by using a pulse jump. The controller also receives a signal Sel4 from state machine 155, indicating that the controller should perform a pulse jump operation to operate the switches in PFM mode. The controller receives an indication that the converter output is high enough for a pulse jump to occur.

[0021] The control voltage output by the converter can be provided by a power regulation feedback loop 161. In the power regulation feedback loop, the voltage output by the converter is provided to a Type III compensator 125. The Type III compensator includes a comparator / amplifier 123 with a resistor / capacitor feedback network. Figure 1In the example, the resistive / capacitive feedback network includes capacitor C1 and resistor R8, which are connected in series between the non-inverting input and output of the comparator / amplifier. Capacitor C4 is coupled in parallel with capacitor C1 and resistor R8. Capacitor C3 and further resistor R8 are also coupled in parallel to resistor R9, which is coupled to the non-inverting input of the comparator / amplifier. The Type III compensator generates a duty cycle voltage signal VDuCy based on the difference between the voltage converter output (possibly modified by the operation of the Type III compensator) and a reference voltage. The duty cycle voltage signal is compared with a sawtooth wave signal, for example, generated by sawtooth wave signal generator 129 and comparator 127, the output of which provides the PWM signal.

[0022] The converter's control can be provided by the freewheeling feedback loop 163 instead. The use of either the power regulation feedback loop or the freewheeling feedback loop is determined by the state machine 155. Figure 1 The diagram shows a multiplexer that, based on the first selection signal Sel1 generated by the state machine, selects either the converter output voltage for the power regulation feedback loop or the freewheeling feedback loop. The multiplexer provides the selected signal to the Type III compensator, thereby effectively selecting either the power regulation feedback loop or the freewheeling feedback loop.

[0023] The freewheeling feedback loop does not use the voltage at the converter output. Instead, it provides a PWM signal to the replicated power stage 141. This replicated power stage, like power stage 111, includes a replicated high-side switch 143a and a replicated low-side switch 143b coupled in series between a higher voltage source (e.g., Pvdd) and a lower voltage source (e.g., ground). In many embodiments, the replicated high-side and replicated low-side switches are much smaller than the power stage high-side and low-side switches, for example, to reduce power usage through the replicated stage. In operation, the replicated high-side switch may be on while the replicated low-side switch is off, or both switches may be off. The controller 142 of the replicated power stage controls the operation of the replicated high-side and replicated low-side switches based on the PWM signal.

[0024] Resistor 145 is not an output inductor, but rather has a first end coupled to a node between the replicated high-side switch and the replicated low-side switch. The second end of the resistor is coupled to ground via a replicated output capacitor 147. The node between the second end of the resistor and the replicated output capacitor provides an output, which is supplied to the Type III compensator 125 via a multiplexer 135. In many embodiments, when the freewheeling feedback loop is open, the voltage reference signal is also set to indicate a voltage slightly higher than a reference voltage, such as the reference voltage plus a bias voltage. (See figure). Figure 1As shown, this is indicated by providing multiplexer 133 with Vref signal 131a and Vref + Vbias 131b. Multiplexer 133 selects one of the Sel2 signals based on the state machine 155.

[0025] Furthermore, a replication load 149, connected in parallel with the replication output capacitor, is coupled to the node between the replication output capacitor and the resistor. The replication load is as follows: Figure 1 In the form of a current source 149. In different embodiments, additional circuit elements, such as resistors or resistor networks, may be provided, which may be connected in parallel or in part in parallel with the current source.

[0026] In some embodiments, the replicated load can be selectively activated to provide an operating mode for the load line (or adaptive voltage positioning). For example... Figure 1 As shown, this is achieved by controlling the current source using switch 153, which is turned on by the third selection signal Sel3 and determined by state machine 155.

[0027] State machine 155 determines the converter's operating mode, for example, by setting a selection signal. In some embodiments, the state machine determines the converter's operating mode based on an indication of the power level used during load operation. Figure 1 In the middle. The state machine determines the operating mode based on the output level of the converter, and the output voltage is as follows. Figure 1 As shown, the level of the duty cycle signal, in Figure 1 The duty cycle signal VDuCy is proportional to the converter's duty cycle complement. A lower duty cycle signal VDuCy indicates higher power consumption, while a lower power consumption indicates higher power consumption. A higher converter output voltage indicates lower load power consumption, and vice versa. VDuCy is directly proportional to the converter's duty cycle complement. Figure 1 As shown, the four comparators are part of or associated with the state machine. Two comparators, 157a and 157b, compare the converter's output voltage with Vref plus or minus a tolerance voltage, respectively. More specifically, one comparator 157a determines whether the converter's output voltage is greater than Vref plus a tolerance voltage ptol2, and the second comparator 157b determines whether the converter's output voltage is less than Vref minus a tolerance voltage ntol2. Two comparators, 159a and 159b, compare the duty cycle voltage VDuCy with Vref plus or minus a tolerance voltage. More specifically, one comparator 159a determines whether VDuCy is greater than Vref plus a tolerance voltage ptol1, while the second comparator 157b determines whether VDuCy is less than Vref minus a tolerance voltage ntol1.

[0028] In some embodiments, the state machine determines that a freewheeling feedback loop should be used when the load uses a higher power level. The state machine determines that a load line mode should be used, either additionally or alternatively, when the load uses a higher power level. The state machine determines that a freewheeling feedback loop should be used, either additionally or alternatively, when the load uses a lower power level. The state machine determines that a PFM mode should be used, either additionally or alternatively, when the load uses a lower power level. A higher power level is a power level at which the converter cannot maintain an output voltage equal to or greater than the reference voltage. A lower power level is a power level at which the converter can maintain an output voltage greater than the reference voltage.

[0029] The state machine determines that a power regulation feedback loop should be used when the load is operating at a medium power level. Alternatively, the state machine determines that PWM mode should be used. A medium power level is the power level at which the converter can maintain the required output voltage or reference voltage when operating in PWM mode.

[0030] Figure 2 This is an example state diagram of a state machine in operation, for example... Figure 1 A state machine, according to a portion of the present invention. In some embodiments, the state diagram is the operation of the state machine. Figure 1 A state diagram describes the operation of a converter, for example... Figure 1 The converter. The state diagram describes the logic used to determine the signals used to select the converter's operation, such as... Figure 1 The converter. The state diagram is implemented using logic circuits or program instructions and can be stored in memory.

[0031] In state 211, the state machine is in regulation mode. In regulation mode, the state machine provides signals indicating that the converter should operate in PWM mode. In regulation mode, the state machine provides signals indicating that the converter should operate using a regulation control feedback loop. The state machine sets the first selection signal S1 to a value indicating that the converter should use the power regulation feedback loop. The state machine sets the second selection signal S2 to a value indicating that the converter should use the value of Vref when determining the converter duty cycle; Vref indicates the desired output voltage of the converter. The state machine sets the third selection signal S3 to a value indicating that the converter should not use load line mode in converter operation. The state machine sets an optional fourth selection signal S4 to a value indicating that the converter should not use PFM mode in converter operation.

[0032] Figure 3 This is a semi-modular block diagram. Figure 1 This is a half-schematic diagram of a DC-DC power converter, which has a voltage regulation feedback loop during operation. Figure 3 Showing Figure 1 One example of a converter is configured to operate in regulation mode by selecting a signal from state machine 155. Figure 3In this configuration, multiplexer 135 is configured to provide the converter's output to a Class III compensator (including comparator / amplifier 123) using a regulation feedback loop instead of a freewheeling feedback loop. The comparator / amplifier also provides a Vref signal for comparison. Comparator 127 compares VDuCy, the output of comparator / amplifier 123, with a sawtooth wave generated by sawtooth generator 129 to form a PWM signal. Power stage 111 operates its switches based on the PWM signal to supply power to load 119.

[0033] Back Figure 2 In some embodiments, the state machine transitions from state 211 to state 215. In some embodiments, the state machine transitions to state 215 under light load conditions. Figure 2 As shown, if condition 213 is met, the state machine transitions to state 215. Condition 213 is that the converter's output voltage is greater than Vref plus the tolerance voltage ptol2, and the duty cycle voltage signal V is greater than Vref plus the tolerance voltage ptol1.

[0034] In state 215, the state machine is in PFM mode. In PFM mode, the state machine provides signals indicating that the converter should operate in PFM mode. In PFM mode, the state machine provides signals indicating that the converter should operate using a freewheeling feedback loop. The state machine sets the first selection signal S1 to a value indicating that the converter should use the freewheeling feedback loop. The state machine sets the second selection signal S2 to a value indicating that the converter should use a Vref bias voltage to determine the converter's duty cycle. The state machine sets the third selection signal S3 to a value indicating that the converter should not use load line mode in converter operation. The state machine sets an optional fourth selection signal S4 to a value indicating that the converter should use PFM mode in converter operation.

[0035] Figure 4 This is a semi-modular block diagram. Figure 1 This is a half-schematic diagram of a DC-DC power converter, operating in PFM mode with a freewheeling feedback loop. Figure 4 An example of a converter is shown. It is configured to operate in PFM mode by selecting a signal from state machine 155. (Example follows) Figure 4As shown, multiplexer 135 is configured by selection signal Sel1 to provide a replicated output to a Class III compensator, including comparator / amplifier 123, enabling the use of a freewheeling feedback loop instead of a regulation feedback loop. Multiplexer 133 is configured by signal Sel2 to pass a bias voltage to comparator / amplifier 123 at Vref. Comparator 127 compares the output VDuCy of comparator / amplifier 123 with a sawtooth wave generated by sawtooth generator 129 to form a PWM signal. Power stage 111 operates its switch based on the PWM signal to supply power to load 119 and according to signal Sel4 indicating that a PFM pulse jump should occur. The pulse jump is performed when the converter's output voltage is greater than Vref plus a tolerance voltage. Furthermore, replicated power stage 141 operates its replicated switch based on the PWM signal. The replicated output is located at the node between resistor 145 and replicated output capacitor 147.

[0036] Figure 6 An example of a pulse skipping circuit is provided. Figure 6 The diagram illustrates the power stage and output elements of a DC-DC power converter, along with associated logic elements for determining the switching states of the power stage switches. In some embodiments, the logic elements are used to perform pulse jumping for the PFM operation of the power converter.

[0037] like Figure 6 The converter shown includes a high-side switch 613A, a low-side switch 613B, a bypass switch 621, an output inductor 615, an output capacitor 617, and logic circuitry 611 for controlling the high-side, low-side, and bypass switches. The high-side switch 613A and the low-side switch 613B are coupled in series between a first voltage source Vin and a second voltage source (e.g., ground). The voltage of the first voltage source is higher than that of the second voltage source. The high-side switch couples the first voltage source to the low-side switch, and the low-side switch couples the second voltage source to the high-side switch. For example, the high-side and low-side switches can be formed with metal-oxide-semiconductor field-effect transistors (MOSFETs), with a p-channel MOSFET forming the high-side switch and an n-channel MOSFET forming the low-side switch. During operation, the high-side switch is in the on state, the low-side switch is in the on state, or both switches are not in the on state. For ease of illustration, the on-resistance (R) provided by the switches is also shown for the high-side and low-side switches. DSONOutput inductor 615 has one end coupled to the node between high-side switch 613a and low-side switch 613b, and also coupled to the first terminal of bypass switch 621. The other end of the output inductor is coupled to output capacitor 617, the second terminal of bypass switch 621, and load 619, through which load current I.sub.LOAD flows. The load can be, for example, a processor core, logic circuitry, or other circuit element that receives regulated power. The node coupling the other end of the output inductor, output capacitor, and load can generally be considered as the output of the regulator.

[0038] Logic circuit 611 can receive output signals from the first and second comparators, as well as PWM signals, typically indicated by freewheeling PWM 653, to control the states of the high-side, low-side, and bypass switches. Logic circuit 611 typically controls the states of the high-side, low-side, and bypass switches by generating control signals for controlling these switches.

[0039] like Figure 6 The latch shown stores the signal generated by comparator 651. The comparator determines whether the converter's output voltage is greater than Vref plus a tolerance voltage ptol2. The latch stores the signal when the PWM signal transitions to a high level. The latch's output (which may be called CMP) BP The circuit provides an OR gate to the gate of the bypass switch and an AND gate after passing through the inverter. The OR gate also receives the PWM signal and provides an output to the gate of the high-side switch. Therefore, the high-side switch is on when its gate input is low, and thus on when both the PWM signal and the latch output are low. The AND gate also receives the PWM signal and provides an output to the gate of the low-side switch. Therefore, the low-side switch is activated when its gate input is high, and thus on when both the inverter latch output and the PWM signal are high.

[0040] Back Figure 2 If the converter's output voltage is less than the predetermined voltage, the state machine switches back to regulation mode. This is in Figure 2 The condition shown is 217, where the converter's output voltage is less than the reference voltage Vref minus a tolerance voltage ntol2.

[0041] In some embodiments, the state machine transitions from state 211 to state 225. The state machine transitions to state 225 under heavy load conditions. Figure 2 As shown, if condition 223 is met, the state machine transitions to state 225. In some embodiments, the duty cycle voltage signal VDuCy for condition 223 is less than Vref minus a tolerance voltage of ntol1.

[0042] In state 225, the state machine is in loadline mode. In loadline mode, the state machine provides signals indicating that the converter should operate in loadline mode. In loadline mode, the state machine provides signals indicating that the converter should operate using a freewheeling feedback loop. The state machine sets the first selection signal S1 to a value indicating that the converter should use the freewheeling feedback loop. The state machine sets the second selection signal S2 to a value indicating that the converter should use the Vref value when determining the converter's duty cycle. The state machine sets the third selection signal S3 to a value indicating that the converter should use loadline mode during converter operation. The state machine sets an optional fourth selection signal S4 to a value indicating that the converter should not use PFM mode during converter operation.

[0043] Figure 5 This is a half-module block diagram; the half-schematic diagram is for a DC-DC power converter. Figure 1 The operation uses a freewheeling feedback loop and employs load line operation. Figure 5 Here is an example. Figure 1 The converter in the converter is configured to operate in load line mode by selecting a signal from state machine 155. Figure 5 In this configuration, multiplexer 135 is configured to provide a replicated output to a Class III compensator, including comparator / amplifier 123, via selection signal Sel1, enabling the use of a freewheeling feedback loop instead of a regulation feedback loop. Multiplexer 133 is configured by signal Sel2 to pass Vref to comparator / amplifier 123. Comparator 127 compares the output VDuCy of comparator / amplifier 123 with a sawtooth wave generated by sawtooth generator 129 to form a PWM signal. Power stage 111 operates its switch based on the PWM signal to supply power to load 119. Furthermore, replicated power stage 141 operates its replicated switch based on the PWM signal. However, the replicated output, positioned at the node between replicated resistor 145 and output capacitor 147, is not solely based on the operation of the replicated switch. Instead, signal Sel3 enables current generator 149 to generate a current indicating the load current, effectively clamping the replicated output to a predetermined level.

[0044] Back Figure 2 If the converter's output voltage exceeds a predetermined voltage, the state machine will switch back to regulation mode. For example... Figure 2 As shown in condition 227, the converter's output voltage is greater than the reference voltage Vref plus a tolerance voltage ptol2.

[0045] Figure 7A and 7B The graph shows the relationship between the two's complement of the duty cycle 1-DuCy (e.g., 1-x, where x is the converter's duty cycle) and the inverse ratio of the load current. The left-hand graph shows the variation of 1-DuCy with the reciprocal of the load current when a regulator without a second-order loop is used. Figure 7A The graph shows that the duty cycle is at its minimum under very light loads and increases as the load increases – initially moderately, then sharply as the load approaches the heavy load area. Figure 7B The graph shows the variation of the regulator 1-DuCy with the reciprocal of the load current using a second-order loop that provides freewheeling PFM and load line mode. Figure 7B The graph shows that under heavy load conditions, the converter operates in load line mode using a freewheeling feedback loop, maintaining a constant duty cycle. Figure 7B In the heavy load condition, the constant duty cycle level approximates the duty cycle level during the transition between heavy and medium loads, and is therefore lower than the level occurring under heavy load conditions. This may result in a decrease in the converter's output voltage, but it can be beneficial for the overall converter and system operation, considering factors such as thermal issues, battery depletion, and other problems. Under light load conditions, the duty cycle also remains constant, and the converter operates in PFM mode using a freewheeling feedback loop. Figure 7B The constant level in the circuit, under light load conditions, is represented by the duty cycle corresponding to the operation of the converter using the freewheeling feedback loop in PFM mode.

[0046] Figure 8 This is a graph showing the load-line regulation curves relating the regulation voltage to the load. Under light load, the output voltage is regulated by adding a tolerance voltage to Vref. Regulating the output voltage slightly higher than Vref improves the response to increased load. Under light load conditions, the converter operates in PFM mode using a freewheeling feedback loop. As the load current increases, the output voltage begins to drop towards Vref. When the output voltage falls below Vref plus a tolerance voltage, the pulse skipping stops. Therefore, although the freewheeling feedback loop continues to operate, the converter effectively operates in PWM mode.

[0047] Once the output voltage drops to Vref, under moderate load, the converter will transition to using a voltage regulation feedback loop, operating in PWM mode. However, as the load current increases further, the converter may be unable to maintain the output voltage at Vref at certain times. When the load current reaches this point or above, the converter operates using a freewheeling feedback loop, clamping the duty cycle.

[0048] Figure 9The transient response damping achieved by using a bypass switch is demonstrated. A converter's transient response to load current can cause output overshoot and ringing. A converter with greater damping (without a bypass switch) may exhibit increased hysteresis when reaching the desired output, as shown in maximum damping curve 911, while a converter with less damping may exhibit increased overshoot and increased settling time, as shown in minimum damping curve 913. However, the use of a bypass switch allows for reduced inductor energy oscillations and can provide increased response time and reduced overshoot and settling time, as shown, for example, in bypass control curve 915.

[0049] Although the invention has been discussed with respect to various embodiments, it should be recognized that the invention is supported by the disclosure of claims that include both novel and non-obvious aspects.

Claims

1. DC-DC power converter, including: The power stage, output inductor, and output capacitor are configured in a buck configuration for coupling to the load; the first feedback loop includes a Type III compensator for determining the duty cycle of the power stage in the first operating mode based on the output voltage supplied to the load; the second feedback loop includes a replicated power stage, a resistor, a replicated output capacitor, and a Type III compensator for determining the duty cycle of the power stage in the second operating mode; logic circuitry is configured to select the use of the first feedback loop in the first operating mode and to select the use of the second feedback loop in the second operating mode. Furthermore, the DC-DC power converter also includes a replica load selectively coupled to a second feedback loop, and the logic circuitry is further configured in a third operating mode to selectively couple the replica load to the second feedback loop.

2. The DC-DC power converter of claim 1, wherein the first operating mode is a voltage regulation operating mode, the second operating mode is a pulse frequency modulation (PFM) freewheeling operating mode, and the third operating mode is a load line operating mode.

3. The DC-DC power converter according to claim 2, wherein the voltage regulation operating mode is a pulse width modulation (PWM) operating mode.

4. The DC-DC power converter according to claim 3, wherein, If the output voltage supplied to the load is greater than the first voltage, and the duty cycle signal indicates that it is currently being used under light load, the logic circuit is configured to transition from the pulse width modulation (PWM) operating mode to the pulse frequency modulation (PFM) freewheeling operating mode.

5. The DC-DC power converter of claim 4, wherein, The logic circuit is configured to transition from PFM freewheeling mode to PWM mode when the output voltage supplied to the load is less than the second voltage.

6. The DC-DC power converter of claim 5, wherein, If the output voltage supplied to the load is less than the second voltage, the logic circuit is configured to transition from the pulse width modulation (PWM) operating mode to the load line operating mode.

7. The DC-DC power converter of claim 6, wherein, If the output voltage supplied to the load is greater than the first voltage, the logic circuit is configured to transition from the load line operation mode to the pulse width modulation (PWM) operation mode.

8. The DC-DC power converter of claim 1, wherein the power stage includes a high-side switch and a low-side switch coupled in series between a higher voltage source and a lower voltage source, a first end of an output inductor being coupled to a node between the high-side switch and the low-side switch, and a second end of the output inductor being coupled to ground via an output capacitor.

9. The DC-DC power converter of claim 8 further includes a bypass switch coupled to a first terminal of the output inductor and a second terminal of the output inductor.

10. The DC-DC power converter of claim 9, wherein the power stage controller controls the operation of the high-side switch, the low-side switch and the bypass switch.

11. The DC-DC power converter of claim 1, wherein the replicated power stage includes a replicated high-side switch and a replicated low-side switch coupled in series between a higher voltage source and a lower voltage source, a first end of a resistor is coupled to a node between the replicated high-side switch and the replicated low-side switch, and a second end of the resistor is coupled to ground through a replicated output capacitor.

12. DC-DC power converters, including: A buck power converter; a power regulation feedback loop including a type III compensation circuit selectively coupled to the buck power converter; a freewheeling feedback loop including a replica power stage selectively coupled to the buck power converter; a state machine configured based on the output voltage of the buck power converter, and / or The duty cycle signal of the buck power converter during operation is used to generate a command signal to control the coupling power regulation feedback loop to the buck power converter, or the coupling freewheeling feedback loop to the buck power converter. Furthermore, the freewheeling feedback loop includes a replica load line selectively coupled to the replica power stage, and wherein the freewheeling feedback loop is configured to operate the buck power converter in pulse width modulation (PWM) mode to clamp the duty cycle, with the replica load line selectively coupled to the replica power stage.

13. The DC-DC power converter of claim 12, wherein, The power regulation feedback loop is configured to operate the buck power converter in pulse width modulation (PWM) mode.

14. The DC-DC power converter of claim 12, wherein, The freewheeling feedback loop is configured to operate the buck power converter in pulse frequency modulation (PFM) freewheeling mode.

15. The DC-DC power converter of claim 12, wherein the state machine is further configured to generate a command signal to decouple the replicated load line to the replicated power stage based on a signal indicating the duty cycle of the buck power converter.

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