Bandgap reference circuit, reference voltage generation method, chip and electronic device

Abstract

The embodiment of the application provides a band gap reference circuit, a reference voltage generation method, a chip and an electronic device, the circuit comprises: a first voltage generation module connected with a first input end of an operational amplifier module, and generating a first voltage with a negative temperature coefficient; a second voltage generation module and a third voltage generation module generating a second voltage and a third voltage, the two are not equal and the difference between the two has a positive temperature coefficient; a first charge storage unit and a second charge storage unit, a first end of the second charge storage unit being connected with a second input end of the operational amplifier module; a switch network, in a first period, connecting the first charge storage unit between the first input end and the second input end, connecting the output end of the operational amplifier module with the second input end, and connecting the second end of the second charge storage unit with the second voltage generation module; in a second period, connecting the first charge storage unit between the second input end and the output end, and connecting the second end of the second charge storage unit with the third voltage generation module, to output a reference voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuits, in particular to a bandgap reference circuit, a reference voltage generation method, a chip and an electronic device. BACKGROUND

[0002] In related technologies, a bandgap reference voltage source is usually generated by adding the base-emitter voltage Vbe of an amplifier region transistor and the difference ΔVbe between the Vbe of different transistors. The voltage source structure usually includes a loop composed of an operational amplifier and a transistor. The input offset voltage of the operational amplifier is amplified and superimposed on the reference voltage, causing the reference voltage to deviate, and the input offset voltage also changes with temperature, thereby introducing an additional temperature drift term, which greatly affects the reference voltage. SUMMARY

[0003] In view of the above problems, the embodiments of the present application provide a bandgap reference circuit, a reference voltage generation method, a chip and an electronic device to solve the above technical problems.

[0004] In a first aspect, the embodiments of the present application provide a bandgap reference circuit, comprising:

[0005] an operational amplifier module;

[0006] a first voltage generation module, connected to a first input terminal of the operational amplifier module, for generating a first voltage with a negative temperature coefficient;

[0007] a second voltage generation module, for generating a second voltage;

[0008] a third voltage generation module, for generating a third voltage, the second voltage and the third voltage being unequal, and the difference between the second voltage and the third voltage having a positive temperature coefficient;

[0009] a charge storage module, comprising: a first charge storage unit and a second charge storage unit, a first terminal of the second charge storage unit being connected to a second input terminal of the operational amplifier module;

[0010] a switch network, for: during a first period, connecting the first charge storage unit between the first input terminal and the second input terminal of the operational amplifier module, connecting the output terminal of the operational amplifier module to the second input terminal, and connecting a second terminal of the second charge storage unit to the second voltage generation module; and during a second period, connecting the first charge storage unit between the second input terminal and the output terminal of the operational amplifier module, and connecting the second terminal of the second charge storage unit to the third voltage generation module;

[0011] wherein the output terminal of the operational amplifier module serves as an output terminal of the reference voltage during the second period.

[0012] In a second aspect, the embodiments of the present application provide a reference voltage production method applied to the bandgap reference circuit, and the method comprises the following steps.

[0013] In the first period, the first charge storage unit is connected between the first input end and the second input end of the operational amplifier module, the output end of the operational amplifier module is connected to the second input end, and the second end of the second charge storage unit is connected to the second voltage generation module; and

[0014] In the second period, the first charge storage unit is connected between the second input end and the output end of the operational amplifier module, the second end of the second charge storage unit is connected to the third voltage generation module, and the output end of the operational amplifier module generates the reference voltage.

[0015] In a third aspect, the embodiments of the present application further provide a chip comprising the bandgap reference circuit.

[0016] In a fourth aspect, the embodiments of the present application further provide an electronic device comprising a device main body and the chip arranged on the device main body.

[0017] The bandgap reference circuit, the reference voltage production method, the chip and the electronic device provided by the embodiments of the present application can store the input offset voltage of the operational amplifier module in the first and second charge storage units in the first period by connecting the first charge storage unit between the first input end and the second input end of the operational amplifier module, connecting the output end of the operational amplifier module to the second input end, connecting the first voltage generation module to the first input end of the operational amplifier module, and connecting the second end of the second charge storage unit to the second voltage generation module; in the second period, the input offset voltage of the operational amplifier module is offset in the output voltage through the first and second charge storage units by connecting the first charge storage unit between the second input end and the output end of the operational amplifier module, connecting the second charge storage unit between the second input end of the operational amplifier module and the second voltage generation module, and connecting the second end of the second charge storage unit to the third voltage generation module, so as to generate a voltage difference opposite to the negative temperature coefficient, and the output end of the operational amplifier module can serve as the output end of the reference voltage in the second period.

[0018] These and other aspects of the present application will become more apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort.

[0020] Figure 1 A circuit diagram of a bandgap reference circuit in the related art is shown.

[0021] Figure 2 A schematic block diagram of a connection structure of a bandgap reference circuit in a first period is shown.

[0022] Figure 3 A schematic block diagram of a connection structure of a bandgap reference circuit in a second period is shown.

[0023] Figure 4 A structural block diagram of a bandgap reference circuit is shown.

[0024] Figure 5 A structural block diagram of a voltage generating module is shown.

[0025] Figure 6 Another structural block diagram of a voltage generating module is shown.

[0026] Figure 7 A circuit diagram of a bandgap reference circuit is shown.

[0027] Figure 8A A circuit diagram of a bandgap reference circuit in phase one is shown.

[0028] Figure 8B A circuit diagram of a bandgap reference circuit in phase two is shown.

[0029] Figure 9 A circuit diagram of a fourth voltage generating module is shown.

[0030] Figure 10 A circuit diagram for generating a voltage proportional to a square of temperature is shown.

[0031] Figure 11 A flow chart of a bandgap reference voltage generating method is shown. DETAILED DESCRIPTION

[0032] Embodiments of the present application are described in detail below with reference to the attached drawings, wherein the same or similar components have the same or similar designations throughout the several views. The embodiments described below are exemplary only and are not intended to be limiting of the present application.

[0033] In the following, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application, so that those skilled in the art can better understand the solutions in the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0034] It should be noted that in the embodiments of the present application, in this document, the terms such as first and second are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations.

[0035] Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or equipment including the element.

[0036] In the description of the embodiments of the present application, the words "example" or "for example" are used to represent example, illustration or description. Any embodiment or design scheme described as "example" or "for example" in the embodiments of the present application is not interpreted as more preferred or having more advantages than another embodiment or design scheme. The words "example" or "for example" are intended to present the relative concept in a clear manner.

[0037] In addition, "multiple" in the embodiments of the present application means two or more, and therefore "multiple" in the embodiments of the present application can also be understood as "at least two". "At least one" can be understood as one or more, for example, as one, two or more. For example, including at least one means including one, two or more, and does not limit which ones are included, for example, including at least one of A, B and C, and the included can be A, B, C, A and B, A and C, B and C, or A and B and C.

[0038] It should be noted that in the embodiments of the present application, the "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases of A alone, A and B together, and B alone. In addition, the character " / ", if not specially specified, generally represents a "or" relationship between the associated objects before and after it.

[0039] It should be noted that the "connection" in the embodiments of the present application can be understood as an electrical connection, and the connection between two electrical elements can be direct or indirect connection between the two electrical elements. For example, A and B are connected, which can be direct connection between A and B, or indirect connection between A and B through one or more other electrical elements.

[0040] The first pole / first end of each transistor in the embodiments of the present application is one of the source and the drain, and the second pole / second end of each transistor is the other of the source and the drain. Since the source and the drain of the transistor can be symmetrical in structure, the source and the drain can be indistinguishable in structure, that is, the first pole / first end and the second pole / second end of the transistor in the embodiments of the present application can be indistinguishable in structure. Illustratively, in the case of a P-type transistor, the first pole / first end of the transistor is the source, and the second pole / second end of the transistor is the drain; illustratively, in the case of an N-type transistor, the first pole / first end of the transistor is the drain, and the second pole / second end of the transistor is the source.

[0041] In the circuit structure provided by the embodiments of the present application, the nodes such as the first node and the second node are not actual components, but are convergence points of relevant couplings in a circuit diagram, that is, these nodes are nodes equivalent to the convergence points of relevant couplings in the circuit diagram.

[0042] The bandgap reference source is one of the important components in an analog circuit, and is commonly used to provide a reference source in various analog modules, such as a power management module, an analog-to-digital converter (ADC), a linear regulator, a memory module, and the like. The accuracy of the bandgap reference directly affects the performance of the entire circuit. Therefore, the bandgap reference is required to have high accuracy and stability.

[0043] In the related art, the bandgap reference voltage source is usually generated by adding the base-emitter voltage Vbe of an amplifier region transistor and the difference ΔVbe between the Vbe of different transistors. The voltage source structure usually includes a loop composed of an operational amplifier and a transistor. The input offset voltage of the operational amplifier is amplified and superimposed on the reference voltage, causing the reference voltage to deviate, and the input offset voltage also changes with temperature, thereby introducing an additional temperature drift term, which greatly affects the reference voltage.

[0044] In order to facilitate understanding of the influence of the input offset voltage of the operational amplifier on the reference voltage, the following will be described in combination with Figure 1 The influence of the input offset voltage of the operational amplifier on the reference voltage is exemplarily analyzed.

[0045] As Figure 1As shown, an exemplary bandgap reference circuit in the related art includes transistors Q1, Q2 and an operational amplifier Al, and resistors R1, R2 and R3. The size ratio of Q1 to Q2 is 1:N. Q1 generates V BE1 , Q2 generates V BE2 , and the voltage division on resistor R3 is ΔV BE . Assuming R1=R2, the output voltage V OUT can be derived as follows:

[0046] V OUT =V BE2 +VT·ln N ·(R3+R2) / R3.

[0047] The input offset voltage of the operational amplifier Al in the circuit causes an error in the output voltage, which can be quantified as V BE1 -V OS ≈V BE2 +R3·I C2 , and V OUT =V BE2 +(R2+R3)·I C2 . Thus, we have:

[0048] V OUT =V BE2 +(R2+R3)·(V BE1 -V BE2 -V OS ) / R3=V BE2 +(1+R2 / R3)·(VT·ln N- V OS ).

[0049] As shown above, the input offset voltage is amplified by a factor of 1+R2 / R3, introducing an error in the input voltage, and the input offset voltage itself varies with temperature, also increasing the temperature coefficient of the output voltage.

[0050] In addition, ΔV BE is a voltage proportional to absolute temperature (PTAT), i.e., a positive temperature coefficient voltage; V BE is a voltage complementary to absolute temperature (CTAT), i.e., a negative temperature coefficient voltage. However, V BE is actually a nonlinear voltage, and a Taylor expansion of it gives V BE =a0+a1T+a2T^2+...+anT^n, while ΔV BE is proportional to V n .BE The addition only realizes the cancellation of the first order component, and the high order term still has a great influence on the reference voltage with temperature change.

[0051] The bandgap reference circuit provided by the embodiments of the present application can reduce the influence of the input offset voltage of the operational amplifier on the temperature drift coefficient of the reference voltage. The bandgap reference circuit provided by some embodiments of the present application can reduce the second order temperature drift. The bandgap reference circuit provided by some embodiments of the present application can reduce the influence of the offset voltage on the temperature drift coefficient of the reference voltage and reduce the second order temperature drift of the reference voltage.

[0052] Figure 2 and Figure 3 The structure block diagram of the bandgap reference circuit provided by the embodiments of the present application is shown in FIG. 1. As shown in FIG. 1, the bandgap reference circuit 100 comprises a first voltage generating module 10, a second voltage generating module 20, a third voltage generating module 30, an operational amplifier module 40, and a charge storage module 50. Figure 2 Figure 3 As shown in FIG. 1, the bandgap reference circuit 100 comprises a first voltage generating module 10, a second voltage generating module 20, a third voltage generating module 30, an operational amplifier module 40, and a charge storage module 50.

[0053] The first voltage generating module 10 is configured to generate a first voltage V1 with a negative temperature coefficient, the second voltage generating module 20 is configured to generate a second voltage V2, and the third voltage generating module 30 is configured to generate a third voltage V3. The second voltage V2 is not equal to the third voltage V3, and the difference between the second voltage V2 and the third voltage V3 has a positive temperature coefficient.

[0054] In the embodiments of the present application, a switch network (not shown in FIG. 2 and FIG. 3) can control the connection relationship of the bandgap reference circuit 100. In the first period (also referred to as the first phase) and the second period (also referred to as the second phase), different circuit structures are formed. Figure 2 3 The structure block diagram of the connection structure of the bandgap reference circuit 100 in the first period is shown in FIG. 2. As shown in FIG. 2, in the first period, the first charge storage unit 51 is connected between the first input end 41 and the second input end 42 of the operational amplifier module 40; the output end 43 of the operational amplifier module 40 is connected to the second input end 42; the first voltage generating module 10 is connected to the first input end 41 of the operational amplifier module 40; the second end of the second charge storage unit 52 is connected to the second voltage generating module 20, and the first end of the second charge storage unit 52 is connected to the second input end 42 of the operational amplifier module 40.

[0055] Figure 2 Figure 2 The structure block diagram of the connection structure of the bandgap reference circuit 100 in the second period is shown in FIG. 3. As shown in FIG. 3, in the second period, the first charge storage unit 51 is connected to the first input end 41 of the operational amplifier module 40; the output end 43 of the operational amplifier module 40 is connected to the first input end 41; the first voltage generating module 10 is connected to the second input end 42 of the operational amplifier module 40; the second end of the second charge storage unit 52 is connected to the third voltage generating module 30, and the first end of the second charge storage unit 52 is connected to the second input end 42 of the operational amplifier module 40.

[0056] Figure 3 ​​​A schematic block diagram showing the connection structure of the bandgap reference circuit 100 in the second period is shown in FIG. 2B. Figure 3 As shown in FIG. 2B, in the second period, the first charge storage unit 51 is connected between the second input terminal 42 and the output terminal 43 of the op-amp module 40; the second charge storage unit 52 is connected between the second input terminal 42 of the op-amp module 40 and the third voltage generating module 30; and the second terminal of the second charge storage unit 52 is connected with the third voltage generating module 30. The output terminal 43 of the op-amp module 40 serves as the output terminal of the reference voltage V REF in the second period.

[0057] Hereinafter, the elimination of the input offset voltage V OS of the op-amp module 40 and the generation of the reference voltage V REF of the bandgap reference circuit 100 are exemplarily explained with the first input terminal 41 of the op-amp module 40 as the positive terminal, the second input terminal 42 as the negative terminal, the capacitance of the first charge storage unit 51 as C1, and the capacitance of the second charge storage unit 52 as C2.

[0058] The second input terminal 42 of the op-amp module 40 is node X. As shown in FIG. 2A, Figure 2 in the first period, the input offset voltage V OS of the op-amp module 40 is stored on the first charge storage unit 51 and the second charge storage unit 52, and the charge Q x1 of node X in the first period is represented as: Q x1 = (C1+C2) · Vos. Figure 3 As shown in FIG. 2B, in the second period, the charge Q x2 of node X is represented as: Q x2 = C2 · (V2-V3+Vos)+C1 · (V1+Vos-V REF ).

[0059] The second input terminal 42 of the op-amp module 40 satisfies the charge conservation in both the first period and the second period, and thus it can be known that: Q x1 = Q x2 . It can be further deduced that: V REF = V1+C2 / C1 · (V2-V3). Assuming V2=V1, V REF = V1+C2 / C1 · (V1-V3). From the above equation, V REF does not contain Vos, that is, the input offset voltage Vos of the op-amp module 40 is eliminated. Moreover, since V1 has a negative temperature coefficient, V1-V3 or V2-V3 has a positive temperature coefficient, so that the temperature compensation of V1 can be performed.

[0060] As previously analyzed in the present specification, the reference voltage further contains high-order temperature drift. Therefore, in some possible implementation manners, as shown in FIG. 3, Figure 4As shown, the charge storage module 50 can further include a third charge storage unit 53. A first end of the third charge storage unit 53 is connected to the second input end 42 of the operational amplifier module 40. During one of the first period and the second period, a second end of the third charge storage unit 53 is connected to a reference ground end. During the other of the first period and the second period, the second end of the third charge storage unit 53 is connected to a second-order compensation end, where the second-order compensation end is configured to receive a fourth voltage V4 proportional to a square of temperature.

[0061] Further in combination with the foregoing example, and assuming that a capacitance of the third charge storage unit 53 is C3, and the second input end 42 of the operational amplifier module 40 is a node X. During the first period, the input offset voltage Vos is stored in the first charge storage unit 51, the second charge storage unit 52, and the third charge storage unit 53, and the charge Q of the node X during the first period is represented as: OS = (C1+C2)·Vos+C3·(V1+Vos-V4). x1 During the second period, the input offset voltage Vos is stored in the first charge storage unit 51, the second charge storage unit 52, and the third charge storage unit 53, and the charge Q of the node X during the second period is represented as: x1 =C3·(V1+Vos)+C2·(V2-V3+Vos)+C1·(V1+Vos-V x2 )。 x2 REF

[0062] The second input end 42 of the operational amplifier module 40 satisfies the charge conservation during both the first period and the second period, and thus it can be known that: x1 =Q x2 . It can be further derived that: REF =V1+C2 / C1·(V2-V3)+C3 / C1·V4. Assuming that V2=V1, it can be known that: REF =V1+C2 / C1·(V1-V3)+C3 / C1·V4. From the above equation, it can be known that V REF does not include the input offset voltage Vos of the operational amplifier module 40, that is, the input offset voltage Vos of the operational amplifier module 40 is eliminated. Moreover, since V1 has a negative temperature coefficient, V1-V3 or V2-V3 has a positive temperature coefficient, and thus first-order temperature compensation can be performed. V4 is a voltage proportional to a square of temperature, and thus second-order temperature compensation can be performed.

[0063] Figure 4 A structure block diagram of the bandgap reference circuit 100 provided by an embodiment of the present application is shown in FIG. 1. As shown in FIG. 1, the bandgap reference circuit 100 includes a first voltage generating module 10, a second voltage generating module 20, a third voltage generating module 30, an operational amplifier module 40, a charge storage module 50, and a switch network. Figure 4 The charge storage module 50 includes a first charge storage unit 51 and a second charge storage unit 52. The bandgap reference circuit 100 can further include the switch network. ​​

[0064] As an implementation, the switch network can comprise: a first switch S101 connected between the first end of the first charge storage unit 51 and the first input end 41 of the op-amp module 40; a second switch S102 connected between the first end of the first charge storage unit 51 and the output end 43 of the op-amp module 40; and a third switch S103 connected between the second input end 42 and the output end 43 of the op-amp module 40. In the first period, the first switch S101 and the third switch S103 are turned on, and the second switch S102 is turned off, so as to connect the first charge storage unit 51 between the first input end 41 and the second input end 42 of the op-amp module 40. In the second period, the second switch S102 is turned on, and the first switch S101 and the third switch S103 are turned off, so as to connect the first charge storage unit 51 between the second input end 42 and the output end 43 of the op-amp module 40.

[0065] In some implementations, the charge storage module 50 can further comprise a third charge storage unit 53. The first end of the third charge storage unit 53 is connected to the second input end 42 of the op-amp module 40. In one of the first period and the second period, the second end of the third charge storage unit 53 is connected to a reference ground end Vgnd. In the other of the first period and the second period, the second end of the third charge storage unit 53 is connected to a second-order compensation end Vb, where the second-order compensation end Vb is configured to receive a fourth voltage V4 proportional to the square of the temperature.

[0066] As an implementation, the switch network further comprises: an eighth switch S108 connected between the third charge storage unit 53 and the reference ground end Vgnd; and a ninth switch S109 connected between the third charge storage unit 53 and the second-order compensation end Vb. In one of the first period and the second period, the eighth switch S108 is turned on, and the ninth switch S109 is turned off, so as to connect the third charge storage unit 53 between the second input end 42 of the op-amp module 40 and the reference ground end Vgnd. In the other of the first period and the second period, the eighth switch S108 is turned off, and the ninth switch S109 is turned on, so as to connect the third charge storage unit 53 between the second input end 42 of the op-amp module 40 and the second-order compensation end Vb.

[0067] In some possible implementations, the bandgap reference circuit 100 can further comprise an output module 60 configured to: sample the output voltage of the output end 43 of the op-amp module 40 in the second period of any period, and take the sampling result as the reference voltage REF of the next period; and take the sampling result of the last period of the current period as the reference voltage REF of the current period in any period. Thus, the reference voltage VREF can be output in both the first period and the second period. REFFor example, the output module 60 may include a notch filter.

[0068] The following is an exemplary description of the implementation of the first, second and third voltage generating modules.

[0069] In some possible implementations, such as Figure 5 As shown, the second voltage generating module 20 may include: a second current mirror 21 for mirroring the preset current to generate a second current I2; a second transistor 22, wherein the first electrode of the second transistor 22 receives the second current I2 during the first period to generate the above-mentioned second voltage V2. Figure 5 As shown, the third voltage generating module 30 may include a third transistor 31, wherein a first electrode of the third transistor 31 receives the second current I2 during the second period to generate the third voltage V3. The third transistor 31 is different from the second transistor 22, such that the second voltage V2 is not equal to the third voltage V3. For example, the third transistor 31 and the second transistor 32 may have different sizes. The second voltage generating module 20 and the third voltage generating module 30 share the second current mirror 21, which can reduce power consumption and circuit area.

[0070] As an implementation method, Figure 5 As shown, the switch network may further include: a fourth switch S104 connected between the second current mirror 21 and the first electrode of the second transistor 22; and a fifth switch S105 connected between the second current mirror 21 and the first electrode of the third transistor 33. During the first period, the fifth switch S105 is turned off and the fourth switch S104 is turned on, so that the second voltage generating module 20 generates the second voltage V2 and the second charge storage unit 52 receives the second voltage V2. During the second period, the fifth switch S105 is turned on and the fourth switch S104 is turned off, so that the third voltage generating module 30 generates the third voltage V3 and the second charge storage unit 52 receives the third voltage V3.

[0071] In some possible implementations, such as Figure 6As shown, the second voltage generating module 20 may include a third current mirror 23 and a fourth transistor 24, and the third voltage generating module 30 may include a fourth current mirror 32. The second voltage generating module 20 and the third voltage generating module 30 reuse the fourth transistor 24. The fourth transistor 24 and the third current mirror 23 constitute the second voltage generating module 20, or the fourth transistor 24 and the fourth current mirror 32 constitute the third voltage generating module 30. The third current mirror 23 may mirror a preset current to generate a third current I3; the fourth current mirror 32 may mirror the preset current to generate a fourth current I4. The fourth current I4 is unequal to the third current I3, so that the second voltage V2 and the third voltage V3 are unequal. The first electrode of the fourth transistor 24 receives the third current I3 during the first period to generate the second voltage V2, and receives the fourth current I4 during the second period to generate the third voltage V3.

[0072] As an implementation method, Figure 6 As shown, the switch network further includes: a sixth switch S106 connected between the third current mirror 23 and the first electrode of the fourth transistor 24; and a seventh switch S107 connected between the fourth current mirror 32 and the first electrode of the fourth transistor 24. During the first period, the seventh switch S107 is off, the sixth switch S106 is on, and the fourth transistor 24 and the third current mirror 23 form a second voltage generating module 20 to generate the second voltage V2. During the second period, the seventh switch S107 is on, the sixth switch S106 is off, and the fourth transistor 24 and the fourth current mirror 32 form a third voltage generating module 30 to generate the third voltage V3.

[0073] As an implementation method, Figure 5 and 6 As shown, the first voltage generating module 10 may include: a first current mirror 11 for mirroring the preset current to generate a first current I1; a first transistor 12, a first electrode of which receives the first current I1 to generate the first voltage V1.

[0074] The following combination Figure 7 Exemplary embodiments of a bandgap reference circuit are described.

[0075] Figure 7 1 shows a circuit diagram of a bandgap reference circuit 700 provided in an embodiment of the present application, as shown in FIG. Figure 7 As shown, the MOS transistor M72 and the MOS transistor M73 mirror the current Ib of the MOS transistor M71 , the current of the branch where the MOS transistor M72 is located is I71 , and the current of the branch where the MOS transistor M73 is located is I72 .

[0076] like Figure 7As shown, transistor Q71 is connected to the branch where MOS transistor M72 resides. Together, transistor Q71 and MOS transistor M72 form the aforementioned first voltage generating unit. Transistor Q71 generates a negative temperature coefficient voltage Vbe1 (corresponding to the aforementioned first voltage V1), which is fed into the positive input terminal (corresponding to the aforementioned first input terminal) of the operational amplifier OP.

[0077] like Figure 7 As shown, transistors Q72 and Q73 are connected to the branch where MOS transistor M73 is located via switches S8 and S9, respectively. When switch S8 is off and switch S9 is on, transistor Q72 is connected to MOS transistor M73 (forming the aforementioned second voltage generation module), and transistor Q72 generates a negative temperature coefficient voltage Vbe2 (corresponding to the aforementioned second voltage V2). When switch S8 is on and switch S9 is off, transistor Q73 is connected to MOS transistor M73 (forming the aforementioned third voltage generation module), and transistor Q73 generates a negative temperature coefficient voltage Vbe3 (corresponding to the aforementioned third voltage V3). Figure 7 As shown, the transistor Q72 is different from the transistor Q73 , and the size ratio of the transistor Q72 to the transistor Q73 is 1:M, where M is a natural number greater than 1, so that Vbe2 is different from Vbe3 .

[0078] like Figure 7 As shown, the first end of capacitor C1 (corresponding to the first charge storage unit) is connected to the negative input terminal (corresponding to the second input terminal) of the operational amplifier OP. The second end of capacitor C1 is connected to the output terminal of the operational amplifier OP via switch S6. The second end of capacitor C1 is also connected to the positive input terminal (corresponding to the first input terminal) of the operational amplifier OP via switch S5. When switch S6 is on and switch S5 is off, capacitor C1 is connected between the output terminal and the negative input terminal of the operational amplifier OP. When switch S5 is on and switch S6 is off, capacitor C1 is connected between the positive input terminal and the negative input terminal of the operational amplifier OP.

[0079] like Figure 7 As shown, the first end of capacitor C2 (corresponding to the second charge storage unit) is connected to the negative input terminal of operational amplifier OP. The second end of capacitor C2 is connected to transistor Q72 via switch S8 and to transistor Q73 via switch S9. When switch S8 is on and switch S9 is off, transistor Q72 is connected to the branch of MOS transistor M73, generating a negative temperature coefficient voltage Vbe2. The second end of capacitor C2 receives the negative temperature coefficient voltage Vbe2. When switch S9 is on and switch S8 is off, transistor Q73 is connected to the branch of MOS transistor M73, generating a negative temperature coefficient voltage Vbe3. The second end of capacitor C2 receives the negative temperature coefficient voltage Vbe3.

[0080] In some possible implementations, such as Figure 7 As shown, the bandgap reference circuit 700 may further include a capacitor C3 (corresponding to the third charge storage unit described above). A first terminal of capacitor C3 is connected to the negative input terminal of the operational amplifier OP, and a second terminal of capacitor C3 is connected to the second-order compensation terminal Vb via switch S10. The second terminal of capacitor C3 is also connected to the reference ground terminal Vgnd via switch S11. When switch S10 is on and switch S11 is off, capacitor C3 is connected between the negative input terminal of the operational amplifier OP and the second-order compensation terminal Vb. When switch S10 is off and switch S11 is on, capacitor C3 is connected between the negative input terminal of the operational amplifier OP and the reference ground terminal Vgnd. The voltage at the second-order compensation terminal Vb is VB, which is proportional to the square of the temperature.

[0081] The operation of the circuit is described below using the example of I71 = I72 = Ib and a size ratio of 1:1:M for transistors Q71, Q72, and Q73.

[0082] In phase one (corresponding to the first period above)

[0083] Switches S5, S7, S8, and S10 are turned on, and switches S6, S9, and S11 are turned off. The connection structure of the bandgap reference circuit 700 is as follows: Figure 8A As shown, the positive and negative inputs of the operational amplifier OP are connected to the two ends of capacitor C1, respectively. The output of the operational amplifier OP is short-circuited to the negative input, forming a unity negative feedback structure. At this point, one end of capacitor C1 is connected to transistor Q71, one end of capacitor C2 is connected to transistor Q72, and capacitor C3 is connected to the second-order compensation terminal Vb, where the second-order compensation terminal Vb receives a voltage VB that is proportional to the square of the temperature. Since M71, M72, and M73 form a current mirror, and both M72 and M73 replicate the current of M71, the currents in M72 and M73 are equal. Therefore, the currents flowing through transistors Q71 and Q72 are equal and of equal magnitude, and Vbe1 = Vbe2. Assuming the offset voltage at the op amp input is Vos, then Vos is stored on capacitors C1, C2, and C3. The sum of the charges on C1, C2, and C3, i.e., the charge Qx1 at node X in phase 1, is:

[0084] Qx1=(C1+C2)·Vos+C3·(Vbe1+Vos-VB).

[0085] In phase two (corresponding to the second period above)

[0086] Switches S5, S7, S9, and S10 are disconnected, and switches S6, S8, and S11 are closed. The connection structure of the bandgap reference circuit 700 is as follows: Figure 8BAs shown, the positive input of the operational amplifier OP is disconnected from the capacitor C1, and is connected to the emitter of the transistor Q71; the capacitor C1 is connected between the output and the negative input of the operational amplifier OP; the capacitor C2 is connected between the X node and the emitter of the transistor Q73; and the capacitor C3 is connected between the X node and the reference ground Vgnd. Assuming that the output voltage of the operational amplifier OP is Vref, the charge Qx2 of the X node in phase two is:

[0087] Qx2=C3·(Vbe1+Vos)+C2·(Vbe1-Vbe3+Vos)+C1·(Vbe1+Vos-Vref)·

[0088] Since the charge of the X node is conserved, i.e., Qx1=Qx2, and since the area ratio of Q73 to Q71 is M:1, Vbe1-Vbe3=VT·ln M, it can be known that:

[0089] Vref=Vbe1+C2 / C1·VT·ln M+C3 / C1·VB·

[0090] Since VB is a voltage proportional to the square of temperature, C3 / C1·VB can compensate the quadratic term in Vbe1, i.e., the second-order temperature drift.

[0091] In the above example, the capacitor C3 accesses the voltage VB of the second-order compensation terminal Vb in phase one, and accesses the voltage of the reference ground Vgnd in phase two. In some examples, the voltage VB of the second-order compensation terminal Vb can also be accessed in phase two, and the voltage of the reference ground Vgnd can be accessed in phase one. At this time, Vref=Vbe1+C2 / C1·VT·ln M-C3 / C1·VB.

[0092] As an implementation, as shown in Figure 7 The bandgap reference circuit 700 can further include a notch filter (corresponding to the output module described above). The notch filter includes switches S1, S2, S3, S4 and capacitors C4, C5. In one period, switches S1, S3 are open, and S2, S4 are closed, at which time capacitor C4 samples the Vref of the current period, and capacitor C5 provides the Vref of the previous period; similarly, in the next period, switches S2, S4 are open, and S1, S3 are closed, at which time capacitor C5 samples the Vref of the current period, and capacitor C4 provides the Vref of the previous period. The notch filter makes the Vref output continuous.

[0093] The following describes an implementation of the fourth voltage (also referred to as VB in the present specification) proportional to the square of temperature.

[0094] In some embodiments, the fourth voltage generating module is configured to generate a seventh current I7 proportional to the square of the temperature based on the fifth current I5 having a positive temperature coefficient and the sixth current I6 having a negative temperature coefficient; and generate the fourth voltage V4 based on the seventh current I7.

[0095] As an implementation method, Figure 9 As shown, taking a transistor as an example, the fourth voltage generating module 900 may include: a fifth transistor Q95, wherein a first electrode of the fifth transistor Q95 receives the fifth current I5 and is used to generate a fifth voltage V5 with a negative temperature coefficient; a sixth transistor Q96, wherein a first electrode of the sixth transistor Q96 is connected to a second electrode of the fifth transistor Q95, and a second electrode of the sixth transistor Q96 is connected to a reference ground terminal Vgnd, and is used to generate a sixth voltage V6 with a negative temperature coefficient; a seventh transistor Q97, wherein a third electrode of the seventh transistor Q97 is connected to a third electrode of the fifth transistor Q95, and a first electrode of the seventh transistor Q97 is connected to a power supply terminal; and an eighth transistor Q98. The third electrode of the eighth transistor Q98 is connected to the second electrode of the seventh transistor Q97, and the second electrode of the eighth transistor Q98 is connected to the reference ground terminal; the first electrode of the eighth transistor Q98 outputs the seventh current I7; the ninth transistor Q99 is used to mirror the current of the sixth transistor Q96, the third electrode of the ninth transistor Q99 is connected to the third electrode of the sixth transistor Q96, the first electrode of the ninth transistor Q99 is connected to the second electrode of the seventh transistor Q97, and the second electrode of the ninth transistor Q99 is connected to the reference ground terminal Vgnd; the sixth current I6 is connected between the second electrode of the seventh transistor Q97 and the second electrode of the eighth transistor Q98.

[0096] The base-emitter voltage of the fifth transistor Q95 is V5, the base-emitter voltage of the sixth transistor Q96 is V6. The base-emitter voltage of the seventh transistor Q97 is V7, and the base-emitter voltage of the eighth transistor Q98 is V8. The current of the fifth transistor Q95 is I95, the current of the sixth transistor Q96 is I96, the current of the seventh transistor Q97 is I97, and the current of the eighth transistor Q98 is I98. Figure 9 As shown, it satisfies:

[0097] V5+V6=V7+V8;

[0098] I97=I5+I6;

[0099] I95=I96=I5.

[0100] From this we can see that: I98=I5 2 / (I5+I6). The fifth current I5 is a positive temperature coefficient current, and the sixth current I6 is a negative temperature coefficient current. Assuming that I5+I6 has zero temperature drift, we can get I98≈I5 2 / K. I98 can be regarded as the seventh current I7 proportional to the square of the temperature.

[0101] In some embodiments, as Figure 10 As shown, the circuit for generating a current proportional to the square of the temperature may include: a first current generating module 1001, for generating the above-mentioned fifth current I5; a conversion branch 1002 (shown as branch 4 in the figure), for generating a voltage with a negative temperature coefficient (shown as Vbe in the figure) based on the fifth current I5 (shown as IPTAT in the figure); a second current generating module 1003, for generating the above-mentioned sixth current I6 (shown as ICTAT in the figure) based on the voltage with a negative temperature coefficient; and the above-mentioned fourth voltage generating module 900.

[0102] As an implementation method, Figure 10 As shown, the first current generating module 1001 includes branch 1, branch 2, and branch 3. Branch 2 is the startup branch, providing bias for branches 1 and 3. Branch 1 generates Vbe1, and branch 3 generates Vbe2. The voltage difference between Vbe1 and Vbe2 in branches 1 and 3 flows through R1 to generate IPTAT. The conversion branch 1002 (i.e., branch 4) generates a conversion voltage Vbe based on IPTAT. The second current generating module 1003 generates ICTAT (i.e., sixth current I6) based on the conversion voltage Vbe flowing through R2.

[0103] An embodiment of the present application provides a reference voltage production method, which is applied to the above-mentioned bandgap reference circuit.

[0104] like Figure 11 As shown, the method includes:

[0105] Step S1101, during a first period, connecting a first charge storage unit between a first input terminal and a second input terminal of an operational amplifier module, connecting an output terminal of the operational amplifier module to the second input terminal, connecting a first voltage generating module to the first input terminal of the operational amplifier module, and connecting a second terminal of the second charge storage unit to the second voltage generating module;

[0106] Step S1102, during the second period, the first charge storage unit is connected between the second input terminal and the output terminal of the operational amplifier module, the second charge storage unit is connected between the second input terminal of the operational amplifier module and the second voltage generating module, the second terminal of the second charge storage unit is connected to the third voltage generating module, and the output terminal of the operational amplifier module generates a reference voltage.

[0107] In the first period, the first charge storage unit is connected between the first input terminal and the second input terminal of the operational amplifier module, the output terminal of the operational amplifier module is connected to the second input terminal, the first voltage generating module is connected to the first input terminal of the operational amplifier module, the second terminal of the second charge storage unit is connected to the second voltage generating module, so that the input offset voltage of the operational amplifier module is stored in the first and second charge storage units; in the second period, the first charge storage unit is connected between the second input terminal and the output terminal of the operational amplifier module, the second charge storage unit is connected between the second input terminal of the operational amplifier module and the second voltage generating module, so that the input offset voltage of the operational amplifier module is offset in the output voltage by the first and second charge storage units, and the second terminal of the second charge storage unit is connected to the third voltage generating module, so that a voltage difference with a positive temperature coefficient is generated, the temperature drift of the first voltage is compensated by the voltage difference, and the output terminal of the operational amplifier module can serve as the output terminal of the reference voltage in the second period.

[0108] As an implementation, the method further includes: in one of the first period and the second period, connecting the second terminal of the third charge storage unit to a reference ground terminal; and in the other of the first period and the second period, connecting the second terminal of the third charge storage unit to a second-order compensation terminal. In this implementation, high-order temperature drift can be compensated.

[0109] Embodiments of the present application also provide a chip including the bandgap reference circuit. The chip can be an integrated circuit (IC), which can be, but is not limited to, a system on chip (SOC) chip or a system in package (SIP) chip. The chip can eliminate the influence of the input offset voltage of the operational amplifier in the bandgap reference circuit on the reference voltage.

[0110] The electronic device can be, but is not limited to, a body weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a vehicle charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a touch pen, a true wireless earphone, a car central control screen, a car, a smart wearable device, a mobile terminal, and a smart home device. The smart wearable device includes, but is not limited to, a smart watch, a smart bracelet, and a cervical vertebra massage instrument. The mobile terminal includes, but is not limited to, a smart phone, a notebook computer, a tablet computer, and a POS (point of sales terminal) machine. The smart home device includes, but is not limited to, a smart socket, a smart rice cooker, a smart sweeper, and a smart lamp. The electronic device can eliminate the influence of the input offset voltage of an operational amplifier in a band gap reference circuit on a reference voltage.

[0111] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as the preferred embodiment, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the equivalent embodiments with the disclosed technical content without departing from the scope of the technical solution of the present application. Any modification, change, and modification of the above embodiments according to the technical essence of the present application are still within the scope of the technical solution of the present application.

Claims

1. A bandgap reference circuit, characterized by, The bandgap reference circuit comprises: an operational amplifier module; a first voltage generating module connected to a first input terminal of the operational amplifier module, configured to generate a first voltage with a negative temperature coefficient; a second voltage generating module configured to generate a second voltage; a third voltage generating module configured to generate a third voltage, the second voltage and the third voltage being different, and a difference between the second voltage and the third voltage having a positive temperature coefficient; a charge storage module comprising a first charge storage unit and a second charge storage unit, a first terminal of the second charge storage unit being connected to a second input terminal of the operational amplifier module; a switch network configured to: connect the first charge storage unit between the first input terminal and the second input terminal of the operational amplifier module, connect an output terminal of the operational amplifier module to the second input terminal, and connect a second terminal of the second charge storage unit to the second voltage generating module during a first period; and connect the first charge storage unit between the second input terminal and the output terminal of the operational amplifier module, and connect the second terminal of the second charge storage unit to the third voltage generating module during a second period; wherein the output terminal of the operational amplifier module serves as an output terminal of a reference voltage during the second period.

2. The bandgap reference circuit of claim 1, wherein: the charge storage module further comprises a third charge storage unit, a first terminal of the third charge storage unit being connected to the second input terminal of the operational amplifier module; the switch network is further configured to: connect a second terminal of the third charge storage unit to a reference ground terminal during one of the first period and the second period; and connect the second terminal of the third charge storage unit to a second order compensation terminal during the other of the first period and the second period; wherein the second order compensation terminal is configured to receive a fourth voltage proportional to a square of temperature.

3. The bandgap reference circuit of claim 1, wherein: the second voltage generating module comprises: a second current mirror configured to mirror a preset current to generate a second current; a second transistor, a first pole of the second transistor being configured to receive the second current to generate the second voltage during the first period; the third voltage generating module comprises: a third transistor, a first pole of the third transistor being configured to receive the second current to generate the third voltage during the second period; wherein the third transistor is different from the second transistor, such that the second voltage is different from the third voltage.

4. The bandgap reference circuit of claim 1, wherein, the second voltage generating module comprises a third current mirror and a fourth transistor, and the third voltage generating module comprises a fourth current mirror; wherein: the third current mirror is configured to mirror the preset current to generate a third current; the fourth current mirror is configured to mirror the preset current to generate a fourth current, the fourth current being different from the third current; a first pole of the fourth transistor is configured to receive the third current to generate the second voltage during the first period, and receive the fourth current to generate the third voltage during the second period.

5. A bandgap reference circuit as claimed in claim 3 or 4, characterized in that, the first voltage generating module comprises: a first current mirror configured to mirror the preset current to generate a first current; a first transistor having a first electrode receiving the first current to generate the first voltage.

6. The bandgap reference circuit of claim 1, wherein, The switch network comprises: a first switch connected between a first end of the first charge storage unit and a first input end of the operational amplifier module; a second switch connected between the first end of the first charge storage unit and an output end of the operational amplifier module; a third switch connected between a second input end and the output end of the operational amplifier module; wherein, during the first period, the first switch and the third switch are turned on, and the second switch is turned off; and during the second period, the second switch is turned on, and the first switch and the third switch are turned off.

7. The bandgap reference circuit of claim 3, wherein, The switch network further comprises: a fourth switch connected between the second current mirror and a first electrode of the second transistor; a fifth switch connected between the second current mirror and a first electrode of the third transistor; wherein, during the first period, the fifth switch is turned on, and the fourth switch is turned off; and during the second period, the fifth switch is turned off, and the fourth switch is turned on.

8. The bandgap reference circuit of claim 4, wherein, The switch network further comprises: a sixth switch connected between the third current mirror and a first electrode of the fourth transistor; a seventh switch connected between the fourth current mirror and the first electrode of the fourth transistor; wherein, during the first period, the seventh switch is turned off, and the sixth switch is turned on; and during the second period, the seventh switch is turned on, and the sixth switch is turned off.

9. The bandgap reference circuit of claim 2, wherein, The switch network further comprises: an eighth switch connected between the third charge storage unit and a reference ground end; a ninth switch connected between the third charge storage unit and a second-order compensation end; wherein, during one of the first period and the second period, the eighth switch is turned on, and the ninth switch is turned off; and during the other of the first period and the second period, the eighth switch is turned off, and the ninth switch is turned on.

10. The bandgap reference circuit of claim 2, wherein, Further comprising: a fourth voltage generation module configured to generate a seventh current proportional to a square of temperature based on a fifth current having a positive temperature coefficient and a sixth current having a negative temperature coefficient; and generate the fourth voltage based on the seventh current. The fourth voltage generation module comprises:

11. The bandgap reference circuit of claim 10, wherein, a fifth transistor having a first electrode receiving the fifth current, configured to generate a fifth voltage having a negative temperature coefficient; a sixth transistor having a first electrode connected to a second electrode of the fifth transistor, and a second electrode connected to a reference ground end, configured to generate a sixth voltage having a negative temperature coefficient; a seventh transistor having a third electrode connected to a third electrode of the fifth transistor, and a first electrode connected to a power supply end; an eighth transistor having a third electrode connected to a second electrode of the seventh transistor, and a second electrode connected to the reference ground end; and a first electrode outputting the seventh current. ​ a ninth transistor for mirroring current of the sixth transistor, a third pole of the ninth transistor being connected with a third pole of the sixth transistor, a first pole of the ninth transistor being connected with a second pole of the seventh transistor, and a second pole of the ninth transistor being connected with a reference ground terminal; the sixth current is connected between the second pole of the seventh transistor and a second pole of the eighth transistor.

12. The bandgap reference circuit of claim 10, wherein, Further comprising: a first current generating module for generating the fifth current; a conversion branch for generating a conversion voltage with negative temperature coefficient based on the fifth current; a second current generating module for generating the sixth current based on the conversion voltage with negative temperature coefficient.

13. The bandgap reference circuit of claim 1, wherein, Further comprising: an output module for sampling the output voltage of the operational amplifier module in the second period of any cycle, and taking the sampling result as a reference voltage of the next cycle; and taking the sampling result of the last cycle of the current cycle as the reference voltage of the current cycle in any cycle.

14. A method of producing a reference voltage, characterized by, The method is applied to the bandgap reference circuit of claim 1, and the method comprises: in the first period, connecting the first charge storage unit between the first input terminal and the second input terminal of the operational amplifier module, connecting the output terminal of the operational amplifier module with the second input terminal, and connecting the second terminal of the second charge storage unit with the second voltage generating module; and in the second period, connecting the first charge storage unit between the second input terminal and the output terminal of the operational amplifier module, and connecting the second terminal of the second charge storage unit with the third voltage generating module, and the output terminal of the operational amplifier module generates a reference voltage.

15. The method of claim 14, wherein the reference voltage is produced by a voltage reference circuit. The method is applied to the bandgap reference circuit of claim 2, and the method further comprises: in one of the first period and the second period, connecting the second terminal of the third charge storage unit with a reference ground terminal; in the other of the first period and the second period, connecting the second terminal of the third charge storage unit with a second-order compensation terminal.

16. A chip, characterized by The bandgap reference circuit of any one of claims 1 to 13 is included.

17. An electronic device, comprising: The device body and the chip of claim 16 are included in the device body.

Images