Turbo code decoding methods and Turbo code decoders

Abstract

The present invention relates to a Turbo code decoding method and a Turbo code decoder, the decoder comprises: a decoding control module, a first component decoder, a second component decoder and a hard decision module; the decoding control module is used to read the data to be decoded in the pre-decoding storage area after reading the decoding start instruction, and after the recovery and puncturing, the recovery and puncturing data are obtained, and the recovery and puncturing data and the deinterleaved data are sent to the first component decoder for decoding to obtain a first decoding result; the decoding control module is also used to obtain interleaved data, and the interleaved data and the recovery and puncturing data are input into the second component decoder to obtain a second decoding result; the hard decision module is used to perform iterative calculation when it is judged that the second decoding result does not meet the preset condition, and output the second decoding result when the second decoding result meets the preset condition. By adding channel confidence, the application is more flexible and the decoding performance is high.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a Turbo code decoding method and a Turbo code decoder. Background Art

[0002] In order to further enhance the anti-interference capability of navigation signals, the satellite navigation system uses Turbo codes with superior performance as its channel coding technology. Turbo codes are a type of cascaded code. The basic principle is that the encoder cascades two component encoders in parallel through an interleaver, and the two component encoders output corresponding check bits respectively; the decoder performs iterative decoding between the two component decoders, and the component decoders transmit external information without positive feedback. Turbo codes have better error correction performance, and the performance is close to the Shannon limit.

[0003] Among many Turbo decoding algorithms, the log-map algorithm has relatively superior performance and complexity. In this algorithm, the impact of carrier phase offset on Turbo decoding performance is mainly reflected in the impact on channel confidence, which is very important in the Turbo decoding process based on maximum a posteriori probability. Therefore, it is urgent to provide a Turbo code decoding method and a Turbo code decoder to ensure that while reducing the resource consumption caused by the channel confidence multiplication operation in channel multiplexing, the main controller can also configure the channel confidence according to the tracked carrier-to-wave ratio to improve flexibility. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a Turbo code decoding method and a Turbo code decoder.

[0005] To solve the above problems, the technical solution adopted by the present invention is:

[0006] In one aspect, a turbo code decoder is provided, comprising: a decoding control module, a first component decoder, a second component decoder, and a hard decision module;

[0007] The decoding control module is used to read the decoding start instruction, read the data to be decoded from the pre-decoding storage area, multiply the data to be decoded by the set channel confidence value, and then perform recovery puncturing to obtain the recovery punctured data; and read the deinterleaved data from the external information storage, the deinterleaved data is obtained in the following manner: the external information obtained by the second component decoder is stored in the external information storage, and the data read from the external information storage is the deinterleaved data according to the data of the deinterleaving table as the storage address;

[0008] The first component decoder is used to perform decoding based on the deinterleaved data and the restored punctured data to obtain a first decoding result;

[0009] The decoding control module is also used to sequentially read out the external information of the decoding result of the first component decoder stored in the external information memory and using the data of the interleaving table as the address of the external information memory, obtain interleaved data, and input the interleaved data and the restored punctured data into the second component decoder;

[0010] The second component decoder is used to decode based on the interleaved data and the restored punctured data to obtain a second decoding result;

[0011] The hard decision module is used to perform iterative calculation when it is determined that the second decoding result does not meet the preset condition, and output the second decoding result when the second decoding result meets the preset condition.

[0012] As an implementation mode of the invention, it also includes: a main controller and a ping-pong memory, and the ping-pong memory is connected to the main controller and the decoding control module respectively; two pre-decoding storage areas are arranged in the ping-pong memory, and at least one of the pre-decoding storage areas is in an idle state;

[0013] The main controller is used to receive the data to be decoded, write the data to be decoded into the pre-decoding storage area in an idle state, and configure the decoding parameters after determining that the entire frame of data has been written;

[0014] The decoding control module is also used to initialize the internal variables of the module before decoding and read the decoding parameters, so that after reading the decoding start instruction, it can process the data to be decoded based on the decoding parameters.

[0015] As an implementation mode of the invention, the decoding control module is further used to send a pre-decoding storage area idle notification to the main controller after multiplying the data to be decoded by a set channel confidence value and completing the recovery and puncturing process.

[0016] As an implementation mode of the invention, the channel confidence value is calculated by the main controller based on the load-to-construction ratio, and is obtained by looking up a table according to the value of the load-to-construction ratio.

[0017] As an embodiment of the invention, the second component decoder includes a forward initialization unit, a backward initialization unit, and a plurality of sub-block decoders connected in sequence;

[0018] The forward initialization unit is used to initialize the forward path metric value of the first sub-block decoder, and the initial value of the forward path metric value of the remaining sub-block decoders is the calculation result of the last information of the previous sub-block;

[0019] The backward initialization unit is used to initialize the backward path metric value of the last sub-block decoder and the initial values ​​of the backward path metric values ​​of other sub-block decoders in the first iteration; in the next iteration, the initial value of the backward path metric value of the decoding of this block except the last sub-block decoder is the result of backward recursion of the next sub-block of the sub-block corresponding to the previous iteration.

[0020] As an implementation mode of the invention, the number of sub-block decoders is obtained in the following manner:

[0021] Input the code length value L / 32 of the information sequence with code length L. If there is no remainder, the number of sub-block decoders N is L / 32, and the information length of all sub-blocks is 32; if there is a remainder, the number of sub-blocks N is the integer part of L / 32 + 1, and the information length of the first N-2 blocks is 32, and the total information length of the remaining 2 blocks is X=L-32*(N-2);

[0022] Among them, if X / 2 has no remainder, the information length of the N-1th block and the Nth block is X / 2; if X / 2 has a remainder, the information length X1 of the N-1th block is the integer part of X / 2+1, and the information length X2 of the Nth block is the integer part of X / 2.

[0023] As an embodiment of the invention, the first component decoder and the second component decoder are both designed as three-stage pipelines, the first stage pipeline is mainly used for data preparation, the second stage pipeline is mainly used for completing the 8-state calculation of the forward path metric value recursive alpha and the backward path metric value recursive beta, and the third stage pipeline is mainly used for completing the calculation of the log-likelihood ratio.

[0024] As an implementation mode of the invention, in each iterative operation, the external information of the decoding result of the second component decoder is deinterleaved through the deinterleaving table and the obtained data is used as the deinterleaved data to participate in the decoding of the first component decoder;

[0025] The deinterleaving table is generated by placing the position numbers of the interleaving table in corresponding positions according to the data in the interleaving table, and re-forming new data, namely the deinterleaving table.

[0026] On the other hand, a Turbo code decoding method is provided, the method comprising:

[0027] After the decoding start instruction is read by the decoding control module, the data to be decoded is read from the pre-decoding storage area, the data to be decoded is multiplied by the set channel confidence value, and then the recovery puncturing is performed to obtain the recovery punctured data; and the deinterleaved data is read from the external information storage, the deinterleaved data is obtained in the following manner: the external information obtained by the second component decoder is stored in the external information storage, and the data read from the external information storage is the deinterleaved data according to the data of the deinterleaving table as the storage address;

[0028] Decoding based on the deinterleaved data and the restored punctured data by a first component decoder to obtain a first decoding result;

[0029] The external information of the decoding result of the first component decoder stored in the external information memory and using the data of the interleaving table as the address of the external information memory is sequentially read out by the decoding control module to obtain interleaved data, and the interleaved data and the restored punctured data are input into the second component decoder;

[0030] Decoding based on the interleaved data and the restored punctured data by a second component decoder to obtain a second decoding result;

[0031] The hard decision module performs iterative calculation when it is determined that the second decoding result does not meet the preset condition, and outputs the second decoding result when the second decoding result meets the preset condition.

[0032] As an embodiment of the invention, the method further comprises:

[0033] Receiving data to be decoded through the main controller, writing the data to be decoded into a pre-decoding storage area in an idle state, and configuring decoding parameters after determining that the entire frame of data has been written;

[0034] The decoding control module initializes the internal variables of the module before decoding and reads the decoding parameters, so that after reading the decoding start instruction, it can process the data to be decoded based on the decoding parameters.

[0035] The beneficial effects of adopting the above technical solution are:

[0036] A Turbo code decoder provided by the present invention can reduce resource consumption caused by channel confidence multiplication operation in channel multiplexing by adding channel confidence in a decoding control module, and can also enable a main controller to configure channel confidence according to the tracked carrier ratio, which is more flexible and more accurate.

[0037] In addition, by setting up a ping-pong memory, which has two pre-decoding storage areas and one of the pre-decoding storage areas is in an idle state, when multiple frames of data need to be decoded, the data can be written to the idle memory to ensure that the decoding of the next frame is started immediately after the subsequent component decoder completes the current decoding, thereby saving a lot of data writing time.

[0038] In addition, both the first component decoder and the second component decoder are designed as three-stage pipelines. The first stage pipeline is mainly used for data preparation, the second stage pipeline is mainly used to complete the 8-state calculation of the forward path metric value recursive alpha and the backward path metric value recursive beta, and the third stage pipeline is mainly used to complete the calculation of the log-likelihood ratio. The first component decoder and the second component decoder can reuse this pipeline, which can reduce a lot of hardware resources.

[0039] In addition, the external information of the decoding result of the second component decoder is deinterleaved through the deinterleaving table and the data obtained is used as deinterleaved data to participate in the decoding of the first component decoder; through the design of the deinterleaving table, the decoding timing of the first component decoder and the second component decoder is the same, which can save time and consider the multiplexing of sub-block decoding.

[0040] The present invention adopts a block-based, reusable block-based pipeline structure Turbo decoder that supports configurable channel confidence, configurable code rate, configurable code length, configurable message polarity, and configurable number of iterations. The decoder is flexible and configurable, has a fast decoding speed, and consumes less resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a schematic diagram of the structure of a Turbo code decoder.

[0042] Figure 2 It is a flowchart of Turbo code decoding.

[0043] Figure 3 It is the decoding front-end data processing.

[0044] Figure 4 This is the alpha initial value design process diagram.

[0045] Figure 5 It is the beta initial value process diagram.

[0046] Figure 6 It is a component decoder decoding pipeline structure.

[0047] Figure 7 It is a sequential pipeline structure for calculating alpha and beta.

[0048] Figure 8 It is an alternating pipeline structure for calculating alpha and beta.

[0049] Fig. 9 It is a graph of data after prior information interleaving and deinterleaving.

[0050] Fig.10 It is the corresponding graph of the prior information de-interleaving table. DETAILED DESCRIPTION

[0051] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is clearly and completely described below in conjunction with specific embodiments.

[0052] The embodiment of the present invention provides a Turbo code decoder, such as Figure 1 As shown, it includes: a decoding control module, a first component decoder, a second component decoder, and a hard decision module;

[0053] The decoding control module is used to read the decoding start instruction, read the data to be decoded in the pre-decoding storage area, multiply the data to be decoded by the set channel confidence value, and then perform recovery puncturing to obtain the recovery punctured data; and read the deinterleaved data from the external information storage, the deinterleaved data is obtained in the following manner: the external information obtained by the second component decoder is stored in the external information storage, and the data read from the external information storage is the deinterleaved data according to the data of the deinterleaving table as the storage address;

[0054] The decoding control module is also used to sequentially read out the external information of the first component decoder decoding result stored in the external information memory and using the data of the interleaving table as the address of the external information memory, obtain interleaved data, and send the deinterleaved data and the restored punctured data to the first component decoder;

[0055] The first component decoder is used to perform decoding based on the deinterleaved data and the restored punctured data to obtain a first decoding result;

[0056] The decoding control module is also used to sequentially read out the external information of the decoding result of the first component decoder stored in the external information memory and using the data of the interleaving table as the address of the external information memory, obtain interleaved data, and input the interleaved data and the restored punctured data into the second component decoder;

[0057] The second component decoder is used to decode based on the interleaved data and the restored punctured data to obtain a second decoding result;

[0058] The hard decision module is used to perform iterative calculation when it is determined that the second decoding result does not meet the preset condition, and output the second decoding result when the second decoding result meets the preset condition.

[0059] The decoding process is as follows Figure 2 The turbo decoding control module starts the decoding process after reading the decoding start valid flag (i.e., the decoding start instruction), reads the data to be decoded from the pre-decoding data memory, and performs the following two processes on the data to be decoded: 1. Reading the data to be decoded in sequence according to the deinterleaving table to obtain deinterleaved data; 2. Multiplying the data to be decoded by the channel confidence value, and then performing recovery and puncturing to obtain recovery and punctured data, and temporarily storing the data in the memory.

[0060] Afterwards, the decoding control module sends the deinterleaved data and the restored punctured data to the first component decoder for decoding, calculates the first external information after obtaining the first decoding result, interleaves the first external information to obtain interleaved data, and sends the interleaved data and the restored punctured data to the second component decoder for decoding.

[0061] The sign bit of each data of the decoding result of the second component decoder is compared with each data of the previous iteration result. If they are completely consistent, the decoding is terminated. If not, it is determined whether the number of iterations has reached the expected set number of iterations. If it has reached, the decoding is terminated. If not, the iteration counter is increased by 1, the second external information is calculated, and the next iteration process is carried out until the decoding exit condition is met.

[0062] A turbo code decoder provided by an embodiment of the present invention can reduce resource consumption caused by channel confidence multiplication operation in channel multiplexing by adding channel confidence in a decoding control module, and can also enable a main controller to configure channel confidence according to a tracked carrier-to-noise ratio, which is more flexible and more accurate. In the present application, the channel confidence value is related to the carrier-to-noise ratio of the tracked channel, the carrier-to-noise ratio is calculated by the main controller, and the channel confidence obtained by looking up a table according to the value of the carrier-to-noise ratio is written to the turbo decoding module, which is simple.

[0063] The present application further describes the structure of a Turbo code decoder below.

[0064] In view of the process in which the decoding control module reads the data to be decoded in the pre-decoding storage area, in order to facilitate the pre-decoding storage area to quickly store data, in a possible implementation, the Turbo code decoder further includes: a main controller and a ping-pong memory, and the ping-pong memory is connected to the main controller and the decoding control module respectively; two pre-decoding storage areas are arranged in the ping-pong memory, and one of the pre-decoding storage areas is in an idle state;

[0065] The main controller is used to receive the data to be decoded, write the data to be decoded into a pre-decoding storage area in an idle state, and configure the decoding parameters after determining that the entire frame of data has been written. The decoding parameters include: code length, code rate, message polarity, number of iterations, number of blocks, data length of the last block, and data length of the second to last block;

[0066] The decoding control module is also used to initialize the internal variables of the module before decoding and read the decoding parameters so that after reading the decoding start instruction, it can process the data to be decoded based on the decoding parameters; and after multiplying the data to be decoded by the set channel confidence value and completing the recovery and puncturing processing, send a pre-decoding storage area idle notification to the main controller.

[0067] Specifically, it involves decoding front-end data processing. Since the decoder input is a continuous bit stream, and the presence of the interleaver makes the decoder process the entire frame. Therefore, a buffer is needed to store the data frame. The schematic diagram of decoding front-end data processing is shown in Figure 2 As shown. The main controller communicates with the decoding module through the bus, specifically, the pre-decoding memory and register in the decoding module communicate through the bus. The bus length is 32 bits, so the data width of 1 / 2 of the memory is 32 bits. Because the data is quantized to 8 bits, 4 valid data can be written to the bus each time, which can shorten the data writing time of the decoded data with a length of L by 4 times.

[0068] Since the Turbo decoder has a large codeword reception delay, it needs to receive the entire frame of data before decoding. It also takes time for the main controller to write data to the decoding module, so a ping-pong memory (i.e. Figure 3 Memory 1 and Memory 2 in the ping-pong memory). After the main controller receives the data, it writes the data to be decoded into the free memory 1 / 2. After the whole frame of data is written, it configures the parameters of code length, code rate, message polarity, number of iterations, number of blocks, data length of the last block, and data length of the second to last block, and starts decoding. After the logic completes the recovery and deletion, it notifies the main controller that there is free space in memory 1 / 2, and can continue to write new data to the free memory of the ping-pong memory.

[0069] In this way, when multiple frames of data need to be decoded, the data can be written to the idle memory in advance to ensure that the decoding of the next frame is started immediately after the decoding of the current frame is completed, thereby saving a lot of data writing time.

[0070] For the decoding process of the first component decoder and the second component decoder, in order to improve the decoding efficiency, in a possible implementation, the first component decoder and the second component decoder are both designed in blocks. It should be noted that: for convolutional codes, when calculating the state matrix, no matter where it starts, as long as it is recursively long enough, its credibility is the same as starting from the start state or the end state, which means that the calculation of β in the maximum a posteriori probability algorithm does not have to start from the end of the sequence. Therefore, the block design of this application can ensure the accuracy of the results.

[0071] Hereinafter, the present invention will be specifically described with respect to the block design of the second component decoder, and the structure of the first component decoder is the same as that of the second component decoder.

[0072] In a possible implementation, the second component decoder includes a forward initialization unit, a backward initialization unit, and a plurality of sequentially connected sub-block decoders;

[0073] The forward initialization unit is used to initialize the forward path metric value of the first sub-block decoder, and the initial value of the forward path metric value of the remaining sub-block decoders is the calculation result of the last information of the previous sub-block;

[0074] The backward initialization unit is used to initialize the backward path metric value of the last sub-block decoder and the initial values ​​of the backward path metric values ​​of other sub-block decoders in the first iteration; in the next iteration, the initial value of the backward path metric value of the decoding of this block except the last sub-block decoder is the result of backward recursion of the next sub-block of the sub-block corresponding to the previous iteration.

[0075] The number of sub-block decoders is obtained in the following way:

[0076] Input the code length value L / 32 of the information sequence with code length L. If there is no remainder, the number of sub-block decoders N is L / 32, and the information length of all sub-blocks is 32; if there is a remainder, the number of sub-blocks N is the integer part of L / 32 + 1, and the information length of the first N-2 blocks is 32, and the total information length of the remaining 2 blocks is X=L-32*(N-2);

[0077] Among them, if X / 2 has no remainder, the information length of the N-1th block and the Nth block is X / 2; if X / 2 has a remainder, the information length X1 of the N-1th block is the integer part of X / 2+1, and the information length X2 of the Nth block is the integer part of X / 2.

[0078] The following block calculation is performed using the information sequence length L as 1811 and L as 1600 as examples:

[0079] Length is 1811: N=1811 / 32= 56.59375, the value of N is 56+1=57, so the information sequence of length 1811 is divided into 57 blocks. Among them, the information length of each block of the first 55 blocks is 32, and the information length of the 56th block is X1=(181155*32) / 2=25.5, so the information length X1 of the 56th block is 26, and the information length X2 of the 57th block is 25.

[0080] The length is 1600: N=1600 / 32=50, the value of N is 50, and the information length of all sub-blocks is 32.

[0081] The execution operation of the second component decoder after the block division in the above manner is specifically as follows, and correspondingly, the execution operation of the first component decoder is the same as the above:

[0082] In all the iterative calculations of the forward recursion, only the forward path metric value of the first sub-block is initialized, and the initial value is (0, -255, -255, -255, -255, -255, -255, -255). The initial value of each sub-block is the calculation result of the last information of the previous sub-block. The initial value of each block of the forward path metric value is as follows: Figure 4 The second component decoder (ie, Figure 4 The second component decoder in the decoder) alpha0 (0, -255, -255, -255, -255, -255, -255, -255) is the initial value of the first sub-block. After recursive calculation 32 times, alpha11 is obtained. Alpha11 is used as the initial value of the second sub-block. After recursive calculation 32 times, alpha12 is obtained. And so on. The last sub-block uses the result calculated by the second to last block as its initial value.

[0083] In the backward recursive calculation, the initial value of the backward path metric value of the last sub-block of the second component decoder is configured by the main controller through the bus. It can be configured as all 0 or (0, -255, -255, -255, -255, -255, -255, -255). The initial value of the backward path metric value of the remaining sub-blocks of the second component decoder in the first iteration is 0. Except for the first iteration, the initial value of the backward path metric value of this block except the last sub-block in this iteration is the result of backward recursion of the next sub-block corresponding to the sub-block of the corresponding component decoder in the previous iteration. The initial value of the backward path metric value of each sub-block is as follows: Figure 5As shown. The initial value Beta0 of the last sub-block of the first component decoder and the second component decoder is input by the main controller. The backward recursive result Beta2 of the second sub-block of the first iteration of the first component decoder is used as the initial value of the backward recursive result of the first sub-block of the second iteration. The backward recursive result Beta3 of the third sub-block of the first iteration is used as the initial value of the backward recursive result of the second sub-block of the second iteration, and so on. The recursive result Beta21 of the second sub-block of the second iteration is used as the initial value of the recursive result of the first sub-block of the third iteration, and so on, until the iteration ends.

[0084] Furthermore, when tracking signals, the number of channels that can be tracked is up to 15, and the bit stream tracked by each channel is continuous, and each bit has a receiving code delay. In order to meet the decoding time requirements of decoding when all 15 channel data are received and not affecting data loss, the decoding process adopts a pipeline design.

[0085] In the present invention, the first component decoder and the second component decoder are both designed as three-stage pipelines. The first stage pipeline mainly performs data preparation, the second stage pipeline mainly completes the 8-state calculation of the forward path metric value recursion alpha and the backward path metric value recursion beta, and the third stage pipeline mainly completes the calculation of the log-likelihood ratio. Figure 6 The first component decoder and the second component decoder can reuse the pipeline, which can reduce a lot of hardware resources.

[0086] The detailed process of calculating alpha and beta pipelines at the second level, the comparison between sequential execution and alternating execution, such as Figure 7 and Figure 8 As shown in the figure, the execution is sequential, clk represents time, and 1 clk represents a clock cycle. a represents the data of forward recursion, and b represents the data of backward recursion. alpha is the result of calculating alpha, and beta is the result of calculating beta.

[0087] from Figure 7 As can be seen from the above, it takes 5 clock cycles to calculate an alpha value. If a block of alpha and beta with a length of 32 is calculated, it takes 5x32x2=320 clock cycles. If an alternating execution scheme is used, such as Figure 8 As shown in the figure, alpha and beta are calculated alternately. Since it takes 5 clock cycles to calculate one alpha, a 0 is inserted after a and b in the original data. Although it seems that the calculation of 0 is a waste, it actually makes the pipeline smoother. Finally, it only takes 99 clocks to calculate a block of alpha and beta with a length of 32, which greatly improves the decoding speed.

[0088] In addition, during the decoding process, the reliable information transmitted between the first component decoder and the second component decoder needs to be interleaved and deinterleaved once for each iteration. The data to be decoded is stored in the pre-decoding storage area, and the prior information such as Fig. 9 Stored in sequence.

[0089] Since the present invention adopts block decoding, an interleaver is used when the second component decoder decodes, so when decoding, it is only necessary to read data from the corresponding position in the prior information storage according to the interleaver table. According to the prior art: Fig. 9 The first block of interleaved data d4, d8, d3, d7 in the first block is subjected to block operation, and the second component decoder can be decoded once according to the block after interleaving. When decoding the first component decoder, the prior information needs to pass through the deinterleaver, such as Fig. 9 As shown in the deinterleaved data, when performing block decoding, the prior information d0 is in the second block of data after deinterleaving, d1 is in the third block of data, d2 is in the first block of data, d3 is in the second block of data, and so on. It is necessary to deinterleave the entire data according to the interleaving table again in each iteration and store it in the memory before decoding. This affects the decoding time. The more iterations there are, the longer the decoding time will be, which seriously affects the decoding speed.

[0090] To avoid the above situation, in the present invention, the external information of the decoding result of the second component decoder is deinterleaved through the deinterleaving table and the data obtained is used as deinterleaved data to participate in the decoding of the first component decoder; the generation method of the deinterleaving table includes: placing the position serial number of the interleaving table in the corresponding position according to the data in the interleaving table, and re-forming new data, that is, the deinterleaving table.

[0091] The deinterleaving table is generated as follows: Fig.10 As shown. The sequence numbers of the interleaving table and the deinterleaving table both start from 0. The sequence number of the first data is 0. The first data of the interleaving table is 4. The sequence number 0 is placed at the position of sequence number 4 of the new data sequence. The second data needs to be 1. The second data of the interleaving table is 8. The sequence number 1 is placed at the position of sequence number 8 of the new data sequence. And so on. The new sequence 10,6,8,2,0,4,11,3,1,7,9,5 is the deinterleaving table.

[0092] By designing the de-interleaving table, the decoding timings of the first component decoder and the second component decoder are the same, which can save time and take into account the multiplexing of sub-block decoding.

[0093] The present invention adopts a block-based, reusable block pipeline result Turbo decoder that supports configurable channel confidence, configurable code rate, configurable code length, configurable message polarity, and configurable number of iterations. The decoder is flexible and configurable, has a fast decoding speed, and consumes less resources.

[0094] The embodiment of the present invention further provides a Turbo code decoding method, the method comprising:

[0095] After the decoding start instruction is read by the decoding control module, the data to be decoded is read from the pre-decoding storage area, the data to be decoded is multiplied by the set channel confidence value, and then the recovery puncturing is performed to obtain the recovery punctured data; and the deinterleaved data is read from the external information storage, the deinterleaved data is obtained in the following manner: the external information obtained by the second component decoder is stored in the external information storage, and the data read from the external information storage is the deinterleaved data according to the data of the deinterleaving table as the storage address;

[0096] Decoding based on the deinterleaved data and the restored punctured data by a first component decoder to obtain a first decoding result;

[0097] The external information of the decoding result of the first component decoder stored in the external information memory and using the data of the interleaving table as the address of the external information memory is sequentially read out by the decoding control module to obtain interleaved data, and the interleaved data and the restored punctured data are input into the second component decoder;

[0098] Decoding based on the interleaved data and the restored punctured data by a second component decoder to obtain a second decoding result;

[0099] The hard decision module performs iterative calculation when it is determined that the second decoding result does not meet the preset condition, and outputs the second decoding result when the second decoding result meets the preset condition.

[0100] Furthermore, the method further comprises:

[0101] Receiving data to be decoded through the main controller, writing the data to be decoded into a pre-decoding storage area in an idle state, and configuring decoding parameters after determining that the entire frame of data has been written;

[0102] The decoding control module initializes the internal variables of the module before decoding and reads the decoding parameters, so that after reading the decoding start instruction, it can process the data to be decoded based on the decoding parameters.

[0103] Furthermore, the method further comprises: after the decoding control module multiplies the data to be decoded by a set channel confidence value and completes the recovery and puncturing process, sending a pre-decoding storage area idle notification to the main controller.

[0104] Furthermore, the channel confidence value is obtained by calculating the load ratio by the main controller and looking up the table according to the value of the load ratio.

[0105] Furthermore, the method further comprises:

[0106] Initializing the forward path metric value of the first sub-block decoder by the forward initialization unit, and the initial value of the forward path metric value of each of the remaining sub-block decoders is the calculation result of the last information of the previous sub-block;

[0107] The backward path metric value of the last sub-block decoder and the initial values ​​of the backward path metric values ​​of other sub-block decoders in the first iteration are initialized by the backward initialization unit; in the next iteration, the initial value of the backward path metric value of the decoding of this block except the last sub-block decoder is the result of backward recursion of the next sub-block of the sub-block corresponding to the previous iteration.

[0108] Furthermore, the number of sub-block decoders is obtained in the following manner:

[0109] Input the code length value L / 32 of the information sequence with code length L. If there is no remainder, the number of sub-block decoders N is L / 32, and the information length of all sub-blocks is 32; if there is a remainder, the number of sub-blocks N is the integer part of L / 32 + 1, and the information length of the first N-2 blocks is 32, and the total information length of the remaining 2 blocks is X=L-32*(N-2);

[0110] Among them, if X / 2 has no remainder, the information length of the N-1th block and the Nth block is X / 2; if X / 2 has a remainder, the information length X1 of the N-1th block is the integer part of X / 2+1, and the information length X2 of the Nth block is the integer part of X / 2.

[0111] Furthermore, the first component decoder and the second component decoder are both designed as three-stage pipelines, the first stage pipeline mainly performs data preparation, the second stage pipeline mainly completes the 8-state calculation of the forward path metric value recursive alpha and the backward path metric value recursive beta, and the third stage pipeline mainly completes the calculation of the log-likelihood ratio.

[0112] Furthermore, the method further comprises:

[0113] In each iterative operation, the external information of the decoding result of the second component decoder is deinterleaved through the deinterleaving table to obtain data to participate in the decoding of the first component decoder as deinterleaved data;

[0114] The deinterleaving table is generated by placing the position numbers of the interleaving table in corresponding positions according to the data in the interleaving table, and re-forming new data, namely the deinterleaving table.

Claims

1. A Turbo code decoder, characterized in that: It includes: Ping Pong A memory, a decoding control module, a first component decoder, a second component decoder, and a hard decision module; The ping-pong memory is connected to the decoding control module, and is provided with two pre-decoding storage areas, and at least one of the pre-decoding storage areas is in an idle state; The decoding control module is used to read the decoding start instruction, read the data to be decoded from the pre-decoding storage area, multiply the data to be decoded by the set channel confidence value, and then perform recovery puncturing to obtain the recovery punctured data; and read the deinterleaved data from the external information storage, the deinterleaved data is obtained in the following manner: the external information obtained by the second component decoder is stored in the external information storage, and the data read from the external information storage is the deinterleaved data according to the data of the deinterleaving table as the storage address; The first component decoder is used to perform decoding based on the deinterleaved data and the restored punctured data to obtain a first decoding result; The decoding control module is also used to sequentially read out the external information of the decoding result of the first component decoder stored in the external information memory and using the data of the interleaving table as the address of the external information memory, obtain interleaved data, and input the interleaved data and the restored punctured data into the second component decoder; The second component decoder is used to decode based on the interleaved data and the restored punctured data to obtain a second decoding result; The hard decision module is used to perform iterative calculation when it is determined that the second decoding result does not meet the preset condition, and output the second decoding result when the second decoding result meets the preset condition.

2. A Turbo code decoder according to claim 1, characterized in that: It also includes: a main controller connected to the ping-pong memory; The main controller is used to receive the data to be decoded, write the data to be decoded into the pre-decoding storage area in an idle state, and configure the decoding parameters after determining that the entire frame of data has been written; The decoding control module is also used to initialize the internal variables of the module before decoding and read the decoding parameters, so that after reading the decoding start instruction, it can process the data to be decoded based on the decoding parameters.

3. A Turbo code decoder according to claim 2, characterized in that: The decoding control module is further configured to send a pre-decoding storage area idle notification to the main controller after multiplying the data to be decoded by a set channel confidence value and completing the recovery and puncturing process.

4. A Turbo code decoder according to claim 2, characterized in that: The channel confidence value is calculated by the main controller based on the load-to-construction ratio, and is obtained by looking up a table according to the value of the load-to-construction ratio.

5. A Turbo code decoder according to claim 1, characterized in that: The second component decoder includes a forward initialization unit, a backward initialization unit, and a plurality of sequentially connected sub-block decoders; The forward initialization unit is used to initialize the forward path metric value of the first sub-block decoder, and the initial value of the forward path metric value of the remaining sub-block decoders is the calculation result of the last information of the previous sub-block; The backward initialization unit is used to initialize the backward path metric value of the last sub-block decoder and the initial value of the backward path metric value of each other sub-block decoder in the first iteration; In the next iteration, the initial value of the backward path metric value of the current block decoded except the last sub-block decoder is the result of the backward recursion of the next sub-block of the corresponding sub-block in the previous iteration.

6. A Turbo code decoder according to claim 5, characterized in that: The number of sub-block decoders is obtained in the following way: Input the code length value L / 32 of the information sequence with code length L. If there is no remainder, the number of sub-block decoders N is L / 32, and the information length of all sub-blocks is 32; if there is a remainder, the number of sub-blocks N is the integer part of L / 32 + 1, and the information length of the first N-2 blocks is 32, and the total information length of the remaining 2 blocks is X=L-32*(N-2); Among them, if X / 2 has no remainder, the information length of the N-1th block and the Nth block is X / 2; if X / 2 has a remainder, the information length X1 of the N-1th block is the integer part of X / 2+1, and the information length X2 of the Nth block is the integer part of X / 2.

7. A Turbo code decoder according to claim 6, characterized in that: The first component decoder and the second component decoder are both designed as three-stage pipelines. The first stage pipeline is mainly used for data preparation, the second stage pipeline is mainly used for completing the 8-state calculation of the forward path metric value recursive alpha and the backward path metric value recursive beta, and the third stage pipeline is mainly used for completing the calculation of the log-likelihood ratio.

8. The Turbo code decoder according to claim 1, characterized in that: In each iterative operation, the external information of the decoding result of the second component decoder is deinterleaved through the deinterleaving table to obtain data to participate in the decoding of the first component decoder as deinterleaved data; The deinterleaving table is generated by placing the position numbers of the interleaving table in corresponding positions according to the data in the interleaving table, and re-forming new data, namely the deinterleaving table.

9. A Turbo code decoding method of a Turbo code decoder according to any one of claims 1 to 8, characterized in that: The method comprises: After the decoding start instruction is read by the decoding control module, the data to be decoded is read from the pre-decoding storage area, the data to be decoded is multiplied by the set channel confidence value, and then the recovery puncturing is performed to obtain the recovery punctured data; and the deinterleaved data is read from the external information storage, the deinterleaved data is obtained in the following manner: the external information obtained by the second component decoder is stored in the external information storage, and the data read from the external information storage is the deinterleaved data according to the data of the deinterleaving table as the storage address; Decoding based on the deinterleaved data and the restored punctured data by a first component decoder to obtain a first decoding result; The external information of the decoding result of the first component decoder stored in the external information memory and using the data of the interleaving table as the address of the external information memory is sequentially read out by the decoding control module to obtain interleaved data, and the interleaved data and the restored punctured data are input into the second component decoder; Decoding based on the interleaved data and the restored punctured data by a second component decoder to obtain a second decoding result; The hard decision module performs iterative calculation when it is determined that the second decoding result does not meet the preset condition, and outputs the second decoding result when the second decoding result meets the preset condition.

10. A Turbo code decoding method according to claim 9, characterized in that: The method further comprises: Receiving data to be decoded through the main controller, writing the data to be decoded into a pre-decoding storage area in an idle state, and configuring decoding parameters after determining that the entire frame of data has been written; The decoding control module initializes the internal variables of the module before decoding and reads the decoding parameters, so that after reading the decoding start instruction, it can process the data to be decoded based on the decoding parameters.

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