A tri-state enable control current source circuit

Abstract

The application belongs to the field of integrated circuit design, and particularly relates to a tri-state enable control current source circuit; the method comprises the following steps: an enable circuit and a bias circuit are connected; the enable circuit comprises a diode D1, a diode D2, a diode D3, a diode D4, a diode D5, an NPN tube Q1, a PNP tube Q2, an NPN tube Q3, a resistor R1, a resistor R3 and a current source I1; the bias circuit comprises a diode D6, a diode D7, a diode D8, a diode D9, a PNP tube Q4, a PNP tube Q5, an NPN tube Q6, a resistor R2, a resistor R4 and a current source I2; the circuit is simple in structure, wider in application range, and meets the requirement of a single-chip circuit for high integration.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, specifically relating to a three-state enable control current source circuit. Background Technology

[0002] In analog integrated circuits, enable circuit structures with switching functions are usually designed to enable and disable the circuit. However, this function is usually only applicable to two control conditions: the input voltage signal is high or low.

[0003] A major drawback of this structure is that it can only perform single-switching control of the bias structure in the circuit, and cannot precisely control the other functional structures within complex analog integrated circuits. Therefore, considering this functional requirement, it is particularly important to provide a current source control structure that can handle three-state input voltage control signals (high level, low level, high impedance). Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention proposes a three-state enable control current source circuit, which includes an enable circuit and a bias circuit, wherein the enable circuit and the bias circuit are connected.

[0005] The enabling circuit includes diodes D1, D2, D3, D4, and D5, NPN transistor Q1, PNP transistor Q2, NPN transistor Q3, resistors R1 and R3, and current source I1. The enable terminal EN is connected to the cathode of diode D1 and the anode of diode D2. The anode of diode D1 is connected to resistor R1 and the anode of diode D4. The cathode of diode D2 is connected to one end of resistor R3 and the cathode of diode D3. The cathode of diode D4 is connected to... The negative terminal of diode D5 is connected to the emitter of PNP transistor Q2; the positive terminal of diode D5 is connected to the base of PNP transistor Q2; the collector of PNP transistor Q2 is connected to the collector and base of NPN transistor Q1; the base of NPN transistor Q3 is connected to the base of NPN transistor Q1, and the collector of NPN transistor Q3 serves as a lead-out terminal to form current source A; the other end of resistor R3 is connected to one end of current source I1; the other end of current source I1, the emitter of NPN transistor Q1, and the emitter of NPN transistor Q3 are all connected to a negative power supply.

[0006] Preferably, the bias circuit includes diodes D6, D7, D8, and D9, PNP transistors Q4 and Q5, NPN transistor Q6, resistors R2 and R4, and a current source I2; the collector of PNP transistor Q4 is connected to resistor R1; the emitters of both PNP transistor Q4 and PNP transistor Q5 are connected to a positive power supply; the base and collector of PNP transistor Q5 are connected to the base of PNP transistor Q4 and one end of resistor R2; the other end of resistor R2 is connected to the base of NPN transistor Q6. The cathode of diode D6 and the anode of diode D7 are connected; the collector of NPN transistor Q6 serves as the lead-out terminal to form current source B; the emitter of NPN transistor Q6 is connected to the anodes of diode D3 and D6; the cathode of diode D7 is connected to the anode of diode D8; the cathode of diode D8 is connected to the anode of diode D9; the cathode of diode D9 is connected to the anode of diode D5 and one end of resistor R4; the other end of resistor R4 is connected to one end of current source I2, and the other end of current source I2 is connected to the negative power supply.

[0007] Furthermore, the emitter area ratio of PNP tube Q4 and PNP tube Q5 is 1:3.

[0008] Furthermore, the current source I1 is set to 15μA, and the current source I2 is set to 50μA.

[0009] Furthermore, resistors R1, R2, and R3 are all 1kΩ, and resistor R4 is 10kΩ.

[0010] Furthermore, when the enable terminal is set to a high level, current source A is turned on and current source B is turned off; when the enable terminal is set to a low level, current source A is turned off and current source B is turned on; when the enable terminal is set to a high impedance state, current source A is turned on and current source B is turned on.

[0011] The beneficial effects of this invention are as follows: The three-state enable control current source circuit structure designed in this invention utilizes the unidirectional conduction characteristic of diodes to provide different bias voltages to the transistors of the two current sources, thereby achieving precise switching control of the output ports of the two current sources. Compared with traditional switching control structures, the circuit structure is simpler, has a wider range of applications, and simultaneously meets the high integration requirements of monolithic circuits. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the three-state enable control current source circuit in this invention. Detailed Implementation

[0013] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0014] This invention proposes a three-state enable control current source circuit, such as... Figure 1 As shown, the method includes the following:

[0015] The three-state enable control current source circuit includes an enable circuit (100) and a bias circuit (200), with the enable circuit and bias circuit connected together. The enable circuit includes diodes D1, D2, D3, D4, and D5, NPN transistor Q1, PNP transistor Q2, NPN transistor Q3, resistors R1 and R3, and current source I1. The enable terminal EN is connected to the cathode of diode D1 and the anode of diode D2. The anode of diode D1 is connected to resistor R1 and the anode of diode D4. The cathode of diode D2 is connected to one end of resistor R3. The cathode of diode D3 is connected to the cathode of diode D5 and the emitter of PNP transistor Q2; the anode of diode D5 is connected to the base of PNP transistor Q2; the collector of PNP transistor Q2 is connected to the collector and base of NPN transistor Q1; the base of NPN transistor Q3 is connected to the base of NPN transistor Q1, and the collector of NPN transistor Q3 serves as a lead-out terminal to form current source A; the other end of resistor R3 is connected to one end of current source I1; the other end of current source I1, the emitter of NPN transistor Q1, and the emitter of NPN transistor Q3 are all connected to a negative power supply.

[0016] The bias circuit includes diodes D6, D7, D8, and D9, PNP transistors Q4 and Q5, NPN transistor Q6, resistors R2 and R4, and a current source I2. The collector of PNP transistor Q4 is connected to resistor R1. The emitters of both PNP transistor Q4 and PNP transistor Q5 are connected to the positive power supply. The base and collector of PNP transistor Q5 are connected to the base of PNP transistor Q4 and one end of resistor R2. The other end of resistor R2 is connected to the base of NPN transistor Q6. The negative terminal of diode D6 is connected to the positive terminal of diode D7; the collector of NPN transistor Q6 serves as the lead-out terminal to form current source B; the emitter of NPN transistor Q6 is connected to the positive terminals of diodes D3 and D6; the negative terminal of diode D7 is connected to the positive terminal of diode D8; the negative terminal of diode D8 is connected to the positive terminal of diode D9; the negative terminal of diode D9 is connected to the positive terminal of diode D5 and one end of resistor R4; the other end of resistor R4 is connected to one end of current source I2, and the other end of current source I2 is connected to the negative power supply.

[0017] Preferably, the emitter area ratio of PNP transistors Q4 and Q5 is 1:3; resistors R1, R2, and R3 are all 1kΩ (the voltage drop across the resistor is small and can be ignored), resistor R4 is 10kΩ (the voltage drop across the resistor is about 0.5V); the base-emitter junction voltage drop of the diode and transistor is 0.8V±0.1V.

[0018] The working principle of this invention is as follows:

[0019] The current source inside the circuit unit of this invention is used as an active load providing a constant current. Due to the effect of the current mirror structure composed of Q1 and Q3, Q4 and Q5, a current mapping relationship is formed within the unit circuit itself. A bias reference voltage structure is formed by Q5, R2, D7, D8, and D9 through R4 and I2, which provides a reference voltage for the base of Q2 and the positive terminal of D3.

[0020] The three-state enable control current source circuit designed in this invention can control the switching of current source A and current source B through three different states of the EN input, improving its applicability. When the enable terminal is set to a high level, current source A is turned on and current source B is turned off; when the enable terminal is set to a low level, current source A is turned off and current source B is turned on; when the enable terminal is set to a high impedance state, current source A is turned on and current source B is turned on. The specific truth table is shown below:

[0021] Table 1 Truth Table for Current Source Status Judgment

[0022]

[0023] The specific operating states of the circuit when the EN terminal is a tri-state input are as follows:

[0024] 1) When EN is high, D1 is off, D2 is on, D3 is off, and D4 is on. The current of I1 is injected through the EN terminal and supplied through D2 and R3. Q4, R1, and D4 supply current to Q2, thereby turning on Q1 and Q3, which in turn turns on current source A. The current of I2 is supplied by Q5, R2, D7, D8, and D9 through R4. Since D3 and D6 are both off, Q6 is off, and current source B is turned off.

[0025] 2) When EN is low, D1 is on, D2 is off, D3 is on, and D4 is off. The current of I1 is provided through R3, D3, and Q6. At this time, current source B is on. At the same time, since D4, D5, and Q2 are all off, Q1 and Q3 are off, and current source A is off. At this time, D6 is off, and the current of I2 is still provided by Q5, R2, D7, D8, and D9 through R4.

[0026] 3) When EN is high impedance, D1 and D2 are both cut off, and the current of I1 is provided through R3, D3 and Q6. At this time, current source B is turned on. At this time, D6 is cut off, and the current of I2 is still provided by Q5, R2, D7, D8 and D9 through R4. Q4 and R1 provide current to Q2 through D4, thereby turning on Q1 and Q3, and then turning on current source A.

[0027] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A three-state enable control current source circuit, characterized in that, include: Enable circuit and bias circuit, with the enable circuit connected to the bias circuit; The enabling circuit includes diodes D1, D2, D3, D4, and D5, NPN transistor Q1, PNP transistor Q2, NPN transistor Q3, resistors R1 and R3, and a current source I1. The enable terminal EN is connected to the cathode of diode D1 and the anode of diode D2. The anode of diode D1 is connected to one end of resistor R1 and the anode of diode D4. The cathode of diode D2 is connected to one end of resistor R3 and the cathode of diode D3. The cathode of diode D4 is connected to... The cathode of diode D5 is connected to the emitter of PNP transistor Q2; the anode of diode D5 is connected to the base of PNP transistor Q2; the collector of PNP transistor Q2 is connected to the collector and base of NPN transistor Q1; the base of NPN transistor Q3 is connected to the base of NPN transistor Q1, and the collector of NPN transistor Q3 serves as a lead-out terminal to form current source A; the other end of resistor R3 is connected to one end of current source I1; the other end of current source I1, the emitter of NPN transistor Q1, and the emitter of NPN transistor Q3 are all connected to a negative power supply. The bias circuit includes diodes D6, D7, D8, and D9, PNP transistors Q4 and Q5, NPN transistor Q6, resistors R2 and R4, and a current source I2. The collector of PNP transistor Q4 is connected to the other end of resistor R1. The emitters of both PNP transistor Q4 and PNP transistor Q5 are connected to a positive power supply. The base and collector of PNP transistor Q5 are connected to the base of PNP transistor Q4 and one end of resistor R2. The other end of resistor R2 is connected to the base of NPN transistor Q6. The collector of NPN transistor Q6 is connected to the cathode of diode D6 and the anode of diode D7; the collector of NPN transistor Q6 is used as a lead to form current source B; the emitter of NPN transistor Q6 is connected to the anode of diode D3 and the anode of diode D6; the cathode of diode D7 is connected to the anode of diode D8; the cathode of diode D8 is connected to the anode of diode D9; the cathode of diode D9 is connected to the anode of diode D5 and one end of resistor R4; the other end of resistor R4 is connected to one end of current source I2, and the other end of current source I2 is connected to the negative power supply.

2. The three-state enable control current source circuit according to claim 1, characterized in that, The emitter area ratio of the PNP tube Q4 and the PNP tube Q5 is 1:

3.

3. The three-state enable control current source circuit according to claim 1, characterized in that, The current source I1 is set to 15μA, and the current source I2 is set to 50μA.

4. A three-state enable control current source circuit according to claim 1, characterized in that, The resistors R1, R2, and R3 are all 1kΩ, and the resistor R4 is 10kΩ.

5. A three-state enable control current source circuit according to claim 1, characterized in that, When the enable terminal is set to a high level, current source A is turned on and current source B is turned off; when the enable terminal is set to a low level, current source A is turned off and current source B is turned on; when the enable terminal is set to a high impedance state, current source A is turned on and current source B is turned on.

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