File information acquisition method, machine training method, system, and storage medium

Abstract

The present application relates to chip design technical field, especially to a kind of file information acquisition method, machine training method, system and storage medium, file information acquisition method includes the following steps: input target file, obtain the netlist file of the target file and design exchange file, create submodule and standard unit based on the netlist file, and obtain corresponding information;Netlist file is hierarchically divided based on standard unit information;Select any level as target level, obtain the quantity information of submodule and standard unit in target level;The total size of standard unit inside submodule is obtained based on the information of standard unit recorded in submodule in target level, and the size of submodule is obtained based on the information of submodule and standard unit in preset acquisition mode;The quantity and size of submodule and standard unit in target level are taken as demand information and output. The level of target file is finely divided, and the fine degree of level information of input file is converted according to demand.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of event chip design, and in particular relates to a file information acquisition method, a machine training method, a system and a storage medium. BACKGROUND

[0002] Chips play an increasingly important role in our lives, and the design and manufacture of high-performance chips cannot be separated from the support of efficient and high-quality chip design automation (EDA) tools. Due to the complexity of chip systems, traditional EDA tools standardize the chip design process into steps such as logic synthesis, floor planning, clock tree synthesis (CTS), placement & routing, etc. The establishment of the standard process simplifies the chip design problem; at the same time, it also leads to a weak correlation between the optimization goals of the pre-stage and the final chip indicators, so a single process often cannot achieve the power performance goal (PPA) of the chip. In order to design and manufacture a chip that meets the requirements, multiple iterations and adjustments are needed, which greatly delays the chip development cycle.

[0003] In order to shorten the chip development cycle and design a better performing chip, more and more researchers are trying to introduce machine learning methods into existing EDA tools. Since machine learning methods are data-driven methods, in order to introduce machine learning methods into EDA tools, a database based on EDA tools and chip design schemes needs to be established first to provide learning and training data sets, which often needs to be completed manually by experienced designers, and only the top-level macro unit and module information can be obtained during data format conversion, and the sub module information of the top-level module cannot be obtained. SUMMARY

[0004] In order to be able to customize the conversion of more detailed hierarchical information in the input file according to the requirements, the present application provides a file information acquisition method, a machine training method, a system and a storage medium.

[0005] The technical problem solving scheme of the present application is to provide a file information acquisition method, which includes the following steps: inputting a target file, obtaining a netlist file and a design exchange file of the target file, creating sub modules and standard cells based on the netlist file, and obtaining corresponding information; performing hierarchical division on the netlist file based on the standard cell information; selecting an arbitrary level as a target level, and obtaining the quantity information of the sub modules and standard cells in the target level; obtaining the total size of the standard cells inside the sub modules based on the information of the standard cells recorded by the sub modules in the target level, and obtaining the size of the sub modules based on the information of the sub modules and standard cells in a preset acquisition manner; and outputting the quantity and size of the sub modules and standard cells in the target level as requirement information.

[0006] Preferably, the hierarchical division of the netlist file based on the standard cell information specifically comprises the following steps: hierarchical division of the netlist file based on the standard cell information according to a corresponding number of levels; and adjustment of the number of sub-modules in each level based on the divided levels.

[0007] Preferably, the file information acquisition method further comprises the steps of creating a macro cell based on the netlist file and arranging the macro cell and the standard cell, specifically comprising the following steps: obtaining a standard cell library exchange file of a target file; creating a standard cell pin based on the netlist file; reading the standard cell library exchange file to obtain the size of the macro cell and the standard cell; obtaining the offset value of the macro cell and the standard cell relative to the standard cell pin; and arranging the macro cell and the standard cell based on the size of the macro cell and the standard cell, and the offset value of the macro cell and the standard cell relative to the standard cell pin.

[0008] Preferably, after the hierarchical division of the netlist file based on the standard cell information, the method further comprises the following steps: obtaining a design exchange file of the target file; creating an input and output pin based on the netlist file; and determining the position of the input and output pin based on the design exchange file.

[0009] Preferably, the levels of the netlist file comprise a top layer and at least one fine layer contained in the top layer in sequence, and the input and output pin is arranged in the top layer.

[0010] Preferably, each level comprises at least one sub-module or macro cell or standard cell.

[0011] The present application also provides a machine training method for file information to solve the above technical problems, specifically comprising the following steps: obtaining output requirement information, offset value information of the standard cell or the macro cell relative to the standard cell pin, and position information of the input and output pin; converting the obtained requirement information, offset value information and position information into a requirement format based on a preset arrangement tool, and inputting a preset model training file for machine learning.

[0012] Preferably, the preset arrangement tool is a chip automatic tool, and the chip automatic tool is based on a single arrangement of the macro cell or a mixed arrangement of the macro cell and the standard cell.

[0013] The application further provides a file information acquisition system for implementing the file information acquisition method, comprising an information acquisition module, a data generation module and a data processing module.

[0014] The application further provides a storage medium comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the file information acquisition method when executing the computer program.

[0015] Compared with the prior art, the file information acquisition method, the machine training method, the system and the storage medium have the following advantages.

[0016] 1. The file information acquisition method comprises the following steps: inputting a target file, acquiring a netlist file and a design exchange file of the target file, creating sub-modules and standard cells based on the netlist file and acquiring corresponding information, performing hierarchical division on the netlist file based on the standard cell information, selecting an arbitrary level as a target level, acquiring quantity information of sub-modules and standard cells in the target level, acquiring total size of standard cells inside the sub-modules based on information of the standard cells recorded in the sub-modules in the target level, acquiring size of the sub-modules in a preset acquisition mode based on the information of the sub-modules and the standard cells, and outputting quantity and size of the sub-modules and the standard cells in the target level as requirement information.

[0017] 2. The file information acquisition method comprises the following steps in the hierarchical division based on the standard cell information: performing corresponding quantity hierarchical division on the netlist file based on the standard cell information, and adjusting quantity of the sub-modules in each level based on the divided levels.

[0018] 3. The document information acquisition method of the present invention further includes the steps of creating macro cells based on the netlist file and laying out macro cells and standard cells. The specific steps are as follows: acquiring the standard cell library exchange file of the target file; creating standard cell pins based on the netlist file; reading the standard cell library exchange file to acquire the dimensions of macro cells and standard cells; acquiring the offset values ​​of standard cells and macro cells relative to the standard cell pins; and laying out macro cells and standard cells based on the dimensions of macro cells and standard cells, and the offset values ​​of standard cells and macro cells relative to the standard cell pins. Acquiring the dimensions of macro cells and standard cells and the offset values ​​of the two types of cells relative to the standard cells themselves before dividing the hierarchy, and laying out macro cells and / or standard cells based on the offset values, can effectively reduce the burden on designers and reduce design time.

[0019] 4. The document information acquisition method of the present invention, after hierarchically dividing the netlist file based on standard cell information, further includes the following steps: acquiring the design exchange file of the target file; creating input / output pins based on the netlist file; and determining the positions of the input / output pins based on the design exchange file. The positional relationship between the input / output pins and submodules or standard cells affects the processing speed of the file in the netlist file. Determining the positions of the input / output pins in this way and appropriately adjusting the positions of the standard cells or submodules can effectively reduce design time.

[0020] 5. This invention also provides a machine learning training method for file information, specifically including the following steps: acquiring output requirement information, offset information of standard cells or macro cells relative to standard cell pins, and position information of input and output pins; converting the acquired requirement information, offset information, and position information into a requirement format based on a preset layout tool, and inputting it into a preset model training file for machine learning. The machine learning data acquired in this way is no longer merely extracted from existing high-quality chip design results, but is universally extracted from every chip design result, making the design data more conventional and accessible. This allows for rapid prediction of later-stage and even final optimization goals in the early stages of the design phase, effectively shortening the number of iterations, improving the design cycle, and further reducing design time.

[0021] 6. The document information acquisition method of the present invention uses a preset layout tool as a chip automation tool. The chip automation tool is based on separate layout of macrocells or on a mixed layout of macrocells and standard cells. Not all layouts require the use of macrocells, therefore, using this chip automation tool for layout can be applied to more documents, thereby improving versatility.

[0022] 7. This invention also provides a file information acquisition system for implementing the file information acquisition method described above, comprising an information acquisition module for acquiring the netlist file and design exchange file of the target file, acquiring the corresponding information of sub-modules and standard units based on the netlist file, acquiring the quantity information of sub-modules and standard units in the target level, acquiring the total size of standard units inside the sub-module based on the information of standard units recorded in the sub-module in the target level, and acquiring the size of the sub-module based on the information of the sub-module and standard units using a preset acquisition method; a data generation module for acquiring sub-modules and standard units based on the netlist file; and a data processing module for hierarchically dividing the netlist file based on the standard unit information and outputting the quantity and size of sub-modules and standard units in the target level as requirement information. The file information acquisition system has the same beneficial effects as the file information acquisition method described above, and will not be elaborated further here.

[0023] 8. The present invention also provides a storage medium, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, it implements the file information acquisition method described above. The storage medium has the same beneficial effects as the file information acquisition method described above, and will not be elaborated further here. [Attached Image Description]

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a flowchart of the steps of a file information acquisition method provided in the first embodiment of the present invention.

[0026] Figure 2 This is the step flow of step S2 in the file information acquisition method provided in the first embodiment of the present invention. Figure 1 .

[0027] Figure 3 This is a flowchart of step S4 in a file information acquisition method provided in the first embodiment of the present invention.

[0028] Figure 4 This is the step flow of step S2 in the file information acquisition method provided in the first embodiment of the present invention. Figure 2 .

[0029] Figure 5 This is a schematic diagram of the top-level design of the chip design file in a file information acquisition method provided in the first embodiment of the present invention.

[0030] Figure 6 This is a schematic diagram of the fine-layer design of the chip design file in a file information acquisition method provided in the first embodiment of the present invention.

[0031] Figure 7 This is a schematic diagram of the number of sub-modules and standard units in the hierarchical relationship of a file information acquisition method provided in the first embodiment of the present invention.

[0032] Figure 8 This is a flowchart of the steps of a machine training method for document information provided in the second embodiment of the present invention.

[0033] Figure 9 This is a schematic diagram of a file information acquisition system provided in the third embodiment of the present invention.

[0034] Figure 10 This is a schematic diagram of a storage medium provided in the fourth embodiment of the present invention.

[0035] Explanation of reference numerals in the attached diagram:

[0036] 1. File information retrieval system; 2. Storage medium;

[0037] 11. Information acquisition module; 12. Data generation module; 13. Data processing module; 21. Memory; 22. Processor; 23. Computer program.

Detailed Implementation Methods

[0038] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0039] Please see Figure 1 The first embodiment of the present invention provides a method for obtaining file information, including the following steps:

[0040] S1: Input the target file, obtain the netlist file and design exchange file of the target file, create sub-modules and standard units based on the netlist file, and obtain the corresponding information;

[0041] S2: Divide the netlist file into hierarchical levels based on standard cell information;

[0042] S3: Select any level as the target level and obtain the number of sub-modules and standard units in the target level;

[0043] S4: Obtain the total size of the standard units inside the submodule based on the information of the standard units recorded in the submodule in the target level, and obtain the size of the submodule based on the information of the submodule and the standard units using a preset acquisition method;

[0044] S5: Output the number and size of sub-modules and standard units in the target level as requirement information.

[0045] It should be noted that the information obtained by this method of acquiring file information can be used as a training dataset for machine learning. To introduce machine learning methods into electronic design automation (EDA) tools, a database based on EDA tools and chip design schemes must first be established. Chip design files are often diverse, including Verilog files (netlist files), DEF files (design exchange files), LEF files (standard cell library exchange files), etc., and their content is often redundant. For example, in addition to defining the dimensions of macrocells, LEF files may also contain hierarchical information on PINs (standard cell pins) and OBS (overlay switch technology). However, the input files for placement tools often only require partial information from some parts of the chip design files.

[0046] Specifically, a netlist file's hierarchy includes a top-level layer and at least one fine-grained layer contained within it. Existing format conversion methods only provide top-level submodule information, which cannot meet users' needs for information at other levels or the requirements of different macro-unit and standard-unit layout tools. Therefore, a conversion method is needed that can adjust the fine-grained level of the input file's hierarchy information, taking into account the requirements of tools or users for submodule hierarchy information. This method could be used in machine learning-assisted layout tools.

[0047] Understandably, this method allows for the precise division of target files into hierarchical levels, and the user can customize the level of detail and corresponding information of the input file's hierarchical information according to their needs.

[0048] For further details, please refer to Figure 2 The hierarchical division of netlist files based on standard cell information includes the following steps:

[0049] S21: Divide the netlist file into corresponding hierarchical levels based on standard cell information;

[0050] S22: Adjust the number of sub-modules in each level based on the partitioned hierarchy.

[0051] It should be noted that the number of submodules is adjusted and assigned according to the level. Specifically, the number of submodules contained in each level during file format conversion is determined by the file's own information. If the information itself is not set accordingly, the connection relationship between standard units is used to determine and divide the submodules.

[0052] Understandably, the hierarchical information of the design file in the target file is often defined in the netlist file. Through submodule and macro unit information, the netlist file defines the hierarchical tree structure of the design file, and the hierarchical information can be directly obtained from the netlist file.

[0053] For further details, please refer to Figure 3 , Figure 5 and Figure 6 The method for obtaining file information also includes steps for creating macro cells based on netlist files and laying out macro cells and standard cells. The specific steps are as follows:

[0054] S41: Obtain the standard unit library exchange file for the target file;

[0055] S42: Creates standard cell pins based on netlist files;

[0056] S43: Read the standard cell library exchange file to obtain the dimensions of macro cells and standard cells;

[0057] S44: Get the offset values ​​of the standard cell and macro cell relative to the standard cell pin;

[0058] S45: Layout the macrocells and standard cells based on their dimensions and the offset values ​​of the standard cells and macrocells relative to the standard cell pins.

[0059] It's important to note that not all files contain macrocells. When macrocells and standard cells are needed for joint placement, macrocells can be created for placement and subsequent steps. The hierarchical information of the design file is often defined in the netlist file. By defining the submodules and standard cell information contained in this hierarchy, the Verilog file defines the hierarchical tree structure of the design file. For flattened netlist files, a netlist file with hierarchical information can also be artificially generated using netlist partitioning techniques. The Verilog file defines the connections and containment relationships of each cell, while the LEF file defines the physical properties of each cell, including the cell size, the dimensions of the pins inside the cell, and their relative positions to other cells. At the placement completion stage, the positions of each cell are fixed; that is, the position information of macrocells or standard cells does not change during subsequent file information conversion. The information of macrocells or standard cells is stored in the DEF file. Therefore, for macrocell placement, the Verilog, LEF, and DEF files completely define the required chip design information. The method for obtaining information from this file can be customized to the level of detail of the input file's hierarchical information according to user needs. It can be used in machine learning-assisted macrocell placement tools or hybrid placement tools for macrocells and standard cells.

[0060] Understandably, obtaining the dimensions of macro cells and standard cells, as well as the offset values ​​of the two types of cells relative to the standard cell itself, before dividing the hierarchy, and then laying out the macro cells and / or standard cells based on the offset values, can effectively reduce the workload of designers and reduce design time.

[0061] For further details, please refer to Figure 4 and Figure 7 After hierarchically dividing the netlist file based on standard cell information, the following steps are also included:

[0062] S23: Obtain the design exchange file for the target file;

[0063] S24: Create input / output pins based on the netlist file;

[0064] S25: Determine the location of input / output pins based on the design exchange document.

[0065] Understandably, the positional relationship between input / output pins and submodules or standard cells affects the processing speed of the netlist file. Determining the position of input / output pins in this way and appropriately adjusting the position of standard cells or submodules can effectively reduce design time.

[0066] Furthermore, each level includes at least one submodule, macrounit, or standard unit.

[0067] It should be noted that there is an inclusion relationship between levels. When a submodule in the upper level is opened, it will not be displayed in the lower level. Only the information in the submodule will be displayed. Therefore, submodules, macro units and standard units may coexist in the same level. However, the level cannot be empty. Therefore, it must contain at least one of the three: submodules, macro units or standard units.

[0068] Specifically, an embodiment is provided to explain the invention. It should be noted that the exemplary embodiments described herein are for illustrative purposes only and do not limit the scope of the invention.

[0069] This embodiment uses a small design at the 28nm node.

[0070] Step 1: Read the Verilog file and obtain the number of input / output pins (Port), macro cells (Macro), and standard cells (Instance): 137, 8, and 109237, respectively;

[0071] Step 2: Read in the Standard Cell Library Exchange (LEF) file to determine the size of the Macro and Instance, as well as the position of the standard cell pins relative to the Instance;

[0072] Step 3: Under different hierarchical settings, the number and size of sub-modules and the number of instances are obtained, as shown in Table 1. It can be seen that by adjusting the hierarchical settings, the level of detail of modules and instances in this design can be obtained at different levels. At the top level, only two modules are visible except for the macro; while at the 8th level, all modules are expanded, and only all instances are visible.

[0073] Finally, based on the results shown in the figure, obtain specific information for a certain level and then perform the following operations:

[0074] Step 4: Read in the Design Exchange File (DEF) and determine the location of the Port;

[0075] Step 5: Write the model training file based on the location of the Port and specific information of a certain level.

[0076] Please see Figure 8 The second embodiment of the present invention provides a machine training method for document information, which specifically includes the following steps:

[0077] S1: Input the target file, obtain the netlist file and design exchange file of the target file, create sub-modules and standard units based on the netlist file, and obtain the corresponding information;

[0078] S2: Divide the netlist file into hierarchical levels based on standard cell information;

[0079] S3: Select any level as the target level and obtain the number of sub-modules and standard units in the target level;

[0080] S4: Obtain the total size of the standard units inside the submodule based on the information of the standard units recorded in the submodule in the target level, and obtain the size of the submodule based on the information of the submodule and the standard units using a preset acquisition method;

[0081] S5: Output the number and size of sub-modules and standard units in the target level as requirement information;

[0082] S6: Obtain the output requirement information, the offset value information of the standard cell relative to the standard cell pin, and the position information of the input and output pins;

[0083] S7: Based on the preset layout tool, the acquired requirement information, offset information and position information are converted into requirement format and input into the preset model training file for machine learning.

[0084] It should be noted that not all files have macro cells. In files that do have macro cells, it is necessary to obtain the offset information of the macro cell relative to the standard cell pin.

[0085] The machine learning data obtained in this way is no longer extracted from existing high-quality chip design results, but is universally extracted from every chip design result, making the design data more conventional and accessible. It can quickly predict the optimization goals in the later stages of the design phase and even the final stage in the early stages of the design phase, effectively shortening the number of iterations, improving the design cycle, and further reducing the design time.

[0086] Furthermore, the preset placement tool is a chip automation tool, which is based on the placement of macrocells alone or on the placement of a mixture of macrocells and standard cells.

[0087] It should be noted that not all layouts require the use of macro cells. Therefore, using this chip automation tool for layout can be applied to more files, thereby improving versatility.

[0088] Please see Figure 9 The third embodiment of the present invention provides a file information acquisition system 1 for implementing the file information acquisition method described above. It includes an information acquisition module 11: for acquiring the netlist file and design exchange file of the target file; acquiring the corresponding information of sub-modules and standard units based on the netlist file; acquiring the quantity information of sub-modules and standard units in the target level; acquiring the total size of standard units within the sub-module based on the information of standard units recorded in the sub-module in the target level; and acquiring the size of the sub-module based on the information of the sub-module and standard units using a preset acquisition method. A data generation module 12: for acquiring sub-modules and standard units based on the netlist file. A data processing module 13: for hierarchically dividing the netlist file based on the standard unit information; and outputting the quantity and size of sub-modules and standard units in the target level as requirement information. The file information acquisition system 1 has the same beneficial effects as the above-described file information acquisition method, and will not be elaborated upon here.

[0089] Please see Figure 10 The fourth embodiment of the present invention provides a storage medium 2, including a memory 21, a processor 22, and a computer program 23 stored on the memory 21 and executable on the processor 22. When the processor 22 executes the computer program 23, it implements the file information acquisition method described above. The storage medium 2 has the same beneficial effects as the file information acquisition method described above, and will not be elaborated further here.

[0090] It is understood that, according to the embodiments disclosed in this invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication component, and / or installed from a removable medium. When the computer program is executed by a central processing unit (CPU), it performs the functions defined in the methods of this application. It should be noted that the computer-readable medium described in this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. Computer-readable storage media include, but are not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on a computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0091] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0092] In the embodiments provided by this invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information.

[0093] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Those skilled in the art should also recognize that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily essential to the invention.

[0094] In various embodiments of the present invention, it should be understood that the sequence number of each process does not necessarily imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0095] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It is particularly important to note that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0096] Compared with the prior art, the document information acquisition method, machine training method, system, and storage medium of the present invention have the following advantages:

[0097] 1. The document information acquisition method of the present invention includes the following steps: inputting a target file, acquiring the netlist file and design exchange file of the target file, creating sub-modules and standard units based on the netlist file, and acquiring corresponding information; hierarchically dividing the netlist file based on the standard unit information; selecting any level as the target level, and acquiring the quantity information of sub-modules and standard units in the target level; acquiring the total size of the standard units inside the sub-module based on the information of the standard units recorded in the sub-module in the target level, and acquiring the size of the sub-module based on the information of the sub-module and standard units using a preset acquisition method; and outputting the quantity and size of sub-modules and standard units in the target level as requirement information. Through this method, the target file can be finely divided into levels, and the fineness of the hierarchical information of the input file can be customized according to user needs.

[0098] 2. The document information acquisition method of the present invention, which divides the netlist file into levels based on standard unit information, specifically includes the following steps: dividing the netlist file into corresponding levels based on standard unit information; adjusting the number of sub-modules in each level based on the divided levels. The hierarchical information of the design file in the target file is often defined in the netlist file. Through sub-modules and macro-unit information, the netlist file defines the hierarchical tree structure of the design file, and the hierarchical information can be directly obtained from the netlist file intuitively.

[0099] 3. The document information acquisition method of the present invention further includes the steps of creating macro cells based on the netlist file and laying out macro cells and standard cells. The specific steps are as follows: acquiring the standard cell library exchange file of the target file; creating standard cell pins based on the netlist file; reading the standard cell library exchange file to acquire the dimensions of macro cells and standard cells; acquiring the offset values ​​of standard cells and macro cells relative to the standard cell pins; and laying out macro cells and standard cells based on the dimensions of macro cells and standard cells, and the offset values ​​of standard cells and macro cells relative to the standard cell pins. Acquiring the dimensions of macro cells and standard cells and the offset values ​​of the two types of cells relative to the standard cells themselves before dividing the hierarchy, and laying out macro cells and / or standard cells based on the offset values, can effectively reduce the burden on designers and reduce design time.

[0100] 4. The document information acquisition method of the present invention, after hierarchically dividing the netlist file based on standard cell information, further includes the following steps: acquiring the design exchange file of the target file; creating input / output pins based on the netlist file; and determining the positions of the input / output pins based on the design exchange file. The positional relationship between the input / output pins and submodules or standard cells affects the processing speed of the file in the netlist file. Determining the positions of the input / output pins in this way and appropriately adjusting the positions of the standard cells or submodules can effectively reduce design time.

[0101] 5. This invention also provides a machine learning training method for file information, specifically including the following steps: acquiring output requirement information, offset information of standard cells or macro cells relative to standard cell pins, and position information of input and output pins; converting the acquired requirement information, offset information, and position information into a requirement format based on a preset layout tool, and inputting it into a preset model training file for machine learning. The machine learning data acquired in this way is no longer merely extracted from existing high-quality chip design results, but is universally extracted from every chip design result, making the design data more conventional and accessible. This allows for rapid prediction of later-stage and even final optimization goals in the early stages of the design phase, effectively shortening the number of iterations, improving the design cycle, and further reducing design time.

[0102] 6. The document information acquisition method of the present invention uses a preset layout tool as a chip automation tool. The chip automation tool is based on separate layout of macrocells or on a mixed layout of macrocells and standard cells. Not all layouts require the use of macrocells, therefore, using this chip automation tool for layout can be applied to more documents, thereby improving versatility.

[0103] 7. This invention also provides a file information acquisition system for implementing the file information acquisition method described above, comprising an information acquisition module for acquiring the netlist file and design exchange file of the target file, acquiring the corresponding information of sub-modules and standard units based on the netlist file, acquiring the quantity information of sub-modules and standard units in the target level, acquiring the total size of standard units inside the sub-module based on the information of standard units recorded in the sub-module in the target level, and acquiring the size of the sub-module based on the information of the sub-module and standard units using a preset acquisition method; a data generation module for acquiring sub-modules and standard units based on the netlist file; and a data processing module for hierarchically dividing the netlist file based on the standard unit information and outputting the quantity and size of sub-modules and standard units in the target level as requirement information. The file information acquisition system has the same beneficial effects as the file information acquisition method described above, and will not be elaborated further here.

[0104] 8. The present invention also provides a storage medium, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, it implements the file information acquisition method described above. The storage medium has the same beneficial effects as the file information acquisition method described above, and will not be elaborated further here.

[0105] The foregoing has provided a detailed description of a file information acquisition method, machine training method, system, and storage medium disclosed in the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention. Any modifications, equivalent substitutions, and improvements made within the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for obtaining file information, characterized in that: Includes the following steps: Input the target file, obtain the netlist file, design exchange file and standard cell library exchange file of the target file, obtain the sub-modules, macro cells and standard cells based on the netlist file, and obtain the corresponding information of the sub-modules, macro cells and standard cells; Read the standard cell library exchange file to obtain the dimensions of macro cells and standard cells; The netlist file is hierarchically divided based on standard cell information; Select any level as the target level and obtain the number of sub-modules and standard units in the target level; The total size of the standard units inside the submodule is obtained based on the information of the standard units recorded in the submodule at the target level. The size of the submodule is obtained based on the information of the submodule and the standard units using a preset acquisition method. The number and size of sub-modules and standard units in the target level are output as the requirements information for machine training.

2. The file information acquisition method as described in claim 1, characterized in that: The hierarchical partitioning of netlist files based on standard cell information includes the following steps: The netlist files are divided into corresponding hierarchical levels based on standard unit information; Adjust the number of sub-modules in each level based on the hierarchical division.

3. The file information acquisition method as described in claim 2, characterized in that: The method for obtaining file information also includes the layout steps for macro cells and standard cells, the specific steps of which are as follows: Create standard cell pins based on the netlist file; Obtain the offset values ​​of the standard cell and macro cell relative to the standard cell pin; Based on the dimensions of macrocells and standard cells, the macrocells and standard cells are laid out according to the offset values ​​of the standard cell pins relative to the standard cell pins.

4. The file information acquisition method as described in claim 3, characterized in that: After hierarchically dividing the netlist file based on standard cell information, the following steps are also included: Obtain the design exchange file of the target file; Create input / output pins based on the netlist file; The location of the input / output pins is determined based on the design exchange document.

5. The file information acquisition method as described in claim 4, characterized in that: The netlist file has a hierarchy including a top layer and at least one fine layer contained within the top layer, and the input / output pins are located in the top layer.

6. The file information acquisition method as described in claim 3, characterized in that: Each level includes at least one submodule, macrounit, or standard unit.

7. A machine training method for document information, wherein the machine is trained using the requirement information obtained by the document information acquisition method as described in any one of claims 1-6, characterized in that: Specifically, the steps include the following: Obtain the required output information, the offset value of the standard cell relative to the pin of the standard cell, and the position information of the input and output pins; Based on the preset layout tool, the acquired requirement information, as well as offset and position information, are converted into the requirement format and input into the preset model training file for machine learning.

8. The machine training method for document information as described in claim 7, characterized in that: The preset layout tool is a chip automation tool, which is based on the layout of macrocells alone or on the layout of a mixture of macrocells and standard cells.

9. A file information acquisition system, used to implement the file information acquisition method as described in any one of claims 1-6, characterized in that: It includes an information acquisition module: used to acquire the netlist file of the target file, the design exchange file and the standard cell library exchange file, acquire the corresponding information of sub-modules, macro cells and standard cells based on the netlist file, acquire the quantity information of sub-modules and standard cells in the target level, acquire the size of macro cells and standard cells based on the standard cell library exchange file, acquire the total size of standard cells inside the sub-module based on the information of standard cells recorded in the sub-module in the target level, and acquire the size of the sub-module based on the information of the sub-module and standard cells in a preset acquisition method; Data generation module: This module retrieves sub-modules and standard units based on netlist files. Data processing module: Based on standard unit information, the netlist file is hierarchically divided, and the number and size of sub-modules and standard units in the target level are output as the requirement information for machine training.

10. A storage medium comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, it implements the file information acquisition method as described in any one of claims 1-6.

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