Image sensor, method of reducing equivalent capacitance, and storage medium

Abstract

This application provides an image sensor, a method for reducing equivalent capacitance, and a storage medium. The image sensor includes a pixel array, pixel output bit lines, and an analog-to-digital converter (ADC). The pixel array is connected to the ADC through the pixel output bit lines. The ADC includes a source follower transistor. The image sensor, method for reducing equivalent capacitance, and storage medium provided in this application, by adding a source follower transistor to the ADC and connecting it to the source follower signal lines on both sides of the pixel output bit lines, not only protect the pixel output bit lines and reduce equivalent parasitic capacitance, but also accelerate signal storage speed.

Description

Technical Field

[0001] This application relates to the field of image sensor technology, specifically to an image sensor, a method for reducing the equivalent capacitance of pixel output bit lines, and a storage medium. Background Technology

[0002] In image sensors (CIS), the pixel bitline traces output from the pixel array need to be protected from the pixel array to the analog-to-digital converter (COLADC). This is typically achieved by grounding the output bitline traces; however, grounding introduces significant parasitic capacitance, which can affect the storage speed of the pixel signals output from the pixel array.

[0003] In conceiving and implementing this application, the inventors discovered at least the following problems: how to ensure the pixel signal storage speed under grounding protection conditions, and how to reduce the equivalent parasitic capacitance and its impact on pixel output.

[0004] The preceding description is intended to provide general background information and does not necessarily constitute prior art. Summary of the Invention

[0005] This application provides an image sensor, a method for reducing the equivalent capacitance of pixel output bit lines, and a storage medium to alleviate the problem that excessive equivalent parasitic capacitance affects the pixel signal storage speed.

[0006] In one aspect, this application provides an image sensor, which optionally includes a pixel array, a pixel output bit line, and an analog-to-digital conversion module;

[0007] The pixel array is connected to the analog-to-digital converter module via the pixel output bit lines;

[0008] The analog-to-digital conversion module includes a source follower transistor, wherein:

[0009] The gate of the source follower transistor is connected to the pixel output bit line, the drain of the source follower transistor is connected to a preset voltage, and the source of the source follower transistor is connected to a current source.

[0010] The source of the source follower transistor is also connected to a source follower signal line, and the source follower signal line includes a first source follower signal sub-line and a second source follower signal sub-line respectively in a direction away from the source of the source follower transistor. The first source follower signal sub-line and the second source follower signal sub-line are both arranged parallel to the pixel output bit line, and the first source follower signal sub-line and the second source follower signal sub-line are respectively located on both sides of the pixel output bit line.

[0011] Optionally, the first source follower signal sub-line and the pixel output bit line in the image sensor have a first parasitic capacitance, and the second source follower signal sub-line and the pixel output bit line have a second parasitic capacitance, wherein the capacitance value of the first parasitic capacitance and the capacitance value of the second parasitic capacitance are equal.

[0012] Optionally, in the image sensor, if the gain of the source follower transistor is A and the parasitic capacitance between the first source follower signal sub-line and the second source follower signal sub-line is C, then the capacitance value of the first parasitic capacitance and the capacitance value of the second parasitic capacitance are both (1-A)*C.

[0013] Optionally, the gain of the source follower transistor in the image sensor is between 0 and 1.

[0014] Optionally, the distance between the first source follower signal sub-line and the pixel output bit line in the image sensor is equal to the distance between the second source follower signal sub-line and the pixel output bit line.

[0015] Optionally, the current source in the image sensor is connected between the source follower transistor and the ground signal to provide a constant current to the source follower transistor.

[0016] Optionally, the pixel array in the image sensor includes a source follower, the source of which is connected to the pixel output bit line.

[0017] On the other hand, this application provides a method for reducing the equivalent capacitance of pixel output bit lines in an image sensor, applied to the image sensor described above, optionally including:

[0018] The pixel array outputs pixel voltage signals;

[0019] The analog-to-digital converter module obtains the pixel voltage signal through the pixel output bit line;

[0020] A source follower voltage signal is generated by a source follower transistor disposed in the analog-to-digital conversion module following the pixel voltage signal.

[0021] The source follower voltage signal generated by the source follower transistor is received by setting the first source follower signal sub-line and the second source follower signal sub-line.

[0022] Optionally, in the method for reducing the equivalent capacitance of the pixel output bit line in the image sensor, if the gain of the source follower transistor is A and the parasitic capacitance between the first source follower signal sub-line and the second source follower signal sub-line is C, then the capacitance value of the first parasitic capacitance and the capacitance value of the second parasitic capacitance are both (1-A)*C.

[0023] On the other hand, this application provides a storage medium, optionally storing a computer program that, when executed by a processor, implements the steps of the method for reducing the equivalent capacitance of the pixel output bit line as described above.

[0024] As described above, the image sensor, the method for reducing the equivalent capacitance of the pixel output bit line, and the storage medium provided in this application, by adding a source follower transistor to the analog-to-digital conversion module and connecting it to the source follower signal lines on both sides of the pixel output bit line, can not only protect the pixel output bit line and reduce the equivalent parasitic capacitance, but also speed up the signal storage speed. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0026] Figure 1 This is a structural diagram of an image sensor according to an embodiment of this application.

[0027] Figure 2 This is a flowchart of a method for reducing the equivalent capacitance of pixel output bit lines in an image sensor according to an embodiment of this application.

[0028] The realization of the objectives, functional features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0029] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0030] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0031] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0032] First Embodiment

[0033] This application provides an image sensor, Figure 1 This is a structural diagram of an image sensor according to an embodiment of this application.

[0034] Please see Figure 1 In one embodiment, the image sensor includes a pixel array 10, a pixel output bit line 20, and an analog-to-digital conversion module 30.

[0035] The pixel array 10 is connected to the analog-to-digital converter module 30 via the pixel output bit line 20. The analog-to-digital converter module 30 includes a source follower transistor (SF).

[0036] Optionally, the pixel array 10 outputs a pixel voltage signal to the analog-to-digital converter module 30 via the pixel output bit line 20. Optionally, the source follower transistor used has a very low output impedance and relatively high power, and has good thermal breakdown resistance. By adding a source follower transistor (SF) to the analog-to-digital converter module 30, the pixel voltage signal can be buffered, making the output of the pixel array 10 more stable.

[0037] In this circuit, the gate of the source follower transistor (SF) is connected to the pixel output bit line 20, the drain of the source follower transistor (SF) is connected to a preset voltage V, the source of the source follower transistor (SF) is connected to the positive terminal of the current source I, and the negative terminal of the current source I is grounded.

[0038] The source of the source follower transistor (SF) is also connected to a source follower signal line. The source follower signal line includes a first source follower signal sub-line 21 and a second source follower signal sub-line 22, respectively, in a direction relative to the source of the source follower transistor (SF). Both the first source follower signal sub-line 21 and the second source follower signal sub-line 22 are arranged parallel to the pixel output bit line 20, and are located on opposite sides of the pixel output bit line.

[0039] For example, the source follower transistor (SF) uses its gate to receive the pixel voltage signal transmitted by the pixel output bit line 20, and uses its source to drive the source follower signal line, so that the source potential energy follows the gate voltage to generate the follower voltage signal of the pixel voltage signal.

[0040] In this embodiment, by adding a source follower transistor (SF) to the analog-to-digital conversion module 30 and connecting it to the first source follower signal sub-line 21 and the second source follower signal sub-line 22 on both sides of the pixel output bit line 20, not only can the pixel output bit line 20 be protected and the equivalent parasitic capacitance reduced, but the signal storage speed can also be accelerated.

[0041] In one embodiment, the first source follower signal sub-line 21 and the pixel output bit line 20 in the image sensor have a first parasitic capacitance, and the second source follower signal sub-line 22 and the pixel output bit line 20 have a second parasitic capacitance, wherein the capacitance values ​​of the first parasitic capacitance and the second parasitic capacitance are equal.

[0042] In this embodiment, the pixel output bit line 20 is connected to the gate of the source follower transistor (SF), and the first source follower signal sub-line 21 and the second source follower signal sub-line 22 are both connected to the source of the source follower transistor (SF). For example, when the first source follower signal sub-line 21 and the second source follower signal sub-line 22 are completely symmetrical with respect to the pixel output bit line 20, the capacitance values ​​of the first parasitic capacitor and the second parasitic capacitor can be made equal.

[0043] In one embodiment, the source follower transistor (SF) in the image sensor has a gain of A, and the parasitic capacitance between the first source follower signal sub-line 21 and the second source follower signal sub-line 22 is C. Then, the capacitance values ​​of the first parasitic capacitance and the second parasitic capacitance are both (1-A)*C.

[0044] In this embodiment, since the capacitance between the gate and source of the source follower transistor (SF) is much smaller than the parasitic capacitance C between the first source follower signal sub-line 21 and the second source follower signal sub-line 22, the effect of this capacitance can be ignored. According to Miller's theorem, when the first source follower signal sub-line 21 and the second source follower signal sub-line 22 are perfectly symmetrical with respect to the pixel output bit line 20, the capacitance values ​​of the first parasitic capacitance and the second parasitic capacitance can be made equal and both (1-A)*C. It can be understood that by setting the first source follower signal sub-line 21 and the second source follower signal sub-line 22 driven by the source follower transistor (SF), the capacitance values ​​of the first parasitic capacitance and the second parasitic capacitance are greatly reduced.

[0045] In one embodiment, the gain of the source follower transistor (SF) in the image sensor is between 0 and 1.

[0046] Since the gain of the source follower transistor (SF) is between 0 and 1, it can be known that both the first and second parasitic capacitances are smaller than the parasitic capacitance C between the two source follower signal sub-lines. In this embodiment, the closer the gain of the source follower transistor (SF) is to 1, the closer the capacitance values ​​of the first and second parasitic capacitances are to 0, which can greatly reduce the impact of parasitic capacitance on the pixel output bit line 20.

[0047] It should be noted that in the above embodiments, this application does not limit the gain of the source follower transistor (SF). Taking into account both cost and gain, a suitable source follower transistor (SF) can be selected.

[0048] In one embodiment, the distance between the first source follower signal sub-line 21 and the pixel output bit line 20 in the image sensor is equal to the distance between the second source follower signal sub-line 22 and the pixel output bit line 20.

[0049] In this embodiment, the source follower signal lines include two sub-lines: a first source follower signal sub-line 21 and a second source follower signal sub-line 22. These two sub-lines are parallel and equidistant, wrapping around both ends of the pixel output bit line 20. These two sub-lines can significantly reduce the equivalent parasitic capacitance between the source follower signal lines and the pixel output bit line 20. When the first source follower signal sub-line 21 and the second source follower signal sub-line 22 are completely symmetrical with respect to the pixel output bit line 20, the capacitance values ​​of the first parasitic capacitance and the second parasitic capacitance can be made equal. It should be noted that the source follower signal lines are simply two source follower signal sub-lines drawn from the source follower transistor (SF) and are not connected to the pixel array 10.

[0050] Please continue reading. Figure 1In one embodiment, a current source I in the image sensor is connected between the source follower transistor (SF) and a ground signal to provide a constant current to the source follower transistor (SF).

[0051] In this embodiment, by adding a current source I to the source follower transistor (SF), a constant current can be provided to the source follower transistor (SF), thereby reducing the influence of the preset voltage V on the source follower voltage signal.

[0052] In one embodiment, the pixel array 10 in the image sensor includes a source follower, the source of which is connected to the pixel output bit line 20.

[0053] In this embodiment, the pixel array 10 outputs the pixel voltage signal to the pixel output bit line 20 through the source follower, which can buffer the output of the pixel voltage signal.

[0054] Second Embodiment

[0055] This application provides a method for reducing the equivalent capacitance of pixel output bit lines in an image sensor, applied to the image sensor of the first embodiment. Figure 2 This is a flowchart of a method for reducing the equivalent capacitance of pixel output bit lines in an image sensor according to an embodiment of this application.

[0056] Please see Figure 2 In one embodiment, the method for reducing the equivalent capacitance of a pixel output bit line includes:

[0057] S10: Pixel array outputs pixel voltage signal.

[0058] S20: The analog-to-digital converter module obtains the pixel voltage signal through the pixel output bit line.

[0059] S30: The source follower voltage signal is generated by following the pixel voltage signal through the source follower transistor set in the analog-to-digital conversion module.

[0060] S40: Receives the source follower voltage signal generated by the source follower transistor by setting the first source follower signal sub-line and the second source follower signal sub-line.

[0061] For example, the pixel array outputs a pixel voltage signal to the analog-to-digital converter module via a pixel output bit line. The source follower transistor receives the pixel voltage signal transmitted by the pixel output bit line through its gate, and drives the first source follower signal sub-line and the second source follower signal sub-line through its source, so that the source potential energy follows the gate voltage to generate a follower voltage signal of the pixel voltage signal.

[0062] In this embodiment, by adding a source follower transistor to the analog-to-digital conversion module, the pixel voltage signal can be buffered, making the output of the pixel array more stable. Connecting the source follower transistor to the first and second source follower signal sub-lines on both sides of the pixel output bit line not only protects the pixel output bit line and reduces the equivalent parasitic capacitance, but also speeds up signal storage.

[0063] In one embodiment, in the method for reducing the equivalent capacitance of the pixel output bit line in an image sensor, the gain of the source follower transistor is set to A, and the parasitic capacitance between the first source follower signal sub-line and the second source follower signal sub-line is set to C. Then, the capacitance values ​​of the first parasitic capacitance and the second parasitic capacitance are both (1-A)*C.

[0064] In one embodiment, the first source follower signal sub-line and the pixel output bit line in the image sensor have a first parasitic capacitance, and the second source follower signal sub-line and the pixel output bit line have a second parasitic capacitance. The pixel output bit line is connected to the gate of the source follower transistor, and both the first and second source follower signal sub-lines are connected to the source of the source follower transistor. According to Miller's theorem, when the first and second source follower signal sub-lines are perfectly symmetrical with respect to the pixel output bit line, the capacitance values ​​of the first and second parasitic capacitances can be made equal. At this time, the capacitance values ​​of the first and second parasitic capacitances are equal and both are (1-A)*C.

[0065] Optionally, since the capacitance between the gate and source in the source follower transistor is much smaller than the parasitic capacitance C between the first and second source follower signal sub-lines, the effect of this capacitance can be ignored. Understandably, by setting the first and second source follower signal sub-lines driven by the source follower transistor, the capacitance values ​​of the first and second parasitic capacitances are greatly reduced. Since the gain of the source follower transistor (SF) is between 0 and 1, both the first and second parasitic capacitances are smaller than the parasitic capacitance C between the two source follower signal sub-lines. The closer the gain of the source follower transistor is to 1, the closer the capacitance values ​​of the first and second parasitic capacitances are to 0, which can greatly reduce the impact of parasitic capacitance on the pixel output bit line.

[0066] Third Embodiment

[0067] This application provides a storage medium, optionally storing a computer program on the storage medium, which, when executed by a processor, implements the steps of the method for reducing the equivalent capacitance of the pixel output bit line described in the second embodiment.

[0068] As described above, this application provides an image sensor, a method for reducing the equivalent capacitance of pixel output bit lines, and a storage medium. By adding a source follower transistor to the analog-to-digital conversion module and connecting it to the source follower signal lines on both sides of the pixel output bit line, it is possible not only to protect the pixel output bit line and reduce the equivalent parasitic capacitance, but also to speed up the signal storage speed.

[0069] It should be noted that step designations such as S10 and S20 are used in this application for the purpose of more clearly and concisely describing the corresponding content, and do not constitute a substantial limitation on the order. In specific implementation, those skilled in the art may execute S20 first and then S10, etc., but these should all be within the protection scope of this application.

[0070] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An image sensor, characterized by, The pixel array, a pixel output bit line and an analog-digital conversion module are included. The pixel array is connected to the analog-digital conversion module through the pixel output bit line. The analog-digital conversion module includes a source follower transistor, wherein: The gate of the source follower transistor is connected to the pixel output bit line, the drain of the source follower transistor is connected to a preset voltage, and the source of the source follower transistor is connected to a current source. The source of the source follower transistor is also connected to a source follower signal line, and the source follower signal line includes a first source follower signal sub-line and a second source follower signal sub-line in opposite directions away from the source of the source follower transistor, both of which are arranged in parallel with the pixel output bit line, and the first source follower signal sub-line and the second source follower signal sub-line are located on both sides of the pixel output bit line.

2. The image sensor of claim 1, wherein, The first source follower signal sub-line and the pixel output bit line have a first parasitic capacitance, and the second source follower signal sub-line and the pixel output bit line have a second parasitic capacitance, and the capacitance values of the first parasitic capacitance and the second parasitic capacitance are equal.

3. The image sensor of claim 2, wherein the first and second photodiodes are configured to generate the first and second signals in response to the same light. The gain of the source follower transistor is A, and the parasitic capacitance between the first source follower signal sub-line and the second source follower signal sub-line is C, and the capacitance values of the first parasitic capacitance and the second parasitic capacitance are both (1-A)*C.

4. The image sensor of claim 3, wherein, The gain of the source follower transistor is between 0 and 1.

5. The image sensor of claim 1, wherein, The distance between the first source follower signal sub-line and the pixel output bit line is equal to the distance between the second source follower signal sub-line and the pixel output bit line.

6. The image sensor of claim 1, wherein, The current source is connected between the source follower transistor and a ground signal to provide a constant current for the source follower transistor.

7. The image sensor of claim 1, wherein, The pixel array includes a source follower, and the source of the source follower is connected to the pixel output bit line.

8. A method for reducing equivalent capacitance of a pixel output bit line in an image sensor, the method comprising: The image sensor is applied to any one of claims 1-7, and includes: The pixel array outputs a pixel voltage signal. The analog-digital conversion module acquires the pixel voltage signal through the pixel output bit line. The source follower transistor in the analog-digital conversion module follows the pixel voltage signal to generate a source follower voltage signal. The first source follower signal sub-line and the second source follower signal sub-line receive the source follower voltage signal generated by the source follower transistor.

9. The method of claim 8, wherein the equivalent capacitance of the pixel output bit line is reduced by, The first source follower signal sub-line and the pixel output bit line have a first parasitic capacitance, and the second source follower signal sub-line and the pixel output bit line have a second parasitic capacitance; the gain of the source follower transistor is A, and the parasitic capacitance between the first source follower signal sub-line and the second source follower signal sub-line is C, and the capacitance values of the first parasitic capacitance and the second parasitic capacitance are both (1-A)*C.

10. A storage medium, characterized by The storage medium stores a computer program, and the computer program is executed by the processor to realize the steps of the pixel output bit line equivalent capacitance reduction method in the image sensor of claim 8 or 9.

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