Chip testing method, device, electronic device and readable storage medium

Abstract

The present disclosure provides a chip testing method, device, electronic device and readable storage medium. Among them, the chip testing method includes: obtaining the original test vector file of the chip under test, the original test vector file includes the timing waveform data of the JTAG interface and the timing waveform data of the function clock interface; modifying each timing waveform data of the JTAG interface so that the duration of the waveform corresponding to each timing waveform data is extended to N times the original duration, thereby obtaining a transformed test vector file; the original duration is equal to the period corresponding to the highest effective frequency of the functionclock interface, and N is equal to the ratio of the highest effective frequency of the function clock interface to the highest effective frequency of the JTAG interface; using the transformed test vector file to test the chip under test. In the present disclosure, by extending the duration of the timing waveform data of the JTAG interface to N times the original duration, the test frequency of the function is maximized in the Function Setup stage of the chip test.

Description

Technical Field

[0001] The present disclosure relates to the field of chip testing technology, and in particular to a chip testing method, device, electronic device and readable storage medium. Background Art

[0002] In the field of chip testing, the chip can be tested by chip testing equipment (such as ATE). Before testing, the test vector file (such as Function setup file or Function Test pattern file) automatically generated by the TetraMAX tool (or Tessent tool, FastScan tool) needs to be input into the chip testing equipment. During the test, the chip testing equipment inputs the corresponding test signal to each interface of the chip under test according to the timing waveform data of each interface in the test vector file.

[0003] During the Function Setup phase of chip testing, the chip testing equipment needs to input corresponding test signals to the JTAG interface and function clock interface of the chip under test. Due to the testable design of the chip under test, the maximum effective frequency of the JTAG interface is usually much lower than the maximum effective frequency of the function clock interface. For example, the maximum effective frequency of the JTAG interface is usually 25Mhz, and the maximum effective frequency of the function clock interface is usually 200Mhz or 400Mhz. In addition, during the Function Setup phase, the test signal frequency of the function clock interface will be subject to the test signal frequency of the JTAG interface, resulting in the function test frequency not being able to be maximized. Summary of the invention

[0004] The purpose of the present disclosure is to provide a chip testing method, device, electronic device and readable storage medium, so that the test frequency of the function can be maximized in the Function Setup stage of the chip test.

[0005] According to one aspect of the present disclosure, a chip testing method is provided, the method comprising:

[0006] Obtaining the original test vector file of the chip under test, the original test vector file includes the timing waveform data of the JTAG interface and the timing waveform data of the function clock interface;

[0007] Modify each timing waveform data of the JTAG interface so that the duration of the waveform corresponding to each timing waveform data of the JTAG interface is extended to N times of the original duration, thereby obtaining a transformed test vector file; the original duration is equal to the period corresponding to the highest effective frequency of the function clock interface, and N is equal to the ratio of the highest effective frequency of the function clock interface to the highest effective frequency of the JTAG interface;

[0008] Use the transformed test vector file to test the chip under test.

[0009] Optionally, the original test vector file includes multiple lines of test vectors and multiple lines of notes; the chip testing method further includes: traversing the notes of the original test vector file, and determining whether each line of notes traversed includes a preset starting position; the preset starting position is used to represent: the starting point of the timing waveform data of the JTAG interface in the original test vector file;

[0010] Each timing waveform data of the JTAG interface is modified, including: after determining the remark including the preset starting position, taking the next line of the remark as the starting point, traversing the remaining lines of the original test vector file, for each line of the test vector traversed, modifying the timing waveform data of the JTAG interface in each line of the test vector until traversing to the remark including the preset end position; the preset end position is used to represent: the end point of the timing waveform data of the JTAG interface in the original test vector file.

[0011] Optionally, the timing waveform data of the JTAG interface includes the timing waveform data of the TCK pin, and the timing waveform of the TCK pin is a pulse waveform;

[0012] For each row of test vectors traversed, the timing waveform data of the JTAG interface in each row of test vectors is modified, including:

[0013] For each row of test vectors traversed, each row of test vectors is transformed into N rows of test vectors; in the first N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 0, and in the last N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 1; or, in the first N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 1, and in the last N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 0.

[0014] Optionally, the timing waveform data of the JTAG interface also includes timing waveform data of at least one of the three pins TDI, TDO and TMS, and the timing waveform data of TDI, TDO or TMS is a binary number; in each line of the N lines of test vectors, the timing waveform data of TDI, TDO or TMS is an original binary number.

[0015] Optionally, the timing waveform data of the function clock interface is pulse data; in each row of the test vectors in the N rows of test vectors, the timing waveform data of the function clock interface is pulse data.

[0016] Optionally, the original test vector file also includes timing waveform data of other interfaces, where other interfaces are interfaces other than the JTAG interface and the function clock interface, and the timing waveform data of other interfaces are binary numbers; in each line of the N lines of test vectors, the timing waveform data of other interfaces are original binary numbers.

[0017] Optionally, the chip under test is tested using the transformed test vector file, including: inputting the clock configuration file and the transformed test vector file into the chip testing equipment to test the chip under test; the clock configuration file includes the clock frequency of the JTAG interface and the clock frequency of the function clock interface, and the clock frequency of the JTAG interface and the clock frequency of the function clock interface are both equal to the highest effective frequency of the function clock interface.

[0018] According to another aspect of the present disclosure, a chip testing device is provided, the device comprising:

[0019] A file acquisition module is used to obtain the original test vector file of the chip under test, wherein the original test vector file includes the timing waveform data of the JTAG interface and the timing waveform data of the function clock interface;

[0020] The duration extension module is used to modify each timing waveform data of the JTAG interface so that the duration of the waveform corresponding to each timing waveform data of the JTAG interface is extended to N times of the original duration, thereby obtaining a transformed test vector file; the original duration is equal to the period corresponding to the highest effective frequency of the function clock interface, and N is equal to the ratio of the highest effective frequency of the function clock interface to the highest effective frequency of the JTAG interface;

[0021] The chip testing module is used to test the chip under test using the transformed test vector file.

[0022] Optionally, the original test vector file includes multiple lines of test vectors and multiple lines of comments; the chip testing device further includes: a starting position determination module;

[0023] The starting position determination module is used to: traverse the notes of the original test vector file, and determine whether each line of the traversed notes includes a preset starting position; the preset starting position is used to represent: the starting point of the timing waveform data of the JTAG interface in the original test vector file;

[0024] The duration extension module is specifically used for: after determining the remark including the preset starting position, taking the next line of the remark as the starting point, traversing the remaining lines of the original test vector file, and for each line of test vector traversed, modifying the timing waveform data of the JTAG interface in each line of test vector until traversing to the remark including the preset end position; the preset end position is used to represent: the end point of the timing waveform data of the JTAG interface in the original test vector file.

[0025] Optionally, the timing waveform data of the JTAG interface includes the timing waveform data of the TCK pin, and the timing waveform of the TCK pin is a pulse waveform;

[0026] The duration extension module is specifically used for: for each row of test vectors traversed, transforming each row of test vectors into N rows of test vectors; in the first N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 0, and in the last N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 1; or, in the first N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 1, and in the last N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 0.

[0027] Optionally, the timing waveform data of the JTAG interface also includes timing waveform data of at least one of the three pins TDI, TDO and TMS, and the timing waveform data of TDI, TDO or TMS is a binary number; in each line of the N lines of test vectors, the timing waveform data of TDI, TDO or TMS is an original binary number.

[0028] Optionally, the timing waveform data of the function clock interface is pulse data; in each row of the test vectors in the N rows of test vectors, the timing waveform data of the function clock interface is pulse data.

[0029] Optionally, the original test vector file also includes timing waveform data of other interfaces, where other interfaces are interfaces other than the JTAG interface and the function clock interface, and the timing waveform data of other interfaces are binary numbers; in each line of the N lines of test vectors, the timing waveform data of other interfaces are original binary numbers.

[0030] Optionally, the chip test module body is specifically used to: input the clock configuration file and the transformed test vector file into the chip test equipment to test the chip under test; the clock configuration file includes the clock frequency of the JTAG interface and the clock frequency of the function clock interface, and the clock frequency of the JTAG interface and the clock frequency of the function clock interface are both equal to the highest effective frequency of the function clock interface.

[0031] According to another aspect of the present disclosure, an electronic device is also provided, which includes: a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate through the bus, and when the machine-readable instructions are executed by the processor, any of the above chip testing methods is implemented.

[0032] According to another aspect of the present disclosure, a storage medium is further provided, on which a computer program is stored. When the computer program is executed by a processor, any of the above chip testing methods is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a flowchart of a chip testing method provided by an embodiment of the present disclosure;

[0034] Figure 2 is a schematic diagram of an original test vector file provided by an embodiment of the present disclosure;

[0035] Figure 3 is a flowchart of a chip testing method provided by another embodiment of the present disclosure;

[0036] Figure 4 is a schematic diagram of converting a test vector row according to an embodiment of the present disclosure;

[0037] Figure 5 is a schematic structural diagram of a chip testing device provided by an embodiment of the present disclosure;

[0038] Figure 6 It is a structural block diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] Before introducing the embodiments of the present disclosure, it should be noted that some embodiments of the present disclosure are described as processing flows. Although the various operation steps of the flow may be given sequential step numbers, the operation steps therein may be implemented in parallel, concurrently or simultaneously.

[0040] In the embodiments of the present disclosure, the terms "first", "second", etc. may be used to describe various features, but these features should not be limited by these terms. These terms are used only to distinguish one feature from another.

[0041] The term “and / or” may be used in embodiments of the present disclosure. “And / or” includes any and all combinations of one or more of the associated features listed.

[0042] It should be understood that when describing the connection or communication relationship between two components, unless it is explicitly stated that the two components are directly connected or directly communicating, the connection or communication between the two components can be understood as direct connection or communication, or as indirect connection or communication through an intermediate component.

[0043] In order to make the technical solutions and advantages of the embodiments of the present disclosure more clearly understood, the exemplary embodiments of the present disclosure are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0044] The purpose of the present disclosure is to provide a solution for generating a test vector file during a chip testing phase, which can maximize the test frequency of a function during chip testing using the test vector file.

[0045] refer to Figure 1 , Figure 1 FIG. 1 is a flow chart of a chip testing method provided by an embodiment of the present disclosure. Figure 1 As shown, the chip testing method includes the following steps:

[0046] S110: Obtaining an original test vector file of the chip under test, where the original test vector file includes timing waveform data of a JTAG interface and timing waveform data of a function clock interface.

[0047] Among them, the JTAG interface (Joint Test Action Group) and the function clock interface are both interfaces of the chip under test. In other words, the chip under test includes the JTAG interface and the function clock interface.

[0048] The original test vector file may be a file in VCD format, or a file in WGL format, or a file in STIL format. It should be noted that the present disclosure does not limit the format of the original test vector file.

[0049] S120: Modify each timing waveform data of the JTAG interface so that the duration of the waveform corresponding to each timing waveform data of the JTAG interface is extended to N times the original duration, thereby obtaining a transformed test vector file; the original duration is equal to the period corresponding to the highest effective frequency of the function clock interface, and N is equal to the ratio of the highest effective frequency of the functionclock interface to the highest effective frequency of the JTAG interface.

[0050] S130: Testing the chip under test using the transformed test vector file.

[0051] For ease of understanding, assuming that the maximum effective frequency of the function clock interface of the chip under test is 200Mhz and the maximum effective frequency of the JTAG interface of the chip under test is 25Mhz, the original duration is equal to the period corresponding to 200Mhz, that is, 1 / (2×10 8 ) seconds, N is equal to 8. In step S120, by modifying each timing waveform data of the JTAG interface, the duration of the waveform corresponding to each timing waveform data of the JTAG interface is extended to 1 / (2×10 8 ) seconds. Thus, in the transformed test vector file, the duration of the waveform corresponding to each timing waveform data of the JTAG interface is equal to 8 / (2×10 8 )Second.

[0052] In the Function Setup stage of chip testing, the chip testing equipment inputs a cycle equal to 1 / (2×10 8 ) seconds (i.e., the frequency is equal to 200Mhz), but the duration of each waveform in the test signal is equal to 8 / (2×10 8 ) seconds. For example, if the test signal is a binary string 10010..., then for the first signal data "1", the chip test equipment continuously inputs 8 high levels to the JTAG interface at 200Mhz. The total duration of these 8 high levels is equal to 8 / (2×10 8 ) seconds. For the second signal data "0", the chip test equipment continuously inputs 8 low levels to the JTAG interface at 200Mhz. The total duration of these 8 low levels is equal to 8 / (2×10 8) seconds. Thus, for the JTAG interface of the chip under test, the actual signal period it senses is 8 / (2×10 8 ) seconds, which just matches the highest effective frequency of the JTAG interface, 25Mhz. It can be seen that in the Function Setup stage of the chip test, the JTAG interface of the chip under test can achieve maximum frequency.

[0053] In the Function Setup phase of chip testing, the chip test equipment inputs a period equal to 1 / (2×10 8 ) seconds (i.e., the frequency is equal to 200Mhz). Since the duration of the waveform of the function clock interface is not extended, the duration of the waveform of the function clock interface is still equal to the period corresponding to the highest effective frequency of the function clock interface, i.e., 1 / (2×10 8 ) seconds. Thus, for the function clock interface of the chip under test, the actual signal period it perceives is 1 / (2×10 8 ) seconds, which just matches the highest effective frequency of the function clock interface, 200Mhz. It can be seen that in the Function Setup phase of the chip test, the function clock interface of the chip under test can also achieve maximum frequency.

[0054] In some possible implementations, such as Figure 2 As shown, the original test vector file may include multiple lines of test vectors and multiple lines of comments. Figure 2 In the figure, / *......* / belongs to the comment line, and the remaining lines belong to the test vector lines.

[0055] refer to Figure 3 , Figure 3 FIG. 1 is a flow chart of a chip testing method provided by another embodiment of the present disclosure. Figure 3 As shown, the chip testing method includes the following steps:

[0056] S310: Obtaining an original test vector file of the chip under test, where the original test vector file includes timing waveform data of a JTAG interface and timing waveform data of a function clock interface.

[0057] S320: Traverse the comments of the original test vector file to determine whether each line of comments traversed includes a preset starting position; the preset starting position is used to represent: the starting point of the timing waveform data of the JTAG interface in the original test vector file.

[0058] In specific implementation, each line of the original test vector file can be traversed line by line. For the current line traversed, determine whether the current line belongs to a remark. If the current line does not belong to a remark, continue to traverse the next line. If the current line belongs to a remark, determine whether the current line includes a preset starting position. If the current line does not include a preset starting position, continue to traverse the next line. The preset starting position can be a string in the form of "start".

[0059] Alternatively, each line of the original test vector file may be traversed line by line. For the current line traversed, it is determined whether the current line includes a preset starting position. If the current line does not include the preset starting position, the next line is traversed. The preset starting position may be a string in the form of "start".

[0060] S330: After determining the remark including the preset starting position, take the next line of the remark as the starting point, traverse the remaining lines of the original test vector file, and for each line of the test vector traversed, modify the timing waveform data of the JTAG interface in each line of the test vector until traversing to the remark including the preset end position; the preset end position is used to represent: the end point of the timing waveform data of the JTAG interface in the original test vector file.

[0061] As mentioned above, the present disclosure modifies each timing waveform data of the JTAG interface so that the duration of the waveform corresponding to each timing waveform data of the JTAG interface is extended to N times the original duration. The original duration is equal to the period corresponding to the highest effective frequency of the function clock interface, and N is equal to the ratio of the highest effective frequency of the function clock interface to the highest effective frequency of the JTAG interface.

[0062] In specific implementation, after determining the remark including the preset starting position, traverse from the next line of the remark as the starting point. For the current line traversed, determine whether the current line belongs to the test vector. If the current line belongs to the test vector, modify the timing waveform data of the JTAG interface in the current line, and then continue to traverse the next line. If the current line does not belong to the test vector, determine whether the current line includes the preset end position. If the current line does not include the preset end position, continue to traverse the next line. If the current line includes the preset end position, stop traversing. Among them, the preset end position can be a string in the form of "end".

[0063] For ease of understanding, Figure 2 The original test vector file shown is processed. Figure 2The 103rd row in the program includes the preset starting position "start", so the 104th row is used as the starting point, and the 104th row and the subsequent rows are traversed. For each row of test vectors traversed, the timing waveform data of the JTAG interface is modified. The traversal stops when the 568th row including the preset end position "end" is traversed.

[0064] It is worth noting that by adding a preset start position and a preset end position in the original test vector file, when the original test vector file is automatically converted, the lines that need to be converted can be automatically determined by identifying the preset start position and the preset end position. In addition, according to the chip test requirements, some lines that do not need to be converted and are used for chip testing can be added before the preset start position or after the preset end position.

[0065] refer to Figure 4 , Figure 4 It is a schematic diagram of converting test vector rows proposed in one embodiment of the present disclosure. Figure 4 In the example, N is 8. Figure 4 The row of data on the left is a row of test vectors before conversion. Figure 4 The 8 rows of data on the right are 8 rows of test vectors formed by converting the 1 row of test vector on the left.

[0066] In the present disclosure, the timing waveform data of the JTAG interface includes the timing waveform data of the TCK pin (Test Clock Input), and the timing waveform of the TCK pin is a pulse waveform. Figure 4 As shown, in the 1-line test vector before conversion, the timing waveform data of the TCK pin is pulse, that is, pulse data.

[0067] When executing the above step S330, if Figure 4 As shown, the test vector can be modified in the following manner: for each row of test vectors traversed, each row of test vectors is transformed into N rows of test vectors; in the first N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 0, and in the last N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 1. Alternatively, in the first N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 1, and in the last N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 0.

[0068] It is worth noting that in the present disclosure, the duration of each row of test vectors is equal to one cycle, that is, the cycle corresponding to the highest effective frequency of the functionclock interface. If the highest effective frequency of the function clock interface is equal to 200Mhz, the duration of each row of test vectors is equal to 1 / (2×10 8 ) seconds. By converting one line of test vector into 8 lines, the total duration of the 8-line test vector is 8 / (2×10 8 ) seconds. Among them, the first 4 / (2×10 8 ) seconds is low level, low level corresponds to binary number 0, and the next 4 / (2×10 8 ) seconds is high level, and high level corresponds to the binary number 1, so the actual pulse frequency felt by the TCK pin is 25Mhz, which is equal to the maximum effective frequency of the JTAG interface.

[0069] In the present disclosure, the timing waveform data of the JTAG interface may also include the timing waveform data of at least one of the following three pins. The three pins are: TDI (test data input pin), TDO (test data output pin) and TMS (test mode selection pin), and the timing waveform data of TDI, TDO or TMS is a binary number. For N rows of test vectors converted from one row of test vectors, in each row of the N rows of test vectors, the timing waveform data of TDI, TDO or TMS is an original binary number. Among them, the original binary number is the binary number of the timing waveform data of TDI, TDO or TMS before conversion.

[0070] For ease of understanding, Figure 4 Take the TDI pin as an example. In the 1-line test vector before conversion, the timing waveform data of TDI is the binary number "1". For the 8-line test vector after conversion, the timing waveform data of TDI in each line of the test vector is the original binary number "1". As mentioned above, the duration of each line of the test vector is equal to 1 / (2×10 8 ) seconds. By converting one line of test vector into 8 lines, the total duration of the 8-line test vector is 8 / (2×10 8 ) seconds. In this way, the high level of the TDI pin (assuming that the binary number 1 corresponds to the high level) will last for 8 / (2×10 8 ) seconds, the signal frequency is 25Mhz, which is equal to the maximum effective frequency of the JTAG interface.

[0071] In the present disclosure, the timing waveform data of the function clock interface is pulse data. Figure 4As shown in FIG. 1 , in the 1-line test vector before conversion, the timing waveform data of the function clock interface is pulse, i.e., pulse data. For the N-line test vector converted from one-line test vector, the timing waveform data of the function clock interface in each line of the N-line test vector is pulse data. Figure 4 As shown in the figure, in each of the 8 test vectors converted, the timing waveform data of the function clock interface is maintained as pulse. Since the duration of each test vector is equal to 1 / (2×10 8 ) seconds, so the pulse frequency of the function clock interface is still 200Mhz, which is equal to the maximum effective frequency of the function clock interface.

[0072] In the present disclosure, the original test vector file may also include the timing waveform data of other interfaces, where other interfaces are interfaces other than the JTAG interface and the function clock interface, and the timing waveform data of other interfaces are binary numbers. For N lines of test vectors converted from one line of test vectors, in each line of the N lines of test vectors, the timing waveform data of other interfaces are original binary numbers. The original binary numbers are the binary numbers of the timing waveform data of other interfaces before conversion.

[0073] For ease of understanding, Figure 4 As shown in the figure, in the 1-line test vector before conversion, the timing waveform data of other interfaces is the binary number "0". For the 8-line test vector converted, the timing waveform data of other interfaces in each line of the test vector is the original binary number "0". As mentioned above, the duration of each line of the test vector is equal to 1 / (2×10 8 ) seconds. By converting one line of test vector into 8 lines, the total duration of the 8-line test vector is 8 / (2×10 8 ) seconds. In this way, the low level of other interfaces (assuming that the binary number 0 corresponds to the low level) will last for 8 / (2×10 8 ) seconds, the signal frequency is 25Mhz.

[0074] In the present disclosure, each vector content in each row of test vectors has a one-to-one correspondence with each pin. Figure 4In each row of test vectors, the first vector content in each row of test vectors corresponds to the TDI pin, the second vector content in each row of test vectors corresponds to the TCK pin, the third vector content in each row of test vectors corresponds to other interfaces, and the fourth vector content in each row of test vectors corresponds to the function clock interface. In this way, when converting one row of test vectors into N rows of test vectors, each test vector can be processed as described above according to the pin corresponding to each vector content in each row of test vectors.

[0075] In some feasible implementations, when the chip under test is tested using the transformed test vector file, a clock configuration file (timing) and the transformed test vector file can be input into a chip testing device to test the chip under test.

[0076] The clock configuration file includes the clock frequency of the JTAG interface and the clock frequency of the function clock interface. The clock frequency of the JTAG interface and the clock frequency of the function clock interface are both equal to the highest valid frequency of the function clock interface. For example, if the highest valid frequency of the function clock interface is 200Mhz, then in the clock configuration file, the clock frequency of the JTAG interface and the clock frequency of the function clock interface are both equal to 200Mhz.

[0077] Above, the present disclosure provides a chip testing method through an embodiment. Below, the present disclosure provides a chip testing device through an embodiment. It should be noted that the principle of the chip testing device is the same as the principle of the above-mentioned chip testing method, so in order to avoid repetition, the chip testing device is briefly described below.

[0078] refer to Figure 5 , Figure 5 FIG. 1 is a schematic diagram of the structure of a chip testing device provided by an embodiment of the present disclosure. Figure 5 As shown, the chip testing device includes:

[0079] The file acquisition module 510 is used to obtain the original test vector file of the chip under test, where the original test vector file includes the timing waveform data of the JTAG interface and the timing waveform data of the function clock interface.

[0080] The duration extension module 530 is used to modify each timing waveform data of the JTAG interface so that the duration of the waveform corresponding to each timing waveform data of the JTAG interface is extended to N times the original duration, thereby obtaining a transformed test vector file; the original duration is equal to the period corresponding to the highest effective frequency of the function clock interface, and N is equal to the ratio of the highest effective frequency of the function clock interface to the highest effective frequency of the JTAG interface.

[0081] The chip testing module 540 is used to test the chip under test using the transformed test vector file.

[0082] In some feasible implementations, the original test vector file includes multiple lines of test vectors and multiple lines of comments. Figure 5 As shown, the chip testing device may further include: a starting position determining module 520 .

[0083] The starting position determination module 520 is used to traverse the comments of the original test vector file and determine whether each line of comments traversed includes a preset starting position; the preset starting position is used to represent: the starting point of the timing waveform data of the JTAG interface in the original test vector file.

[0084] The duration extension module 530 is specifically used for: after determining the remark including the preset starting position, taking the next line of the remark as the starting point, traversing the remaining lines of the original test vector file, and for each line of the test vector traversed, modifying the timing waveform data of the JTAG interface in each line of the test vector until traversing to the remark including the preset end position; the preset end position is used to represent: the end point of the timing waveform data of the JTAG interface in the original test vector file.

[0085] In some feasible implementations, the timing waveform data of the JTAG interface includes the timing waveform data of the TCK pin, and the timing waveform of the TCK pin is a pulse waveform.

[0086] The duration extension module 530 is specifically used for: for each row of test vectors traversed, transforming each row of test vectors into N rows of test vectors; in the first N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 0, and in the last N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 1; or, in the first N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 1, and in the last N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 0.

[0087] In some feasible implementations, the timing waveform data of the JTAG interface also includes timing waveform data of at least one of the three pins TDI, TDO and TMS, and the timing waveform data of TDI, TDO or TMS is a binary number; in each line of the test vector in the N lines of test vectors, the timing waveform data of TDI, TDO or TMS is the original binary number.

[0088] In some feasible implementations, the timing waveform data of the function clock interface is pulse data; in each row of the test vectors in the N rows of test vectors, the timing waveform data of the function clock interface is pulse data.

[0089] In some feasible implementations, the original test vector file also includes timing waveform data of other interfaces, where other interfaces are interfaces other than the JTAG interface and the function clock interface, and the timing waveform data of other interfaces are binary numbers; in each line of the test vector in the N lines of test vectors, the timing waveform data of other interfaces are original binary numbers.

[0090] In some feasible implementations, the chip test module body 540 is specifically used to: input the clock configuration file and the transformed test vector file into the chip testing equipment to test the chip under test; the clock configuration file includes the clock frequency of the JTAG interface and the clock frequency of the function clock interface, and the clock frequency of the JTAG interface and the clock frequency of the function clock interface are both equal to the highest effective frequency of the function clock interface.

[0091] See also Figure 6 , Figure 6 It is a structural block diagram of an electronic device provided in one embodiment of the present disclosure, wherein the electronic device 600 includes a processor 610, a memory 620, and one or more applications, wherein the one or more applications are stored in the memory 620 and configured to be executed by one or more processors 610, and the one or more programs are configured to execute the above-mentioned chip testing method.

[0092] In some embodiments, the electronic device 600 in the present disclosure may include one or more of the following components: a processor 610, a memory 620, and one or more applications, wherein the one or more applications may be stored in the memory 620 and configured to be executed by one or more processors 610, and the one or more programs are configured to execute the methods described in the aforementioned method embodiments.

[0093] The processor 610 may include one or more processing cores. The processor 610 uses various interfaces and lines to connect various parts of the entire electronic device 600, and executes various functions and processes data of the electronic device 600 by running or executing instructions, programs, code sets or instruction sets stored in the memory 620, and calling data stored in the memory 620. Optionally, the processor 610 can be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), and programmable logic array (Programmable Logic Array, PLA). The processor 610 can integrate one or a combination of a central processing unit (Central Processing Unit, CPU), a graphics processing unit (Graphics Processing Unit, GPU) and a modem. Among them, the CPU mainly processes the operating system, user interface and application programs; the GPU is responsible for rendering and drawing display content; and the modem is used to process wireless communications. It can be understood that the above-mentioned modem may not be integrated into the processor 610, but may be implemented separately through a communication chip.

[0094] The memory 620 may include a random access memory (RAM) or a read-only memory (ROM). The memory 620 may be used to store instructions, programs, codes, code sets or instruction sets. The memory 620 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above-mentioned various method embodiments, etc. The data storage area may also store data created by the electronic device 600 during use, etc.

[0095] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0096] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram and the combination of processes and / or blocks in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the process in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0097] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0098] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit its protection scope. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the field should understand that after reading the present invention, those skilled in the art can still make various changes, modifications or equivalent substitutions to the specific implementation methods of the invention, but these changes, modifications or equivalent substitutions are all within the protection scope of the pending claims of the invention.

[0100] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0101] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A chip testing method, comprising: Obtaining an original test vector file of the chip under test, wherein the original test vector file includes timing waveform data of a JTAG interface and timing waveform data of a function clock interface; Modifying each timing waveform data of the JTAG interface so that the duration of the waveform corresponding to each timing waveform data of the JTAG interface is extended to N times the original duration, thereby obtaining a transformed test vector file; the original duration is equal to the period corresponding to the highest effective frequency of the function clock interface, and N is equal to the ratio of the highest effective frequency of the function clock interface to the highest effective frequency of the JTAG interface; Using the transformed test vector file to test the chip under test; The original test vector file includes multiple lines of test vectors and multiple lines of notes; the method further includes: traversing the notes of the original test vector file, and determining whether each line of notes traversed includes a preset starting position; the preset starting position is used to represent: the starting point of the timing waveform data of the JTAG interface in the original test vector file; The modifying of each timing waveform data of the JTAG interface comprises: After determining the remark including the preset starting position, the next line of the remark is used as the starting point, and the remaining lines of the original test vector file are traversed. For each line of the test vector traversed, the timing waveform data of the JTAG interface in each line of the test vector is modified until the remark including the preset end position is traversed; the preset end position is used to represent: the end point of the timing waveform data of the JTAG interface in the original test vector file; the timing waveform data of the JTAG interface includes the timing waveform data of the TCK pin, and the timing waveform of the TCK pin is a pulse waveform; The step of modifying the timing waveform data of the JTAG interface in each row of the test vectors traversed includes: For each row of test vectors traversed, each row of test vectors is transformed into N rows of test vectors; in the first N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 0, and in the last N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 1; or, in the first N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 1, and in the last N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 0.

2. According to the method described in claim 1, the timing waveform data of the JTAG interface also includes the timing waveform data of at least one of the three pins TDI, TDO and TMS, and the timing waveform data of TDI, TDO or TMS is a binary number; in each row of the test vectors in the N rows of test vectors, the timing waveform data of TDI, TDO or TMS is an original binary number.

3. According to the method of claim 1, the timing waveform data of the function clock interface is pulse data; in each row of the test vectors in the N rows of test vectors, the timing waveform data of the function clock interface is pulse data.

4. According to the method described in claim 1, the original test vector file also includes timing waveform data of other interfaces, and the other interfaces are interfaces other than the JTAG interface and the function clock interface, and the timing waveform data of the other interfaces are binary numbers; in each line of the test vectors in the N lines of test vectors, the timing waveform data of the other interfaces are original binary numbers.

5. The method according to any one of claims 1 to 4, wherein the step of testing the chip under test using the transformed test vector file comprises: Inputting the clock configuration file and the transformed test vector file into a chip testing device to test the chip under test; The clock configuration file includes the clock frequency of the JTAG interface and the clock frequency of the function clock interface, and the clock frequency of the JTAG interface and the clock frequency of the function clock interface are both equal to the highest valid frequency of the functionclock interface.

6. A chip testing device, comprising: A file acquisition module, used to obtain the original test vector file of the chip under test, wherein the original test vector file includes the timing waveform data of the JTAG interface and the timing waveform data of the function clock interface; A duration extension module, used for modifying each timing waveform data of the JTAG interface so that the duration of the waveform corresponding to each timing waveform data of the JTAG interface is extended to N times of the original duration, thereby obtaining a transformed test vector file; the original duration is equal to the period corresponding to the highest effective frequency of the function clock interface, and N is equal to the ratio of the highest effective frequency of the function clock interface to the highest effective frequency of the JTAG interface; A chip testing module, used for testing the chip under test using the transformed test vector file; The original test vector file includes multiple lines of test vectors and multiple lines of notes; the device also includes: a starting position determination module; The starting position determination module is used to traverse the notes of the original test vector file to determine whether each line of the traversed notes includes a preset starting position; the preset starting position is used to represent: the starting point of the timing waveform data of the JTAG interface in the original test vector file; The duration extension module is specifically used for: after determining the remark including the preset starting position, taking the next line of the remark as the starting point, traversing the remaining lines of the original test vector file, and for each line of the test vector traversed, modifying the timing waveform data of the JTAG interface in each line of the test vector until traversing to the remark including the preset end position; the preset end position is used to represent: the end point of the timing waveform data of the JTAG interface in the original test vector file; The timing waveform data of the JTAG interface includes the timing waveform data of the TCK pin, and the timing waveform of the TCK pin is a pulse waveform; The duration extension module is specifically used for: for each row of test vectors traversed, transforming each row of test vectors into N rows of test vectors; in the first N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 0, and in the last N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 1; or, in the first N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 1, and in the last N / 2 rows of test vectors of the N rows of test vectors, the timing waveform data of the TCK pin in each row of test vectors is 0.

7. According to the device of claim 6, the timing waveform data of the JTAG interface also includes the timing waveform data of at least one of the three pins TDI, TDO and TMS, and the timing waveform data of TDI, TDO or TMS is a binary number; in each line of the test vectors in the N lines of test vectors, the timing waveform data of TDI, TDO or TMS is an original binary number.

8. According to the device of claim 6, the timing waveform data of the function clock interface is pulse data; in each row of the test vectors in the N rows of test vectors, the timing waveform data of the function clock interface is pulse data.

9. According to the device according to claim 6, the original test vector file also includes timing waveform data of other interfaces, the other interfaces are interfaces other than the JTAG interface and the function clock interface, and the timing waveform data of the other interfaces are binary numbers; in each line of the test vectors in the N lines of test vectors, the timing waveform data of the other interfaces are original binary numbers.

10. According to the device described in any one of claims 6 or 9, the chip test module body is specifically used to: input the clock configuration file and the transformed test vector file into the chip testing equipment to test the chip under test; the clock configuration file includes the clock frequency of the JTAG interface and the clock frequency of the function clock interface, and the clock frequency of the JTAG interface and the clock frequency of the function clock interface are both equal to the highest effective frequency of the function clock interface.

11. An electronic device, comprising: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via the bus, and when the machine-readable instructions are executed by the processor, the method according to any one of claims 1 to 5 is implemented.

12. A storage medium having a computer program stored thereon, wherein the computer program implements the method according to any one of claims 1 to 5 when executed by a processor.

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