Calibration method and calibration processing device for time interval measurement circuit

Abstract

The application provides a calibration method and a calibration processing device for a time interval measurement circuit. The calibration method comprises: Lth calibration of a first stage TDC circuit, which comprises: multiple times of determination of one or more first delay timers and corresponding second delay timers as to-be-calibrated first delay timers and to-be-calibrated second delay timers; wherein, each time of determination of the to-be-calibrated first delay timers is one more than the last time of determination of the to-be-calibrated first delay timers; in the case that the to-be-calibrated first delay timers and the to-be-calibrated second delay timers form a vernier introduced vernier delay difference, inputting calibration pulses to the first ring delay chain and the second ring delay chain, and based on preset fixed time, calibration of actual delay difference between the to-be-calibrated first delay timers and the to-be-calibrated second delay timers is determined based on calibration time count information output by the first counter and the second counter.

Description

Technical Field

[0001] This invention relates to the field of time interval measurement, and more particularly to a calibration method and calibration processing device for a time interval measurement circuit. Background Technology

[0002] A time interval measurement circuit can be understood as a circuit used to measure the time interval between a start signal and a stop signal, and may include a Time-to-Digital Converter (TDC) circuit. The Time-to-Digital Converter (TDC) can be understood as any circuit capable of detecting the time interval between the input start signal and the received signal, which can be generated based on the rising and falling edges of a trigger pulse.

[0003] Before using the time interval measurement circuit, it needs to be calibrated. During the calibration process, usually only the delay of the delay circuit in the delay circuit is calibrated. However, in some time interval measurement circuits, a vernier delay control mechanism is introduced into the TDC circuit. Vernier delay control will bring a large delay. In the existing technology, there is no solution to calibrate the delay caused by the vernier. Summary of the Invention

[0004] This invention provides a calibration method and calibration processing device for a time interval measurement circuit to solve the problem of lacking a solution for calibrating the delay caused by the vernier.

[0005] According to a first aspect of the present invention, a calibration method for a time interval measurement circuit is provided.

[0006] The time interval measurement circuit includes a first-stage TDC circuit;

[0007] The first-stage TDC circuit includes a first ring delay chain, a second ring delay chain, a first counter, and a second counter; the first ring delay chain includes N first delay units connected in a ring, and the second ring delay chain includes N second delay units connected in a ring; the first timer and the second counter are used to count the number of signal transmission cycles of the first ring delay chain and the second ring delay chain, respectively, and output the corresponding count information; where N is an integer greater than or equal to 1;

[0008] The calibration method includes: performing at least one calibration on the first-stage TDC circuit; wherein the Lth calibration of the first-stage TDC circuit includes:

[0009] One or more first delay units and their corresponding second delay units are repeatedly identified as the first delay unit to be calibrated and the second delay unit to be calibrated; wherein, each time the first delay unit to be calibrated is identified, there is one more first delay unit to be calibrated than the previous one;

[0010] Each time the first delay unit to be calibrated and the second delay unit to be calibrated are determined, a calibration pulse is input to the first circular delay chain and the second circular delay chain when a vernier delay difference is formed between the first delay unit to be calibrated and the second delay unit to be calibrated. Based on the calibration count information output by the first counter and the second counter within a preset fixed time, the actual delay difference introduced by the vernier between the first delay unit to be calibrated and the second delay unit to be calibrated is calibrated and determined.

[0011] Where L is an integer greater than or equal to 1.

[0012] Optionally, based on the calibration count information output by the first counter and the second counter within a preset fixed time period, the actual delay difference introduced by the vernier between the first delay unit to be calibrated and the second delay unit to be calibrated is determined, including:

[0013] Obtain the first count information during calibration output from the first counter, and the second count information during calibration output from the second counter;

[0014] The reciprocal of the first count information is used as the first oscillation period, and the reciprocal of the second count information is used as the second oscillation period;

[0015] The difference between the first oscillation period and the second oscillation period is calculated as the actual delay difference.

[0016] Optionally, the first-stage TDC circuit further includes N first arbitrators, each of which is used to compare the phase sequence of the signals transmitted by the corresponding first delay and second delay to obtain the corresponding comparison information;

[0017] The calibration of the first-stage TDC circuit at least once also includes a Jth calibration, which includes:

[0018] When the first ring delay chain and the second ring delay chain are configured to theoretically perform the same delay, and a first calibration signal with a phase difference of 0 is input to the first ring delay chain and the second ring delay chain, the first-stage TDC circuit is calibrated based on the first comparison information output by the first arbitrator.

[0019] Optionally, the first comparison information output by the first arbitrator is:

[0020] The first level indicates that the phase of the signal transmitted by the corresponding first delay unit leads that of the corresponding second delay unit; or:

[0021] The second level indicates that the phase of the signal transmitted by the corresponding first delay unit lags behind that of the corresponding second delay unit;

[0022] Based on the first comparison information output by the first arbitrator, the first-stage TDC circuit is calibrated, including:

[0023] For any k-th first arbiter, the average level of the first comparison information output by the k-th first arbiter is controlled to match the average level of the first level and the second level by adjusting the delay implemented by the corresponding k-th first delay and the k-th second delay.

[0024] Optionally, the time interval measurement circuit further includes a second-stage TDC circuit;

[0025] The second-stage TDC circuit includes: a first delay line, a second delay line, and M second arbitrators. The first delay line includes M third delay units connected in sequence, and the second delay line includes M fourth delay units connected in sequence. Each second arbitrator is used to compare the phase relationship between the signals transmitted by the corresponding third delay unit and the fourth delay unit to obtain the corresponding comparison information. M is an integer greater than or equal to 1.

[0026] The calibration method includes:

[0027] Perform at least one calibration on the second-stage TDC circuit, wherein one calibration of the second-stage TDC circuit includes:

[0028] When the first delay line and the second delay line are configured to theoretically perform the same delay, and a second calibration signal with a phase difference of 0 is input to the first delay line and the second delay line, the first-stage TDC circuit is calibrated based on the second comparison information output by the second arbitrator.

[0029] Optionally, the second comparison information is:

[0030] The third level indicates that the phase of the signal transmitted by the corresponding third delay unit leads that of the corresponding fourth delay unit; or:

[0031] The fourth level indicates that the phase of the signal transmitted by the corresponding third delay unit lags behind that of the corresponding fourth delay unit;

[0032] Based on the second comparison information output by the second arbitrator, the second-stage TDC circuit is calibrated, including:

[0033] For any i-th second arbiter, the average level of the second comparison information output by the i-th second arbiter is controlled to match the average level of the third level and the fourth level by adjusting the delay implemented by the corresponding i-th third delay and i-th fourth delay.

[0034] Optionally, each of the delay units includes a signal transmission unit and a vernier delay control unit;

[0035] The signal transmission unit of any delay unit is connected to the signal transmission units of one or two adjacent delay units to perform the transmission of the corresponding signal; the one or two adjacent delay units include: the delay unit before and / or the delay unit after any delay unit.

[0036] The vernier delay control unit of any delay unit is connected to the signal transmission unit of any delay unit, and is used to control whether a vernier delay difference caused by the vernier occurs between the two delay lines or between the two ring delay chains. Optionally, the signal transmission unit includes a cascaded first inverter and a second inverter, and the vernier delay control unit includes a first transistor and a second transistor;

[0037] The input terminal of the first inverter in any delay unit is connected to the output terminal of the second inverter in the previous delay unit, the input terminal of the second inverter in any delay unit is connected to the output terminal of the first inverter in any delay unit, and the output terminal of the second inverter in any delay unit is connected to the input terminal of the first inverter in the next delay unit.

[0038] In any of the delay circuits, the input terminal of the second inverter is also connected to the control terminal of the first transistor, the first terminal of the first transistor is connected to the output terminal of the second inverter, the second terminal of the first transistor is connected to the first terminal of the second transistor, and the second terminal of the second transistor is grounded.

[0039] The signal connected to the control terminal of the second transistor in any of the delay units is used to determine whether a vernier delay difference caused by the vernier is formed.

[0040] Optionally, each of the delay units also includes a delay calibration unit;

[0041] The delay calibration unit includes a plurality of transistors connected in parallel. The plurality of transistors connected in parallel are connected to the power supply terminal of the first inverter. The plurality of transistors connected in parallel are configured to be selectively turned on to control the delay implemented by the corresponding delay unit.

[0042] According to a second aspect of the invention, a calibration processing apparatus is provided for performing a calibration method for a time interval measurement circuit as described in the first aspect and its alternatives.

[0043] In the calibration method and calibration processing device for the time interval measurement circuit provided by the present invention, after determining the first delay unit and the second delay unit to be calibrated each time, when the first delay unit and the second delay unit to be calibrated form a vernier delay difference introduced by the vernier, a calibration pulse is input to the first circular delay chain and the second circular delay chain. Based on the calibration count information output by the first counter and the second counter within a preset fixed time, the actual delay difference introduced by the vernier between the first delay unit and the second delay unit to be calibrated is calibrated and determined. Thus, the delay difference introduced by the vernier can be accurately calibrated, avoiding the mismatch of the delay unit itself from affecting the time interval measurement, and providing a sufficient and reliable basis for the calculation of the time interval when actually using the TDC circuit. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a schematic diagram of the construction of the first-stage TDC circuit of the time interval measurement circuit in one embodiment of the present invention;

[0046] Figure 2 This is a schematic diagram of the construction of the second-stage TDC circuit of the time interval measurement circuit in one embodiment of the present invention;

[0047] Figure 3 This is a circuit diagram of the first-stage TDC circuit of the time interval measurement circuit in one embodiment of the present invention;

[0048] Figure 4 This is a circuit diagram of the second-stage TDC circuit of the time interval measurement circuit in one embodiment of the present invention;

[0049] Figure 5 This is a schematic diagram of the time interval measurement circuit in one embodiment of the present invention;

[0050] Figure 6 This is a flowchart illustrating the calibration method of the time interval measurement circuit in one embodiment of the present invention. Figure 1 ;

[0051] Figure 7 This is a flowchart illustrating step S103 in one embodiment of the present invention;

[0052] Figure 8This is a flowchart illustrating the calibration method of the time interval measurement circuit in one embodiment of the present invention. Figure 2 . Detailed Implementation

[0053] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0054] In the description of this invention, it should be understood that the terms "upper part", "lower part", "upper end", "lower end", "lower surface", "upper surface", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention.

[0055] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0056] In the description of this invention, "a plurality of" means multiple, such as two, three, four, etc., unless otherwise explicitly specified.

[0057] In the description of this invention, unless otherwise explicitly specified and limited, the term "connection" and other such terms should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral connection; it can refer to a mechanical connection, an electrical connection, or a connection that allows communication between the components; it can refer to a direct connection or an indirect connection through an intermediate medium; it can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0058] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0059] Please refer to Figure 1 To facilitate understanding of the calibration method for the time interval measurement circuit provided in the embodiments of the present invention, the various optional schemes for the time interval measurement circuit will be described in detail below.

[0060] The time interval measurement circuit includes a first-stage TDC circuit 100;

[0061] The first-stage TDC circuit includes a first ring delay chain, a second ring delay chain, a first counter 1, and a second counter 2.

[0062] The first ring delay chain includes N first delay units 3 connected in a ring, and the second ring delay chain includes N second delay units 4 connected in a ring.

[0063] The first timer 1 and the second counter 2 are used to count the number of signal transmission cycles of the first and second circular delay chains, respectively, and output the corresponding count information; where N is an integer greater than or equal to 1.

[0064] Please combine Figure 1 , Figure 3 and Figure 5 The first counter 1 and the second counter 2 can both be connected to the processing module 9. The processing module can be any circuit module capable of data processing, such as an MCU, CPU, logic processing module, digital circuit, digital logic circuit, etc. In addition, the processing module 9 can include a processing unit, and the arbitrator and timer of the first-level TDC circuit and the arbitrator of the second-level TDC circuit can be connected to the same processing unit. In other examples, the processing module 9 can include two processing units, and the arbitrator and timer of the first-level TDC circuit can be connected to one processing unit, and the arbitrator of the second-level TDC circuit can be connected to another processing unit.

[0065] Furthermore, the calibration processing device used to perform the calibration method can be the processing module 9, or other circuit modules or devices. The calibration processing device can also be directly or indirectly connected to the input terminals of the first delay line, the second delay line, the first ring delay chain, and the second ring delay chain (which can be understood as the input terminals of the first first delay unit, the first second delay unit, the first third delay unit, and the first fourth delay unit) to realize the output of the corresponding calibration signal and calibration pulse. Specifically, the calibration processing device can directly output the calibration signal and calibration pulse, or control other devices (such as margin calculation circuit, signal generation circuit, etc.) to generate the calibration signal and calibration pulse.

[0066] For specific examples, please refer to Figure 1 , Figure 3 and Figure 5 The first-stage TDC circuit 100 further includes N first arbitrators 7, each of which is used to compare the phase order of the signals transmitted by the corresponding first delay and second delay to obtain the corresponding comparison information.

[0067] Each first arbitrator 7 is connected to a first delay 3 and a second delay 4. Thus, each first arbitrator 7 corresponds to the first delay 3 and the second delay 4 connected to it, and the first delay 3 and the second delay 4 connected to the same first arbitrator 7 are corresponding to each other.

[0068] The first arbiter 7 can be connected to the processing module and calibration processing equipment, thereby enabling them to obtain the corresponding comparison information output by the first arbiter 7.

[0069] The first delay unit 3 and the second delay unit 4 connected to the first arbiter 7 are in the same order in the corresponding circular delay chain; the order refers to the arrangement order of the delay unit from the first delay unit to the last delay unit in a single cycle of the corresponding circular delay chain.

[0070] The first comparison information output by the first arbitrator 7 is:

[0071] The first level indicates that the phase of the signal transmitted by the corresponding first delay unit leads that of the corresponding second delay unit; or:

[0072] The second level indicates that the phase of the signal transmitted by the corresponding first delay unit lags behind that of the corresponding second delay unit;

[0073] If the first level is high, then the second level is low; if the first level is low, then the second level is high.

[0074] When using the first-stage TDC circuit, the start signal (e.g., a start signal) is input to the first circular delay chain, and the end signal (e.g., a stop signal) is input to the second circular delay chain. Given the cursor delay difference between the two circular delay chains, initially, each of the first arbitrators 7 will determine that the end signal transmitted in the second circular delay chain lags behind the start signal transmitted in the first circular delay chain. Due to the cursor delay difference, the transmission speed of the second circular delay chain is faster than that of the first circular delay chain. As transmission continues, one of the first arbitrators 7 will determine that the second circular delay chain... The end signal transmitted in the time chain precedes the start signal. Therefore, based on the output of the first arbitrator 7, it can be determined which first delay units 3 and second delay units 4 the start and end signals have passed through. Based on the delay units passed through, the actual delay difference between each pair of first delay units 3 and second delay units 4, and the counting results of the first counter 1 and the second counter 2, the time interval information between the start and end signals can be calculated. For example, the time that the start signal and / or end signal has been transmitted at this time can be calculated first, and the time interval information between the start and end signals can be deduced accordingly.

[0075] To ensure that the first-stage TDC circuit can meet the above requirements, the first-stage TDC circuit needs to be calibrated. The calibration requirements may include at least one of the following:

[0076] Requirement a: To calibrate the actual delay difference caused by the vernier between each pair of first and second delay units (which can be understood as vernier delay difference);

[0077] Requirement b: Calibrate the first and second circular delay chains so that, when no delay difference caused by the vernier is formed, the delays of the two circular delay chains are the same or similar.

[0078] The specific scheme of the calibration method in this embodiment of the invention can meet the above requirements, for example, Figures 6 to 8 Steps S101 to S103 can satisfy requirement a. Figure 6 , Figure 8 Step S105 in the above process can satisfy requirement b. In addition to the above requirements, any calibration means implemented in the art based on any other calibration requirements can also be used as an optional solution in the embodiments of the present invention.

[0079] Please refer to Figure 2 , Figure 4 and Figure 5 The time interval measurement circuit further includes: a second-stage TDC circuit;

[0080] The second-stage TDC circuit includes: a first delay line, a second delay line, and M second arbitrators. The first delay line includes M third delay units 5 connected in sequence, and the second delay line includes M fourth delay units 6 connected in sequence. Each second arbitrator 8 is used to compare the phase relationship between the signals transmitted by the corresponding third delay unit 5 and the fourth delay unit 6 to obtain the corresponding comparison information. Here, M is an integer greater than or equal to 1.

[0081] Each second arbitrator 8 is connected to a third delay 5 and a fourth delay 6. Thus, each second arbitrator 8 corresponds to the third delay 5 and the fourth delay 6 connected to it, and the third delay 5 and the fourth delay 6 connected to the same second arbitrator 8 are corresponding to each other.

[0082] The second arbitrator 8 can be connected to the processing module and calibration processing equipment, thereby enabling them to obtain the corresponding comparison information output by the second arbitrator 8.

[0083] The third delay unit 5 and the fourth delay unit 6 connected to the second arbitrator 8 are in the same order in the corresponding delay line; the order refers to the arrangement order of the delay unit from the first delay unit to the last delay unit in the corresponding delay line.

[0084] The second comparison information output by the second arbitrator 8 is:

[0085] The third level indicates that the phase of the signal transmitted by the corresponding third delay unit leads that of the corresponding fourth delay unit; or:

[0086] The fourth level indicates that the phase of the signal transmitted by the corresponding third delay unit lags behind that of the corresponding fourth delay unit;

[0087] If the third level is high, then the fourth level is low; if the third level is low, then the fourth level is high.

[0088] When using the second-stage TDC circuit, the start signal (e.g., start) res The signal is input to the first delay line, and the end signal (e.g., stop) is input to the first delay line. res When the signal is input to the second delay line, and the two delay lines form a vernier delay difference caused by the vernier, initially, each second arbitrator 8 will determine that the end signal transmitted in the second delay line lags behind the start signal transmitted in the first delay line. Due to the existence of the vernier delay difference, the transmission speed of the second delay line is faster than that of the first delay line. As transmission continues, the second arbitrator 8 will determine that the end signal transmitted in the second delay line leads the start signal. Therefore, based on the output of the second arbitrator 8, it can be determined which third delay units 5 and fourth delay units 6 the start and end signals have passed through. Based on the delay units passed through and the actual delay difference between each pair of third delay units 5 and fourth delay units 6, the time interval information between the start and end signals can be calculated. For example, the transmission time of the start signal and / or end signal at this time can be calculated first, and the time interval information between the start and end signals can be deduced accordingly.

[0089] To ensure that the second-stage TDC circuit can meet the above requirements, the second-stage TDC circuit needs to be calibrated. The calibration requirements may include at least one of the following:

[0090] Requirement c: calibrate the actual delay difference caused by the vernier between each pair of first and second delay units (which can be understood as vernier delay difference);

[0091] Requirement d: Calibrate the first delay line and the second delay line so that, when no delay difference caused by the vernier is formed, the delay of the two delay lines is the same or similar.

[0092] In a specific embodiment of the calibration method of the present invention, for example, Figure 8 Step S105 can satisfy requirement d. In other examples, similar steps S101 to S103 can also be introduced to satisfy requirement c. In addition to the above requirements, calibration methods implemented in the art based on any other calibration requirements can also be used as an optional solution in the embodiments of the present invention.

[0093] Furthermore, in a specific example, when actually using the first-stage TDC circuit and the second-stage TDC circuit, the start signal input to the first-stage TDC circuit can be the start signal of the TDC, and the end signal input to the first-stage TDC circuit can be the stop signal of the TDC.

[0094] The start signal input to the second-stage TDC circuit can be start res The signal ANDed with the second-stage TDC circuit can be the stop signal. res The signal, calculated based on the second-stage TDC circuit, is the start signal. res Signal and the stop res The time interval information between signals can be used as the final time interval information between the start signal and the stop signal, where the start signal... res Signals and Stop res The time interval of the signal is matched with the current time interval information determined by the first-stage TDC circuit.

[0095] by Figure 5 For example, the second-stage TDC circuit is used to obtain the start... res Signals and Stop res Signal, and determine the start res Signal and the stop res The time interval information between the signals is determined, and then, based on this time interval information and the current time interval information determined by the first-stage TDC circuit, the final time interval information between the start signal and the stop signal is determined. res Signals and Stop res The time interval of the signal is matched to the time interval between the start signal and the end signal output by the first-stage TDC circuit after the cyclic transmission stops.

[0096] by Figure 5 For example, the signal output circuit 8 can be controlled by the processing module 9 (or the signal output circuit 10 can be directly output without being controlled by the processing module 5) to start. res Signals and Stop res The signal, in this field, achieves margin calculation between two stages of TDC circuitry to output the start signal. res Signals and Stop res Any of the signal schemes can be considered as options for the signal output circuit 8. In a specific example, the signal output circuit 10 can also be connected to the output terminals of two ring delay chains, thereby acquiring the signals output from the output terminals of the two ring delay chains after the cyclic transmission stops.

[0097] In one example, the signal transmitting circuit 10 may only perform the function of signal transmission, while in other examples, the signal transmitting circuit 10 may also perform functions such as amplification and adjustment of the time interval.

[0098] For specific examples, please refer to Figures 1 to 4 The first delay unit 3, the second delay unit 4, the fourth delay unit 5, and the fifth delay unit 6 each include a signal transmission module (e.g., signal transmission module 32 in the first delay unit 3, signal transmission module 42 in the second delay unit 40, and signal transmission module 52 in the third delay unit 5) and a vernier delay control module (e.g., vernier delay control module 33 in the first delay unit 3, vernier delay control module 43 in the second delay unit 4, vernier delay control module 53 in the third delay unit 5, and vernier delay control module 53 in the fourth delay unit 5).

[0099] The signal transmission module of any delay unit is connected between the signal transmission modules of one or two adjacent delay units to perform the transmission of the corresponding signal; the previous delay unit and / or the next delay unit of any delay unit;

[0100] Specifically, for a circular delay chain, if the first delay unit is any of the aforementioned delay units, the previous delay unit is the last delay unit, and the next delay unit is the second delay unit. If the last delay unit is any of the aforementioned delay units, the previous delay unit is the second-to-last delay unit, and the next delay unit is the first delay unit. If a delay unit that is neither the last nor the first is any of the aforementioned delay units, the previous delay unit and the next delay unit are the preceding and following delay units in the signal transmission direction.

[0101] As can be seen, the signal transmission module is responsible for transmitting the input signals when the TDC is working.

[0102] For a specific example, please refer to Figure 3 and Figure 4 The signal transmission module includes a cascaded first inverter and a second inverter.

[0103] The first inverter can be, for example, Figure 3 The first inverter formed by transistors M1 and M2 shown can also be, for example... Figure 3 The first inverter formed by transistors M4 and M5 shown; or, for example... Figure 4 The first inverter formed by transistors M7 and M8 shown in the figure Figure 4 The first inverter is formed by transistors M10 and M11 shown.

[0104] The second inverter can be, for example, Figure 3The second inverter X1 shown can also be, for example, Figure 3 The second inverter X2 shown; may also be, for example Figure 4 The second inverter X3 shown is Figure 4 The second inverter X4 shown;

[0105] The input terminal of the first inverter in any delay unit is connected to the output terminal of the second inverter in the previous delay unit, the input terminal of the second inverter in any delay unit is connected to the output terminal of the first inverter in any delay unit, and the output terminal of the second inverter in any delay unit is connected to the input terminal of the first inverter in the next delay unit.

[0106] In this circuit, the first terminal of transistor M1 (and transistors M4, M7, and M10) is directly or indirectly connected to the power supply terminal; the second terminal of transistor M1 (and transistors M4, M7, and M10) is connected to the first terminal of transistor M2 (and transistors M5, M8, and M11); the second terminal of transistor M2 (and transistors M5, M8, and M11) is directly or indirectly grounded; and the control terminal (e.g., the gate) of transistor M1 (and transistors M4, M7, and M10) is directly or indirectly connected to the output terminal of the second inverter (e.g., second inverter X1, second inverter X2, second inverter X3, and second inverter X4) of the previous delay circuit.

[0107] The second inverter can be constructed in the same or similar way as the first inverter, or it can be different. The second inverter can also be implemented using a NOT gate.

[0108] Correspondingly, the arbitrator is connected to the output of the first inverter in the corresponding delay unit;

[0109] When determining phase comparison information, the arbitrator is specifically used to: determine the corresponding comparison information by comparing the signals output by the first inverters of the two connected delay units.

[0110] In addition, the signal transmission module may also include a ground control transistor (e.g., ground control transistor M3 in the first delay 3, ground control transistor M6 in the second delay 4, ground control transistor M9 in the third delay 5, and ground control transistor M12 in the fourth delay 6), which can be connected between the first inverter and ground to realize the ground control of the first inverter.

[0111] The vernier delay control module of any delay unit is connected to the signal transmission module of any delay unit. The connection method can vary based on the functional implementation of the vernier delay control module. The vernier delay control module of any delay unit is used to control whether a delay difference is generated between the first circular delay chain and the second circular delay chain.

[0112] For example, the vernier delay control units of the first and second delay units can control whether the first and second circular delay chains form a vernier delay difference caused by the vernier at the corresponding delay units, and the vernier delay control units of the third and fourth delay units can control whether the first and second delay lines form a vernier delay difference caused by the vernier at the corresponding delay units.

[0113] In a specific example, the vernier delay control module includes a first transistor (e.g., the first transistor Q1 of the vernier delay control module 33 in the first delayer 3, the first transistor Q3 of the vernier delay control module 43 in the second delayer 4, the first transistor Q5 of the vernier delay control module 53 in the third delayer 5, and the first transistor Q7 of the vernier delay control module 63 in the fourth delayer 6) and a second transistor (e.g., the second transistor Q2 of the vernier delay control module 33 in the first delayer 30, the second transistor Q4 of the vernier delay control module 43 in the second delayer 40, the second transistor Q6 of the vernier delay control module 53 in the third delayer 5, and the second transistor Q8 of the vernier delay control module 63 in the fourth delayer 6).

[0114] In any of the delay units, the input terminal of the second inverter is also connected to the control terminal of the first transistor, the first terminal of the first transistor is connected to the output terminal of the second inverter, the second terminal of the first transistor is connected to the first terminal of the second transistor, and the second terminal of the second transistor is grounded.

[0115] The signal connected to the control terminal of the second transistor in any of the delayers is used to determine whether the delay difference is generated.

[0116] in:

[0117] If the signal connected to the control terminal of the second transistor in any k-th first delay unit is at the same level as the signal connected to the control terminal of the second transistor in the k-th second delay unit, then: the delay of the k-th first delay unit and the k-th second delay unit are theoretically the same;

[0118] If the signal connected to the control terminal of the second transistor in any k-th first delay unit is at a different level than the signal connected to the control terminal of the second transistor in the k-th second delay unit, then: the delay between the k-th first delay unit and the k-th second delay unit is theoretically a vernier delay difference (the actual delay difference needs to be calibrated and determined).

[0119] If the signal connected to the control terminal of the second transistor in any j-th third delay is at the same level as the signal connected to the control terminal of the second transistor in the j-th fourth delay, then: the delay of the j-th third delay is theoretically the same as that of the j-th fourth delay.

[0120] If the signal connected to the control terminal of the second transistor in any j-th third delay is at a different level than the signal connected to the control terminal of the second transistor in the j-th second delay, then: after calibration, the delay between the j-th first delay and the j-th second delay will theoretically be a vernier delay difference (the actual delay difference needs to be determined by calibration).

[0121] As can be seen, the vernier delay control module receives control signals (e.g., DCW, VDD) from the processing module (e.g., digital circuit) to control the delay difference between the two ring delay chains and the two delay lines. When the input levels of the vernier delay control modules of the two ring delay chains (or two delay lines) are the same, no vernier delay is introduced, and the delays of the two ring delay chains (or two delay lines) are theoretically the same. When the input levels of the vernier delay control modules of the two ring delay chains (or two delay lines) are different, a delay difference will be generated between the two ring delay chains (or two delay lines). This delay difference is the resolution of the vernier TDC, and the vernier TDC can work normally in this case.

[0122] Specifically, the delay difference generated in the first-stage TDC circuit can be understood as a relatively large delay difference. The corresponding delay difference in the second-stage circuit is relatively small, smaller than the delay difference in the first-stage TDC circuit. Therefore, the resolution of the vernier TDC implemented by the first-stage TDC circuit is smaller than the resolution of the vernier TDC implemented by the second-stage TDC circuit, thus meeting the requirements of coarse and fine TDC measurements.

[0123] In one implementation method, please refer to Figures 1 to 4 The first delay unit 3, the second delay unit 4, the third delay unit 5, and the fourth delay unit 6 all further include a delay calibration module (e.g., delay calibration module 31 in the first delay unit 3, delay calibration module 41 in the second delay unit 3, delay calibration module 51 in the third delay unit 5, and delay calibration module 61 in the fourth delay unit 6).

[0124] Please refer to Figure 3 , Figure 4The delay calibration module includes multiple transistors connected in parallel. These multiple transistors are connected to one end of the power supply terminal of the first inverter (e.g., the first terminals of transistors M1, M4, M7, and M3 in the first inverter). The multiple transistors connected in parallel (e.g., transistors S1, S2, S3, and S4) are configured to be selectively turned on to control the delay implemented by the corresponding delay unit.

[0125] As can be seen, the delay calibration module can be composed of several transistors of different sizes connected in parallel. The delay of the delay circuit can be controlled by controlling the on and off states of the transistors. This module receives a calibration signal from the control module (e.g., a digital circuit) and calibrates the delay of the delay circuit so that, when DCW and VDD are the same, the delays of the upper and lower delay chains are equal.

[0126] Regarding the time interval measurement circuit mentioned above, embodiments of the present invention provide a calibration method for the time interval measurement circuit, including...

[0127] Perform at least one calibration on the first-stage TDC circuit;

[0128] Please refer to the following: Figure 6 The Lth calibration of the first-stage TDC circuit includes:

[0129] S101: Determine one or more first delay units and their corresponding second delay units as first delay units and second delay units to be calibrated, such that: the first delay units to be calibrated determined this time are one more than the first delay units to be calibrated determined in the previous time.

[0130] S102: When the first delay unit to be calibrated and the second delay unit to be calibrated form a vernier delay difference introduced by the vernier, a calibration pulse is input to the first circular delay chain and the second circular delay chain;

[0131] S103: Based on the calibration count information output by the first counter and the second counter within a preset fixed time period, calibrate and determine the actual delay difference introduced by the vernier between the first delay unit to be calibrated and the second delay unit to be calibrated.

[0132] After step S103, you can return to step S101. If a first delay unit and a second delay unit are added, redetermine the first delay unit and the third delay unit to be calibrated, and then repeat steps S102 and S103. Repeat this process until the first delay unit and the second delay unit to be calibrated determined in step S101 are all the first delay units and second delay units.

[0133] As can be seen, through the above loop, one or more first delay units and their corresponding second delay units can be determined multiple times as the first delay unit to be calibrated and the second delay unit to be calibrated; wherein, each time the first delay unit to be calibrated is determined by one more than the first delay unit to be calibrated determined in the previous time; after each determination of the first delay unit to be calibrated and the second delay unit to be calibrated, steps S102 and S103 are implemented.

[0134] Where L is an integer greater than or equal to 1.

[0135] The situation where a vernier delay difference is introduced can be understood as follows: as long as the circuit can form any circuit state that generates the vernier delay difference, the first-stage TDC circuit can enter the circuit state that generates the vernier delay difference under the control of the calibration processing equipment (such as a processing module or other equipment, specifically a digital processing circuit). Manual control or control via external signals to generate the vernier delay difference is also possible. Specifically, this can be achieved by controlling the vernier delay control unit in the delay unit.

[0136] The actual delay difference can also be understood as the actual value of the vernier delay difference.

[0137] In one implementation method, please refer to Figure 7 Step S103 may include:

[0138] S1031: Obtain the first count information during calibration output by the first counter, and the second count information during calibration output by the second counter;

[0139] S1032: Calculate the reciprocal of the first count information as the first oscillation period, and the reciprocal of the second count information as the second oscillation period;

[0140] S1033: Calculate the difference between the first oscillation period and the second oscillation period as the actual delay difference.

[0141] The above scheme can accurately calibrate the delay difference introduced by the vernier, avoiding the mismatch of the delay unit itself from affecting the time interval measurement, and providing a sufficient and reliable basis for calculating the time interval when actually using the TDC circuit. It can be seen that through this Lth calibration, the actual delay difference (which can be understood as the vernier delay difference) caused by the vernier can be calibrated between each pair of first and second delay units, providing a basis for the use of the first-stage TDC circuit.

[0142] Specific examples of steps S101 to S103 above may include:

[0143] 1. DCW1 The level is set to 0. DCW2——DCW8Set to high to introduce the delay difference of DCW1. At this time, the first delay unit of DCW1 and its corresponding second delay unit are to be calibrated. The difference in the period of the upper and lower circular delay chains is the vernier delay difference introduced by the vernier delay unit of the first delay unit and the second delay unit. This process can be understood as the process of forming the vernier delay difference introduced by the vernier introduced by the vernier after the completion of step S101 in the first loop.

[0144] 2. Input a pulse at the beginning of the two loops to make the two circular delay chains start oscillating. This process can be understood as the implementation process of step S102.

[0145] 3. Calculate the number of times the signal propagates in the upper and lower loops within a fixed time using the count values ​​of counters CNT1 and CNT2, and then calculate the oscillation period by taking the reciprocal of these counts; this process can be understood as the implementation of steps S1031 and S1032.

[0146] 4. The additional delay difference introduced by the first vernier delay unit is deduced from the difference in oscillation period. This value is the accurate LSB1 after calibration (i.e. the corresponding actual delay difference). This process can be understood as the implementation process of step S1033.

[0147] This completes the first loop. Then, we can return to step S301 and begin the second loop.

[0148] 5. Set DCW1-2 to 0. It can be seen that in the second cycle, the first delay unit to be calibrated includes not only the first delay unit of DCW1, but also the first delay unit of DCW2. At this time, the delay difference is the vernier delay difference introduced by DCW1 and DCW2. Repeat the above steps, and the difference of the periods obtained is the value of LSB1+LSB2, which is the corresponding actual delay difference.

[0149] Then, the second cycle can be completed.

[0150] 6. Set DCW1-3, 1-4...DCW1-8 to 0 in sequence to calculate the delay difference introduced by each vernier delay unit, and then the calibration is complete.

[0151] In one embodiment, at least one calibration of the first-stage TDC circuit further includes a Jth calibration, please refer to [reference needed]. Figure 8 This includes:

[0152] S105: When the first ring delay chain and the second ring delay chain are configured to theoretically perform the same delay, and a first calibration signal with a phase difference of 0 is input to the first ring delay chain and the second ring delay chain, the first-stage TDC circuit is calibrated based on the first comparison information output by the first arbitrator.

[0153] J can be any integer greater than or equal to 1.

[0154] In one example, J can be less than L. Therefore, for the first-stage TDC circuit, the calibration in step S105 is performed first, and then the calibration in steps S101 to S103 is performed in multiple cycles.

[0155] exist Figure 8 In the example shown, J is 1 and L is 2. Then, for the first-stage TDC circuit, the first calibration of the first-stage TDC circuit is achieved through step S105, and the second calibration of the first-stage TDC circuit is achieved through multiple cycles of steps S101 to S103.

[0156] In other examples, the order and content of calibration may not be limited to... Figure 8 As shown, other calibration processes can be performed between, before, and after the Jth calibration and the Lth calibration, without departing from the scope of the embodiments of the present invention.

[0157] The calibration of the first-stage TDC circuit based on the first comparison information output by the first arbitrator includes:

[0158] For any k-th first arbiter, the average level of the first comparison information output by the k-th first arbiter is controlled to match the average level of the first level and the second level by adjusting the delay implemented by the corresponding k-th first delay and the k-th second delay.

[0159] A specific example of step S105 may be as follows:

[0160] 1. Reset all first arbiters and change the control signal of the vernier delay control unit so that the two ring delay chains theoretically have the same delay.

[0161] 2. Input a set of calibration signals with a phase difference of 0 from the input terminals of the two ring delay chains.

[0162] 3. Determine the output level of the first arbiter. Theoretically, if there is no error caused by mismatch, the output level of the first arbiter should have the same probability of being high and low, meaning the average output level of the first arbiter should be the middle level. If there is an error, the output of the first arbiter will be biased towards either a high or low level.

[0163] 4. Adjust the delay of the delay unit by adjusting the input signal of the delay calibration unit according to the output result of the first arbitrator, so that it moves to a position that makes the average value of the first arbitrator output the middle level (which can be understood as the average value of the high level and the low level). After adjustment, the calibration signal can be input again to observe the output level of the arbitrator.

[0164] 5. Repeat the above steps until the average output level of the first arbiter is at the middle level. At this point, the calibration of this stage is complete.

[0165] 6. Repeat the above calibration algorithm to calibrate the 2nd, 3rd, 4th... on the delay chain in sequence, until the last delay timer connected to the first arbitrator and the second delay timer.

[0166] In one embodiment, the calibration method includes:

[0167] Perform at least one calibration on the second-stage TDC circuit, where please refer to... Figure 8 The first calibration of the second-stage TDC circuit includes:

[0168] S104: When the first delay line and the second delay line are configured to theoretically perform the same delay, and a second calibration signal with a phase difference of 0 is input to the first delay line and the second delay line, the first-stage TDC circuit is calibrated based on the second comparison information output by the second arbitrator.

[0169] exist Figure 8 In the example shown, step S104 can be implemented before step S105. In other examples, step S104 can also be implemented before or after any calibration of the first-stage TDC circuit, all of which do not depart from the scope of the embodiments of the present invention.

[0170] The calibration of the second-stage TDC circuit based on the second comparison information output by the second arbitrator may include:

[0171] For any i-th second arbiter, the average level of the second comparison information output by the i-th second arbiter is controlled to match the average level of the third level and the fourth level by adjusting the delay implemented by the corresponding i-th third delay and i-th fourth delay.

[0172] A specific example of step S104 may be as follows:

[0173] 1. Reset all second arbitrators and change the control signal of the vernier delay control unit so that the two ring delay chains theoretically have the same delay.

[0174] 2. Input a set of calibration signals with a phase difference of 0 from the input terminals of the two delay lines.

[0175] 3. Determine the output level of the first second arbitrator. Theoretically, if there is no error caused by mismatch, the output level of the second arbitrator should have the same probability of being high and low, meaning the average output level of the second arbitrator should be the middle level. If there is an error, the output of the second arbitrator will be biased towards either a high or low level.

[0176] 4. Adjust the delay of the delay unit by adjusting the input signal of the delay calibration unit according to the output result of the second arbitrator, so that it moves to a position that makes the average value of the second arbitrator output the middle level (which can be understood as the average value of the high level and the low level). After adjustment, the calibration signal can be input again to observe the output level of the arbitrator.

[0177] 5. Repeat the above steps until the average output level of the second arbitrator is at the middle level. At this point, the calibration of this stage is complete.

[0178] 6. Repeat the above calibration algorithm to calibrate the 2nd, 3rd, 4th... on the delay line in sequence, until the first delay and the second delay connected to the last second arbitrator.

[0179] Through the above steps S104, S105, and the loop of S101 to S103, in the specific scheme, the second calibration of the first-stage TDC circuit can more accurately calculate the specific value of the calibration delay difference introduced by each vernier delay unit. The signal link delay of the TDC is divided into two parts: the delay introduced by the signal transmission unit and the delay introduced by the vernier delay control unit. The mismatch caused by the signal transmission unit is calibrated in the first calibration of the first-stage TDC circuit and the calibration of the second-stage TDC circuit, while the nonlinear error introduced by the vernier delay control module is also calibrated in calibration step 3. Thus, all nonlinear errors are covered by the calibration steps. It can be seen that the specific scheme of the present invention is a complete processing procedure that can accurately calibrate all nonlinear errors of the TDC of this structure.

[0180] This invention also provides a calibration processing device for performing the calibration method of the time interval measurement circuit involved in the above optional schemes. It can be any device or combination of devices with data processing capabilities.

[0181] In the description of this specification, the references to terms such as "an embodiment," "an example," "a specific implementation process," and "an example" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0182] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A calibration method for a time interval measurement circuit, characterized in that, The time interval measurement circuit includes a first-stage TDC circuit; The first-stage TDC circuit includes a first ring delay chain, a second ring delay chain, a first counter, and a second counter; the first ring delay chain includes N first delay units connected in a ring, and the second ring delay chain includes N second delay units connected in a ring; the first timer and the second counter are used to count the number of signal transmission cycles of the first ring delay chain and the second ring delay chain, respectively, and output the corresponding counting information; Where N is an integer greater than or equal to 1; The calibration method includes: performing at least one calibration on the first-stage TDC circuit; wherein the Lth calibration of the first-stage TDC circuit includes: One or more first delay units and their corresponding second delay units are repeatedly identified as the first delay unit to be calibrated and the second delay unit to be calibrated; wherein, each time the first delay unit to be calibrated is identified, there is one more first delay unit to be calibrated than the previous one; Each time the first delay unit to be calibrated and the second delay unit to be calibrated are determined, a calibration pulse is input to the first circular delay chain and the second circular delay chain when a vernier delay difference is formed between the first delay unit to be calibrated and the second delay unit to be calibrated. Based on the calibration count information output by the first counter and the second counter within a preset fixed time, the actual delay difference introduced by the vernier between the first delay unit to be calibrated and the second delay unit to be calibrated is calibrated and determined. Where L is an integer greater than or equal to 1.

2. The calibration method for the time interval measurement circuit according to claim 1, characterized in that, Based on the calibration count information output by the first counter and the second counter within a preset fixed time period, the actual delay difference introduced by the vernier between the first delay unit to be calibrated and the second delay unit to be calibrated is determined, including: Obtain the first count information during calibration output from the first counter, and the second count information during calibration output from the second counter; The reciprocal of the first count information is used as the first oscillation period, and the reciprocal of the second count information is used as the second oscillation period; The difference between the first oscillation period and the second oscillation period is calculated as the actual delay difference.

3. The calibration method for the time interval measurement circuit according to claim 1, characterized in that, The first-stage TDC circuit also includes N first arbitrators, each of which is used to compare the phase order of the signals transmitted by the corresponding first delay and second delay to obtain the corresponding comparison information; The calibration of the first-stage TDC circuit at least once also includes a Jth calibration, which includes: When the first ring delay chain and the second ring delay chain are configured to theoretically perform the same delay, and a first calibration signal with a phase difference of 0 is input to the first ring delay chain and the second ring delay chain, the first-stage TDC circuit is calibrated based on the first comparison information output by the first arbitrator. J is an integer greater than or equal to 1, and J is less than L. The J-th calibration is performed before the L-th calibration.

4. The calibration method for the time interval measurement circuit according to claim 3, characterized in that, The first comparison information output by the first arbitrator is: The first level indicates that the phase of the signal transmitted by the corresponding first delay unit is ahead of the phase of the corresponding second delay unit; or: The second level indicates that the phase of the signal transmitted by the corresponding first delay unit lags behind that of the corresponding second delay unit; Based on the first comparison information output by the first arbitrator, the first-stage TDC circuit is calibrated, including: For any k-th first arbiter, the average level of the first comparison information output by the k-th first arbiter is controlled to match the average level of the first level and the second level by adjusting the delay implemented by the corresponding k-th first delay and the k-th second delay. k is an integer greater than or equal to 1 and less than or equal to N, where N is the number of first arbitrators. The kth first arbitrator corresponds to the kth first delay and the kth second delay.

5. The calibration method for the time interval measurement circuit according to claim 1, characterized in that, The time interval measurement circuit also includes a second-stage TDC circuit; The second-stage TDC circuit includes: a first delay line, a second delay line, and M second arbitrators. The first delay line includes M third delay units connected in sequence, and the second delay line includes M fourth delay units connected in sequence. Each second arbitrator is used to compare the phase relationship between the signals transmitted by the corresponding third delay unit and the fourth delay unit to obtain the corresponding comparison information. The calibration method includes: Perform at least one calibration on the second-stage TDC circuit, wherein one calibration of the second-stage TDC circuit includes: When the first delay line and the second delay line are configured to theoretically perform the same delay, and a second calibration signal with a phase difference of 0 is input to the first delay line and the second delay line, the first-stage TDC circuit is calibrated based on the second comparison information output by the second arbitrator.

6. The calibration method for the time interval measurement circuit according to claim 5, characterized in that, The second comparison information is: The third level indicates that the phase of the signal transmitted by the corresponding third delay unit is ahead of the third level of the corresponding fourth delay unit; or: The fourth level indicates that the phase of the signal transmitted by the corresponding third delay unit lags behind the fourth level of the corresponding fourth delay unit; Based on the second comparison information output by the second arbitrator, the second-stage TDC circuit is calibrated, including: For any i-th second arbiter, the average level of the second comparison information output by the i-th second arbiter is controlled to match the average level of the third level and the fourth level by adjusting the delay implemented by the corresponding i-th third delay and i-th fourth delay. i is an integer greater than or equal to 1 and less than or equal to M, where M is the number of second arbitrators. The i-th second arbitrator corresponds to the i-th third delay and the i-th fourth delay.

7. The calibration method for the time interval measurement circuit according to any one of claims 1 to 6, characterized in that, The delay units all include a signal transmission unit and a vernier delay control unit; The signal transmission unit of any delay is connected to the signal transmission units of one or two adjacent delays to perform the transmission of the corresponding signal; The adjacent one or two delays include: the previous delay and / or the next delay of any one of the delays; The vernier delay control unit of any delay unit is connected to the signal transmission unit of any delay unit and is used to control whether a vernier delay difference caused by the vernier is generated between the two delay lines or between the two circular delay chains.

8. The calibration method for the time interval measurement circuit according to claim 7, characterized in that, The signal transmission unit includes a cascaded first inverter and a second inverter, and the vernier delay control unit includes a first transistor and a second transistor; The input terminal of the first inverter in any delay unit is connected to the output terminal of the second inverter in the previous delay unit, the input terminal of the second inverter in any delay unit is connected to the output terminal of the first inverter in any delay unit, and the output terminal of the second directional unit in any delay unit is connected to the input terminal of the first inverter in the next delay unit. In any of the delay circuits, the input terminal of the second inverter is also connected to the control terminal of the first transistor, the first terminal of the first transistor is connected to the output terminal of the second inverter, the second terminal of the first transistor is connected to the first terminal of the second transistor, and the second terminal of the second transistor is grounded. The signal connected to the control terminal of the second transistor in any of the delay units is used to determine whether a vernier delay difference caused by the vernier is formed.

9. The calibration method for the time interval measurement circuit according to claim 8, characterized in that, The delay units all include a delay calibration unit; The delay calibration unit includes a plurality of transistors connected in parallel. The plurality of transistors connected in parallel are connected to the power supply terminal of the first inverter. The plurality of transistors connected in parallel are configured to be selectively turned on to control the delay implemented by the corresponding delay unit.

10. A calibration processing device, characterized in that, A calibration method for performing the time interval measurement circuit according to any one of claims 1 to 9.

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