Time interval measurement circuit and its second stage tdc circuit, electronic device

Abstract

The application provides a time interval measurement circuit, a second-stage TDC circuit of the time interval measurement circuit and an electronic device, wherein the second-stage TDC circuit comprises a first delay line, a second delay line and N comparison and judgment units, the first delay line comprises N first delay units, the second delay line comprises N second delay units, the signal transmission speed of the second delay line to the end signal is faster than the signal transmission speed of the first delay line to the start signal, the comparison and judgment unit is used for determining signal comparison information, and the signal comparison information represents whether the phase of the start signal in the first delay unit connected to the comparison and judgment unit is ahead of or lags behind the phase of the end signal in the second delay unit, and a processing module is used for determining target time interval information based on the signal comparison information of part or all of the comparison and judgment units.

Description

Technical Field

[0001] This invention relates to the field of time measurement, and more particularly to a time interval measurement circuit and its second-stage TDC circuit and electronic equipment. Background Technology

[0002] A time-to-digital converter (TDC) can be understood as any circuit capable of detecting the time interval between an input start signal and a received signal, which can be generated based on the rising and falling edges of a trigger pulse.

[0003] In existing related technologies, time interval measurement circuits can include two-stage TDC circuits, with the second-stage TDC circuit typically employing a charge pump + ADC structure. The charge pump is a common time-to-voltage conversion circuit, and theoretically, its conversion rate can be increased to any value by increasing the output current. However, in reality, this conversion rate is limited by circuit technology and the length of the conversion time. When the time length is very small (e.g., less than 10 ps), the excitation pulse of the charge pump will be too short to drive the transistor to produce a linear current output, at which point the charge pump will fail. Increasing the length of the input time allows the charge pump to function properly, but this comes at the cost of increasing the ADC bit depth and error. This means that this TDC structure has a resolution upper limit limited by the charge pump, currently around 0.8 ps. Summary of the Invention

[0004] This invention provides a time interval measurement circuit and its second-stage TDC circuit and electronic device to solve the problems caused by the use of a charge pump in the second-stage TDC circuit.

[0005] According to a second aspect of the present invention, a second-stage TDC circuit for a time interval measurement circuit is provided, comprising: a first delay line, a second delay line, and N comparison and judgment units, wherein the first delay line comprises N first delay units, and the second delay line comprises N second delay units;

[0006] The N first delay units are connected in sequence, and a start signal is received through the first first delay unit. The first delay unit in the first delay line is used to: transmit the start signal and perform a delay on the start signal during transmission; the N second delay units are connected in sequence, and an end signal is received through the first second delay unit. The second delay unit in the second delay line is used to: transmit the end signal and perform a delay on the end signal during transmission.

[0007] Wherein, the signal transmission speed of the second delay line to the end signal is faster than the signal transmission speed of the first delay line to the start signal;

[0008] Each comparison and judgment unit is connected to a corresponding first delay unit and a second delay unit, and the first delay unit and the second delay unit connected to the comparison and judgment unit are in the same order in the corresponding delay line;

[0009] The comparison and judgment unit is used to determine signal comparison information, which indicates whether the phase of the start signal propagating in the first delay unit connected to the comparison and judgment unit is ahead of or behind the phase of the end signal propagating in the second delay unit connected to the comparison and judgment unit.

[0010] The comparison and judgment unit is connected to the processing module; the processing module is used to: determine the target time interval information based on the signal comparison information of some or all comparison and judgment units, the target time interval information representing the time interval between the start signal and the end signal before the corresponding delay line delay.

[0011] Optionally, when determining the target time interval information based on the signal comparison information of some or all comparison and judgment units, the processing module is specifically used for:

[0012] If the signal comparison information output by any j-th comparison judgment unit is different from the signal comparison information output by the (j-1)-th comparison judgment unit, then the target quantity information is determined, and the target time interval information is determined based on the target quantity information. The target quantity information represents the number of time delays that the start signal and / or the end signal have passed through in the corresponding delay line when propagating to the time delay connected to the j-th comparison judgment unit.

[0013] Optionally, the first delay unit and the second delay unit corresponding to the first delay line and the second delay line have the same structure and the same device size.

[0014] Optionally, both the first delay unit and the second delay unit include a signal transmission unit and a vernier delay control unit;

[0015] The signal transmission unit of any delay unit is connected to the signal transmission units of one or two adjacent delay units to perform the propagation of the corresponding signal; the corresponding signal is the start signal or the end signal; the one or two adjacent delay units include: the delay unit before and / or the delay unit of any delay unit;

[0016] The vernier delay control unit of any delay unit is connected to the signal transmission unit of any delay unit and is used to control whether a delay difference is generated between the first delay line and the second delay line.

[0017] Optionally, the signal transmission unit includes a cascaded first inverter and a second inverter, and the vernier delay control unit includes a first transistor and a second transistor;

[0018] The input terminal of the first inverter in any delay unit is connected to the output terminal of the second inverter in the previous delay unit, the input terminal of the second inverter in any delay unit is connected to the output terminal of the first inverter in any delay unit, and the output terminal of the second directional unit in any delay unit is connected to the input terminal of the first inverter in the next delay unit.

[0019] In any of the delay circuits, the input terminal of the second inverter is also connected to the control terminal of the first transistor, the first terminal of the first transistor is connected to the output terminal of the second inverter, the second terminal of the first transistor is connected to the first terminal of the second transistor, and the second terminal of the second transistor is grounded.

[0020] The signal connected to the control terminal of the second transistor in the first delay and the second delay is used to determine whether the delay difference is generated.

[0021] Optionally, if the signal connected to the control terminal of the second transistor in any k-th first delay is at the same level as the signal connected to the control terminal of the second transistor in the k-th second delay, then: the delay between the k-th first delay and the k-th second delay is the same;

[0022] If the signal connected to the control terminal of the second transistor in any k-th first delay unit is at a different level than the signal connected to the control terminal of the second transistor in the k-th second delay unit, then the delay between the k-th first delay unit and the k-th second delay unit has a specified delay difference.

[0023] Optionally, both the first delay unit and the second delay unit further include a delay calibration unit;

[0024] The delay calibration unit includes a plurality of transistors connected in parallel. The plurality of transistors connected in parallel are connected to the power supply terminal of the first inverter. The plurality of transistors connected in parallel are configured to be selectively turned on to control the delay implemented by the corresponding delay unit.

[0025] Optionally, the comparison and judgment unit is connected to the output terminal of the first inverter;

[0026] When judging signal comparison information, the comparison and judgment unit is specifically used to: judge the signal comparison information by comparing the signals output by the first inverter of the first delay unit and the first inverter of the second delay unit.

[0027] According to a second aspect of the present invention, a time interval measurement circuit is provided, comprising a two-stage TDC circuit;

[0028] The second stage of the two-stage TDC circuit is the second-stage TDC circuit involved in the first aspect and its optional schemes;

[0029] The first-stage TDC circuit in the two-stage TDC circuit is used to acquire the start signal and the stop signal, and to determine the preliminary time interval information between the start signal and the stop signal;

[0030] The start signal input to the second-stage TDC circuit is a time interval that matches the end signal, which is the initial time interval information determined by the first-stage TDC circuit.

[0031] According to a third aspect of the invention, an electronic device is provided, comprising the time interval measurement circuit described in the second aspect.

[0032] The time interval measurement circuit and its second-stage TDC circuit and electronic device provided by this invention employ a first delay line containing N first delay units, a second delay line containing N second delay units, and a comparison and judgment unit. Through the delay transmission of the two delay lines and the judgment of the comparison and judgment unit, it can accurately reflect which delay unit the end signal catches up with the start signal, thus providing sufficient basis for determining the target time interval information. It can be seen that this invention does not require the use of a charge pump, and therefore, it does not suffer from resolution limitations caused by the use of a charge pump. At the same time, the delay difference between the two delay lines in this invention can achieve a corresponding resolution, which can change with the delay difference. In the implementation process, after configuring and calibrating to achieve a suitable delay difference, the required resolution can be achieved. Therefore, this invention provides a reliable implementation method to ensure resolution. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of the construction of the second-stage TDC circuit in one embodiment of the present invention;

[0035] Figure 2 This is a schematic diagram of the construction of the second-stage TDC circuit in another embodiment of the present invention;

[0036] Figure 3 This is a schematic diagram of the construction of the second-stage TDC circuit in another embodiment of the present invention;

[0037] Figure 4 This is a circuit diagram of a time interval measurement circuit according to an embodiment of the present invention.

[0038] Explanation of reference numerals in the attached figures:

[0039] 1-First delay unit;

[0040] 11-Delay calibration module;

[0041] 12-Signal transmission module;

[0042] 13-Vernier Delay Control Module;

[0043] 2-Second delay unit;

[0044] 21-Delay calibration module;

[0045] 22-Signal transmission module;

[0046] 23-Vernier Delay Control Module;

[0047] 3-Comparison and Judgment Unit;

[0048] 4-Processing module;

[0049] 5-First-stage TDC circuit;

[0050] 6-Signal output circuit;

[0051] 7-Second-stage TDC circuit. Detailed Implementation

[0052] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0053] In the description of this invention, it should be understood that the terms "upper part", "lower part", "upper end", "lower end", "lower surface", "upper surface", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention.

[0054] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0055] In the description of this invention, "a plurality of" means multiple, such as two, three, four, etc., unless otherwise explicitly specified.

[0056] In the description of this invention, unless otherwise explicitly specified and limited, the term "connection" and other such terms should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral connection; it can refer to a mechanical connection, an electrical connection, or a connection that allows communication between the components; it can refer to a direct connection or an indirect connection through an intermediate medium; it can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0057] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0058] Please refer to Figure 1 This invention provides a second-stage TDC circuit for a time interval measurement circuit, comprising: a first delay line, a second delay line, and N comparison and judgment units 3. The first delay line includes N first delay units 1, and the second delay line includes N second delay units 2. Wherein, N is an integer greater than or equal to 2.

[0059] The N first delay units 1 are connected in sequence, and the start signal is received through the first first delay unit 1. The first delay unit 1 in the first delay line is used to: transmit the start signal and perform a delay of the start signal during the transmission process.

[0060] The N second delay units 2 are connected in sequence, and the end signal is received through the first second delay unit 2. The second delay unit 2 in the second delay line is used to: transmit the end signal and perform a delay of the end signal during the transmission process;

[0061] Any solution in this field that can both transmit signals and implement delay during transmission can be considered as an option.

[0062] The start signal can be understood as a signal indicating the start point of the required measurement time interval, such as the start signal input to the second-stage TDC circuit. res Signal. The start signal is... res The signal can be Figure 4 The signal output circuit shown is generated under the control of processing module 4.

[0063] The end signal can be understood as a signal indicating the end of the required measurement time interval, such as a stop signal input to the second-stage TDC circuit. res Signals. The stop signal is one of them. res The signal can be Figure 4 The signal output circuit shown is generated under the control of processing module 4.

[0064] The second delay line transmits the end signal faster than the first delay line transmits the start signal; thus, due to its faster transmission speed, the end signal can catch up with and surpass the start signal as it propagates.

[0065] Each comparison and judgment unit 3 is connected to a corresponding first delay unit 1 and a second delay unit 2, and the order of the first delay unit 1 and the second delay unit 2 connected to the comparison and judgment unit 3 in the corresponding delay line is the same; the order refers to the arrangement order of the first delay unit to the last delay unit in the corresponding delay line.

[0066] The comparison and judgment unit 3 is used to determine signal comparison information;

[0067] The signal comparison information indicates whether the phase of the start signal propagating in the first delay unit connected to the comparison judgment unit is ahead of or behind the phase of the end signal propagating in the second delay unit connected to the comparison judgment unit.

[0068] After both signals are received, the comparison and judgment unit can determine that the phase of the end signal transmitted by the second delay unit lags behind the phase of the end signal transmitted by the first delay unit. At this time, the comparison and judgment unit can output a level (e.g., high level). As the cycle continues, the end signal will catch up with the start signal. After catching up and surpassing, the corresponding comparison and judgment unit will reverse to output another level (e.g., low level). The processing module can obtain the corresponding phase comparison information, thereby completing the corresponding calculation process and obtaining the target time interval information.

[0069] The comparison and judgment unit 3 is connected to the processing module 4; the processing module can be any circuit module capable of data processing, such as an MCU, CPU, logic processing module, digital circuit, digital logic circuit, etc.; in addition, the two or more TDC circuits in the time interval measurement circuit can reuse or share the same processing module, or they can use different processing modules respectively.

[0070] The processing module is used to determine the target time interval information based on the signal comparison information of some or all comparison and judgment units.

[0071] The target time interval information represents the time interval between the start signal and the end signal before the corresponding delay line delays. It can also be understood that if the start signal and the end signal are generated and emitted by the signal emitting circuit, the target time interval information can represent the time interval between the generation and emission of the two signals by the signal emitting circuit.

[0072] In one example, when the processing module determines the target time interval information based on the signal comparison information of some or all comparison and judgment units, it is specifically used for:

[0073] If the signal comparison information output by any j-th comparison judgment unit is detected to be different from the signal comparison information output by the (j-1)-th comparison judgment unit, then target quantity information is determined, and based on the target quantity information, target time interval information is determined. The target quantity information represents the number of delay units through which the start signal and / or the end signal has propagated in the corresponding delay line when propagating to the delay unit connected to the j-th comparison judgment unit. Here, j is any integer greater than or equal to 2.

[0074] Specifically:

[0075] The signal comparison information output by the (j-1)th comparison and judgment unit indicates that the phase of the start signal propagating in the first delay unit connected to the (j-1)th comparison and judgment unit leads the phase of the end signal propagating in the second delay unit connected to the unit.

[0076] The signal comparison information output by the j-th comparison and judgment unit indicates that the phase of the start signal propagating in the first delay unit connected to the j-th comparison and judgment unit lags behind the phase of the end signal propagating in the second delay unit connected to the j-th comparison and judgment unit.

[0077] As can be seen, a specific example of integrating the above processing steps may include the following steps:

[0078] The module's workflow is as follows:

[0079] S1. The start signal enters the first delay line before the end signal and begins to propagate;

[0080] S2, the end signal, begins propagation on the second delay line.

[0081] S3. Since the propagation speed of the second delay line is slightly faster than that of the upper delay line, the end signal will slowly catch up with the start signal, and the delay difference between the two signals will gradually shorten during this process.

[0082] S4. The end signal catches up with the start signal, causing the output level of the comparison and judgment unit to reverse. After being judged by the processing module (e.g., digital circuit), the output of the comparison and judgment unit outputs the converted LSB (e.g., ...). Figure 3 The values ​​of LSB1, LSB2, ..., LSB8 shown are the outputs of the second-stage TDC circuit.

[0083] To achieve high resolution, the impact of mismatch caused by factors such as process variations on TDC is minimized. In one embodiment, the corresponding first and second delay units in the first and second delay lines have identical structures and the same device dimensions. Furthermore, since the circuit structure and dimensional parameters of the upper and lower delay lines are completely identical and symmetrical (and the vernier delay difference is introduced externally by a digital control signal), mismatch problems caused by process variations can be largely avoided.

[0084] In this invention, the second-stage TDC circuit employs a first delay line containing N first delay units, a second delay line containing N second delay units, and a comparison and judgment unit. Through the delay transmission of the two delay lines and the judgment of the comparison and judgment unit, it can accurately reflect which delay unit the end signal catches up with the start signal, thus providing sufficient basis for determining the target time interval information. Therefore, this invention does not require the use of a charge pump, and thus avoids resolution limitations caused by the use of a charge pump. At the same time, the delay difference between the two delay lines in this invention can achieve a corresponding resolution, which can change with the delay difference. In the implementation process, after configuring and calibrating to achieve a suitable delay difference, the required resolution can be achieved. Therefore, this invention provides a reliable implementation method to ensure resolution.

[0085] In one implementation method, please refer to Figure 2 and Figure 3 Both the first delay unit and the second delay unit include a signal transmission unit (e.g., signal transmission unit 12 in the first delay unit 1 and signal transmission unit 22 in the second delay unit 2) and a vernier delay control unit (e.g., vernier delay control unit 13 in the first delay unit 1 and vernier delay control unit 23 in the second delay unit 2).

[0086] The signal transmission unit of any delay unit is connected to the signal transmission units of one or two adjacent delay units to perform the propagation of the corresponding signal; the corresponding signal is the start signal or the end signal; the one or two adjacent delay units include: the delay unit before and / or the delay unit of any delay unit;

[0087] That is: the signal transmission unit 12 of the first delay unit is connected between the signal transmission units 12 of two adjacent first delay units, and is used to propagate the start signal, which can achieve a certain delay during propagation; the signal transmission unit 22 of the second delay unit is connected between the signal transmission units 22 of two adjacent second delay units, and is used to propagate the end signal, which can achieve a certain delay during propagation.

[0088] In one example, the signal transmission unit includes a cascaded first inverter and a second inverter.

[0089] The first inverter can be, for example, Figure 3 The first inverter formed by transistors M1 and M2 shown can also be, for example... Figure 3 The first inverter formed by transistors M4 and M5 shown; the second inverter therein can be, for example... Figure 4 The second inverter X1 shown can also be, for example, Figure 4 The second inverter X2 shown;

[0090] The input terminal of the first inverter in any delay unit is connected to the output terminal of the second inverter in the previous delay unit, the input terminal of the second inverter in any delay unit is connected to the output terminal of the first inverter in any delay unit, and the output terminal of the second directional unit in any delay unit is connected to the input terminal of the first inverter in the next delay unit.

[0091] In this circuit, the first terminal of transistor M1 (and transistor M4) is directly or indirectly connected to the power supply terminal, the second terminal of transistor M1 (and transistor M4) is connected to the first terminal of transistor M2 (and transistor M5), the second terminal of transistor M2 (and transistor M5) is directly or indirectly grounded, and the control terminal (e.g., the gate) of transistor M1 (and transistor M4) is directly or indirectly connected to the output terminal of the second inverter (e.g., the second inverter X1, the second inverter X2) of the previous delay circuit.

[0092] The second inverter can be constructed in the same or similar way as the first inverter, or it can be different. The second inverter can also be implemented using a NOT gate.

[0093] Correspondingly, the comparison and judgment unit 3 is connected to the output terminal of the first inverter;

[0094] When judging signal comparison information, the comparison and judgment unit 3 is specifically used to: judge the signal comparison information by comparing the signals output by the first inverter of the first delay unit and the second delay unit.

[0095] In addition, the signal transmission unit may also include a ground control transistor (e.g., ground control transistor M3 in the first delay 1 and ground control transistor M6 in the second delay 2), which can be connected between the first inverter and ground to realize the ground control of the first inverter.

[0096] The vernier delay control unit of any delay unit is connected to the signal transmission unit of any delay unit and is used to control whether a delay difference is generated between the first delay line and the second delay line.

[0097] When a delay difference is generated, different delays can be achieved between the two delay lines, thereby enabling the second delay line to propagate the end signal faster than the first delay line to propagate the start signal. When no delay difference is generated, and other module units have not formed a delay difference (for example, after the delay calibration unit calibrates the two delay lines), synchronization of the two delay lines can be achieved. This situation can be used in scenarios other than those for calculating time interval information, such as scenarios for verifying circuits.

[0098] For specific examples, please refer to Figure 3 The vernier delay control unit includes a first transistor and a second transistor; for example, the vernier delay control unit 13 in the first delayer 1 includes a first transistor Q1 and a second transistor Q2, and the vernier delay control unit 23 in the second delayer 2 includes a first transistor Q3 and a second transistor Q4.

[0099] In any of the delay circuits, the input terminal of the second inverter is also connected to the control terminal of the first transistor, the first terminal of the first transistor is connected to the output terminal of the second inverter, the second terminal of the first transistor is connected to the first terminal of the second transistor, and the second terminal of the second transistor is grounded.

[0100] The signal connected to the control terminal of the second transistor in the first delay and the second delay is used to determine whether the delay difference is generated.

[0101] Optionally, if the signal connected to the control terminal of the second transistor in any k-th first delay unit is at the same level as the signal connected to the control terminal of the second transistor in the k-th second delay unit, then: the delay between the k-th first delay unit and the k-th second delay unit is the same; specifically, after the delay calibration unit, the delay between the k-th first delay unit and the k-th second delay unit is the same.

[0102] If the signal connected to the control terminal of the second transistor in any k-th first delay unit is at a different level than the signal connected to the control terminal of the second transistor in the k-th second delay unit, then: the delay between the k-th first delay unit and the k-th second delay unit has a specified delay difference; specifically, after the delay calibration unit, the delay between the k-th first delay unit and the k-th second delay unit has a specified delay difference.

[0103] Furthermore, the signal input to the control terminal of the second transistor Q2 in each of the first delay units can be the same, i.e. Figure 3 The DCW in each of the second delay units is the same, and the signal input to the control terminal of the second transistor Q4 in each second delay unit can be the same, for example... Figure 4 VDD is the same in both cases. When a delay difference occurs, DCW is different from VDD; when no delay difference occurs, DCW is the same as VDD.

[0104] As can be seen, the vernier delay control unit receives control signals (e.g., DCW, VDD) from the processing module (e.g., digital circuit) to control the delay difference between the two delay lines. When the input levels of the two vernier delay control units are the same, no vernier delay is introduced, and the delays of the two delay lines are the same. When the input levels of the two vernier delay control units are different, a delay difference will be generated between the two delay lines. This delay difference is the resolution of the vernier TDC, and the vernier TDC can work normally in this case.

[0105] Specifically, if the first-stage TDC circuit also uses a vernier TDC, the delay difference between the two delay lines of the second-stage TDC is less than the delay difference between the two delay lines of the vernier TDC in the first-stage TDC circuit. Therefore, the resolution of the vernier TDC implemented by the first-stage TDC circuit is less than the resolution of the vernier TDC implemented by the second-stage TDC circuit, thus meeting the requirements of coarse and fine TDC measurements.

[0106] In one implementation method, please refer to Figure 2 and Figure 3 Both the first delay unit 1 and the second delay unit 2 further include a delay calibration unit (e.g., delay calibration unit 11 in the first delay unit 1 and delay calibration unit 21 in the second delay unit 2);

[0107] The delay calibration unit includes multiple transistors connected in parallel. These multiple transistors are connected to the power supply terminal of the first inverter (e.g., the first terminal of transistors M1 and M4 in the first inverter). The multiple transistors are configured to be selectively turned on to control the delay implemented by the corresponding delay unit.

[0108] As can be seen, the delay calibration unit can be composed of several transistors of different sizes connected in parallel. The delay of the delay circuit can be controlled by controlling the on and off states of the transistors. This module receives a calibration signal from the control module (e.g., a digital circuit) and calibrates the delay of the delay circuit so that, when DCW and VDD are the same, the delays of the two delay lines are equal.

[0109] In this scheme, each delay unit is equipped with a delay calibration unit, which can calibrate the delay of each delay unit separately with high accuracy. The introduction of this calibration method can calibrate the existing nonlinear error to a very low level, greatly reducing the impact of mismatch on the effective resolution of TDC.

[0110] This invention provides a time interval measurement circuit, including a two-stage TDC circuit;

[0111] The second stage of the two-stage TDC circuit is the second-stage TDC circuit involved in the above optional schemes;

[0112] The first-stage TDC circuit in the two-stage TDC circuit is used to acquire the start signal and the stop signal, and determine the preliminary time interval information between the start signal and the stop signal; at the same time, it can also output the stop signal and the start signal (which can be understood as start) delayed by two delay chains (e.g., a circular delay chain) of the first-stage TDC circuit. res Signals and Stop res Signal);

[0113] The start signal input to the second-stage TDC circuit has a time interval matching the time interval between the start and end signals to the time interval between the two signals output by the first-stage TDC circuit. For example, if the first-stage TDC circuit uses two circular delay chains, the loop can be stopped in both circular delay chains, thus outputting a start signal. res Signals and Stop res When the signal is received, the second-stage TDC circuit can obtain the start signal from the outputs of the two ring delay chains. res Signals and Stop res Signal.

[0114] by Figure 4 For example, the signal output circuit 6 can be controlled by the processing module 4 (or the signal output circuit 8 can be directly output without being controlled by the processing module 5) start. res Signals and Stop res The signals serve as the start and end signals for the second-stage TDC circuit. In this field, the start signal is determined and output between the two TDC circuit stages. res Signals and Stop res Any of the signal schemes can be considered as one of the options for the signal output circuit 6. In terms of connection, the signal output circuit 6 can be connected to the output terminal of the first-stage TDC circuit to obtain the signal output by the first-stage TDC circuit, or it can be connected to the input terminals of the first delay line and the second delay line.

[0115] In one example, the signal transmitting circuit 6 may only perform the function of signal transmission; in other examples, the signal transmitting circuit 6 may also perform functions such as amplification and adjustment of the time interval.

[0116] This invention also provides an electronic device, including the time interval measurement circuit described above.

[0117] In the description of this specification, the references to terms such as "an embodiment," "an example," "a specific implementation process," and "an example" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A second-stage TDC circuit for a time interval measurement circuit, characterized in that, include: A first delay line, a second delay line, and N comparison and judgment units, wherein the first delay line includes N first delay units, and the second delay line includes N second delay units; The N first delay units are connected in sequence, and a start signal is received through the first first delay unit. The first delay unit in the first delay line is used to: transmit the start signal and perform a delay on the start signal during transmission; the N second delay units are connected in sequence, and an end signal is received through the first second delay unit. The second delay unit in the second delay line is used to: transmit the end signal and perform a delay on the end signal during transmission. Wherein, the signal transmission speed of the second delay line to the end signal is faster than the signal transmission speed of the first delay line to the start signal; Each comparison and judgment unit is connected to a corresponding first delay unit and a second delay unit, and the first delay unit and the second delay unit connected to the comparison and judgment unit are in the same order in the corresponding delay line; The comparison and judgment unit is used to determine signal comparison information, which indicates whether the phase of the start signal propagating in the first delay unit connected to the comparison and judgment unit is ahead of or behind the phase of the end signal propagating in the second delay unit connected to the comparison and judgment unit. The comparison and judgment unit is connected to the processing module; the processing module is used to: determine the target time interval information based on the signal comparison information of some or all of the comparison and judgment units, the target time interval information representing: the time interval between the start signal and the end signal before the corresponding delay line delay; Both the first delay unit and the second delay unit include a signal transmission unit and a vernier delay control unit; The signal transmission unit of any delay unit is connected to the signal transmission units of one or two adjacent delay units to perform the propagation of the corresponding signal; the corresponding signal is the start signal or the end signal; the one or two adjacent delay units include: the delay unit before and / or the delay unit of any delay unit; The vernier delay control unit of any delay unit is connected to the signal transmission unit of any delay unit and is used to control whether a delay difference is generated between the first delay line and the second delay line; The signal transmission unit includes a cascaded first inverter and a second inverter, and the vernier delay control unit includes a first transistor and a second transistor; The input terminal of the first inverter in any delay unit is connected to the output terminal of the second inverter in the previous delay unit, the input terminal of the second inverter in any delay unit is connected to the output terminal of the first inverter in any delay unit, and the output terminal of the second directional unit in any delay unit is connected to the input terminal of the first inverter in the next delay unit. In any of the delay circuits, the input terminal of the second inverter is also connected to the control terminal of the first transistor, the first terminal of the first transistor is connected to the output terminal of the second inverter, the second terminal of the first transistor is connected to the first terminal of the second transistor, and the second terminal of the second transistor is grounded. The signal connected to the control terminal of the second transistor in the first delay and the second delay is used to determine whether the delay difference is generated.

2. The TDC circuit according to claim 1, characterized in that, When determining the target time interval information based on the signal comparison information of some or all comparison and judgment units, the processing module is specifically used for: If the signal comparison information output by any j-th comparison judgment unit is different from the signal comparison information output by the (j-1)-th comparison judgment unit, then the target quantity information is determined, and the target time interval information is determined based on the target quantity information. The target quantity information represents the number of time delays that the start signal and / or the end signal have passed through in the corresponding delay line when propagating to the time delay connected to the j-th comparison judgment unit.

3. The TDC circuit according to claim 1, characterized in that, The first delay circuit and the second delay circuit have the same structure and the same component size.

4. The TDC circuit according to claim 1, characterized in that, If the signal connected to the control terminal of the second transistor in any k-th first delay unit is at the same level as the signal connected to the control terminal of the second transistor in the k-th second delay unit, then: the delay between the k-th first delay unit and the k-th second delay unit is the same; If the signal connected to the control terminal of the second transistor in any k-th first delay unit is at a different level than the signal connected to the control terminal of the second transistor in the k-th second delay unit, then the delay between the k-th first delay unit and the k-th second delay unit has a specified delay difference.

5. The TDC circuit according to claim 1, characterized in that, Both the first delay unit and the second delay unit further include a delay calibration unit; The delay calibration unit includes a plurality of transistors connected in parallel. The plurality of transistors connected in parallel are connected to the power supply terminal of the first inverter. The plurality of transistors connected in parallel are configured to be selectively turned on to control the delay implemented by the corresponding delay unit.

6. The TDC circuit according to claim 1, characterized in that, The comparison and judgment unit is connected to the output terminal of the first inverter; When judging signal comparison information, the comparison and judgment unit is specifically used to: judge the signal comparison information by comparing the signals output by the first inverter of the first delay unit and the first inverter of the second delay unit.

7. A time interval measurement circuit, characterized in that, Includes a two-stage TDC circuit; The second stage of the two-stage TDC circuit is the second-stage TDC circuit as described in any one of claims 1 to 6; The first-stage TDC circuit in the two-stage TDC circuit is used to acquire the start signal and the stop signal, and to determine the preliminary time interval information between the start signal and the stop signal; The time interval between the start signal and the end signal input to the second-stage TDC circuit is matched with the time interval between the two signals output by the first-stage TDC circuit.

8. An electronic device, characterized in that, Includes the time interval measurement circuit as described in claim 6 or 7.

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