Chip, manufacturing method and electronic device

Abstract

The application discloses a chip, a preparation method and an electronic device. At least one channel structure, a gate, a gate oxide layer and a source-drain electrode layer are arranged on a substrate. The source and the drain of a transistor are formed by the source-drain electrode layer. The gate oxide layer realizes isolation between the gate and the channel region of the channel layer. The gate surrounds the channel region of the channel layer, and realizes that the gate structure wraps the channel. The sacrificial layer around the channel region is removed, the sacrificial layer in the remaining area is reserved, and the content of the doped ions in the sacrificial layer is not more than 5%. The doped semiconductor material in the sacrificial layer and the undoped semiconductor material in the channel layer can be regarded as different doping concentrations of the same semiconductor material, a homojunction can be formed between the adjacent sacrificial layer and the channel layer, the stress between the adjacent channel layer and the sacrificial layer is reduced, and the possibility of dislocation and warping is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a chip, a preparation method and an electronic device. BACKGROUND

[0002] Complementary Metal Oxide Semiconductor (CMOS) technology is the mainstream technology of Integrated Circuit (IC) at present. With the continuous reduction of device size, the integration degree increases exponentially, and the circuit performance is continuously improved. However, with the feature size of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) devices entering the deep submicron and nanometer range, the short channel effect will have an important impact on the device performance, and at the same time, the traditional device structure and preparation process also face new challenges. In order to continue the effectiveness of Moore's law, new device structures such as Fin Field-Effect Transistor (Fin FET) and Gate All Around Field-Effect Transistor (GAAFET) are widely studied. Among them, the superior ability of GAAFET in suppressing short channel effect and improving current control makes it one of the most powerful competitors of future MOSFET devices.

[0003] At present, the common preparation method of GAAFET device is: first, epitaxially grow a Si and SiGe multilayer stack structure, then, using selective etching technology, using SiGe as a sacrificial layer, removing SiGe and leaving Si as a channel layer; or using Si as a sacrificial layer, removing Si and leaving SiGe as a channel layer, thereby forming a GAAFET. However, due to the existence of a large lattice mismatch between SiGe and Si, the existing lattice mismatch stress will form dislocations (dislocations will affect the reliability and performance of the device) and warping (warping will affect the alignment of IC process, especially affecting photolithography). SUMMARY

[0004] The chip, the preparation method and the electronic device provided by the embodiments of the present application are used for improving the dislocations and warping caused by the stress generated by the lattice mismatch.

[0005] In a first aspect, an embodiment of the present application provides a chip, at least one transistor is arranged on a substrate, the transistor includes at least one channel structure, a gate, a source-drain electrode layer and a gate oxide layer arranged on the substrate. The gate oxide layer is arranged between the gate and the channel layer to achieve isolation between the gate and the channel region of the channel layer. The gate surrounds the channel region of the channel layer, and the arrangement of the gate structure wrapping the channel can achieve ideal control of the channel to form a GAAFET. The source-drain electrode layer covers the first region and the second region of the channel layer in the orthographic projection of the substrate, and the orthographic projection of the source-drain electrode layer on the substrate does not overlap with the orthographic projection of the gate on the substrate, and the source and the drain of the transistor are formed by the source-drain electrode layer. Furthermore, the orthographic projection of the channel region of the channel layer on the substrate does not overlap with the orthographic projection of the sacrificial layer on the substrate, and the orthographic projection of the first region and the second region of the channel layer on the substrate overlaps with the orthographic projection of the sacrificial layer on the substrate. In this way, the sacrificial layer around the channel region can be removed, and the sacrificial layer in the remaining area (i.e., the first region and the second region) is retained. Furthermore, by making the content of the doping ions in the sacrificial layer not more than 5%, the semiconductor material and the doping ions will not form an alloy after the doping ions are doped into the semiconductor material, but the doped semiconductor material and the undoped semiconductor material are regarded as different doping concentrations of the same kind of semiconductor material. That is, the doped semiconductor material in the sacrificial layer and the undoped semiconductor material in the channel layer can be regarded as different doping concentrations of the same kind of semiconductor material, so that a homojunction can be formed between the adjacent sacrificial layer and the channel layer, and the stress between the adjacent channel layer and the sacrificial layer is reduced, thereby reducing the possibility of dislocation and warping.

[0006] In a possible implementation of the present application, the channel layer can be arranged to extend along a first direction, and the sacrificial layer and the channel layer are arranged to alternately arrange along a second direction. The gate is arranged to extend along a third direction. The first direction, the second direction and the third direction are perpendicular to each other.

[0007] In a possible implementation of the present application, the doping concentration of the doping ions in the sacrificial layer is not less than 1E16 atom / cm 3 and not more than 1E22 atom / cm 3 . This indicates that the above-mentioned doping ions are doped in the sacrificial layer, and the above-mentioned doping ions are not doped in the channel layer, so that the doped semiconductor material in the sacrificial layer and the undoped semiconductor material in the channel layer can be regarded as different doping concentrations of the same kind of semiconductor material, thereby further ensuring that a homojunction structure is formed between the sacrificial layer and the channel layer.

[0008] In a possible implementation of the present application, the doping concentration of the doping ions in the sacrificial layer is not less than 1E17 atom / cm 3 and not more than 1E21 atom / cm 3Optionally, the doping concentration of the doping ions in the sacrificial layer is not less than 1E18 atom / cm 3 and not more than 1E20 atom / cm 3 . Exemplarily, the doping concentration of the doping ions in the sacrificial layer can be set as 1E16 atom / cm 3 , 5E16 atom / cm 3 , 1E17 atom / cm 3 , 5E17 atom / cm 3 , 1E18 atom / cm 3 , 5E18 atom / cm 3 , 1E19 atom / cm 3 , 5E19 atom / cm 3 , 1E20 atom / cm 3 , 5E20 atom / cm 3 , 1E21 atom / cm 3 , 5E21 atom / cm 3 or 1E22 atom / cm 3 .

[0009] In a possible implementation of the present application, when the doping concentration of the doping ions in the sacrificial layer is 1E22 atom / cm 3 , the content of the doping ions in the sacrificial layer is approximately equal to 5%. When the doping concentration of the doping ions in the sacrificial layer is 1E21 atom / cm 3 , the content of the doping ions in the sacrificial layer is approximately equal to 2%. When the doping concentration of the doping ions in the sacrificial layer is 1E20 atom / cm 3 , the content of the doping ions in the sacrificial layer is approximately equal to 1%. Then, when the doping concentration of the doping ions in the sacrificial layer is less than 1E22 atom / cm 3 and greater than 1E21 atom / cm 3 , the content of the doping ions in the sacrificial layer is less than 5% and greater than 2%. When the doping concentration of the doping ions in the sacrificial layer is less than 1E21 atom / cm 3 and greater than 1E20 atom / cm 3 , the content of the doping ions in the sacrificial layer is less than 2% and greater than 1%. When the doping concentration of the doping ions in the sacrificial layer is less than 1E20 atom / cm 3 , the content of the doping ions in the sacrificial layer is less than 1%.

[0010] In a possible implementation of the present application, the semiconductor material in the channel layer includes at least one of an elemental semiconductor, an inorganic compound semiconductor, and an organic compound semiconductor. For example, the semiconductor material in the channel layer can be Si. In a specific implementation, the semiconductor material in the channel layer is not limited to Si, but can also be a semiconductor such as SiGe, Ge, and the like, a compound semiconductor such as GaAs, InP, GaN, SiC, and the like, an oxide semiconductor such as GaO, ZnO, and the like, and a ferroelectric and two-dimensional material, and the like.

[0011] In a possible implementation of the present application, the doping ions can be N-type doping ions. For example, the N-type doping ions can include at least one of phosphorus ions, arsenic ions, and antimony ions. For example, when the semiconductor material in the channel layer is Si, and the N-type doping ions are phosphorus ions, the phosphorus ions can be doped in the Si when the sacrificial layer is formed, thereby forming a sacrificial layer in the form of Si:P. When the N-type doping ions are arsenic ions, the arsenic ions can be doped in the Si when the sacrificial layer is formed, thereby forming a sacrificial layer in the form of Si:As. When the N-type doping ions are antimony ions, the antimony ions can be doped in the Si when the sacrificial layer is formed, thereby forming a sacrificial layer in the form of Si:Sb.

[0012] Since the etching rate of the P-type doped semiconductor material is slow, if the semiconductor material with P-type doping ions is used as the sacrificial layer in the present application, a long time is required to etch the sacrificial layer. Although the sacrificial layer and the channel layer have an etching selectivity, if a long time is required to etch the sacrificial layer with P-type doping ions, the channel layer is in the etching environment for a long time, which can cause damage to the channel layer, thereby affecting the carrier mobility and lifetime of the channel layer. In the embodiments of the present application, the N-type doping ions are doped in the semiconductor material to form the sacrificial layer. When the sacrificial layer is etched, a high etching rate can be achieved, and a short time is required to etch the sacrificial layer corresponding to the channel region, so that the channel layer is in the etching environment for a short time, thereby avoiding damage to the channel layer and improving the carrier mobility and lifetime of the channel layer.

[0013] In the actual process, when SiGe is used as the sacrificial layer, a large thickness and a high Ge proportion of SiGe are required to obtain a better etching result, but this results in an increased defect density and is not conducive to the size reduction of the GAAFET device. Moreover, after the SiGe is etched, by-products are deposited at the outlet, affecting the contact between the etching solution and the sacrificial layer, and a better etching effect cannot be achieved. In the present application, the electron concentration in the N-type doped semiconductor material (for example, Si:P) in the homojunction can be controlled by doping to control and improve the etching rate of the sacrificial layer. In addition, in the present application, the thickness of the N-type doped semiconductor material (for example, Si:P) in the homojunction can also be controlled to control and improve the etching rate of the sacrificial layer.

[0014] In a possible implementation of the present application, an NN-type homojunction, a PP-type homojunction or a PN-type homojunction can be formed between adjacent sacrificial layers and channel layers.

[0015] In some embodiments provided by the present application, the material forming the source-drain electrode layer can be a metal material. For example, the metal material forming the source-drain electrode layer can include W, Al, Ti, Cu, Mo or Pt.

[0016] In some embodiments provided by the present application, a barrier layer is further arranged between the source-drain electrode layer and the gate to insulate the gate and the source-drain electrode layer. For example, the material of the barrier layer can be an insulating material. Optionally, the insulating material forming the barrier layer can include silicon oxide, silicon nitride, etc.

[0017] In a possible implementation of the present application, the material of the gate can be a polysilicon material, or a metal (for example, W, Al, Ti, Cu, Mo or Pt) or other material with good conductive properties, which is not limited herein.

[0018] In a second aspect, the embodiments of the present application further provide a method for manufacturing a chip, which can include: providing a substrate, epitaxially growing a sacrificial layer including a semiconductor material and a dopant and a channel layer including the semiconductor material on the substrate alternately to form a stack structure. After etching inwardly from an exposed surface of the stack structure to the substrate, forming an isolation structure to define a region where a channel structure in the stack structure is located. Forming a dummy gate structure across the channel structure, and making the dummy gate structure cover part of a top wall and part of a sidewall of the channel structure, and the extension direction of the dummy gate structure is perpendicular to the extension direction of the channel structure. Taking the dummy gate structure as a mask, forming a source-drain electrode layer on the exposed channel structure to form a source electrode and a drain electrode. Removing the sacrificial layer in the region covered by the dummy gate structure and the dummy gate structure, retaining the rest of the sacrificial layer, forming a gate opening and exposing a channel region of the channel layer, and performing an oxidation treatment on the channel region of the channel layer to form a gate oxide layer. In the gate opening, forming a gate surrounding the channel region of the channel layer. In this way, the formed GAAFET can realize the setting of the gate wrapping the channel, and realize the ideal control of the channel.

[0019] In addition, by making the content of the dopant in the sacrificial layer not more than 5%, after the dopant is doped into the semiconductor material, the semiconductor material and the dopant do not form an alloy, but the doped semiconductor material and the undoped semiconductor material are regarded as different doping concentrations of the same semiconductor material. That is, the doped semiconductor material in the sacrificial layer and the undoped semiconductor material in the channel layer can be regarded as different doping concentrations of the same semiconductor material, so that a homojunction can be formed between adjacent sacrificial layers and channel layers, and the stress between adjacent channel layers and sacrificial layers is reduced, thereby reducing the possibility of dislocation and warping.

[0020] In a possible implementation of the present application, in order to form the stack structure, the epitaxially growing the sacrificial layer and the channel layer on the substrate alternately to form the stack structure can include the following steps: placing the substrate in a reaction chamber, first keeping the reaction chamber at a first temperature and a first pressure, respectively introducing a carrier gas, a silicon source and a doping gas into the reaction chamber, and forming a silicon atom layer with a dopant of a first thickness as a sacrificial layer by epitaxial growth; then keeping the reaction chamber at a second temperature and a second pressure, respectively introducing a carrier gas and a silicon source into the reaction chamber, and forming a silicon atom layer of a second thickness as a channel layer by epitaxial growth; repeating the above steps until the stack structure is formed on the substrate.

[0021] In one possible implementation of the present application, after the substrate is placed in the reaction chamber, the reaction chamber is first kept at a first temperature and a first pressure, carrier gas, Si source (such as DCS, TCS, SiH4, etc.) and phosphorus doping source (such as PH3) are respectively introduced into the reaction chamber, and a silicon atomic layer with phosphorus doping ions is formed by epitaxial growth method as a Si:P sacrificial layer with a first thickness; the reaction chamber is then kept at a second temperature and a second pressure, carrier gas and Si source (such as DCS, TCS, SiH4, etc.) are respectively introduced into the reaction chamber, and a silicon atomic layer is formed by epitaxial growth method as a Si channel layer with a second thickness; the above process is repeated until a stack structure of Si and Si:P is formed on the substrate.

[0022] In one possible implementation of the present application, after the substrate is placed in the reaction chamber, the reaction chamber is first kept at a first temperature and a first pressure, carrier gas, Si source (such as DCS, TCS, SiH4, etc.) and arsenic doping source (such as AsH3) are respectively introduced into the reaction chamber, and a silicon atomic layer with arsenic doping ions is formed by epitaxial growth method as a Si:As sacrificial layer with a first thickness; the reaction chamber is then kept at a second temperature and a second pressure, carrier gas and Si source (such as DCS, TCS, SiH4, etc.) are respectively introduced into the reaction chamber, and a silicon atomic layer is formed by epitaxial growth method as a Si channel layer with a second thickness; the above process is repeated until a stack structure of Si and Si:As is formed on the substrate.

[0023] In one possible implementation of the present application, after the substrate is placed in the reaction chamber, the reaction chamber is first kept at a first temperature and a first pressure, carrier gas, Si source (such as DCS, TCS, SiH4, etc.) and antimony doping source are respectively introduced into the reaction chamber, and a silicon atomic layer with antimony doping ions is formed by epitaxial growth method as a Si:Sb sacrificial layer with a first thickness; the reaction chamber is then kept at a second temperature and a second pressure, carrier gas and Si source (such as DCS, TCS, SiH4, etc.) are respectively introduced into the reaction chamber, and a silicon atomic layer is formed by epitaxial growth method as a Si channel layer with a second thickness; the above process is repeated until a stack structure of Si and Si:Sb is formed on the substrate.

[0024] Thirdly, embodiments of this application also provide an electronic device, which can be a smartphone, smart TV, laptop, or similar device. The electronic device may include a circuit board and a chip, with the chip connected to the circuit board. The chip may be a chip as described in the first aspect or various embodiments thereof, or a chip prepared using the second aspect or various embodiments thereof. Because the transistors in the aforementioned chip have good performance, the electronic device including the aforementioned chip also has good performance. Furthermore, the principle by which this electronic device solves the problem is similar to that of the aforementioned chip; therefore, the implementation of this electronic device can refer to the implementation of the aforementioned chip, and repeated details will not be elaborated further. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0026] Figure 2 for Figure 1 The structural diagram shown is a cross-sectional view along the AA' direction;

[0027] Figure 3 for Figure 1 The structural diagram shown is a cross-sectional view along the BB' direction;

[0028] Figure 4 A schematic flowchart illustrating a chip fabrication method provided in an embodiment of this application;

[0029] Figure 5a This is a schematic diagram of a chip fabrication process provided in an embodiment of this application;

[0030] Figure 5b for Figure 5a The structural diagram shown is a cross-sectional view along the AA' direction;

[0031] Figure 6a This is a schematic diagram of another chip fabrication process provided in an embodiment of this application;

[0032] Figure 6b for Figure 6a The structural diagram shown is a cross-sectional view along the AA' direction;

[0033] Figure 7a This is a schematic diagram of another chip fabrication process provided in an embodiment of this application;

[0034] Figure 7b for Figure 5a The structural diagram shown is a cross-sectional view along the AA' direction;

[0035] Figure 8aA structural schematic diagram of another process for preparing a chip provided in an embodiment of the present application is shown in FIG. 6;

[0036] Figure 8b A structural schematic diagram of another process for preparing a chip provided in an embodiment of the present application is shown in FIG. 6; Figure 8a A cross-sectional structural schematic diagram along the AA' direction of the structural schematic diagram shown in FIG. 6 is shown in FIG. 7;

[0037] Figure 8c A structural schematic diagram of another process for preparing a chip provided in an embodiment of the present application is shown in FIG. 6; Figure 8a A cross-sectional structural schematic diagram along the BB' direction of the structural schematic diagram shown in FIG. 6 is shown in FIG. 8;

[0038] Figure 9a A structural schematic diagram of another process for preparing a chip provided in an embodiment of the present application is shown in FIG. 6;

[0039] Figure 9b A structural schematic diagram of another process for preparing a chip provided in an embodiment of the present application is shown in FIG. 6; Figure 9a A cross-sectional structural schematic diagram along the BB' direction of the structural schematic diagram shown in FIG. 6 is shown in FIG. 8;

[0040] Figure 10a A structural schematic diagram of another process for preparing a chip provided in an embodiment of the present application is shown in FIG. 6;

[0041] Figure 10b A structural schematic diagram of another process for preparing a chip provided in an embodiment of the present application is shown in FIG. 6; Figure 10a A cross-sectional structural schematic diagram along the BB' direction of the structural schematic diagram shown in FIG. 6 is shown in FIG. 8;

[0042] Figure 11a A structural schematic diagram of another process for preparing a chip provided in an embodiment of the present application is shown in FIG. 6;

[0043] Figure 11b A structural schematic diagram of another process for preparing a chip provided in an embodiment of the present application is shown in FIG. 6; Figure 11a A cross-sectional structural schematic diagram along the BB' direction of the structural schematic diagram shown in FIG. 6 is shown in FIG. 8;

[0044] Figure 12a A structural schematic diagram of another process for preparing a chip provided in an embodiment of the present application is shown in FIG. 6;

[0045] Figure 12b A structural schematic diagram of another process for preparing a chip provided in an embodiment of the present application is shown in FIG. 6; Figure 12a A cross-sectional structural schematic diagram along the BB' direction of the structural schematic diagram shown in FIG. 6 is shown in FIG. 8;

[0046] Figure 13a A structural schematic diagram of another process for preparing a chip provided in an embodiment of the present application is shown in FIG. 6;

[0047] Figure 13b A structural schematic diagram of another process for preparing a chip provided in an embodiment of the present application is shown in FIG. 6; Figure 13a A cross-sectional structural schematic diagram along the BB' direction of the structural schematic diagram shown in FIG. 6 is shown in FIG. 8;

[0048] Figure 14a A structural schematic diagram of another process for preparing a chip provided in an embodiment of the present application is shown in FIG. 6;

[0049] Figure 14b for Figure 14a The structural diagram shown is a cross-sectional view along the AA' direction;

[0050] Figure 15a This is a schematic diagram of another chip fabrication process provided in an embodiment of this application;

[0051] Figure 15b for Figure 15a The structural diagram shown is a cross-sectional view along the AA' direction;

[0052] Figure 16a This is a schematic diagram of another chip fabrication process provided in an embodiment of this application;

[0053] Figure 16b for Figure 16a The structural diagram shown is a cross-sectional view along the AA' direction;

[0054] Figure 17a This is a schematic diagram of another chip fabrication process provided in an embodiment of this application;

[0055] Figure 17b for Figure 17a The structural diagram shown is a cross-sectional view along the AA' direction. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of this application clearer, a further detailed description of this application will be provided below in conjunction with the accompanying drawings. However, the exemplary embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms describing position and direction as described in this application are illustrative based on the accompanying drawings, but changes may be made as needed, and all such changes are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0057] It should be noted that specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many ways other than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below. The following descriptions are preferred embodiments for carrying out this application; however, these descriptions are for the purpose of illustrating the general principles of this application and are not intended to limit the scope of this application.

[0058] To facilitate understanding of the chip, fabrication method, and electronic device provided in the embodiments of this application, their application scenarios will be introduced first below.

[0059] The transistors provided in this application embodiment, due to the gate structure enclosing the channel, enable ideal control of the channel, forming a GAAFET. When this GAAFET is applied in a chip, it can improve the chip's performance. Furthermore, the chips provided in this application embodiment can be widely used in various electronic devices, such as those with logic devices or memory devices. Exemplarily, such electronic devices can be smartphones, smart TVs, laptops, PDAs (personal digital assistants), wearable devices with wireless communication capabilities (such as smartwatches, smart glasses, and smart bracelets), or in-vehicle devices. It should be noted that the chips proposed in this application embodiment are intended for use in, but not limited to, these and any other suitable types of electronic devices.

[0060] Currently, the common fabrication method for GAAFET devices is as follows: first, a multilayer stacked structure of Si and SiGe is epitaxially grown; then, selective etching is used, with SiGe as a sacrificial layer, to remove SiGe, leaving Si as the channel layer; or, Si is used as a sacrificial layer, to remove Si, leaving SiGe as the channel layer, and other GAAFET structures are formed on it. However, the Ge content in common SiGe materials is greater than 30%, making SiGe an alloy. This results in a heterojunction structure between SiGe and Si, leading to a significant lattice mismatch. This lattice mismatch causes stress, which can lead to dislocations (dislocations affect device reliability and performance) and warpage (warpage affects chip alignment, especially photolithography).

[0061] To address the aforementioned problems, this application proposes a chip that can avoid dislocations and warping, as well as a method for fabricating the same. The various embodiments of this application will be described in detail below.

[0062] Reference Figures 1 to 3 , Figure 1 This paper shows a schematic diagram of the structure of a chip provided in one embodiment of the present application. Figure 2 This application shows Figure 1 A schematic diagram of the cross-sectional structure along the AA' direction. Figure 3 This application shows Figure 1 A cross-sectional view along the BB' direction is shown in the diagram. The chip in this application may have one or more transistors, and each transistor may have one or more channel structures. Figures 1 to 3The three channel structures 30_1-30_3 are only taken as an example of being stacked in one transistor.

[0063] With reference to Figures 1 to 3 In some embodiments provided by the present application, the channel structure 30_1 can include a sacrificial layer 31_1 and a channel layer 32_1 stacked on the substrate 10, the channel structure 30_2 can include a sacrificial layer 31_2 and a channel layer 32_2 stacked on the substrate 10, and the channel structure 30_3 can include a sacrificial layer 31_3 and a channel layer 32_3 stacked on the substrate 10. The sacrificial layer 31_1 is closest to the substrate 10 compared with the channel layer 32_1, the channel layer 32_1 is located on the side of the sacrificial layer 31_1 away from the substrate 10, the sacrificial layer 31_2 is located on the side of the channel layer 32_1 away from the substrate 10, the channel layer 32_2 is located on the side of the sacrificial layer 31_2 away from the substrate 10, the sacrificial layer 31_3 is located on the side of the channel layer 32_2 away from the substrate 10, and the channel layer 32_3 is located on the side of the sacrificial layer 31_3 away from the substrate 10. In addition, each of the channel layers 32_1-32_3 can have a first region S and a second region D, and a channel region G between the first region S and the second region D. In addition, the first regions S in the channel layers 32_1-32_3 can overlap in the orthographic projection of the substrate 10, the second regions D in the channel layers 32_1-32_3 can overlap in the orthographic projection of the substrate 10, and the channel regions G in the channel layers 32_1-32_3 can overlap in the orthographic projection of the substrate 10. It should be noted that in the actual process, due to the limitation of process conditions or other factors, the above-mentioned overlap may not be completely overlapped, and there may be some deviation, so as long as the above-mentioned overlap relationship approximately meets the above-mentioned condition, it belongs to the protection scope of the present application. For example, the above-mentioned overlap can be an allowed overlap within an error allowable range.

[0064] With reference to Figures 1 to 3 In some embodiments provided by the present application, the chip can include a substrate 10 and transistors and isolation structures 20 on the substrate. The substrate 10 has a shallow trench isolation region to define an area covered by the substrate 10 on which the channel structure is located, and the isolation structures 20 are arranged in the shallow trench isolation region. In this way, the channel structures of different transistors are isolated in the area on the substrate 10 by the isolation structures 20.

[0065] With reference to Figures 1 to 3In some embodiments provided in the present application, the transistor can include the channel structure 30_1, the channel structure 30_2, the channel structure 30_3, the gate 40, the source-drain electrode layer 90, the barrier layer 82 and the gate oxide layer 50 located on the substrate 10. The channel structure 30_1 is located on the side of the isolation structure 20 away from the substrate 10, the channel structure 30_2 is located on the side of the channel structure 30_1 away from the substrate 10, the channel structure 30_3 is located on the side of the channel structure 30_2 away from the substrate 10, the gate 40 is located on the side of the isolation structure 20 away from the substrate 10 and surrounds the channel region G of the channel layer 32_1-32_3, the gate oxide layer 50 is located between the gate 40 and the channel layer 32_1-32_3 to isolate the gate 40 and the channel region G by the gate oxide layer 50. The barrier layer 82 is located between the gate 40 and the source-drain electrode layer 90 to isolate the gate 40 and the source-drain electrode layer 90 by the barrier layer 82. In addition, the orthogonal projection of the source-drain electrode layer 90 on the substrate 10 covers the first region S and the second region D of the channel layer 32_1-32_3 on the substrate 10, and the orthogonal projection of the source-drain electrode layer 90 on the substrate 10 does not overlap with the orthogonal projection of the gate 40 on the substrate 10. For example, the source-drain electrode layer 90 covering the first region S can be used as the source electrode for transmitting the electrical signal, and the source-drain electrode layer 90 covering the second region D can be used as the drain electrode for transmitting the electrical signal. Alternatively, the source-drain electrode layer 90 covering the first region S can be used as the drain electrode for transmitting the electrical signal, and the source-drain electrode layer 90 covering the second region D can be used as the source electrode for transmitting the electrical signal.

[0066] Referring to Figures 1 to 3 In some embodiments provided in the present application, the orthogonal projection of the channel region G of the channel layer 32_1-32_3 on the substrate 10 does not overlap with the orthogonal projection of the sacrificial layer 31_1-31_3 on the substrate 10. That is, the orthogonal projection of the channel region G of the channel layer 32_1-32_3 on the substrate 10 is completely non-overlapping with the orthogonal projection of the sacrificial layer 31_1-31_3 on the substrate 10.

[0067] Referring to Figures 1 to 3 In some embodiments provided in the present application, the orthogonal projection of the first region S and the second region D of the channel layer 32_1-32_3 on the substrate 10 overlaps with the orthogonal projection of the sacrificial layer 31_1-31_3 on the substrate 10. For example, the orthogonal projection of the first region S and the second region D of the channel layer 32_1-32_3 on the substrate 10 overlaps with the orthogonal projection of the sacrificial layer 31_1-31_3 on the substrate 10. That is, the orthogonal projection of the first region S and the second region D of the channel layer 32_1-32_3 on the substrate 10 has the same shape and size as the orthogonal projection of the sacrificial layer 31_1-31_3 on the substrate 10.

[0068] It should be noted that in actual processes, due to the limitation of process conditions or other factors, the above non-overlapping relationship and overlapping relationship may have some deviations, so as long as the above non-overlapping relationship and overlapping relationship are within the error allowable range, they all belong to the protection scope of the present application.

[0069] With reference to Figures 1 to 3 In some embodiments provided in the present application, the channel layers 32_1-32_3 comprise semiconductor materials, and the sacrificial layers 31_1-31_3 comprise semiconductor materials and doping ions. In addition, the semiconductor materials in the sacrificial layers 31_1-31_3 and the semiconductor materials in the channel layers 32_1-32_3 are the same. Since the content of the doping ions in the sacrificial layers 31_1-31_3 is not more than 5%, the content of the doping ions in the sacrificial layers 31_1-31_3 is as small as possible, so that after the doping ions are doped into the semiconductor materials, the semiconductor materials and the doping ions do not form an alloy, but the doped semiconductor materials and the undoped semiconductor materials are regarded as different doping concentrations of the same kind of semiconductor materials. That is, the doped semiconductor materials in the sacrificial layers 31_1-31_3 and the undoped semiconductor materials in the channel layers 32_1-32_3 can be regarded as different doping concentrations of the same kind of semiconductor materials, so that the adjacent sacrificial layers 31_1-31_3 and channel layers 32_1-32_3 can form a homojunction, and the stress between the adjacent channel layers 32_1-32_3 and the sacrificial layers 31_1-31_3 is reduced, thereby reducing the possibility of generating dislocations and warping. Specifically, the sacrificial layer 31_1 and the channel layer 32_1 can form a homojunction, the channel layer 32_1 and the sacrificial layer 31_2 can form a homojunction, the sacrificial layer 31_2 and the channel layer 32_2 can form a homojunction, the channel layer 32_2 and the sacrificial layer 31_3 can form a homojunction, and the sacrificial layer 31_3 and the channel layer 32_3 can form a homojunction. Therefore, the lattice mismatch between the sacrificial layer 31_1 and the channel layer 32_1 is small, the lattice mismatch between the channel layer 32_1 and the sacrificial layer 31_2 is small, the lattice mismatch between the sacrificial layer 31_2 and the channel layer 32_2 is small, the lattice mismatch between the channel layer 32_2 and the sacrificial layer 31_3 is small, and the lattice mismatch between the sacrificial layer 31_3 and the channel layer 32_3 is small. Therefore, the stress between the channel layers 32_1-32_3 and the sacrificial layers 31_1-31_3 is also relatively small, thereby reducing the possibility of generating dislocations and warping.

[0070] In the prior art, a stack structure of a sacrificial layer and a channel layer is usually formed by using a SiGe and Si stack arrangement. The common SiGe material has a Ge content greater than 30%, which causes the SiGe material to be an alloy, so that the SiGe and Si are heterojunctions, and further causes the existing lattice mismatch stress to form dislocations (which affect device reliability and performance) and warping (which affects IC process alignment, especially photolithography) due to the relatively large lattice mismatch between the SiGe and Si. By forming a homojunction between the sacrificial layer and the channel layer, the present application can make the lattice mismatch between the sacrificial layer and the channel layer smaller, thereby reducing the possibility of generating dislocations and warping.

[0071] With reference to Figures 1 to 3 In some embodiments provided by the present application, the channel layers 32_1-32_3 can be arranged to extend along a first direction F1, and the sacrificial layers 31_1-31_3 and the channel layers 32_1-32_3 can be arranged to alternately arrange along a second direction F2. The gate 40 can be arranged to extend along a third direction F3. The first direction F1, the second direction F2, and the third direction F3 are perpendicular to each other.

[0072] In some embodiments provided by the present application, the content of the dopant ions in the sacrificial layers 31_1-31_3 can be not greater than 5%. In this way, the content of the dopant ions in the sacrificial layers 31_1-31_3 can be as small as possible, further avoiding the formation of an alloy after the dopant ions are doped in the sacrificial layers 31_1-31_3, thereby further ensuring that a homojunction structure is formed between the sacrificial layers 31_1-31_3 and the channel layers 32_1-32_3. Exemplarily, the content of the dopant ions in the sacrificial layers 31_1-31_3 can also be not greater than 2%. Alternatively, the content of the dopant ions in the sacrificial layers 31_1-31_3 can also be not greater than 1%.

[0073] In some embodiments provided by the present application, the doping concentration of the dopant ions in the sacrificial layers 31_1-31_3 can be not less than 1E16 atom / cm 3 and not greater than 1E22 atom / cm 3 . In this way, it can be indicated that the above-mentioned dopant ions are doped in the sacrificial layers 31_1-31_3, and the above-mentioned dopant ions are not doped in the channel layers 32_1-32_3, so that the semiconductor material doped in the sacrificial layers 31_1-31_3 and the semiconductor material not doped in the channel layers 32_1-32_3 can be regarded as different doping concentrations of the same semiconductor material, thereby further ensuring that a homojunction structure is formed between the sacrificial layers 31_1-31_3 and the channel layers 32_1-32_3.

[0074] In one possible implementation of the present application, the doping concentration of the dopant ions in the sacrificial layers 31_1-31_3 can be not less than 1E17 atom / cm3 and no more than 1E21 atom / cm 3 Optionally, the doping concentration of the doping ions in the sacrificial layer 31_1-31_3 is no less than 1E18 atom / cm 3 and no more than 1E20 atom / cm 3 Exemplarily, the doping concentration of the doping ions in the sacrificial layer 31_1-31_3 can be set as 1E16 atom / cm 3 , 5E16 atom / cm 3 , 1E17 atom / cm 3 , 5E17 atom / cm 3 , 1E18 atom / cm 3 , 5E18 atom / cm 3 , 1E19 atom / cm 3 , 5E19 atom / cm 3 , 1E20 atom / cm 3 , 5E20 atom / cm 3 , 1E21 atom / cm 3 , 5E21 atom / cm 3 or 1E22 atom / cm 3 In actual applications, the specific value of the doping concentration of the doping ions in the sacrificial layer 31_1-31_3 can be determined according to the requirements of actual applications, which is not limited herein.

[0075] In a possible implementation of the present application, when the doping concentration of the doping ions in the sacrificial layer 31_1-31_3 is 1E22 atom / cm 3 , the content of the doping ions in the sacrificial layer 31_1-31_3 is approximately equal to 5%. When the doping concentration of the doping ions in the sacrificial layer 31_1-31_3 is 1E21 atom / cm 3 , the content of the doping ions in the sacrificial layer 31_1-31_3 is approximately equal to 2%. When the doping concentration of the doping ions in the sacrificial layer 31_1-31_3 is 1E20 atom / cm 3 , the content of the doping ions in the sacrificial layer 31_1-31_3 is approximately equal to 1%. When the doping concentration of the doping ions in the sacrificial layer 31_1-31_3 is less than 1E22 atom / cm 3 and greater than 1E21 atom / cm 3 , the content of the doping ions in the sacrificial layer 31_1-31_3 is less than 5% and greater than 2%. When the doping concentration of the doping ions in the sacrificial layer 31_1-31_3 is less than 1E21 atom / cm 3 and greater than 1E20 atom / cm 3When the doping concentration of the doping ions in the sacrificial layers 31_1-31_3 is less than 1E20 atom / cm 3 When the doping concentration of the doping ions in the sacrificial layers 31_1-31_3 is less than 1E20 atom / cm

[0076] In some embodiments provided by the present application, the semiconductor material in the channel layers 32_1-32_3 includes at least one of an elemental semiconductor, an inorganic compound semiconductor, and an organic compound semiconductor. For example, the semiconductor material in the channel layers 32_1-32_3 can be Si. In specific implementations, the semiconductor material in the channel layers 32_1-32_3 is not limited to Si, but can also be a semiconductor such as SiGe, Ge, etc., a compound semiconductor such as GaAs, InP, GaN, SiC, etc., an oxide semiconductor such as GaO, ZnO, etc., a ferroelectric, and a two-dimensional material, etc. In actual applications, the specific implementation of the semiconductor material in the channel layers 32_1-32_3 can be determined according to the requirements of actual applications, which is not limited herein.

[0077] In some embodiments provided by the present application, the doping ions can be N-type doping ions. For example, the N-type doping ions can include at least one of phosphorus ions, arsenic ions, and antimony ions. For example, when the semiconductor material in the channel layers 32_1-32_3 is Si, and the N-type doping ions are phosphorus ions, the phosphorus ions can be doped in Si when the sacrificial layers 31_1-31_3 are formed, so as to form the sacrificial layers 31_1-31_3 in the form of Si:P. When the N-type doping ions are arsenic ions, the arsenic ions can be doped in Si when the sacrificial layers 31_1-31_3 are formed, so as to form the sacrificial layers 31_1-31_3 in the form of Si:As. When the N-type doping ions are antimony ions, the antimony ions can be doped in Si when the sacrificial layers 31_1-31_3 are formed, so as to form the sacrificial layers 31_1-31_3 in the form of Si:Sb.

[0078] It should be noted that the etching rate of the P-type doped semiconductor material is slow at present. If the P-type doped semiconductor material is used as the sacrificial layer in the present application, a long time is required to etch the sacrificial layer. Although the etching selectivity ratio between the sacrificial layer and the channel layer is provided, the time required to etch the P-type doped semiconductor material is long, and the channel layer is in the etching environment for a long time, which may cause damage to the channel layer and affect the carrier mobility and lifetime of the channel layer. In the embodiments of the present application, the N-type doped ions are doped into the semiconductor material to form the sacrificial layer. When the sacrificial layer is etched, a high etching rate can be achieved, and the time required to etch the sacrificial layer corresponding to the channel region is short, so that the channel layer is in the etching environment for a short time, thereby avoiding damage to the channel layer and improving the carrier mobility and lifetime of the channel layer.

[0079] In the actual process, when SiGe is used as the sacrificial layer, a large thickness and a high Ge ratio of SiGe are required to obtain a better etching result, but this increases the defect density and is not conducive to the size reduction of the GAAFET device. Moreover, after the SiGe is etched, the by-products generated are deposited at the outlet, which affects the contact between the etching solution and the sacrificial layer, and the etching effect cannot be achieved. In the present application, the electron concentration in the N-type doped semiconductor material (for example, Si:P) in the homojunction can be controlled by doping to control and improve the etching rate of the sacrificial layer. In addition, in the present application, the thickness of the N-type doped semiconductor material (for example, Si:P) in the homojunction can also be controlled to control and improve the etching rate of the sacrificial layer.

[0080] In some embodiments provided in the present application, the adjacent sacrificial layers 31_1-31_3 and the channel layers 32_1-32_3 can form an NN-type homojunction, a PP-type homojunction or a PN-type homojunction. In the actual process, the specific form of the homojunction can be determined according to the semiconductor material and the doped ions in the channel layers 32_1-32_3, which is not limited herein.

[0081] In some embodiments provided in the present application, the material forming the source-drain electrode layer can be a metal material. For example, the metal material forming the source-drain electrode layer can include W, Al, Ti, Cu, Mo or Pt. In actual applications, the material of the source-drain electrode layer can be determined according to the requirements of actual applications, which is not limited herein.

[0082] In some embodiments provided in the present application, the material of the barrier layer can be an insulating material. For example, the insulating material forming the barrier layer can include silicon oxide, silicon nitride, etc. In actual applications, the material of the barrier layer can be determined according to the requirements of actual applications, which is not limited herein.

[0083] In some embodiments provided in this application, the gate material can be polycrystalline silicon or other materials with good conductivity, such as metals (e.g., W, Al, Ti, Cu, Mo, or Pt), and is not limited thereto. It should be noted that the comparison of dopant ion content in the sacrificial layer and channel layer in this application refers only to the comparison of the content of doped N-type ions (e.g., phosphorus, arsenic, and antimony ions), and not a comparison of the content of the original impurity components in the semiconductor material when the sacrificial layer and channel layer are not doped with N-type dopant ions.

[0084] Reference Figure 4 , Figure 4 This is a schematic flowchart illustrating a chip fabrication method according to an embodiment of this application. The fabrication method may include the following steps:

[0085] S101, Provide a substrate 10.

[0086] In some embodiments, the substrate 10 may be made of suitable elemental semiconductors such as silicon, diamond, or germanium; suitable alloys or compound semiconductors such as group IV compound semiconductors (e.g., silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn), and group III-V compound semiconductors (e.g., gallium arsenide, indium gallium arsenide, indium arsenide, indium phosphide, indium antimonide, gallium arsenide phosphide, or indium gallium phosphide). Insulating materials such as glass may also be used as the substrate. Exemplarily, an N-type Si substrate is used as an example in this application.

[0087] S102. Sacrificial layers and channel layers are epitaxially grown alternately on substrate 10 to form a stacked structure.

[0088] In some examples, with Figure 1 The structure of the chip shown is an example. The semiconductor materials of the sacrificial layers 31_1 to 31_3 and the channel layers 32_1 to 32_3 are Si, and the doping ions of the sacrificial layers 31_1 to 31_3 are phosphorus ions.

[0089] Reference Figure 5a and Figure 5bAs shown, the sacrificial layer 31_1 can be epitaxially grown on the substrate 10. Exemplarily, the cleaned substrate 10 is placed in a reaction chamber (such as a plasma vapor deposition reaction chamber), the temperature of the reaction chamber is rapidly raised to a first temperature, the pressure is adjusted to a first pressure, and the reaction chamber is kept at the first temperature and the first pressure. And, while the reaction chamber is kept at the first temperature and the first pressure, the carrier gas, the silicon source and the N-type doping gas are respectively introduced into the reaction chamber, and a silicon atomic layer with N-type doping ions with a first thickness is formed as the sacrificial layer 31_1 according to a first growth rate by epitaxial growth method.

[0090] Exemplarily, the first temperature can be in the range of 400-900°C. Alternatively, the first temperature can be in the range of 600-800°C. In specific implementation, the first temperature can be set to 400°C, 450°C, 500°C, 550°C, 600°C, 650°C, 700°C, 750°C, 800°C or 900°C. In actual application, the specific value of the first temperature can be determined according to the actual application requirements, which is not limited here.

[0091] Exemplarily, the first pressure can be in the range of 0.1-1000 Torr (1 Torr = 133.3 Pa). Alternatively, the first pressure can be in the range of 1-900 Torr. In specific implementation, the first pressure can be set to 0.1 Torr, 1 Torr, 5 Torr, 10 Torr, 100 Torr, 500 Torr, 700 Torr, 760 Torr, 800 Torr, 900 Torr or 1000 Torr. In actual application, the specific value of the first pressure can be determined according to the actual application requirements, which is not limited here.

[0092] Exemplarily, the first growth rate can be in the range of 0.01-10 μm / min. Alternatively, the first growth rate can be in the range of 0.1-5 μm / min. In specific implementation, the first growth rate can be set to 0.01 μm / min, 0.1 μm / min, 1 μm / min, 3 μm / min, 5 μm / min or 10 μm / min. In actual application, the specific value of the first growth rate can be determined according to the actual application requirements, which is not limited here.

[0093] Exemplarily, the first thickness can be in a range from 1 nm to 100 nm. Alternatively, the first thickness can be in a range from 10 nm to 90 nm. In a specific implementation, the first thickness can be set to 1 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm or 100 nm. In an actual application, a specific value of the first pressure can be determined according to a requirement of an actual application, which is not limited herein.

[0094] Exemplarily, the carrier gas can include H2. Alternatively, a flow rate of the carrier gas can be in a range from 10000 sccm to 50000 sccm. For example, the flow rate of the carrier gas can be set to 10000 sccm, 20000 sccm, 30000 sccm, 40000 sccm or 50000 sccm. In an actual application, a specific value of the flow rate of the carrier gas can be determined according to a requirement of an actual application, which is not limited herein.

[0095] Exemplarily, the silicon source can include one or more of SiH4, Si2H6, Si3H8, SiHCl3 (i.e., TCS) and SiH2Cl2 (i.e., DCS). Alternatively, a flow rate of the silicon source can be in a range from 100 sccm to 300 sccm. For example, the flow rate of the silicon source can be set to 100 sccm, 200 sccm or 300 sccm. In an actual application, a specific value of the flow rate of the silicon source can be determined according to a requirement of an actual application, which is not limited herein.

[0096] Exemplarily, the N-type doping gas can be a phosphorus doping source. Alternatively, the phosphorus doping source can include PH3. Alternatively, a flow rate of the doping gas is one percent of a flow rate of the carrier gas, according to a flow rate range of the carrier gas in a range from 10000 sccm to 50000 sccm, a flow rate range of the doping gas can be in a range from 100 sccm to 500 sccm.

[0097] Referring to Figure 6a With Figure 6b As shown in FIG. 3, the channel layer 32_1 can be epitaxially grown outside the sacrificial layer 31_1. Exemplarily, the temperature of the reaction chamber is quickly adjusted to a second temperature, and the pressure is adjusted to a second pressure, so that the reaction chamber is kept at the second temperature and the second pressure. And when the reaction chamber is kept at the second temperature and the second pressure, the carrier gas and the silicon source are respectively introduced into the reaction chamber, and a silicon atom layer with a second thickness is formed as the channel layer 32_1 according to a second growth rate by using an epitaxial growth method.

[0098] Exemplarily, the second temperature can be in a range from 400 °C to 900 °C. Alternatively, the second temperature can be in a range from 600 °C to 800 °C. In implementation, the second temperature can be set to 400 °C, 450 °C, 500 °C, 550 °C, 600 °C, 650 °C, 700 °C, 750 °C, 800 °C or 900 °C. In actual application, the specific value of the second temperature can be determined according to the requirement of actual application, which is not limited herein. In some examples, the first temperature can be the same as the second temperature, so that the temperature in the reaction chamber does not need to be adjusted additionally after the adjustment of the first temperature.

[0099] Exemplarily, the second pressure can be in a range from 0.1 Torr to 1000 Torr. Alternatively, the second pressure can be in a range from 1 Torr to 900 Torr. In implementation, the second pressure can be set to 0.1 Torr, 1 Torr, 5 Torr, 10 Torr, 100 Torr, 500 Torr, 700 Torr, 760 Torr, 800 Torr, 900 Torr or 1000 Torr. In actual application, the specific value of the second pressure can be determined according to the requirement of actual application, which is not limited herein. In some examples, the first pressure can be the same as the second pressure, so that the pressure in the reaction chamber does not need to be adjusted additionally after the adjustment of the first pressure.

[0100] Exemplarily, the second growth rate can be in a range from 0.01 μm / min to 10 μm / min. Alternatively, the second growth rate can be in a range from 0.1 μm / min to 5 μm / min. In implementation, the second growth rate can be set to 0.01 μm / min, 0.1 μm / min, 1 μm / min, 3 μm / min, 5 μm / min or 10 μm / min. In actual application, the specific value of the second growth rate can be determined according to the requirement of actual application, which is not limited herein. In some examples, the first growth rate can be the same as the second growth rate, so that the sacrificial layer and the channel layer can be epitaxially grown according to the same growth rate, further reducing the lattice mismatch between the sacrificial layer and the channel layer.

[0101] Exemplarily, the second thickness can be in a range from 1 nm to 100 nm. Alternatively, the second thickness can be in a range from 10 nm to 90 nm. In implementations, the second thickness can be set to 1 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm or 100 nm. In actual applications, the specific value of the second thickness can be determined according to the requirements of actual applications, which is not limited herein. In some examples, the first thickness can be the same as the second thickness, so that the thicknesses of the epitaxially grown sacrificial layer and the channel layer are the same, and the lattice mismatch between the sacrificial layer and the channel layer is further reduced.

[0102] Exemplarily, the carrier gas can include H2. Alternatively, the flow rate of the carrier gas can be in a range from 10000 sccm to 50000 sccm. For example, the flow rate of the carrier gas can be set to 10000 sccm, 20000 sccm, 30000 sccm, 40000 sccm or 50000 sccm. In actual applications, the specific value of the flow rate of the carrier gas can be determined according to the requirements of actual applications, which is not limited herein. In some examples, the carrier gas for forming the sacrificial layer and the channel layer and the flow rate of the carrier gas can be the same, and the lattice mismatch between the sacrificial layer and the channel layer is further reduced.

[0103] Exemplarily, the silicon source can include one or more of SiH4, Si2H6, Si3H8, SiHCl3 (i.e., TCS) and SiH2Cl2 (i.e., DCS). Alternatively, the flow rate of the silicon source can be in a range from 100 sccm to 300 sccm. For example, the flow rate of the silicon source can be set to 100 sccm, 200 sccm or 300 sccm. In actual applications, the specific value of the flow rate of the silicon source can be determined according to the requirements of actual applications, which is not limited herein. In some examples, the silicon source for forming the sacrificial layer and the channel layer and the flow rate of the silicon source can be the same, and the lattice mismatch between the sacrificial layer and the channel layer is further reduced.

[0104] Referring to Figure 7a With Figure 7b , the above-mentioned Figure 5a With Figure 5b and Figure 6a With Figure 6b The corresponding preparation process can epitaxially grow the sacrificial layer 31_2, the channel layer 32_2, the sacrificial layer 31_3 and the channel layer 32_3 in sequence on the channel layer 32_1 to form a stacked structure.

[0105] S103, after etching from the exposed surface of the stacked structure to the substrate 10, an isolation structure is formed to define the area where the channel structure in the stacked structure is located.

[0106] Referring to Figures 8a to 8c A plurality of base axes 60 are formed on the channel layer 32_3 of the stack structure, and the extending direction of the base axes 60 is the same as the extending direction of the channel layer to be formed. Optionally, the base axes 60 can be made of polysilicon material. Of course, other materials can also be used to make the base axes 60, which are not limited here. In the actual process, a full-surface base axis film layer can be formed on the channel layer 32_3 of the stack structure, and then a plurality of base axes 60 are obtained on the channel layer 32_3 of the stack structure by etching process. It should be noted that Figures 8a to 8c Only one base axis 60 is shown.

[0107] Referring to Figure 9a With Figure 9b Side walls 70 are formed at the side walls of the base axes. Optionally, a full-surface side wall film layer can be made on the stack structure by using silicon nitride material, and then the side wall film layer is etched. Due to the geometric effect of the side walls of the base axes 60, the material of the side wall film layer at the side walls of the base axes 60 will not be etched, so that the side walls 70 are formed at the side walls of the base axes 60.

[0108] Referring to Figure 10a With Figure 10b The plurality of base axes 60 are removed by etching process, and the side walls 70 are retained.

[0109] Referring to Figure 11a With Figure 11b With the plurality of side walls 70 as a shield, etching is performed from the exposed surface of the stack structure (i.e. the exposed surface of the channel layer 32_3) in the direction from the channel layer 32_3 to the substrate 10. After etching into the substrate 10, a shallow trench isolation region is formed after etching the substrate 10 by a first distance (which can be determined according to the distance required for forming the shallow trench isolation region). The region where the channel structure in the stack structure is located is defined. Then, the shallow trench isolation region is filled with insulating material such as silicon oxide or silicon nitride, and the upper surface of the filled silicon oxide or silicon nitride is substantially flush with the upper surface of the substrate 10 that is not etched, forming an isolation structure 20 such as a shallow trench isolation structure. That is, the region covered by the side walls 70 is the region where the first region S, the second region D and the channel region G of the channel layers 32_1-32_3 are located. Optionally, the isolation structure 20 can divide the substrate 10 into a plurality of regions, which can be distributed in parallel or arranged arbitrarily according to the region where the channel layers 32_1-32_3 are located. It should be noted that the first distance can be determined according to the requirements of actual application, which is not limited here.

[0110] Referring to Figure 12a With Figure 12b The plurality of side walls 70 are removed by etching process to obtain the stack structure of the region where the channel layers 32_1-32_3 are located.

[0111] S104, referring to Figure 13a with Figure 13b The pseudo gate structure 81 is formed across the channel structure. The pseudo gate structure 81 covers part of the top wall and part of the side wall of the channel structure, and the extension direction of the pseudo gate structure 81 is perpendicular to the extension direction of the channel structure. That is, the extension direction of the pseudo gate structure 81 can be the same as the extension direction of the gate 40.

[0112] Exemplarily, the pseudo gate structure 81 can be made of polysilicon. In the actual process, a full-area pseudo gate film layer can be formed on the substrate 10, and then a plurality of pseudo gate structures 81 spaced from each other can be obtained by etching process. Then, a barrier layer 82 can also be formed on the side wall of the pseudo gate structure 81. The barrier layer 82 can be made of insulating materials such as silicon oxide and silicon nitride. Exemplarily, in the actual process, a silicon nitride material can be used to make a full-area barrier layer film layer on the semiconductor substrate 10, and then the barrier layer film layer is etched in full area. Due to the geometric effect of the side wall of the pseudo gate structure 81, the material of the barrier layer film layer at the side wall of the pseudo gate structure 81 will not be etched off, so as to form the barrier layer 82 at the side wall of the pseudo gate structure 81.

[0113] Exemplarily, the thickness of the pseudo gate structure 81 and the thickness of the barrier layer 82 need to be 5nm-100nm more than the thickness of the stack structure. In actual application, the specific values of the thickness of the pseudo gate structure 81 and the thickness of the barrier layer 82 can be determined according to the requirements of actual application, which are not limited herein.

[0114] It should be noted that the region of the channel layer 32_1-32_3 covered by the pseudo gate structure 81 is the channel region G, and the region not covered by the pseudo gate structure 81 is the source region S and the drain region D.

[0115] S105, referring to Figure 14a with Figure 14b The source-drain electrode layer 90 is formed on the exposed channel structure by taking the pseudo gate structure 81 as a mask. Exemplarily, in the actual process, the metal material is deposited on the exposed channel structure by taking the pseudo gate structure 81 and the barrier layer 82 as a mask, to form the source-drain electrode layer 90 covering the first region S and the second region D.

[0116] Exemplarily, the source-drain electrode layer 90 covering the first region S can be used as the source electrode for transmitting the electrical signal, and the source-drain electrode layer 90 covering the second region D can be used as the drain electrode for transmitting the electrical signal. Alternatively, the source-drain electrode layer 90 covering the first region S can be used as the drain electrode for transmitting the electrical signal, and the source-drain electrode layer 90 covering the second region D can be used as the source electrode for transmitting the electrical signal.

[0117] Exemplarily, the metal material forming the source-drain electrode layer can include W, Al, Ti, Cu, Mo or Pt. In practical applications, the material of the source-drain electrode layer can be determined according to the requirements of practical applications, which is not limited herein.

[0118] Afterwards, referring to Figure 15a and Figure 15b The first interlayer dielectric layer 110 can also be deposited on the substrate 10 to form a full-area layer, so as to insulate the source-drain electrode layers of the different first regions S and second regions D.

[0119] S106, the sacrificial layers in the pseudo-gate structure and the area covered by the pseudo-gate structure are removed, and the remaining sacrificial layers are reserved, so as to form a gate opening and expose the channel regions G of the channel layers.

[0120] Referring to Figure 16a and Figure 16b The pseudo-gate structure 81 and the first interlayer dielectric layer 110 covering the pseudo-gate structure 81 can be removed by etching, so as to expose the areas where the sacrificial layers 31_1-31_3 and the channel layers 32_1-32_3 covered by the pseudo-gate structure 81 are located. Then, the exposed areas where the sacrificial layers 31_1-31_3 are located can be removed by selective etching, and the exposed areas where the channel layers 32_1-32_3 are located are reserved, that is, the exposed areas where the channel layers 32_1-32_3 are located are the channel regions G. Since the sacrificial layers 31_1-31_3 in the remaining areas are shielded by the source-drain electrode layer and the barrier layer 82, the sacrificial layers 31_1-31_3 in these areas will not be etched, so that the sacrificial layers 31_1-31_3 in the areas shielded by the source-drain electrode layer 90 and the barrier layer 82 can be reserved. That is, the source-drain electrode layer 90 and the barrier layer 82 cover the projections of the reserved sacrificial layers 31_1-31_3 on the substrate.

[0121] Exemplarily, the selective etching process can be dry etching. Specifically, Cl2 and plasma gas can be used to remove the exposed areas where the sacrificial layers 31_1-31_3 in the form of Si:P are located by using plasma etching.

[0122] Exemplarily, the selective etching process can be wet etching. Specifically, H3PO4 solution or H2SO4 and NH4OH solution can be used to remove the exposed areas where the sacrificial layers 31_1-31_3 in the form of Si:P are located.

[0123] It should be noted that, in the present application, the channel layer is grown by Si gas phase epitaxy, and the Si:P form of the sacrificial layer is grown by Si gas phase epitaxy and doped by PH3. By controlling the flow rate of the gas filled into the reaction chamber, the doping concentration of P can be controlled to be as high as 4E20 atom / cm 3 and as low as 1E18 atom / cm 3 In this way, the lattice mismatch between the adjacent channel layer and the sacrificial layer is small, and the formation of defect dislocations is avoided.

[0124] In addition, in the Si:P form of the sacrificial layer, the doping concentration of P can be as high as 4E20 atom / cm 3 and as low as 1E18 atom / cm 3 In this way, after P is doped in Si, an N-type semiconductor is formed, and there are more free electrons. The sacrificial layer is etched by using a chlorine-based material. Under the action of electrons, chlorine becomes chloride ions, so it is easy to incorporate and corrode the Si material in the sacrificial layer doped with P, but not to corrode the Si material in the channel layer which is not doped with P. Therefore, the etching rate of the sacrificial layer can be much higher than that of the channel layer which is not doped with P, thereby realizing selective etching.

[0125] It should be noted that, in the formation of the Si:As form of the sacrificial layer 31_1-31_3, the N-type doping gas can be an arsenic doping source. Alternatively, the arsenic doping source can include AsH3. The remaining preparation process can refer to the preparation process of forming the Si:P form of the sacrificial layer 31_1-31_3 described above, and will not be repeated here.

[0126] It should be noted that, in the formation of the Si:Sb form of the sacrificial layer 31_1-31_3, the N-type doping gas can be an antimony doping source. The remaining preparation process can refer to the preparation process of forming the Si:P form of the sacrificial layer 31_1-31_3 described above, and will not be repeated here.

[0127] S107, the channel region G of the channel layer is subjected to oxidation treatment to form a gate oxide layer 50. Illustratively, in the actual process, the surface of the channel region G of the exposed channel layer 32_1-32_3 can be subjected to oxidation treatment, so that the surface of the channel region G of the channel layer 32_1-32_3 forms a gate oxide layer 50.

[0128] Exemplarily, the oxidation treatment process can be performed in a plasma-containing environment (such as decoupled plasma oxidation or rapid thermal oxidation), a thermal environment (such as a furnace), or a thermal plasma environment. The oxidation treatment process can be performed by using an oxygen-containing gas mixture in the treatment environment to form silicon oxide on the surface of the channel region G without damaging the lattice structure formed by Si atoms inside the channel region G. In one embodiment, the oxygen-containing gas mixture includes at least one of an oxygen-containing gas with or without an inert gas. Suitable examples of the oxygen-containing gas include O2, O3, H2O, NO2, N2O, steam, water vapor, and the like. Suitable examples of the inert gas supplied together with the treatment gas mixture include at least one of Ar, He, Kr, and the like. In an exemplary implementation, the oxygen-containing gas supplied in the oxygen-containing gas mixture is O2 gas with a flow rate of between about 50 sccm and about 1000 sccm.

[0129] S108, referring to Figure 17a with Figure 17b In the gate opening, a gate 40 is formed around the channel region G disposed in the channel layer. Exemplarily, in the actual process, polycrystalline silicon can be used to deposit the gate 40.

[0130] It should be noted that in the present application, deposition processes can be used to form various structures in the chip. Exemplarily, the deposition processes are, for example, but not limited to, epitaxial growth processes, vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE). Other deposition processes can also be used, such as chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), combinations thereof, and the like.

[0131] It should be noted that the cross-sectional structure schematic diagram in the AA' direction in the present application is a cross-sectional structure schematic diagram of the GAAFET in the same plane (for example, the plane defined by the directions F1 and F2) in the chip. The cross-sectional structure schematic diagram in the BB' direction in the present application is a cross-sectional structure schematic diagram of the GAAFET in the same plane (for example, the plane defined by the directions F1 and F3) in the chip.

[0132] Exemplarily, the above-mentioned etching process can be a dry etching process or a wet etching process, which is not limited herein.

[0133] The embodiment of the present application further provides an electronic device, which comprises a circuit board (such as a printed circuit board) and any one of the chips provided in the above-mentioned embodiments of the present application, and the chip is connected with the circuit board. Since the principle for solving problems of the electronic device is similar to that of the above-mentioned chip, the implementation of the electronic device can be referred to the implementation of the above-mentioned chip, and the repeated parts will not be described herein.

[0134] Obviously, various modifications and changes can be made to the present application by those skilled in the art without departing from the spirit and scope of the present application. Thus, it is intended that the present application cover the modifications and changes of this application or its equivalents.

Claims

1. A chip, characterized by The application relates to a transistor, comprising: a substrate; a transistor disposed on the substrate; wherein the transistor comprises: at least one channel structure on the substrate; wherein the channel structure comprises a sacrificial layer and a channel layer which are disposed on the substrate in a stack manner; a channel region of the channel layer does not overlap with a projection of the sacrificial layer on the substrate, and a first region and a second region of the channel layer overlap with the projection of the sacrificial layer on the substrate; the sacrificial layer comprises semiconductor material and doping ions, and the semiconductor material in the sacrificial layer is the same as that in the channel layer, and the content of the doping ions in the sacrificial layer is not more than 5%; a gate electrode on the substrate; wherein the gate electrode surrounds the channel region of the channel layer; a gate oxide layer between the gate electrode and the channel layer; a source-drain electrode layer on the substrate; wherein the source-drain electrode layer covers the projections of the first region and the second region of the channel layer on the substrate, and the source-drain electrode layer does not overlap with the projection of the gate electrode on the substrate.

2. The chip of claim 1, wherein, The doping ions are N-type doping ions.

3. The chip of claim 2, wherein, The N-type doping ions comprise at least one of phosphorus ions, arsenic ions and antimony ions.

4. The chip of any one of claims 1-3, wherein, The doping concentration of the doping ions is not less than 1E16 atom / cm 3 and not more than 1E22 atom / cm 3 .

5. The chip of any one of claims 1-3, wherein, The semiconductor material in the channel layer comprises at least one of elemental semiconductor, inorganic compound semiconductor and organic compound semiconductor.

6. A method of producing a chip, characterized by The application relates to a transistor, comprising: providing a substrate; alternately epitaxially growing a sacrificial layer and a channel layer on the substrate to form a stack structure; wherein the sacrificial layer comprises semiconductor material and doping ions, and the semiconductor material in the sacrificial layer is the same as that in the channel layer; the content of the doping ions in the sacrificial layer is not more than 5%; forming an isolation structure after etching from an exposed surface of the stack structure to the substrate, so as to define a region of a channel structure in the stack structure; forming a pseudo-gate structure which crosses the channel structure; wherein the pseudo-gate structure covers part of a top wall and part of a side wall of the channel structure, and the extending direction of the pseudo-gate structure is perpendicular to the extending direction of the channel structure; forming a source-drain electrode layer on the exposed channel structure by taking the pseudo-gate structure as a mask; removing the pseudo-gate structure and the sacrificial layer in the region covered by the pseudo-gate structure, retaining the remaining sacrificial layer, forming a gate opening and exposing a channel region of the channel layer; performing an oxidation treatment on the channel region of the channel layer to form a gate oxide layer; forming a gate electrode which surrounds the channel region of the channel layer in the gate opening.

7. The production method according to claim 6, wherein The alternately epitaxially growing a sacrificial layer and a channel layer on the substrate to form a stack structure comprises: placing the substrate in a reaction chamber, keeping the reaction chamber in a condition of a first temperature and a first pressure, forming a silicon atom layer with N-type doping ions of a first thickness as the sacrificial layer by an epitaxial growth method; and keeping the reaction chamber in a condition of a second temperature and a second pressure, forming a silicon atom layer of a second thickness as the channel layer by an epitaxial growth method; repeating the above until the stack structure is formed on the substrate.

8. The production method according to claim 7, wherein The forming a silicon atom layer of a second thickness by an epitaxial growth method comprises: when the reaction chamber is kept in the condition of the second temperature and the second pressure, respectively introducing a carrier gas and a silicon source into the reaction chamber, and forming the silicon atom layer of the second thickness by the epitaxial growth method.

9. The production method according to claim 8, wherein The forming a silicon atom layer with N-type doping ions of a first thickness by an epitaxial growth method comprises: when the reaction chamber is kept in the condition of the first temperature and the first pressure, respectively introducing the carrier gas, the silicon source and an N-type doping gas into the reaction chamber, and forming the silicon atom layer of the first thickness by the epitaxial growth method.

10. An electronic device, comprising: comprising a circuit board and a chip, the chip being connected with the circuit board; The chip is the chip according to any one of claims 1-5, or the chip is formed by the preparation method according to any one of claims 6-9.

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