Device and circuit for hybrid loop unrolling decision feedback equalizer

Abstract

The present disclosure relates to a hybrid cycle unrolling decision feedback equalizer architecture. A keeper device is used in a hybrid cycle unrolling (DFE) circuit to selectively output signals from equalizers corresponding to a specific possibility of a value for a previous bit (e.g., a logic high or logic low) when DFE techniques are not being used. Equalizers corresponding to possibilities other than the specific possibility of the value for the previous bit are disabled in the hybrid cycle unrolling (DFE) circuit. Consequently, the hybrid cycle unrolling (DFE) circuit conserves power when the DFE techniques are not being used because only a portion of the total equalizers in the hybrid cycle unrolling (DFE) circuit are powered.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the field of semiconductor memory devices. More specifically, embodiments of the present disclosure relate to a hybrid loop-unrolling decision feedback equalizer (DFE) architecture for a semiconductor memory device that provides loop unrolling when DFE techniques are used but reverts to a traditional receiver architecture to save power when DFE techniques are not used. Background Art

[0002] The operating rates of memory devices, including their data rates, have been increasing over time. As a side effect of increased memory device speeds, data errors caused by distortion can increase. For example, intersymbol interference (ISI) can occur between transmitted data, whereby previously received data affects currently received data (e.g., previously received data affects and interferes with subsequently received data). One way to correct for this interference is through the use of a decision feedback equalizer (DFE) circuit, which can be programmed to counteract (i.e., eliminate, mitigate, or cancel) the effects of the channel on the transmitted data.

[0003] Furthermore, correcting distortion in transmitted signals remains important. However, conventional distortion correction techniques are unable to adequately correct signal distortion. Errors introduced by the slow processing of conventional distortion correction techniques result in additional distortion in the final data, thereby reducing the reliability of data transmitted within the memory device. One way to correct for this slow process is by using a loop-unrolled decision feedback equalizer (DFE) circuit, which means that possible decisions for a single previous data bit are processed in parallel using corresponding latches. However, loop unrolling can result in increased power consumption due to the use of more latches to process a single data bit. Summary of the Invention

[0004] On the one hand, the present disclosure provides a device comprising: a first equalizer configured to generate a first signal; a second equalizer configured to generate a second signal; a selection device configured to receive the first signal and the second signal; and a retainer device configured to generate a retainer signal based on a disable signal, wherein the disable signal is configured to disable one of the first equalizer and the second equalizer, and wherein the selection device is configured to selectively output one of the first signal and the second signal in response to receiving the retainer signal from the retainer device.

[0005] On the other hand, the present disclosure further provides a method comprising: receiving a disable command; determining a disable signal of an equalizer based on the disable command; determining an adjustment signal of the equalizer based on the disable signal; sending the disable signal to a retainer device, wherein the retainer device is configured to generate a retainer signal based on the disable signal; and sending the retainer signal to a selection device, wherein the selection device is configured to receive a signal from the equalizer and selectively output the signal based on the retainer signal.

[0006] On the other hand, the present disclosure further provides a circuit comprising: a first equalizer configured to generate a first signal; a second equalizer configured to generate a second signal; a first retainer device configured to generate a first retainer signal based on a disable signal, wherein the circuit is configured to selectively output the second signal in response to receiving the first retainer signal from the first retainer device; and a second retainer device configured to generate a second retainer signal based on the disable signal, wherein the circuit is configured to selectively output the first signal in response to receiving the second retainer signal from the second retainer device.

[0007] On the other hand, the present disclosure further provides a device comprising: a plurality of equalizers configured to receive data and generate a plurality of signals based on the data, wherein the plurality of equalizers are configured to correct distortion of the data using decision feedback equalization; and one or more retainer devices configured to generate corresponding retainer signals based on a disable signal, wherein the disable signal is provided to disable the decision feedback equalization of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present disclosure may be better understood after reading the following detailed description and referring to the drawings, in which:

[0009] Figure 1 is a simplified block diagram illustrating certain features of a memory device according to an embodiment of the present disclosure;

[0010] Figure 2 The present invention is shown in FIG. Figure 1 Block diagram of the data transceiver of the I / O interface;

[0011] Figure 3 Describe the embodiment according to the present disclosure Figure 2 A block diagram of an embodiment of a data transceiver;

[0012] Figure 4 Describe the embodiment according to the present disclosure Figure 2 A block diagram of a second embodiment of a data transceiver;

[0013] Figure 5 A block diagram illustrating a distortion correction circuit according to an embodiment of the present disclosure;

[0014] Figure 6 Describe the embodiment according to the present disclosure Figure 5 A circuit diagram of a portion of a decision feedback equalizer (DFE);

[0015] Figure 7 A second embodiment of a distortion correction circuit according to an embodiment of the present disclosure is described;

[0016] Figure 8 Describe the embodiment according to the present disclosure Figure 7 A circuit diagram of a portion of the DFE;

[0017] Figure 9 A third embodiment of the distortion correction circuit according to the embodiment of the present disclosure is described;

[0018] Figure 10 A fourth embodiment of the distortion correction circuit according to the embodiment of the present disclosure is described;

[0019] Figure 11 Describe the embodiment according to the present disclosure Figure 10 A circuit diagram of a portion of the DFE;

[0020] Figure 12 A fifth embodiment of the distortion correction circuit according to the embodiment of the present disclosure will be described.

[0021] Figure 13 A sixth embodiment of the distortion correction circuit according to an embodiment of the present disclosure is described; and

[0022] Figure 14 A flowchart illustrating a method for correcting distortion according to an embodiment of the present disclosure;

[0023] Figure 15 A seventh embodiment of the distortion correction circuit according to the embodiment of the present disclosure is described;

[0024] Figure 16 describes an embodiment of a distortion correction circuit connected to a holder device according to an embodiment of the present disclosure;

[0025] Figure 17 A second embodiment of a distortion correction circuit connected to a holder device according to an embodiment of the present disclosure is described; and

[0026] Figure 18 A flow chart illustrating a method for implementing a retainer apparatus according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] One or more specific embodiments are described below. To provide a concise description of these embodiments, not all features of an actual implementation are described in this specification. It should be understood that in the development of any such actual implementation, as with any engineering design or design project, numerous implementation-specific decisions must be made to achieve the developer's specific goals, such as meeting system-related and business-related constraints, which may vary from implementation to implementation. Furthermore, it should be understood that such a development effort can be complex and time-consuming, but remains a routine task of design, fabrication, and manufacture for those of ordinary skill in the art having the benefit of this disclosure.

[0028] Using a memory device's decision feedback equalizer (DFE) to perform distortion correction techniques can be valuable, for example, to correctly compensate for distortion in received data from the memory device. This ensures that accurate values ​​are stored in the memory of the memory device. The DFE can use previous bit data to create correction values ​​to compensate for distortion caused by the previous bit data. For example, the most recent previous bit may have a greater distorting effect on the current bit than a bit transmitted several data points earlier, resulting in a difference in correction values ​​between the two bits. With these levels to be corrected, the DFE can operate to correct for distortion in the transmitted bits.

[0029] In some embodiments, the DFE can utilize multiple previous data bits to accurately calculate the distortion correction factor. In other embodiments, when multiple bits are received and processed, the DFE cannot receive a correction voltage for the distorted bit from the most recent bit because there may be an additional time delay in correcting the distorted bit while waiting for the correction voltage from the most recent bit. Loop unrolling techniques and associated hardware reduce the delay in correcting the distorted bit caused by the delay in receiving the previous bit by applying a correction to the distorted bit from an assumed value of the previous bit (e.g., assumed to be logic high or logic low) and passing this bit to a selection circuit. Once the previous bit is known, the selection of the corrected distorted bit is made based on the assumed corrected distorted bit. Loop unrolling techniques and associated hardware can allow multiple bits to be received and processed nearly simultaneously, resulting in a very efficient system that can process distortion of received bits faster than can be accomplished via traditional DFE solutions. However, loop unrolling techniques consume more power due to the additional processing for the assumed value of the previous bit.

[0030] In some embodiments, DFE techniques in the loop unrolling DFE circuit may not be used, and this technique and associated hardware reduces power consumption by restoring the loop unrolling DFE circuit to a traditional receiver circuit without implementing DFE techniques to reduce power.

[0031] Decision Feedback Equalizer Architecture

[0032] Now turning to the figure, Figure 1 is a simplified block diagram illustrating certain features of memory device 10. Specifically, Figure 1The block diagram is a functional block diagram illustrating certain functionality of memory device 10. According to one embodiment, memory device 10 may be a fifth-generation double data rate SDRAM (DDR5 SDRAM) device. Various features of DDR5 SDRAM allow for reduced power consumption, increased bandwidth, and increased storage capacity compared to previous generations of DDR SDRAM.

[0033] Memory device 10 may include several memory banks 12. For example, memory banks 12 may be DDR5 SDRAM memory banks. Memory banks 12 may be provided on one or more chips (e.g., SDRAM chips) arranged on a dual in-line memory module (DIMM). It should be understood that each DIMM may include several SDRAM memory chips (e.g., x8 or x16 memory chips). Each SDRAM memory chip may include one or more memory banks 12. Memory device 10 represents a portion of a single memory chip (e.g., an SDRAM chip) having several memory banks 12. For DDR5, memory banks 12 may be further arranged to form memory bank groups. For example, for 8 gigabit (Gb) DDR5 SDRAM, a memory chip may include 16 memory banks 12 arranged in 8 memory bank groups, each memory bank group including 2 memory banks. For example, for 16GB DDR5 SDRAM, a memory chip may include 32 memory banks 12 arranged in 8 memory bank groups, each memory bank group including 4 memory banks. Various other configurations, organizations, and sizes of banks 12 on memory device 10 may be utilized depending on the application and design of the overall system.

[0034] Memory device 10 may include a command interface 14 and an input / output (I / O) interface 16, which are configured to exchange (e.g., receive and transmit) signals with an external device. Command interface 14 is configured to provide a number of signals (e.g., signal 15) from an external device (not shown), such as a processor or controller. The processor or controller may provide various signals 15 to memory device 10 to facilitate the transmission and reception of data written to or read from memory device 10.

[0035] It should be understood that the command interface 14 may include several circuits, such as a clock input circuit 18 and a command address input circuit 20, to ensure proper handling of the signal 15. The command interface 14 may receive one or more clock signals from an external device. Typically, double data rate (DDR) memory utilizes a differential pair of system clock signals, referred to herein as a true clock signal (Clk_t) and a complementary clock signal (Clk_c). A positive clock edge in DDR refers to the point where a rising true clock signal Clk_t crosses a falling complementary clock signal Clk_c, while a negative clock edge indicates a transition of a falling true clock signal Clk_t and a rise of a complementary clock signal Clk_c. Commands (e.g., read commands, write commands, etc.) are typically input on the positive edge of the clock signal, and data is transmitted or received on both the positive and negative clock edges.

[0036] The clock input circuit 18 receives the true clock signal (Clk_t) and the complementary clock signal (Clk_c) and generates an internal clock signal CLK. The internal clock signal CLK is supplied to an internal clock generator 30, such as a delay-locked loop (DLL) circuit. The internal clock generator 30 generates a phase-controlled internal clock signal LCLK based on the received internal clock signal CLK. The phase-controlled internal clock signal LCLK is supplied to, for example, the I / O interface 16 and serves as a timing signal that determines the output timing of read data.

[0037] The internal clock signal CLK may also be provided to various other components within the memory device 10 and may be used to generate various additional internal clock signals. For example, the internal clock signal CLK may be provided to a command decoder 32. The command decoder 32 may receive command signals from a command bus 34 and may decode the command signals to provide various internal commands. For example, the command decoder 32 may provide the command signal to the internal clock generator 30 via a bus 36 to coordinate the generation of the phase-controlled internal clock signal LCLK. For example, the phase-controlled internal clock signal LCLK may be used to clock data passing through the I / O interface 16.

[0038] Furthermore, the command decoder 32 may decode commands such as read commands, write commands, mode register set commands, activate commands, etc. and provide access to the specific memory bank 12 corresponding to the command via the bus path 40. It should be appreciated that the memory device 10 may include various other decoders such as row decoders and column decoders to facilitate access to the memory banks 12. In one embodiment, each memory bank 12 includes a bank control block 22 that provides the necessary decoding (e.g., row decoders and column decoders) as well as other features such as timing control and data control to facilitate command execution to and from the memory bank 12. The memory banks 12 and the bank control block 22 may be collectively referred to as a memory array 23.

[0039] The memory device 10 performs operations such as read and write commands based on command / address signals received from an external device (e.g., a processor). In one embodiment, the command / address bus may be a 14-bit bus that accommodates command / address signals (CA<13:0>). The command / address signals are clocked using clock signals (Clk_t and Clk_c) for transmission to the command interface 14. The command interface may include a command and address input circuit 20 configured to receive and transmit commands to provide access to the memory banks 12, such as through a command decoder 32. Additionally, the command interface 14 may receive a chip select signal (CS_n). The CS_n signal enables the memory device 10 to process commands incoming on the CA<13:0> bus. Access to a specific memory bank 12 within the memory device 10 is encoded on the CA<13:0> bus along with the command.

[0040] In addition, the command interface 14 can be configured to receive several other command signals. For example, a die termination command / address (CA_ODT) signal can be provided to facilitate proper impedance matching within the memory device 10. A reset command (RESET_n) can be used to reset the command interface 14, status registers, state machines, and the like, for example, during power-up. The command interface 14 can also receive a command address inversion (CAI) signal, which can be provided to, for example, invert the state of the command / address signals CA<13:0> on the command / address bus, depending on the command / address routing of a particular memory device 10. A mirror (MIR) signal can also be provided to facilitate mirroring functionality. The MIR signal can be used to multiplex signals so that they can be swapped based on the configuration of multiple memory devices in a particular application to achieve specific routing of signals to the memory device 10. Various signals can also be provided to facilitate testing of the memory device 10, such as a test enable (TEN) signal. For example, the TEN signal can be used to place the memory device 10 in a test mode for connectivity testing.

[0041] The command interface 14 can also be used to provide an alert signal (ALERT_n) to the system processor or controller for specific detectable errors. For example, if a cyclic redundancy check (CRC) error is detected, an alert signal (ALERT_n) can be transmitted from the memory device 10. Other alert signals can also be generated. In addition, the bus and pins used to transmit the alert signal (ALERT_n) from the memory device 10 can be used as input pins during certain operations, such as the connectivity test mode performed using the TEN signal, as described above.

[0042] Utilizing the command and timing signals discussed above, data can be sent to and from the memory device 10 by transmitting and receiving data signals 44 via the I / O interface 16. More specifically, data can be sent to and retrieved from the memory bank 12 via a data bus 46, which includes a plurality of bidirectional data buses. Data I / O signals (often referred to as DQ signals) are typically transmitted and received on one or more bidirectional data buses. For a particular memory device, such as a DDR5 SDRAM memory device, the I / O signals can be separated into high-order and low-order bytes. For example, for a x16 memory device, the I / O signals can be separated into high-order and low-order I / O signals (e.g., DQ<15:8> and DQ<7:0>), corresponding to, for example, the high-order and low-order bytes of the data signals.

[0043] To allow for higher data rates within the memory device 10, certain memory devices, such as DDR memory devices, may utilize a data strobe signal, commonly referred to as a DQS signal. The DQS signal is driven by an external processor or controller sending data (e.g., for a write command) or by the memory device 10 (e.g., for a read command). For a read command, the DQS signal is effectively an additional data output (DQ) signal with a predetermined pattern. For a write command, the DQS signal serves as a clock signal to capture the corresponding input data. Like the clock signals (Clk_t and Clk_c), the data strobe (DQS) signal may be provided as a differential pair of data strobe signals (DQS_t and DQS_c) for providing differential pair signaling during read and write operations. For certain memory devices, such as DDR5 SDRAM memory devices, the differential pair of DQS signals may be divided into high-order and low-order data strobe signals (e.g., UDQS_t and UDQS_c; LDQS_t and LDQS_c), corresponding to, for example, the high-order and low-order bytes of data sent to and from the memory device 10.

[0044] An impedance (ZQ) calibration signal may also be provided to the memory device 10 via the I / O interface 16. The ZQ calibration signal may be provided to a reference pin and used to tune the output driver and ODT value by adjusting the pull-up and pull-down resistors of the memory device 10 across variations in process, voltage, and temperature (PVT) values. Because PVT characteristics can affect the ZQ resistor value, the ZQ calibration signal may be provided to a ZQ reference pin for adjusting the resistance to calibrate the input impedance to a known value. It should be understood that a precision resistor is typically coupled between the ZQ pin on the memory device 10 and GND / VSS external to the memory device 10. This resistor serves as a reference for adjusting the internal ODT and drive strength of the IO pins.

[0045] In addition, a loopback signal (LOOPBACK) may be provided to the memory device 10 via the I / O interface 16. The loopback signal may be used during a test or debug phase to set the memory device 10 to a mode in which signals are looped back through the memory device 10 via the same pins. For example, the loopback signal may be used to set up the memory device 10 to test the data output of the memory device 10. The loopback may include both the data and strobe pins or may only include the data pins. This is often desirable for monitoring data captured by the memory device 10 at the I / O interface 16.

[0046] It should be understood that various other components, such as power supply circuits (for receiving external VDD and VSS signals), mode registers (for defining various modes of programmable operation and configuration), read / write amplifiers (for amplifying signals during read / write operations), temperature sensors (for sensing the temperature of the sensor system 10), etc., may also be incorporated into the memory device 10. Therefore, it should be understood that Figure 1 The block diagram is only provided to emphasize certain functional features of the memory device 10 to assist in the subsequent detailed description.

[0047] In some embodiments, memory device 10 may be disposed in a host device (physically integrated into the host device or otherwise connected to the host device) or otherwise coupled to the host device. The host device may include any of a desktop computer, a laptop computer, a pager, a cellular phone, a personal organizer, a portable audio player, a control circuit, a camera, and the like. The host device may also be a network node, such as a router, a server, or a client (e.g., one of the aforementioned computer types). The host device may be some other kind of electronic device, such as a copier, a scanner, a printer, a game console, a television, a set-top video distribution or recording system, a cable box, a personal digital media player, a factory automation system, an automotive computer system, or a medical device. (The terms used to describe these various examples of systems, like many other terms used herein, may share some references and thus should not be construed narrowly by listing other terms.)

[0048] The host device may thus be a processor-based device that controls system functions and processing requests in the host, and may include a processor, such as a microprocessor. Furthermore, any host processor may include multiple processors that share system control. The host processor may be coupled directly or indirectly to additional system components of the host, such that the host processor controls the operation of the host by executing instructions that may be stored within or external to the host.

[0049] As discussed above, data can be written to and read from the memory device 10 by, for example, a host, whereby the memory device 10 operates as a volatile memory, such as a double data rate DRAM (e.g., DDR5 SDRAM). In some embodiments, the host may also include a separate non-volatile memory, such as a read-only memory (ROM), PC-RAM, silicon-oxide-nitride-oxide-silicon (SONOS) memory, metal-oxide-nitride-oxide-silicon (MONOS) memory, polysilicon floating gate-based memory, and / or other types of flash memory of various architectures (e.g., NAND memory, NOR memory, etc.), as well as other types of memory devices (e.g., storage devices), such as a solid-state drive (SSD), a multimedia media card (MMC), a secure digital (SD) card, a compact flash (CF) card, or any other suitable device. Furthermore, it should be understood that the host may include one or more external interfaces (e.g., Universal Serial Bus (USB), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Small Computer System Interface (SCSI), IEEE 1394 (firmware), or any other suitable interface) and one or more input devices to allow a user to input data into the host, such as, for example, buttons, switches, a keyboard, a light pen, a stylus, a mouse, and / or a voice recognition system. The host may also optionally include output devices, such as a display coupled to the processor and a network interface device (e.g., a network interface card (NIC)) for interfacing with a network (e.g., the Internet). It should be understood that the host may include many other components depending on the application of the host.

[0050] The host is operable to transfer data to the memory device 10 for storage and to read data from the memory device 10 to perform various operations at the host. Therefore, to facilitate these data transfers, in some embodiments, the I / O interface 16 may include a data transceiver 48 that operates to receive and transmit DQ signals from and to the I / O interface 16.

[0051] Figure 2 The I / O interface 16 of the memory device 10 is generally described, and more specifically, the data transceiver 48 is described. As illustrated, the data transceiver 48 of the I / O interface 16 may include a DQ connector 50, a DQ transceiver 52, and a serializer / deserializer 54. It should be noted that in some embodiments, multiple data transceivers 48 may be utilized, such that each single data transceiver 48 may be utilized in conjunction with each respective one of the upper and lower I / O signals (e.g., DQ<15:8> and DQ<7:0>), for example, corresponding to the upper and lower bytes of a data signal. Thus, the I / O interface 16 may include multiple data transceivers 48, each corresponding to one or more I / O signals (e.g., including a respective DQ connector 50, DQ transceiver 52, and serializer / deserializer 54).

[0052] DQ connector 50 can be, for example, a pin, a pad, a combination thereof, or another type of interface that operates to receive DQ signals, such as for transmitting data to memory array 23 as part of a data write operation. Additionally, DQ connector 50 can operate to transmit DQ signals from memory device 10, such as for transmitting data from memory array 23 as part of a data read operation. To facilitate these data reads / writes, DQ transceivers 52 are present within data transceivers 48. In some embodiments, for example, DQ transceivers 52 can receive a clock signal generated by internal clock generator 30 as a timing signal for determining output timing for data read operations from memory array 23. The clock signal transmitted by internal clock generator 30 can be based on one or more timing signals received by memory device 10 at clock connector 56 (e.g., a pin, a pad, a combination thereof, etc.) and routed to internal clock generator 30 via clock input circuitry 18. Thus, DQ transceivers 52 can receive the clock signal generated by internal clock generator 30 as a timing signal for determining output timing for data read operations from memory array 23.

[0053] Figure 2 The DQ transceiver 52 may also receive one or more DQS signals, for example, to operate in a strobe data mode as part of a data write operation. The DQS signals may be received at a DQS connector 58 (e.g., a pin, a pad, a combination thereof, etc.) and routed to the DQ transceiver 52 via a DQS transceiver 60, which operates to control the data strobe mode via selective transmission of the DQS signals to the DQ transceiver 52. Thus, the DQ transceiver 52 may receive DQS signals to control data write operations with respect to the memory array 23.

[0054] As described above, the data transceiver 48 can operate in a mode to facilitate the transfer of data to and from the memory device 10 (e.g., to and from the memory array 23). For example, to allow for higher data rates within the memory device 10, a data strobe mode can occur in which the DQS signal is utilized. The DQS signal can be driven by an external processor or controller that sends data (e.g., for a write command) received by the DQS connector 58 (e.g., a pin, a pad, a combination thereof, etc.). In some embodiments, the DQS signal is used as a clock signal to capture the corresponding input data.

[0055] In addition, if Figure 2, the data transceiver 48 further includes a serializer / deserializer 54 that operates to translate serial data bits (e.g., a serial bit stream) into parallel data bits (e.g., a parallel bit stream) for transmission along the data bus 46 during a data write operation of the memory device 10. Similarly, the serializer / deserializer 54 operates to translate parallel data bits (e.g., a parallel bit stream) into serial data bits (e.g., a serial bit stream) during a read operation of the memory device 10. In this manner, the serializer / deserializer 54 operates to translate data in a serial format received from, for example, a host device into a parallel format suitable for storage in the memory array 23. Likewise, the serializer / deserializer 54 operates to translate data in a parallel format received from, for example, the memory array 23 into a serial format suitable for transmission to the host device.

[0056] Figure 3 The data transceiver 48 is illustrated as including a DQ connector 50 coupled to a data transfer bus 51, a DQ receiver 62, a DQ transmitter 64 (which, in combination with the DQ receiver 62, forms the DQ transceiver 52), a deserializer 66, and a serializer 68 (which, in combination with the deserializer 66, forms the serializer / deserializer 54). In operation, as part of a data write operation to the memory device 10, a host (e.g., the host processor described above or another memory device) may be operable to transmit data in serial form across the data transfer bus 51 to the data transceiver 48. This data is received at the DQ connector 50 and transmitted to the DQ receiver 62. The DQ receiver 62 may, for example, perform one or more operations on the data (e.g., amplification, driving, etc. of the data signal) and / or may operate as a latch for the data until receiving a corresponding DQS signal that operates to coordinate (e.g., control) the transmission of the data to the deserializer 66. As part of a data write operation, the deserializer 66 is operable to convert (e.g., translate) the data from a format in which the data is transmitted along the data transfer bus 51 (e.g., serial form) into a format (e.g., parallel form) for transmitting the data to the memory array 23 for storage therein.

[0057] Similarly, during a read operation (e.g., reading data from the memory array 23 and transmitting the read data to the host via the data transfer bus 51), the serializer 68 can receive data read from the memory array in one format (e.g., parallel form) used by the memory array and can convert (e.g., translate) the received data into a second format (e.g., serial form) so that the data is compatible with the data transfer bus 51 and / or one or more of the host. The converted data can be transmitted from the serializer 68 to the DQ transmitter 64, whereupon one or more operations on the data (e.g., attenuation, driving, etc.) can occur. Additionally, the DQ transmitter 64 can operate as a latch for the received data until receiving a corresponding clock signal, e.g., from the internal clock generator 30, which operates to coordinate (e.g., control) the transmission of data to the DQ connector 50 for transmission along the data transfer bus 51 to one or more components of the host.

[0058] In some embodiments, data received at DQ connector 50 may be distorted. For example, data received at DQ connector 50 may be affected by inter-symbol interference (ISI), where previously received data interferes with subsequently received data. For example, due to an increase in the amount of data transmitted to DQ connector 50 across data transfer bus 51, the data received at DQ connector 50 may be distorted relative to the data transmitted by the host. One technique to mitigate (e.g., offset or cancel) this distortion and effectively undo the effects of ISI is to apply equalization to the data. Figure 4 An embodiment of a data transceiver 48 including an equalizer that may be used in this equalization operation is described.

[0059] Figure 4 One embodiment of a data transceiver 48 including an equalizer, specifically a decision feedback equalizer (DFE) 70, is illustrated. As illustrated, the DFE 70 is a multi-tap (e.g., four-tap) DFE 70. However, fewer or more than four taps may be utilized in conjunction with the DFE 70. Similarly, the DFE 70 may be disposed separately from or within the deserializer 66 or DQ receiver 62. In operation, binary outputs (e.g., from a latch or decision limiter) are captured in one or more data latches or data registers. In this embodiment, these data latches or data registers may be disposed in the deserializer 66, and the values ​​stored therein may be latched or transmitted along paths 72, 74, 76, and 78.

[0060] When a data bit is received at the DQ receiver 62, it may be recognized as being transmitted from the host as bit "n" and may be received at time t0 as a distorted bit n (e.g., bit n that has been distorted by ISI). -1The most recent bit received) can be identified as n-1 and illustrated as being transmitted from the data latch or data register along path 72. The distorted bit n is received before it is received at the DQ receiver 62 (e.g., immediately after time t -1 The time before t -2 The second most recent bit received at the DQ receiver 62 may be identified as n-2 and illustrated as being transmitted from the data latch or data register along path 74. -2 The time before t -3 The third most recent bit received) may be identified as n-3 and illustrated as being transmitted from the data latch or data register along path 76. The distorted bit n is received before it is received at the DQ receiver 62 (e.g., immediately after time t -2 The time before t -3 The fourth most recent bit of the received data (e.g., bit n-1, n-2, n-3, and n-4) may be identified as n-4 and illustrated as being transmitted from the data latch or data register along path 78. Bits n-1, n-2, n-3, and n-4 may be considered a group of bits that interferes with the received distorted bit n (e.g., bits n-1, n-2, n-3, and n-4 cause ISI to host transmit bit n), and DFE 70 may be operable to cancel the distortion caused to host transmit bit n by the group of bits n-1, n-2, n-3, and n-4.

[0061] Thus, the values ​​latched or transmitted along paths 72, 74, 76, and 78 may correspond to the most recently transmitted data values ​​(e.g., previous bits n-1, n-2, n-3, and n-4), respectively, transmitted from DQ receiver 62 for storage in memory array 23. These previously transmitted bits are fed back to DFE 70 along paths 72, 74, 76, and 78, which operates to generate weighted taps (e.g., voltages) that can be added to the received input signal (e.g., data received from DQ connector 50, e.g., distorted bit n) via a summer (e.g., a summing amplifier). In other embodiments, the weighted taps (e.g., voltages) may be combined with an initial reference value to generate a cancellation that corresponds to or mitigates the distortion of the received data (e.g., mitigates the distortion of distorted bit n). In some embodiments, taps weighted to reflect the most recently received data (e.g., bit n-1) may have a stronger effect on the distortion of the received data (e.g., distorted bit n) than bits received at earlier times (e.g., bits n-1, n-2, and n-3). DFE 70 is operable to generate a magnitude and polarity of taps (eg, voltages) due to each previous bit to collectively cancel the distortion caused by those previously received bits.

[0062] For example, for the present embodiment, each of the previously received bits n-1, n-2, n-3, and n-4 may have one of two values ​​(e.g., binary 0 or 1) that are transmitted to the deserializer 66 for transmission to the memory array 23 and additionally latched or saved in a register for subsequent transmission along the respective paths 72, 74, 76, and 78. In the illustrated embodiment, this results in sixteen (e.g., 2 4 ) possible binary combinations (e.g., 0000, 0001, 0010, ..., 1110, or 1111). DFE 70 operates to select and / or generate corresponding tap values, whichever corresponding tap values ​​of the aforementioned sixteen combinations are determined to be present (e.g., based on received values ​​along paths 72, 74, 76, and 78) for use in adjusting an input value received from DQ connector 50 (e.g., distorted bit n) or modifying a reference value, which is then applied to the input value received from DQ connector 50 (e.g., distorted bit n) in order to cancel ISI distortion from previous bits (e.g., the group of bits n-1, n-2, n-3, and n-4) in the data stream.

[0063] The use of distortion correction (e.g., DFE 70) can advantageously allow data transmitted from DQ connector 50 to be correctly represented in memory array 23 without distortion. Thus, it can be used to store previous bit data for use in distortion correction. Figure 5 As illustrated in the block diagram of FIG, distortion correction circuitry 80 may be included as part of DQ receiver 62, but may not be required to be physically located therein (e.g., distortion correction circuitry 80 may instead be coupled to DQ receiver 62). In some embodiments, distortion correction circuitry 80 is operable to provide previously transmitted bit data to correct distorted bits 81 (e.g., bits that have been distorted due to ISI and / or systematic distortion) transmitted via channel 84 (e.g., a connection, transmission line, and / or conductive material).

[0064] The distorted bit 81 may be transmitted from the channel 84 to an amplification device 82 (e.g., a variable gain amplifier). From the amplification device 82, the distorted bit 81 may be transmitted to the DFE 70, which is illustrated as having a single weighted tap 86. The distorted bit 81 may be transmitted to the DFE 70 simultaneously with a DQ reference signal 83. The DQ reference signal 83 may represent a threshold (e.g., a voltage level) for determining whether a transmitted bit received by the DQ connection 50 is a logic low (e.g., a 0) or a logic high (e.g., a 1).

[0065] DFE 70 can be operated to correct the distortion from distorted bit 81 using taps weighted by the previous bit data (e.g., n-1 bit data). The n-1 bit of data (e.g., a logic 1 or a logic 0) can be transmitted via path 72. The magnitude and polarity of a single weighted tap 86 can cancel the total distortion caused by the n-1 bit via summer circuit 85, which operates as a current summer that applies a current to distorted bit 81 to cancel the distortion caused by the n-1 bit. For example, if the bit received at DQ connection 50 is determined to be lower than DQ reference signal 83, then the received bit 81 is transmitted to memory array 23 as a logic low. The magnitude and polarity of weighted tap 86 can correct the distorted bit 81 and DQ reference signal 83.

[0066] The modified version of the distortion bit 81 and the modified version of the DQ reference signal 83 may be transmitted to the data latch 94. The correction bit 88 may be generated via the data latch 94 and transmitted from the data latch 94 to the deserializer 66, which may occur on the rising edge of the DQS signal 96. In other embodiments, variations of the timing scheme may be followed to include additional or alternative methods of data transmission. The value of the new n-1 bit may be stored, for example, in the deserializer 66 for transmission along the path 72 when the correction bit 88 is received in the deserializer 66. The distortion correction circuitry associated with the DFE 70 and the amplification device 82 will be described in more detail below.

[0067] Figure 6 The distortion associated with the distortion bit 81 can be eliminated. Figure 5 1 is a circuit diagram of a portion of DFE 70. Data bits may be received at first input 102 and second input 104 of summer circuit 85. First input 102 and second input 104 may be communicatively coupled to devices that may be enabled or disabled (e.g., field effect transistors 106 and 108). Distortion bits 81 may be received by first input 102 and DQ reference signal 83 may be received by second input 104. In this manner, both field effect transistors 106 and 108 may be controlled by distortion bits 81 and DQ reference signal 83.

[0068] The weighted tap 86 and its inverse value (e.g., inverse weighted tap 87) may be transmitted to outputs 110 and 112 to correct the distortion of the distorted bit 81. A logic high for the n-1 bit is transmitted via path 72. In this case, the n-1 bit may be implemented to generate the weighted tap 86 and the inverse weighted tap 87 as two field effect transistors 116 and 118 implement control signals that contribute the weighted tap values ​​86 and 87 to the outputs 110 and 112.

[0069] The weighted tap values ​​86 and 87 may allow current to be applied to outputs 110 and 112, whereby the supplied current is controlled by a controllable source 120 (e.g., a current source controlled by a digital-to-analog converter). Outputs 110 and 112 may be modified values ​​of one or more of the DQ reference signal 83 and the distortion bit 81 and may be transmitted to a data latch 94 (e.g., a regeneration latch or limiter that produces a binary output). Correction bits 88 may be generated based on outputs 110 and 112 via the data latch 94 and may be transmitted to the deserializer 66 on the rising edge of the DQS signal 96. The n-1 bits of information stored for transmission along the path 72 in the deserializer 66 may be updated with correction bits 88 for future distortion correction.

[0070] In some applications, the correction bits 88 need to be adjusted with greater precision than the weighted taps 86 and 87 can provide. Figure 7 A block diagram illustrates a distortion correction circuit 160 that can receive four previous data bits (e.g., n-1 bit data, n-2 bit data, n-3 bit data, and n-4 bit data) to create four weighted taps 86, 162, 164, and 166 to perform more accurate distortion correction on the distorted bit 81. In a manner similar to the distortion correction circuit 80, the distorted bit 81 can be transmitted to the amplification device 82 via a channel 84. A DQ reference signal 83 can also be transmitted to the amplification device 82.

[0071] The distorted bit 81 and the DQ reference signal 83 may be transmitted from the amplification device 82 to the DFE 70. Bit data of the previous bit may be transmitted through paths 72, 74, 76, and 78. The DFE 70 may be operated to correct the distortion from the distorted bit 81 using four weighted taps 86, 162, 164, and 166 created from the bit data of the four previous bits. The DFE 70 may be operated to generate the magnitude and polarity of each of the weighted taps 86, 162, 164, and 166 for each of the previous bits transmitted along paths 72, 74, 76, and 78, which may be designed to cancel the total distortion of the distorted bit 81 caused by the previously received bit.

[0072] One or more of the modified version of the distortion bits 81 and the modified version of the DQ reference signal 83 may be transmitted to the data latch 94. The correction bits 88 may be transmitted from the data latch 94 to the deserializer 66 on the rising edge of the DQS signal 96. The deserializer 66 may be updated with the values ​​of the n-1 bit, n-2 bit, n-3 bit, and n-4 bit and the values ​​may be stored for transmission along paths 72, 74, 76, and 78. The distortion correction circuitry associated with the DFE 70 may be described in more detail below.

[0073] Figure 8 Description of the distortion can be eliminated Figure 7 A circuit diagram of a portion of the DFE 70 is shown. Figure 8As further illustrated in FIG. 1 , DFE 70 may receive n-1, n-2, n-3, or n-4 bits of logic high or low, or any combination thereof, via data transmitted on paths 72, 74, 76, and 78. In this case, the data transmitted along paths 72, 74, 76, and 78 may be implemented to generate weighted taps 86, 162, 164, and 166 and inverse weighted taps 87, 163, 165, and 167 as control signals for field effect transistors 116, 118, 182, 184, 186, 188, 190, and 192 to control the outputs transmitted therefrom to outputs 110 and 112. Field effect transistors 116, 118, 182, 184, 186, 188, 190, and 192 may be selectively and controllably activated to reflect the sixteen (e.g., 2) bits represented by various combinations of the previous correction bits. 4 ) one of the different possible binary states (e.g., 0000, 0001, 0010, ..., 1111).

[0074] Weighted tap values ​​86, 87, 162, 163, 164, 166, and 167 may be applied to outputs 110 and 112, whereby the supplied current is controlled by controllable source 120 and additional controllable sources 194, 196, and 198 (e.g., current sources controlled by digital-to-analog converters). Outputs 110 and 112 may be transmitted to data latches 94. Correction bits 88 may be generated based on outputs 110 and 112 via data latches 94 and may be transmitted to deserializer 66 on the rising edge of DQS signal 96. The n-1, n-2, n-3, and n-4 bits of information stored for transmission along paths 72, 74, 76, and 78 in the deserializer 66 may be updated with correction bits 88 (e.g., the n-4 bits will be updated to reflect the n-3 data, the n-3 bits will be updated to reflect the n-2 data, the n-2 data will be updated to reflect the n-1 data, and the n-1 data will be updated with the latest correction bits) for future distortion correction.

[0075] Figure 9 The distortion correction circuit 200 is shown as being capable of receiving and processing four data bits in a rolling manner. For example, the distortion correction circuit 200 may include four distortion correction circuits 202, 204, 206, and 208, each of which is similar to Figure 7 The distortion correction circuits 202, 204, 206 and 208 include summers 210, 212, 214 and 216, respectively, which may be as shown in FIG. Figure 8 The general operation is described with respect to summer circuit 85. The four distortion circuits 202, 204, 206, and 208 are referred to as first circuit 202, second circuit 204, third circuit 206, and fourth circuit 208. One embodiment for implementing rolling distortion correction using distortion correction circuit 200 is described below.

[0076] The distorted bit stream may be received at the amplification device 82. A first distorted bit 81 of the bit stream may be received by the first circuit 202 (e.g., after being amplified by the amplification device 82), a second distorted bit 218 of the bit stream may be received by the second circuit 204, a third distorted bit 220 of the bit stream may be received by the third circuit 206, a fourth distorted bit 222 of the bit stream may be received by the fourth circuit 208, and once the first iteration of distortion correction of the distorted bit 81 has completed, the fifth distorted bit may be rolled back to be received by the first circuit.

[0077] To further illustrate, the first circuit 202 may receive the distorted bit 81 from the amplification device 82 and may begin processing it using the methods described above with respect to the distortion correction circuit 160, such as using the previous bits or weighted tap data transmitted along paths 72, 74, 76, and 78 to calculate the value required by the summer circuit 210. The voltage correction signal 224 (e.g., the amplified DQ reference signal 83) may also be transmitted to the first circuit 202 and used to correct the distorted bit 81. The correction bit 88 of the data latch 226 may be transmitted from the output 234 on the rising edge of the DQS signal 96 as a DFE adjustment bit.

[0078] The input used to determine the correction bit transmitted from the output 236 of the second circuit 204 may be different from the input of the first circuit 202. After the distorted bit 81 is received and processed by the first circuit 202, the second circuit 204 may receive the second distorted bit 218 and the voltage correction signal 224 and begin processing the second distorted bit 218. The method described with respect to the distortion correction circuit 160 may be used to correct the second distorted bit 218 using the summer circuit 212 because the previous bits or weighted tap data transmitted along the paths 72, 74, 76, and 78 may be used to correct the second distorted bit 218 via the second circuit 202. Figure 8 The circuitry described in performs more accurate distortion correction on the distorted bits 218. The DFE adjustments (eg, correction bits) of the data latches 228 may be transmitted from the output 236 on the rising edge of the DQS signal 96.

[0079] The input used to determine the correction bit transmitted from the output 238 of the third circuit 206 may be different from the input of the second circuit 204. After the second distorted bit 218 is received and processed by the second circuit 204, the third circuit 206 may receive the third distorted bit 220 and the voltage correction signal 224 and begin processing the third distorted bit 220. The method described with respect to the distortion correction circuit 160 may be used to correct the third distorted bit 220 using the summer circuit 214 because the previous bits or weighted tap data transmitted along the paths 72, 74, 76, and 78 may be used to correct the third distorted bit 220 via the second circuit 204. Figure 8 The circuitry described in performs more accurate distortion correction on distorted bit 220. The DFE adjustment (eg, correction bit) of data latch 230 may be transmitted from output 238 on the rising edge of DQS signal 96.

[0080] The input used to determine the correction bit transmitted from the output 240 of the fourth circuit 208 may be different from the input of the third circuit 206. After the third distorted bit 220 is received and processed by the third circuit 206, the fourth circuit 208 may receive the fourth distorted bit 222 and the voltage correction signal 224 and begin processing the fourth distorted bit 222. The method described with respect to the distortion correction circuit 160 may be used to correct the fourth distorted bit 222 using the summer circuit 216 because the previous bits or weighted tap data transmitted along the paths 72, 74, 76, and 78 may be used to correct the fourth distorted bit 222 via the third circuit 206. Figure 8 The circuitry described in performs more accurate distortion correction on distorted bits 222. The DFE adjustment (eg, correction bit) of data latch 232 may be transmitted from output 240 on the rising edge of DQS signal 96.

[0081] The outputs 234, 236, 238, and 240 from the first, second, third, and fourth circuits 202, 204, 206, and 208 may be sent to the deserializer 66 at the conclusion of each final decision to generate a corresponding correction bit from the first, second, third, and fourth circuits 202, 204, 206, and 208. In the deserializer 66, the n-1 bit, n-2 bit, n-3 bit, and n-4 bit may be used to update the data stored in the deserializer 66 for transmission along paths 72 through 78 according to the correction bit data (e.g., the correction bit from the first circuit 202 will be stored for transmission along path 78, the correction bit data from the second circuit 204 will be stored for transmission along path 76, the correction bit data from the third circuit 206 will be stored for transmission along path 74, and the correction bit data from the fourth circuit 208 will be stored for transmission along path 72). It should be noted that the correction bits may not have completed transmission to the deserializer 66 prior to receiving the fifth distorted bit, the values ​​stored for transmission along paths 72 to 78 are not updated, and thus the method of delaying final determination of the correction bits may continue.

[0082] Figure 10 A block diagram illustrating a distortion correction circuit 242 that can receive four previous data bits (e.g., n-1 bit data, n-2 bit data, n-3 bit data, and n-4 bit data) to create four weighted taps 86, 162, 164, and 166 to perform more accurate distortion correction on the distorted bit 81. In a manner similar to the distortion correction circuit 160, the distorted bit 81 can be transmitted via channel 84. However, as illustrated, Figure 10 The distortion correction circuit 242 can eliminate Figure 7 Eliminating this amplification device 82 may allow, for example, increasing the bandwidth transmission of the bit stream containing the distorted bits 81 in the DQ receiver 62 by eliminating an amplification device that may otherwise slow down the reception of the bit stream containing the distorted bits 81.

[0083] Alternatively, the distorted bit 81 and the DQ reference signal 83 may be transmitted to the DFE 244 at inputs 250 and 252, respectively. The bit data of the previous bit may be transmitted via paths 72, 74, 76, and 78. The DFE 244 may be operated to correct the distortion from the distorted bit 81 using four weighted taps 86, 162, 164, and 166 created from the bit data of the four previous bits. The DFE 244 may be operated to generate the magnitude and polarity of each of the weighted taps 86, 162, 164, and 166 for each of the previous bits transmitted along paths 72, 74, 76, and 78, which may be designed to cancel the total distortion of the distorted bit 81 caused by the previously received bit.

[0084] One or more of the modified version of the distortion bits 81 and the modified version of the DQ reference signal 83 may be transmitted to the data latch portion of the DFE 244. The correction bits 88 may be transmitted from the data latch portion of the DFE 244 to the deserializer 66 on the rising edge of the DQS signal 96. The deserializer 66 may be updated with the values ​​of the n-1 bit, n-2 bit, n-3 bit, and n-4 bit and the values ​​may be stored for transmission along paths 72, 74, 76, and 78. The distortion correction circuitry associated with the DFE 244 may be described in more detail below.

[0085] Figure 11 Description of the distortion can be eliminated Figure 10 2. A circuit diagram of an equalizer or DFE 244 (eg, regenerative latch circuitry and DFE circuitry, such as summer circuitry, combined or integrated into one device) is shown. One of ordinary skill in the art will appreciate that the additional stages result in reduced bandwidth.

[0086] In a first portion 260 (e.g., the first portion of a regenerative comparator or regenerative latch), data bits may be received at the first input 102 and the second input 104 of the equalizer 244. The first and second inputs 102, 104 may be communicatively coupled to devices that may be enabled or disabled (e.g., field-effect transistors 106 and 108). Distortion bits 81 may be received at the first input 102, and DQ reference signal 83 may be received at the second input 104. In this manner, both field-effect transistors 106 and 108 may be controlled by distortion bits 81 and DQ reference signal 83. When the DQS signal, for example, transitions high, data outputs 262 and 264 from field-effect transistors 106 and 108 are sent to the second portion 266 based on the DQS signal 96 as a clock signal for the first portion 260, which operates to track the input voltages applied at the inputs 102 and 104.

[0087] The second portion 266 of the circuit diagram of the equalizer 244 typically applies weighted tap values ​​to the output from the first portion 260 and thus typically operates as a summer circuit (e.g., a summing amplifier). Figure 8 , DFE 244 can receive logic highs or lows, or any combination thereof, for n-1, n-2, n-3, and n-4 bits via data transmitted on paths 72, 74, 76, and 78. The data transmitted along paths 72, 74, 76, and 78 can be implemented to generate weighted taps 86, 162, 164, and 166 and inverse weighted taps 87, 163, 165, and 167 as control signals for field effect transistors 116, 118, 182, 184, 186, 188, 190, and 192 to control outputs transmitted therefrom to outputs 272 and 274. Field effect transistors 116, 118, 182, 184, 186, 188, 190, and 192 can be selectively and controllably activated to reflect the sixteen (e.g., 2) bits represented by various combinations of the previous correction bits. 4 ) one of the different possible binary states (e.g., 0000, 0001, 0010, ..., 1111).

[0088] Weighted tap values ​​86, 87, 162, 163, 164, 166, and 167 may be applied to outputs 110 and 112, whereby the supplied current is controlled by controllable source 120 and additional controllable sources 194, 196, and 198 (e.g., current sources controlled by digital-to-analog converters). Outputs 272 and 274 may be transmitted to a third portion 268 (e.g., a second portion of a regenerative comparator or regenerative latch). In third portion 268, feedback may be applied, for example, when the DQS signal goes low, to be output from third portion 268, for example, when DQS signal 96 goes high again. Correction bits 88 may be generated based on outputs 110 and 112 via equalizer 244 and may be transmitted to deserializer 66 on the rising edge of DQS signal 96. In this manner, first portion 260 and third portion 268 operate as regenerative latches in a manner similar to data latch 94 and second portion 266 operates as a summer circuit that operates in a manner similar to summer circuit 85 to generate correction bits 88. The n-1-bit, n-2-bit, n-3-bit, and n-4-bit information stored for transmission along paths 72, 74, 76, and 78 in deserializer 66 may be updated with correction bits 88 (e.g., n-4 bits will be updated to reflect n-3 data, n-3 bits will be updated to reflect n-2 data, n-2 data will be updated to reflect n-1 data, and n-1 data will be updated with the latest correction bits) for future distortion correction.

[0089] One solution to the delay in processing that may occur with the distortion correction circuit 242 may include calculating the distortion weights for the n-2, n-3, and n-4 bits using two possibilities for the value of the n-1 bit (e.g., logic high and logic low) and discarding the value when determining the value calculated using the incorrect value of the n-1 bit. Figure 12 A distortion correction circuit 280 is illustrated that may implement this solution.

[0090] Figure 12 A block diagram illustrating a distortion correction circuit 280 that can implement an efficient solution for handling data transmitted faster than could otherwise be handled. Additionally, a distortion correction circuit 280 that does not include any amplification devices 82 can be utilized. The distortion correction circuit 280 includes a first equalizer 282 and a second equalizer 284 (each of which can operate generally as described above with respect to the DFE 244) and a selection device 286 (e.g., a multiplexer). Distortion bits 81 can be transmitted to the input 250 of the first equalizer 282 and the input 250 of the second equalizer 284.

[0091] Input 252 of first equalizer 282 also receives voltage correction signal 292, and input 252 of second equalizer receives voltage correction signal 294. Voltage correction signal 292 transmitted to equalizer 282 may be different from voltage correction signal 294 transmitted to equalizer 284. Equalizer 282 may receive voltage correction signal 292 as DQ reference signal 83 modified by an adjustment amount associated with the most recently received bit n-1 corresponding to a logic high. Similarly, equalizer 284 may receive voltage correction signal 294 as DQ reference signal 83 modified by an adjustment amount associated with the most recently received bit n-1 corresponding to a logic low.

[0092] Equalizers 282 and 284 can use three inputs to correct the distortion associated with distorted bit 81 using the previous bits or weighted tap data transmitted along paths 74, 76, and 78 to calculate the value required by the equalizer. This can be done in such a way that when the n-1 bit is a logic high, the output 296 from equalizer 282 represents the corrected bit 88, while when the n-1 bit is a logic low, the output 298 from equalizer 284 represents the corrected bit 88. Thus, each of equalizers 282 and 284 can be similar to Figure 10 The equalizer 244 operates in a partial manner as in FIG. 1 , with one difference; only three paths (e.g., corresponding to bits n-2, n-3, and n-4) from which distortion can be eliminated are utilized and their corresponding weighted taps and the current is supplied via three corresponding controllable sources.

[0093] Once the outputs 296 and 298 are transmitted to the selection device 286, sufficient time will have passed for the n-1 bit to be determined, stored, and transmitted from the deserializer 66 so that the selection device 286 can receive the value transmitted along the path 72 as a selection control signal (e.g., a multiplexer selection or control signal). The n-1 bit value transmitted along the path 72 can be used to select the correction bit from the outputs 296 and 298. If the n-1 bit is a logic high, then the output 296 can be selected as the correction bit 88. However, if the n-1 bit is a logic low, then the output 298 can be selected as the correction bit 88. The output from the selection device 286 can be sent to the deserializer 66 as the correction bit 88. In the deserializer 66, the n-1 bit, n-2 bit, n-3 bit, and n-4 bit may be updated according to the correction bits 88 (e.g., the n-4 bit will be updated to reflect the n-3 data, the n-3 bit will be updated to reflect the n-2 data, the n-2 data will be updated to reflect the n-1 data, and the n-1 data will be updated with the latest correction bits 88). It should be noted that the correction bits 88 may not have completed transmission and updating of all values ​​before receiving the second distorted bit 218, so the above-described method of utilizing double calculation of the correction bit value based on the proportion from the n-1 bit being both logic high and logic low may be repeated.

[0094] Figure 13 Distortion correction circuit 300 is illustrated as being capable of processing four data bits at a four-bit distortion correction level and includes distortion correction circuit 280, second circuit 302, third circuit 304, and fourth circuit 306. Second circuit 302, third circuit 304, and fourth circuit 306 may be distortion correction circuits similar to distortion correction circuit 280 with their respective inputs modified. Distortion bit 81 may be received by first circuit 280, second distortion bit 218 may be received by second circuit 302, third distortion bit 220 may be received by third circuit 304, and fourth distortion bit 222 may be received by fourth circuit 306. Once the first iteration of distortion correction is complete, the fifth distortion bit may be rolled back to be received by first circuit 280.

[0095] To further illustrate, first circuit 280 may receive distorted bit 81 and may begin processing it using the methods described with respect to distortion correction circuit 280, using the previous bit or weighted tap data transmitted along paths 74, 76, and 78 to calculate the values ​​needed to supply equalizers 282 and 284. Voltage correction signals 292 and 294 may represent modified DQ reference signal 83 adjusted for the proportion of n-1 bit values ​​being logic high and low, respectively, and may be used to correct distorted bit 81. Outputs 296 and 298 to select device 286 may be transmitted on the rising edge of DQS signal 96. Select device 286 may use the n-1 bit value stored in deserializer 66 and transmitted along path 72 to make the final decision as to which value to use for correction bit 88 (e.g., output 296 or output 298).

[0096] The input used to determine the correction bit 88 of the second circuit 302 may be different from the input of the first circuit 280. The second circuit 302 may receive the second distorted bit 218 and may begin processing the second distorted bit 218 in parallel with each of the voltage correction signal 308 (which is the DQ reference signal 83 modified by an adjustment amount associated with the most recently received bit value transmitted along path 78 corresponding to a logic high) and the voltage correction signal 310 (which is the DQ reference signal 83 modified by an adjustment amount associated with the most recently received bit value transmitted along path 78 corresponding to a logic low). The method described with respect to the distortion correction circuit 280 may be used to correct the distorted bit 218, except that the previous bit or weighted tap data transmitted along paths 72, 74, and 76 may be used to calculate the values ​​needed to provide correction to the equalizers 287 and 288. The outputs 312 and 314 to the select device 316 may be transmitted on the rising edge of the DQS signal 96. The selection device 316 of the second circuit 302 may use the bit value stored in the deserializer 66 for transmission along the path 78 to make a final decision regarding the value of the correction bit 88 of the second distorted bit 218 .

[0097] The input used to determine the correction bit 88 of the third circuit 304 may be different from the input of the second circuit 302. The third circuit 304 may receive the third distorted bit 220 and may begin processing the third distorted bit 220 in parallel with each of the voltage correction signal 318 (which is the DQ reference signal 83 modified by an adjustment amount associated with the most recently received bit value transmitted along path 76 corresponding to a logic high) and the voltage correction signal 320 (which is the DQ reference signal 83 modified by an adjustment amount associated with the most recently received bit value transmitted along path 76 corresponding to a logic low). The method described with respect to the distortion correction circuit 280 may be used to correct the distorted bit 220, except that the previous bit or weighted tap data transmitted along paths 72, 74, and 78 may be used to calculate the values ​​needed to provide correction to the equalizers 322 and 324. The outputs 326 and 328 to the select device 330 may be transmitted on the rising edge of the DQS signal 96. The selection device 330 of the third circuit 304 may use the bit value stored in the deserializer 66 for transmission along the path 76 to make a final decision regarding the value of the correction bit 88 of the third distorted bit 220 .

[0098] The input used to determine the correction bit 88 of the fourth circuit 306 may be different from the input of the third circuit 304. The fourth circuit 306 may receive the fourth distortion bit 222 and may begin processing the fourth distortion bit 222 in parallel with each of the voltage correction signal 331 (which is the DQ reference signal 83 modified by an adjustment amount associated with the most recently received bit value transmitted along path 74 corresponding to a logic high) and the voltage correction signal 332 (which is the DQ reference signal 83 modified by an adjustment amount associated with the most recently received bit value transmitted along path 74 corresponding to a logic low). The method described with respect to the distortion correction circuit 280 may be used to correct the distortion bit 222, except that the previous bit or weighted tap data transmitted along paths 72, 76, and 78 may be used to calculate the values ​​needed to provide correction to the equalizers 334 and 336. The outputs 338 and 340 to the select device 342 may be transmitted on the rising edge of the DQS signal 96. The selection device 342 of the fourth circuit 306 may use the bit value stored in the deserializer 66 for transmission along the path 74 to make a final decision regarding the value of the correction bit 88 of the fourth distorted bit 222 .

[0099] The outputs from the selection devices 286, 316, 330, and 342 can be sent to the deserializer 66 at the conclusion of each final decision regarding the correction bit 88. In the deserializer 66, the n-1 bit, n-2 bit, n-3 bit, and n-4 bit can be used to update the data stored in the deserializer 66 for transmission along paths 72 through 78 based on the correction bit 88 data. It should be noted that the correction bit 88 may not have completed transmission to the deserializer 66 before the fifth distorted bit is received, and the value stored for transmission along paths 72 through 78 is not updated, thus continuing the method of delaying the final selection of the correction bit 88. Therefore, the first circuit 280 can apply the weighted values ​​from the fourth circuit 306 in parallel until the correction bit 88 is determined from the fourth circuit 306 and used as the selection bit for the first circuit 280. Similarly, the second circuit 302 can apply the weighted values ​​from the first circuit 280 in parallel until the correction bit 88 is determined from the first circuit 280 and used as the selection bit for the second circuit 302. Likewise, the third circuit 304 may apply the weighted values ​​from the second circuit 302 in parallel until the correction bit 88 is determined from the second circuit 302 and used as the select bit for the third circuit 304. The fourth circuit 306 may apply the weighted values ​​from the third circuit 304 in parallel until the correction bit 88 is determined from the third circuit 304 and used as the select bit for the fourth circuit 306.

[0100] Figure 14 Is used to illustrate the Figure 12 and 13Flowchart of the ISI-induced correction performed by the embodiment of the present invention described in [ 1 ]. In the first step, data is received by the receiver (block 350). As illustrated in the flowchart, this may be bit n, and the previously received bits are n-1, n-2, n-3, n-4, ... . Next, bit n is corrected by n-2, n-3, n-4 (block 352), since bit n-1 may not have been deserialized yet. Instead of waiting for bit n to be corrected by bit n-1, the input is corrected by two parallel paths. In one example, n is corrected when it is assumed that n-1 is read as high (block 354), and in another case, n is corrected when it is assumed that n-1 is read as low (block 356). Sometime after these corrections are applied, the correction bit n-1 is received (block 358). Based on the value of bit n-1, the correction bit n is selected from the n values ​​determined in blocks 354 and 356. The selected (block 360) correction bit is then sent to the deserializer (block 362).

[0101] Figure 15 A distortion correction circuit 364 is illustrated for a basic 2-phase input receiver with a loop-unrolled 1-tap DFE capable of processing two data bits, one received at DQS0 (i.e., at a first phase (e.g., the rising edge of DQS signal 96)) and one received at DQS180 (i.e., at a second phase (e.g., the falling edge of DQS signal 96)). Distortion correction circuit 364 includes a first circuit 366 and a second circuit 368, which may be similar to distortion correction circuit 280 with their respective inputs and feedback modified to correspond to the 2-phase input and feedback. Alternatively, circuits 366 and 368 may be utilized without any amplification device 82. For example, distorted bit 81 may be received by first circuit 366 at DQS0, second distorted bit 218 may be received by second circuit 368 at DQS180, and once the first iteration of distortion correction is complete, the third distorted bit may be rolled back to be received by first circuit 366.

[0102] To further illustrate, the first circuit 366 can receive the distorted bit 81 and can begin processing it using the method described with respect to the distortion correction circuit 280, and an enable signal (i.e., EN) can be used to enable or disable the corresponding equalizer (e.g., equalizer 370 or equalizer 372). Voltage correction signals 374 (i.e., VRHI) and 376 (i.e., VRLO) can represent modified DQ reference signals 83 that have been adjusted for both the proportion of logical high and low values ​​of bit values ​​n-1, respectively, and can be used to correct the distorted bit 81. Outputs 378 and 380 from equalizers 370 and 372, respectively, to a selection device 386 can be transmitted at DQS0 (e.g., the rising edge of the DQS signal 96). Outputs 382 and 384 from equalizers 370 and 372, respectively, to a selection device 388 can be transmitted at DQS0 (e.g., the rising edge of the DQS signal 96). The select devices 386 and 388 can use the n-1 bit value generated by the second circuit 368 and transmitted along the path 390 (e.g., the bit value received at the second phase) to make the final decision as to which value to take for the correction bit 88 (e.g., the value of the output 378 or output 380 of the select device 386 or the value of the output 382 or 384 of the select device 388). The select device 392 can utilize the outputs from the select devices 386 and 388 to generate a signal 394 for the second circuit 368 based on the polarity of the tap 1 bias sign bit (which is the polarity of the tap 1 bias that can be programmed and input into the mode register). For example, the mode register can be programmed for a tap 1 correction +50 mV bias, which indicates a positive sign for the tap 1 bias (i.e., the tap 1 bias sign bit is "+"), and the select device 392 can use the output of the select device 386. In some embodiments, the mode register may be programmed for a −50 mV bias, which indicates a negative sign for the tap 1 bias (ie, the tap 1 bias sign bit is “−”), and select device 392 may use the output of select device 388 .

[0103] Similarly, the second circuit 368 can receive the distorted bit 81 and can begin processing it using the method described with respect to the distortion correction circuit 366, and the enable signal (i.e., EN) can be used to enable or disable the corresponding equalizer (e.g., equalizer 396 or equalizer 398). Voltage correction signals 400 (i.e., VRHI) and 402 (i.e., VRLO) can represent modified DQ reference signals 83 that have been adjusted for the proportion of bit values ​​of n-1 that are logic high and low, respectively, and can be used to correct the distorted bit 81. Outputs 404 and 406 from equalizers 396 and 398 to a select device 412 can be transmitted at DQS 180 (e.g., the falling edge of DQS signal 96). Outputs 408 and 410 from equalizers 396 and 398 to a select device 414 can be transmitted at DQS 180 (e.g., the falling edge of DQS signal 96). The select devices 412 and 414 can use the n-1 bit value generated by the first circuit 366 and transmitted along the path 394 (e.g., the bit value received at the first phase) to make the final decision as to which value the correction bit 88 value should take (e.g., the value of the output 404 or output 406 of the select device 412 or the value of the output 408 or 410 of the select device 414). The select device 416 can utilize the outputs from the select devices 412 and 414 to generate the signal 390 for the first circuit 366 based on the polarity of the tap 1 bias sign bit (which is the polarity of the tap 1 bias that can be programmed and input into the mode register). For example, the mode register can be programmed for a tap 1 correction +50 mV bias, which indicates a positive sign for the tap 1 bias (i.e., the tap 1 bias sign bit is "+"), and the select device 416 can select the output of the select device 412. In some embodiments, the mode register may be programmed for a −50 mV bias, which indicates a negative sign for the tap 1 bias (ie, the tap 1 bias sign bit is “−”), and the select device 416 may select the output of the select device 414 .

[0104] Hybrid loop unrolling DFE architecture

[0105] In some embodiments, the DFE (decision feedback equalization) technique in the hybrid loop unrolling DFE circuit may not be used, which can be used in low-speed modes, various DIMM architectures, and the like. For example, in this hybrid loop unrolling DFE architecture, only one of the two latches of the distortion correction circuit (e.g., distortion correction circuit 280) may be used. That is, only those equalizers corresponding to one possible value of the previous bit (e.g., logic high or logic low) may be used in the hybrid loop unrolling DFE circuit. Those equalizers corresponding to the other possible values ​​of the previous bit may be disabled in the hybrid loop unrolling DFE circuit when the DFE technique is not used (e.g., if logic high is used, logic low may be disabled, and if logic low is used, logic high may be disabled). Thus, the hybrid loop unrolling DFE architecture can save power when the DFE technique is not used because only a portion of the total equalizers in the hybrid loop unrolling DFE circuit may be used. Figure 16 A hybrid loop unrolling DFE architecture is illustrated for the distortion correction circuit 280 that may implement this solution.

[0106] Figure 16 A block diagram illustrating the hybrid loop unrolling DFE architecture of the distortion correction circuit 280, i.e., the hybrid loop unrolling DFE circuit 281, which may implement an efficient solution to disable one of the two latches (i.e., equalizer 282 or 284) to save power when the DFE is not in use. Figure 16 In FIG. 2 , when DFE is not used, the voltage correction signal 292 transmitted to the equalizer 282 may be the same as the voltage correction signal 294 transmitted to the equalizer 284. When the n-1 bit is a logic high, the output 296 from the equalizer 282 represents the correction bit 88, and the ENHI signal may be used to enable / disable the equalizer 282. When the n-1 bit is a logic low, the output 298 from the equalizer 284 represents the correction bit 88, and the ENLO signal may be used to enable / disable the equalizer 284.

[0107] In some embodiments, the DFE may be enabled or disabled based on the value of a disable (DisF) signal. When the DisF signal has a high value, the DFE may be enabled, and both equalizers (i.e., equalizer 282 and equalizer 284) in the hybrid loop unrolling DFE circuit 281 may be enabled. When the DisF signal has a low value, the DFE may be disabled, and one of the two equalizers (i.e., equalizer 282 or equalizer 284) in the hybrid loop unrolling DFE circuit 281 may be selected to be disabled.

[0108] In some embodiments, when the DFE is disabled, those equalizers that represent the correction bit 88 when the n-1 bit is a logic high may be enabled (e.g., equalizer 282 in the hybrid loop unrolling DFE circuit 281), and the DisF signal may be applied to ENLO. Thus, equalizer 284 may be disabled and equalizer 282 may be used in the hybrid loop unrolling DFE architecture of the hybrid loop unrolling DFE circuit 281. In the above embodiment, the ENHI signal may be calculated based on the logical AND of the EN signal and the external VDD, and the ENLO signal may be calculated based on the logical AND of the EN signal and the DisF signal. In some embodiments, the equalizer 284 and its associated circuitry may be disabled by disconnecting the equalizer 284 and its associated circuitry from a power source (e.g., a voltage source).

[0109] In some embodiments, when the DFE is disabled, those equalizers that represent the correction bit 88 when the n-1 bit is a logic low can be enabled (e.g., equalizer 284 in the hybrid loop unrolling DFE circuit 281), and the DisF signal can be applied to ENHI. In the above embodiment, the ENLO signal can be calculated based on the logical AND of the EN signal and the external VDD, and the ENHI signal can be calculated based on the logical AND of the EN signal and the DisF signal. Thus, equalizer 282 can be disabled and equalizer 284 can be used in the hybrid loop unrolling DFE architecture of the hybrid loop unrolling DFE circuit 281. In some embodiments, equalizer 282 and its associated circuitry can be disabled by disconnecting the equalizer 282 and its associated circuitry from a power source (e.g., a voltage source).

[0110] In some embodiments, when the DisF signal has a high value, the DFE may be enabled, and an n-1-bit data signal (e.g., a logic 1 or a logic 0) may be transmitted via path 72. When the DisF signal has a low value, the DFE may be disabled, and the n-1-bit data signal (e.g., a logic 1 or a logic 0) may be floating, and a keeper signal 418 from the keeper device 420 may be transmitted along path 72 as a selection control signal (e.g., a multiplexer selection or control signal) to the selection device 286, such that the output from the selection device 286 may be selected from the output signal 296 and the output signal 298 according to the keeper signal 418. In these embodiments, when the DFE is disabled, the DisF signal is transmitted to the keeper device 420, and the keeper device 420 may output the keeper signal 418 based on the DisF signal (e.g., the keeper signal 418 may be a logic high signal, a logic low signal, or may be floating based on the value of the DisF signal). In one embodiment, the keeper device 420 may include a transistor configured to receive the DisF signal at its gate. In the above embodiment, when DisF has a high value, the transistors are arranged so that the keeper signal 418 can be floating.

[0111] In some embodiments, when the DFE is disabled, those equalizers that represent the correction bit 88 when the n-1 bit is a logic high may be enabled (e.g., the equalizer 282 in the hybrid loop unrolling DFE circuit 281), and the keeper signal 418 may provide a logic high signal to the selection device 286. Thus, the output 296 from the equalizer 282 may be selected as the correction bit 88. In the above embodiment, when the DisF has a low value and the keeper signal 418 is a logic high signal, the keeper device 420 may be arranged with its associated circuitry (e.g., an additional signal indicating that those equalizers that represent the correction bit 88 when the n-1 bit is a logic high may be used) to output a feedback high.

[0112] In some embodiments, when DFE is disabled, those equalizers that represent the correction bit 88 when the n-1 bit is a logic low may be used (e.g., the equalizer 284 in the hybrid loop unrolling DFE circuit 281), the keeper signal 418 may provide a logic low signal, and the output 298 from the equalizer 284 may be selected as the correction bit 88. In the above embodiment, when DisF has a low value and the keeper signal 418 is a logic low signal, the keeper device 420 may be arranged with its associated circuitry (e.g., an additional signal indicating that those equalizers that represent the correction bit 88 when the n-1 bit is a logic low may be used) to output a feedback low.

[0113] Figure 17 An embodiment of a hybrid cycle unrolling DFE architecture for distortion correction circuit 364 (i.e., a basic 2-phase input receiver with a cycle-unrolled 1-tap DFE) is illustrated, namely, hybrid cycle unrolling DFE circuit 365, which can implement an efficient solution to disable one of the two latches of each circuit (i.e., equalizer 370 or 372 of first circuit 366, equalizer 396 or 398 of second circuit 368) when the DFE is not in use to save power. Hybrid cycle unrolling DFE circuit 365 includes first circuit 366 and second circuit 368, which can be distortion correction circuits similar to distortion correction circuit 280 with their respective inputs and feedback modified to correspond to the 2-phase input and feedback. Therefore, first circuit 366 and second circuit 368 in hybrid cycle unrolling DFE circuit 365 can operate in a manner similar to hybrid cycle unrolling DFE circuit 281.

[0114] To further elaborate, Figure 17In FIG. 3 , when DFE is not used, the voltage correction signal 374 transmitted to equalizer 370 may be the same as the voltage correction signal 376 transmitted to equalizer 372. For the same reason, the voltage correction signal 400 transmitted to equalizer 396 may be the same as the voltage correction signal 402 transmitted to equalizer 398. The ENHI signal may be used to enable / disable equalizers 370 and 396, and the ENLO signal may be used to enable / disable equalizers 372 and 398. In some embodiments, the DFE may be enabled or disabled based on the value of the DisF signal. When the DisF signal has a high value, the DFE may be enabled, and all equalizers in the hybrid cycle unrolling DFE circuit 365 (i.e., equalizers 370, 372, 396, and 398) may be enabled. When the DisF signal has a low value, the DFE may be disabled, and one of the two equalizers in each circuit (e.g., the first circuit 366 or the second circuit 368) of the hybrid cycle unrolling DFE circuit 365 (i.e., the equalizer 370 or 372 in the first circuit 366 or the equalizer 396 or 398 in the second circuit 368) may be selected to be disabled.

[0115] In some embodiments, when DFE is disabled, equalizers that represent the correction bit 88 when the n-1 bit is a logic high may be enabled (e.g., equalizer 370 in first circuit 366 and equalizer 396 in second circuit 368), and the DisF signal may be applied to ENLO. In these embodiments, the ENHI signal may be calculated based on the logical AND of the EN signal and the external VDD, and the ENLO signal may be calculated based on the logical AND of the EN signal and the DisF signal. Thus, equalizers 372 and 398 may be disabled, and equalizers 370 and 396 may be enabled in the hybrid loop unrolling DFE circuit 365. In some embodiments, equalizer 372 and its associated circuitry may be disabled by disconnecting equalizer 372 and its associated circuitry from a power source (e.g., a voltage source). In some embodiments, equalizer 398 and its associated circuitry may be disabled by disconnecting equalizer 398 and its associated circuitry from a power source (e.g., a voltage source).

[0116] In some embodiments, when DFE is disabled, equalizers that represent correction bit 88 when bit n-1 is logic low (e.g., equalizer 372 in first circuit 366 and equalizer 398 in second circuit 368) can be enabled, and DisF can be applied to ENHI. In the above embodiment, the ENLO signal can be calculated based on the logical AND of the EN signal and external VDD, and the ENHI signal can be calculated based on the logical AND of the EN signal and the DisF signal. Thus, equalizers 370 and 396 can be disabled, and equalizers 372 and 398 can be used in the hybrid loop unrolling DFE architecture of hybrid loop unrolling DFE circuit 365. In some embodiments, equalizer 370 and its associated circuitry can be disabled by disconnecting equalizer 370 and its associated circuitry from a power source (e.g., a voltage source). In some embodiments, equalizer 396 and its associated circuitry can be disabled by disconnecting equalizer 396 and its associated circuitry from a power source (e.g., a voltage source).

[0117] In some embodiments, when the DisF signal has a high value, the DFE may be enabled, and the n-1-bit value generated by the selection device 416 in the second circuit 368 (e.g., the bit value received in the second phase) may be transmitted along the path 390 to the selection devices 386 and 388. When the DisF signal has a low value, the DFE may be disabled, and the n-1-bit value generated by the selection device 416 in the second circuit 368 (e.g., the bit value received in the second phase) may be configured to float, and the keeper signal 422 from the keeper device 424 may be transmitted along the path 390 as a selection control signal (e.g., a multiplexer select or control signal) to the selection devices 386 and 388, such that the outputs from the selection devices 386 and 388 may be selected according to the keeper signal 422. In these embodiments, when the DFE is disabled, the DisF signal is transmitted to the keeper device 424, and the keeper device 424 may output a keeper signal 422 based on the DisF signal (e.g., the keeper signal 422 may be a logic high signal, a logic low signal, or may be floating based on the value of the DisF signal). In one embodiment, the keeper device 424 may include a transistor configured to receive the DisF signal at its gate. In the above embodiment, when the DisF has a high value, the transistor is arranged so that the keeper signal 422 may be floating.

[0118] In some embodiments, when the DFE is disabled, those equalizers that represent the correction bit 88 when the n-1 bit is a logic high may be enabled (e.g., equalizers 370 and 396 in the hybrid loop unrolling DFE circuit 365), and the keeper signal 422 may provide a logic high signal to the selection devices 386 and 388, so that the outputs 378 and 382 from the equalizer 370 may be selected as the correction bit 88 for the selection devices 386 and 388, respectively. In the above embodiment, when the DisF signal has a low value and the keeper signal 422 is a logic high signal, the keeper device 424 may be arranged with its associated circuitry (e.g., an additional signal indicating that those equalizers that represent the correction bit 88 when the n-1 bit is a logic high may be used) to output a feedback high.

[0119] In some embodiments, when the DFE is disabled, those equalizers that represent the correction bit 88 when the n-1 bit is a logic low may be enabled (e.g., equalizers 372 and 398 in the hybrid loop unrolling DFE circuit 365), and the keeper signal 422 may provide a logic low signal to the selection devices 386 and 388, so that the outputs 380 and 384 from the equalizer 372 may be selected as the correction bit 88 for the selection devices 386 and 388, respectively. In the above embodiment, when the DisF signal has a low value and the keeper signal 422 is a logic low signal, the keeper device 424 may be arranged with its associated circuitry (e.g., an additional signal indicating that those equalizers that represent the correction bit 88 when the n-1 bit is a logic high may be used) to output a feedback low.

[0120] In some embodiments, when the DisF signal has a high value, the DFE may be enabled, and the n-1-bit value generated by the selection device 392 in the second circuit 368 (e.g., the bit value received in the second phase) may be transmitted along the path 394 to the selection devices 412 and 414. When the DisF signal has a low value, the DFE may be disabled, and the n-1-bit value generated by the selection device 392 in the second circuit 368 (e.g., the bit value received in the second phase) may be configured to float, and the keeper signal 426 from the keeper device 428 may be transmitted along the path 394 as a selection control signal (e.g., a multiplexer select or control signal) to the selection devices 412 and 414, such that the outputs from the selection devices 412 and 414 may be selected according to the keeper signal 426. In these embodiments, when the DFE is disabled, the DisF signal is transmitted to the keeper device 428, and the keeper device 428 may output a keeper signal 426 based on the DisF signal (e.g., the keeper signal 426 may be a logic high signal, a logic low signal, or may be floating based on the value of the DisF signal). In one embodiment, the keeper device 428 may include a transistor configured to receive the DisF signal at its gate. In the above embodiment, when the DisF has a high value, the transistor is arranged so that the keeper signal 426 may be floating.

[0121] In some embodiments, when the DFE is disabled, those equalizers that represent the correction bit 88 when the n-1 bit is a logic high may be enabled (e.g., equalizers 370 and 396 in the hybrid loop unrolling DFE circuit 365), and the keeper signal 426 may provide a logic high signal to the selection devices 412 and 414, so that the outputs 404 and 408 from the equalizer 396 may be selected as the correction bit 88 for the selection devices 412 and 414, respectively. In the above embodiment, when the DisF has a low value and the keeper signal 426 is a logic high signal, the keeper device 428 may be arranged with its associated circuitry (e.g., an additional signal indicating that those equalizers that represent the correction bit 88 when the n-1 bit is a logic high may be used) to output a feedback high.

[0122] In some embodiments, when the DFE is disabled, those equalizers that represent the correction bit 88 when the n-1 bit is a logic low may be enabled (e.g., equalizers 372 and 398 in the hybrid loop unrolling DFE circuit 365), and the keeper signal 426 may provide a logic low signal to the selection devices 412 and 414, so that the outputs 406 and 410 from the equalizer 398 may be selected as the correction bit 88 for the selection devices 412 and 414, respectively. In the above embodiment, when the DisF has a low value and the keeper signal 426 is a logic low signal, the keeper device 428 may be arranged with its associated circuitry (e.g., an additional signal indicating that those equalizers that represent the correction bit 88 when the n-1 bit is a logic high may be used) to output a feedback low.

[0123] In some embodiments, Figure 16 and Figure 17 The techniques and methods described in the present invention can be used in a hybrid cycle unrolling DFE circuit with a multi-phase input (e.g., 2-phase or 4-phase). In some embodiments, Figure 16 and Figure 17 The techniques and methods described in

[0014] can be used in multi-tap hybrid loop expansion DFE circuits (e.g., n-4, n-3, n-2, and n-1 bit loop expansion distortion correction circuits). In some embodiments, Figure 16 and Figure 17 The techniques and methods described in the present disclosure may be used in complex hybrid cycle unrolling DFE circuits, which may include a mixture of cycle unrolling DFE circuits having multi-phase inputs with different numbers of phases (e.g., one or more 2-phase cycle unrolling DFE circuits mixed with one or more 4-phase cycle unrolling DFE circuits, etc.), a mixture of multi-tap cycle unrolling DFE circuits with different taps (e.g., one or more tap 1 cycle unrolling DFE circuits mixed with one or more tap 2 cycle unrolling DFE circuits, etc.), and any combination thereof.

[0124] Figure 18Is used to illustrate the Figure 16 and 17 4. At block 432, a disable command may be received by the memory device 10. The disable command may include information related to an identification of distortion correction circuits that may be disabled for the DFE technique (e.g., n-4, n-3, n-2, or n-1 bit loop unrolling distortion correction circuits in a loop unrolling DFE circuit). In some embodiments, the disable command may include an identification of an equalizer in each of the distortion correction circuits that may be disabled for the DFE technique, such as the equalizer corresponding to the previous bit data (e.g., n-4, n-3, n-2, or n-1 bit) that was read as a logic high or low. Figure 18 The flowchart illustrates that at block 434, those equalizers that are disabled, such as the correction latch when assuming n-1 reads high or the correction latch when assuming n-1 reads low (e.g., equalizer 282 or 284 in hybrid loop unrolling DFE circuit 281), may be determined. Figure 18 At block 434, a disable (DisF) signal is also determined.

[0125] exist Figure 18 At blocks 436 and 438 of the MCU, the ENHI and ENLO signals may be determined based on the disable command. The ENHI signal may be used to enable / disable equalizers when n-1 is read as high, and the ENLO signal may be used to enable / disable equalizers when n-1 is read as low. For example, in the hybrid loop unrolling DFE circuit 281, the ENHI signal may be used to enable / disable equalizer 282, and the ENLO signal may be used to enable / disable equalizer 284. In some embodiments, the ENHI signal may be calculated based on the logical AND of the EN signal and the external VDD, and the ENLO signal may be calculated based on the logical AND of the EN signal and the disable (DisF) signal. Thus, in these embodiments, equalizer 284 may be disabled and equalizer 282 may be used in the hybrid loop unrolling DFE circuit 281. It should be noted that in some embodiments, the ENLO signal may be calculated based on the logical AND of the EN signal and the external VDD, and the ENHI signal may be calculated based on the logical AND of the EN signal and the disable (DisF) signal, and therefore, in those embodiments, the equalizer 282 may be disabled and the equalizer 284 may be used in the hybrid loop unrolling DFE circuit 281.

[0126] exist Figure 18 At block 440 , a disable (DisF) signal may be transmitted to a keeper device (e.g., the keeper device 420 in the hybrid cycle unrolling DFE circuit 281 ), and the keeper device may output a keeper signal based on the disable (DisF) signal (e.g., the keeper signal 418 from the keeper device 420 may be a logic high signal, a logic low signal, or may be floating based on the value of the disable (DisF) signal).

[0127] exist Figure 18 At block 442 of FIG. 4 , the keeper signal is transmitted to a selection device, such as selection device 286 in hybrid loop unrolling DFE circuit 281. The selection device may receive the output from the equalizer assuming n-1 reads high (e.g., output 296 from equalizer 282) and the output from the equalizer assuming n-1 reads low (e.g., output 298 from equalizer 284).

[0128] exist Figure 18 At box 444, the output from the selection device can be selected based on the retainer signal from the outputs produced by those equalizers when it is assumed that n-1 is read as high (e.g., output 296 from equalizer 282) and the outputs produced by those equalizers when it is assumed that n-1 is read as low (e.g., output 298 from equalizer).

[0129] Therefore, the technical effects of the present disclosure include a method and system that, when the DFE is not in use, only enables those equalizers in a hybrid cycle unrolling DFE circuit that correspond to a specific possibility (e.g., logic high or logic low) of the value of the previous bit. Equalizers corresponding to possibilities other than the specific possibility of the value of the previous bit can be disabled in the hybrid cycle unrolling DFE circuit. As a result, the hybrid cycle unrolling DFE architecture can save power when the DFE is not in use, as only a portion of the total equalizers in the hybrid cycle unrolling DFE circuit can be enabled and powered, while the other equalizers in the hybrid cycle unrolling DFE circuit can be disabled and disconnected from power.

[0130] While the present disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the present disclosure is not intended to be limited to the particular forms disclosed. Rather, the present disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.

[0131] Reference to the techniques presented and claimed herein and their application to material objects and specific examples of practical nature clearly advances the art and is therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to the end of this specification contains one or more elements referred to as "means for [performing] [the function]" or "a step for [performing] [the function]," it is intended that such elements be interpreted under 35 U.S.C. § 112(f). However, for any claim containing elements referred to in any other manner, it is intended that such elements not be interpreted under 35 U.S.C. § 112(f).

Claims

1. An apparatus for a hybrid loop unrolling decision feedback equalizer, comprising: a first equalizer configured to generate a first signal for an input signal based on a first value of a previous signal received before receiving the input signal; a second equalizer configured to generate a second signal for the input signal based on a second value of the previous signal received before receiving the input signal; a selection device configured to receive the first signal and the second signal; and A keeper device configured to generate a keeper signal based on a disable signal, wherein the disable signal is configured to disable one of the first equalizer and the second equalizer based on the first value or the second value, and wherein the selection device is configured to selectively output one of the first signal and the second signal in response to receiving the keeper signal from the keeper device.

2. The device of claim 1, wherein the keeper device comprises a transistor.

3. The device of claim 1 , wherein the first equalizer is configured to: receiving a first input signal; receiving a first reference signal; receiving a first adjustment signal; and The first signal is generated based on a first set of data transmitted via the first input signal, the first reference signal, and a clock signal, wherein the first adjustment signal is determined based on the disable signal.

4. The device of claim 3, wherein the second equalizer is configured to: receiving a second input signal; receiving a second reference signal; receiving a second adjustment signal; and The second signal is generated based on the first set of data transmitted via the second input signal, the second reference signal, and the clock signal, wherein the second adjustment signal is determined based on the disable signal.

5. The device of claim 4, wherein the second equalizer is configured to be disabled based on the second adjustment signal. The device of claim 3 , wherein the first equalizer is configured to be disabled based on the first adjustment signal. The apparatus of claim 6 , wherein disabling the first equalizer comprises disconnecting the first equalizer from a power source.

8. The apparatus of claim 1, wherein the selecting means comprises a multiplexer.

9. The device of claim 1, wherein the selecting means is configured to output the first signal to a deserializer based on the keeper signal having a first value.

10. The device of claim 9, wherein the selecting means is configured to output the second signal to the deserializer based on the keeper signal having a second value.

11. A method for implementing a retainer device, comprising: receiving a deactivation command; determining a disable signal for an equalizer based on the disable command, wherein the equalizer is configured to generate a corresponding signal for the input signal based on a value of a previous signal received by the equalizer prior to receiving the input signal, and wherein the disable signal is determined based on the value; determining an adjustment signal for the equalizer based on the deactivation signal; sending the disable signal to a keeper device, wherein the keeper device is configured to generate a keeper signal based on the disable signal; and The keeper signal is sent to a selection device, wherein the selection device is configured to receive the corresponding signal from the equalizer and selectively output the corresponding signal based on the keeper signal. The method of claim 11 , comprising disabling the equalizer based on the adjustment signal. The method of claim 12 , wherein disabling the equalizer comprises disconnecting the equalizer from a power source.

14. The method of claim 11, wherein the selection device is configured to selectively output the corresponding signal from the equalizer based on the holder signal having a first value.

15. A distortion correction circuit comprising: a first equalizer configured to generate a first signal for a first input signal received by the distortion correction circuit, wherein the first signal is generated based on a value of a previous signal, and wherein the previous signal is determined to be for a second input signal received by the distortion correction circuit prior to receiving the first input signal; a second equalizer configured to generate a second signal for the second input signal; a first keeper device configured to generate a first keeper signal based on a disable signal, wherein the distortion correction circuit is configured to selectively output the second signal as the disable signal determined for the second input signal in response to the first keeper signal from the first keeper device; and a second keeper device configured to generate a second keeper signal based on the disable signal, wherein the distortion correction circuit is configured to selectively output the first signal in response to the second keeper signal from the second keeper device, and wherein the first equalizer is selectively disabled based on a value of the disable signal. 16 . The distortion correction circuit of claim 15 , comprising a first multiplexer configured to receive the second keeper signal and the first signal, wherein the first multiplexer is configured to selectively output the first signal based on the second keeper signal.

17. The distortion correction circuit of claim 15, comprising a second multiplexer configured to receive the first keeper signal and the second signal, wherein the second multiplexer is configured to selectively output the second signal as the disable signal determined for the second input signal based on the first keeper signal.

18. The distortion correction circuit of claim 15, wherein the first equalizer is configured to generate the first signal based on a first clock signal, and the second equalizer is configured to generate the second signal based on a second clock signal.

19. The distortion correction circuit of claim 15, wherein the first equalizer is configured to be disabled based on the disable signal.

20. The distortion correction circuit of claim 19, wherein disabling the first equalizer comprises disconnecting the first equalizer from a power source.

21. An apparatus for a hybrid loop unrolling decision feedback equalizer, comprising: a plurality of equalizers configured to receive one or more input signals and generate a plurality of signals based on the one or more input signals, wherein the plurality of equalizers are configured to correct distortion of the one or more input signals using decision feedback equalization by generating the plurality of signals based on one or more previous signals received before receiving the one or more input signals; and One or more keeper devices configured to generate respective keeper signals based on a disable signal, wherein the disable signal is provided to disable decision feedback equalization of the device based on the one or more previous signals received prior to receiving the one or more input signals.

22. The device of claim 21, comprising one or more multiplexers configured to receive the multiple signals generated by the multiple equalizers and selectively output corresponding signals based on corresponding keeper signals received from the one or more keeper devices.

23. The device of claim 21, wherein at least one of the plurality of equalizers is disabled based on the disable signal.

24. The device of claim 23, wherein disabling the at least one of the plurality of equalizers comprises disconnecting the at least one of the plurality of equalizers from a power source.

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