Clock generation circuit, control method and image sensor

Abstract

The present application provides a clock generation circuit, a control method and an image sensor, which tracks the frequency and phase of a received input clock signal through a phase-locked loop circuit to output a first output clock signal, and feeds back a second output clock signal to the input end of the phase-locked loop circuit; a delay circuit delays the first output clock signal to output a delayed clock signal; a detection circuit receives an external input reference clock signal and a delayed clock signal, and outputs a detection signal based on the frequency and / or phase of the two; the delay circuit adjusts the delay time of the first output clock signal based on the detection signal, and establishes an internal clock signal with the same phase as the second output clock signal based on the delayed clock signal and the delay time; a selection circuit selects to output an external input reference clock signal or an internal clock signal to the phase-locked loop circuit based on the detection signal; the present application does not need to occupy the interface input external input reference clock signal, thereby improving data transmission efficiency.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic circuits, and in particular relates to a clock generation circuit, a control method for the clock generation circuit, and an image sensor. Background Art

[0002] Miniature camera modules are small and simple in structure, typically using an Inter-Integrated Circuit (I2C) interface for data transmission. However, if a single port is used for clock signal input, operation becomes cumbersome and data transmission efficiency is low. Therefore, when miniature camera modules use a four-port structure, it is impossible to allocate a port to provide a reference clock signal to the module's internal phase-locked loop (PLL). In this case, the clock signal must be generated entirely within the module's internal circuitry. However, the frequency generated by the oscillator varies significantly depending on factors such as process technology, making it difficult to meet application requirements. Summary of the Invention

[0003] The purpose of this application is to provide a clock generating circuit, a control method of the clock generating circuit and an image sensor, aiming to solve the problem that the related clock generating circuit cannot generate a clock signal through the internal circuit of the module.

[0004] The embodiment of the present application provides a clock generation circuit, comprising: a phase-locked loop circuit, a delay circuit, a selection circuit, and a detection circuit;

[0005] The phase-locked loop circuit is configured to track the frequency and phase of the input clock signal it receives, so as to output a first output clock signal to the delay circuit, and feed back a second output clock signal to the input end of the phase-locked loop circuit;

[0006] The delay circuit is configured to delay the first output clock signal to output a delayed clock signal;

[0007] The detection circuit is configured to receive an external input reference clock signal and the delayed clock signal, and output a detection signal based on the frequency and / or phase of the two;

[0008] The delay circuit adjusts the delay time of the first output clock signal based on the detection signal, and establishes an internal clock signal based on the delayed clock signal and the delay time, wherein the internal clock signal has the same phase as the second output clock signal;

[0009] The selection circuit is configured to receive the external input reference clock signal and the internal clock signal, and select to output the external input reference clock signal or the internal clock signal to the phase-locked loop circuit based on the detection signal.

[0010] The embodiment of the present application also provides a control method for the above-mentioned clock generating circuit, wherein the clock generating circuit includes a clock signal establishment state and a clock signal stable output state;

[0011] In the clock signal establishment state, the external input reference clock signal is connected to the detection circuit and the selection circuit, and the selection circuit outputs the external input reference clock signal to the phase-locked loop circuit as the input clock signal of the phase-locked loop circuit; the phase-locked loop circuit outputs the first output clock signal and the second output clock signal with a constant phase difference based on the external input reference clock signal; the delay circuit delays the first output clock signal and outputs the delayed clock signal; the detection circuit compares the frequency and phase of the external input reference clock signal and the delayed clock signal, and outputs the detection signal; the delay circuit adjusts the delay time based on the detection signal to output the internal clock signal with the same frequency and phase as the second output clock signal;

[0012] When the clock signal is in a stable output state, the connection of the external input reference clock signal is disconnected, and the selection circuit outputs the internal clock signal to the phase-locked loop circuit as the input clock signal of the phase-locked loop circuit.

[0013] An embodiment of the present invention further provides an image sensor, which includes the above-mentioned clock generating circuit and a control method of the above-mentioned clock generating circuit.

[0014] Compared with the prior art, the embodiments of the present invention have the following advantages: after the internal clock signal is aligned with the external input reference clock signal, the internal clock signal is used as the reference clock, and the clock terminal SCL of the external interface is no longer required to access the external input reference clock signal. At this time, the clock terminal SCL can be used to transmit data, thereby improving the data transmission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical inventions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 A schematic diagram of the structure of a clock generation circuit provided in one embodiment of the present application;

[0017] Figure 2 Another structural diagram of a clock generation circuit provided in an embodiment of the present application;

[0018] Figure 3 A schematic diagram of the structure of a logic circuit in a clock generation circuit provided in one embodiment of the present application;

[0019] Figure 4 A schematic structural diagram of a phase-locked loop circuit in a clock generation circuit provided in an embodiment of the present application;

[0020] Figure 5 A schematic diagram of the structure of a delay circuit in a clock generation circuit provided in one embodiment of the present application;

[0021] Figure 6 Another structural diagram of a phase-locked loop circuit in a clock generation circuit provided in an embodiment of the present application;

[0022] Figure 7 A partial exemplary circuit schematic diagram of a clock generation circuit provided in one embodiment of the present application;

[0023] Figure 8 A schematic diagram of an output waveform of a voltage-controlled oscillator in a clock generation circuit provided in an embodiment of the present application;

[0024] Figure 9 A schematic diagram of a key waveform of a clock generation circuit provided in one embodiment of the present application;

[0025] Figure 10 Another key waveform diagram of the clock generation circuit provided in one embodiment of the present application;

[0026] Figure 11 Schematic diagram of the four-port structure of the micro camera module. DETAILED DESCRIPTION

[0027] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0028] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0029] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0030] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0031] Figure 1 A schematic diagram of the structure of a clock generation circuit provided in a preferred embodiment of the present application is shown. For ease of explanation, only the parts related to this embodiment are shown, which are described in detail as follows:

[0032] The clock generating circuit includes a phase-locked loop circuit 12 , a delay circuit 13 , a selection circuit 11 and a detection circuit 15 .

[0033] The PLL circuit 12 is configured to track the frequency and phase of the input clock signal it receives, so as to output a first output clock signal to the delay circuit 13 , and feed back a second output clock signal to the input terminal of the PLL circuit 12 .

[0034] The delay circuit 13 is configured to delay the first output clock signal to output a delayed clock signal.

[0035] The detection circuit 15 is configured to receive an external input reference clock signal and a delayed clock signal, and output a detection signal based on the frequency and / or phase of the two.

[0036] The delay circuit 13 adjusts the delay time of the first output clock signal based on the detection signal, and establishes an internal clock signal based on the delayed clock signal and the delay time. The internal clock signal has the same phase as the second output clock signal.

[0037] The selection circuit 11 is configured to receive an external input reference clock signal and an internal clock signal, and select to output the external input reference clock signal or the internal clock signal to the phase-locked loop circuit 12 based on the detection signal.

[0038] In different stages, the input clock signal is an external input reference clock signal or an internal clock signal.

[0039] The working process of the clock generation circuit is divided into the following three stages:

[0040] 1. Phase-locked loop establishment stage. At this stage, the external input reference clock signal is input from the clock terminal SCL of the I2C interface. The selection circuit 11 connects the external input reference clock signal to the phase-locked loop circuit 12 as the reference clock. That is, the input clock signal received by the phase-locked loop circuit 12 at this stage is the external input reference clock signal.

[0041] 2. Self-calibration signal generation stage. After a certain period of time, the phase-locked loop circuit locks, and the phase-locked loop circuit 12 outputs two signals with a phase difference (a first output clock signal and a second output clock signal). The first output clock signal is delayed by the delay circuit 13, and the detection circuit 15 compares the adjusted first output clock signal with the external input reference clock. Ultimately, the two input signals of the detection circuit 15 (the adjusted first output clock signal and the external input reference clock signal) have no phase difference, and the delay circuit 13 outputs the adjusted first output clock signal with no phase difference as the internal clock signal.

[0042] 3. Phase-locked loop output stabilization stage. When the internal clock signal is aligned with the external input reference clock signal, the detection signal output by the detection circuit 15 is flipped, thereby triggering the selection circuit 11 to connect the internal clock signal to the phase-locked loop circuit 12 as the reference clock. That is, at this stage, the input clock signal received by the phase-locked loop circuit 12 is the internal clock signal. After that, the output frequency of the phase-locked loop circuit 12 is stable and no longer relies on the clock terminal SCL to connect to the external input reference clock signal.

[0043] Through the above three stages, the external input reference clock signal connected to the clock terminal SCL of the external interface is used to establish the internal clock signal. When the internal clock signal is aligned with the external input reference clock signal, the internal clock signal is used as the reference clock, and the clock terminal SCL no longer needs to be connected to the external input reference clock signal. At this time, the clock terminal SCL can be used to transmit data, thereby improving data transmission efficiency.

[0044] like Figure 2 As shown, the clock generating circuit further includes a logic circuit 16 .

[0045] The logic circuit 16 is electrically connected to the detection circuit 15 and the delay circuit 13 , and is configured to output a delay control signal to the delay circuit 13 according to the detection signal, so as to control the delay time of the delay circuit 13 .

[0046] The delay circuit 13 is specifically configured to delay the first output clock signal according to the delay control signal to output the internal clock signal; wherein, when the delay control signal is locked, the phase of the internal clock signal is the same as the phase of the second output clock signal.

[0047] like Figure 3 As shown, the logic circuit 16 includes a judgment circuit 161 , a counter 162 and a digital circuit 163 .

[0048] The determination circuit 161 is connected to the detection circuit 15 and configured to output a trigger signal and maintain or cut off the output of the trigger signal based on the detection signal.

[0049] The counter 162 is connected to the judgment circuit 161 and is configured to count and output a counting result when a trigger signal is received, and stop counting and lock the counting result when the trigger signal is disconnected.

[0050] The digital circuit 163 is connected to the counter 162 and the delay circuit 13 and is configured to output a delay control signal according to the counting result.

[0051] Since counter 162 counts and outputs a count result upon receiving a trigger signal, and digital circuit 163 outputs a delay control signal based on the count result, the delay control signal is gradually adjusted when the internal clock signal is misaligned with the external input reference clock signal. Since judgment circuit 161 disconnects the output of the trigger signal upon receiving a detection signal, counter 162 stops counting when the trigger signal is disconnected to lock the count result. Therefore, the delay control signal is locked when the internal clock signal is aligned with the external input reference clock signal.

[0052] like Figure 4 As shown, the phase-locked loop circuit 12 includes a phase frequency detector 121 , a charge pump 122 , a main loop filter 123 and a voltage-controlled oscillator 124 .

[0053] The phase frequency detector 121 is connected to the selection circuit 11 and is configured to detect a phase difference between the input clock signal and the second output clock signal and generate a first control signal.

[0054] It can be understood that, at different stages, the input clock signal is an external input reference clock signal or an internal clock signal.

[0055] The charge pump 122 is connected to the phase and frequency detector 121 and is configured to charge and discharge according to the first control signal to output a first control voltage.

[0056] The main loop filter 123 is connected to the charge pump 122 and is configured to filter the first control voltage to generate a modulation voltage.

[0057] The voltage controlled oscillator 124 is connected to the main loop filter 123 and the delay circuit 13 and is configured to output a first output clock signal and a second output clock signal whose frequencies are proportional to the modulation voltage.

[0058] like Figure 5 As shown, the delay circuit 13 includes a first frequency divider 132 and a variable delay module 131. The variable delay module 131 delays the first output clock signal based on the detection signal and outputs the delayed clock signal to the first frequency divider 132 to expand the frequency range of the delayed clock signal. Figure 6 As shown, the phase-locked loop circuit 12 further includes a second frequency divider 125 , which is connected to the voltage-controlled oscillator 124 and the phase frequency detector 121 , and is configured to divide the second output clock signal to output the divided second output clock signal to the input end of the phase frequency detector 121 .

[0059] The first frequency divider 132 and the second frequency divider 125 have the same frequency division ratio.

[0060] When the frequency of the output clock signal of the phase-locked loop circuit 12 is too high, since the phase frequency detector 121 has a certain upper frequency limit, the output signal needs to be reduced from high to low frequency using a frequency divider.

[0061] The present application also provides a control method for the above-mentioned clock generating circuit, which includes a clock signal establishment state and a clock signal stable output state; in the clock signal establishment state, an external input reference clock signal is connected to the detection circuit 15 and the selection circuit 11, and the selection circuit 11 outputs the external input reference clock signal to the phase-locked loop circuit 12 as the input clock signal of the phase-locked loop circuit 12; the phase-locked loop circuit 12 outputs a first output clock signal and a second output clock signal with a constant phase difference based on the external input reference clock signal; the delay circuit 13 delays the first output clock signal and outputs a delayed clock signal; the detection circuit 15 compares the frequency and phase of the external input reference clock signal and the delayed clock signal, and outputs a detection signal; the delay circuit 13 adjusts the delay time based on the detection signal to output an internal clock signal with the same frequency and phase as the second output clock signal.

[0062] In the clock signal stable output state, the connection of the external input reference clock signal is disconnected, and the selection circuit 11 outputs the internal clock signal to the phase-locked loop circuit 12 as the input clock signal of the phase-locked loop circuit 12 .

[0063] In combination with the three stages of the clock generation circuit operation process, the clock signal establishment state of this embodiment includes the phase-locked loop establishment stage and the self-calibration signal generation stage, and the clock signal stable output state is the phase-locked loop stable output stage.

[0064] Figure 7 A partial exemplary circuit structure of a clock generation circuit provided by an embodiment of the present invention is shown. For ease of illustration, only the portion related to the embodiment of the present invention is shown, which is described in detail as follows:

[0065] The voltage controlled oscillator 124 includes an operational amplifier U1 , a first inverter U2 , a second inverter U3 , and a third inverter U4 .

[0066] The non-inverting input terminal of the operational amplifier U1 serves as the modulation voltage input terminal of the voltage-controlled oscillator 124 and is connected to the main loop filter 123 to receive the modulation voltage; the inverting input terminal of the operational amplifier U1 is connected to the output terminal of the operational amplifier U1, the power supply terminal of the first inverter U2, the power supply terminal of the second inverter U3, and the power supply terminal of the third inverter U4; the input terminal of the first inverter U2 and the output terminal of the third inverter U4 jointly serve as the first output clock signal output terminal of the voltage-controlled oscillator 124 and are connected to the delay circuit 13 to output the first output clock signal; the output terminal of the second inverter U3 and the input terminal of the third inverter U4 jointly serve as the second output clock signal output terminal of the voltage-controlled oscillator 124 and are connected to the second frequency divider 125 to output the second output clock signal; the output terminal of the first inverter U2 is connected to the input terminal of the second inverter U3.

[0067] The voltage-controlled oscillator 124 is implemented through a three-stage ring oscillator. The modulation voltage is added to the power supply terminal of the inverter through the operational amplifier U1 (the operational amplifier U1 is used to prevent the ring oscillator from jittering) to control the ring oscillation frequency. It should be noted that the ring oscillator can be composed of three inverters connected to each other, or it can be composed of five inverters connected to each other. The number of inverters can be an odd number greater than 2 and form a loop.

[0068] Figure 8 is the output waveform of the three-stage ring oscillator. VX and VZ in the figure are the first output clock signal and the second output clock signal, respectively. It can be seen from the figure that the first output clock signal is delayed by 2π / 3 cycles, that is, it coincides with the waveform of the second output clock signal. Therefore, the circuit delay time at this time is 2π / 3 cycles.

[0069] like Figure 7 As shown, the variable delay module 131 includes a first field effect transistor M1, a second field effect transistor M2, a third field effect transistor M3, a fourth field effect transistor M4, a fifth field effect transistor M5, a sixth field effect transistor M6, n capacitors Ci and n switch transistors Ki; wherein n is a natural number greater than 0, and i is a positive integer less than or equal to n.

[0070] The drain of the first field-effect transistor M1 and the drain of the fifth field-effect transistor M5 are commonly connected to the first power supply VAA. The gate of the first field-effect transistor M1 serves as the first bias signal input terminal of the variable delay module 131 to receive the first bias signal. The source of the first field-effect transistor M1 is connected to the drain of the second field-effect transistor M2. The gate of the second field-effect transistor M2 and the gate of the third field-effect transistor M3 serve as the first output clock signal input terminal of the variable delay module 131 and are connected to the phase-locked loop circuit 12 to receive the first output clock signal. The source of the second field-effect transistor M2 is connected to the drain of the third field-effect transistor M3, the first input and output terminals of the n switching transistors Ki, the gate of the fifth field-effect transistor M5, and the gate of the sixth field-effect transistor M6. The i-th switching transistor K The second input and output terminals of the variable delay module 131 are connected to the first terminal of the i-th capacitor Ci. The second terminals of the n capacitors Ci, the source of the fourth field-effect transistor M4, and the source of the sixth field-effect transistor M6 are commonly connected to the power ground. The source of the third field-effect transistor M3 is connected to the drain of the fourth field-effect transistor M4. The gate of the fourth field-effect transistor M4 serves as the second bias signal input terminal of the variable delay module 131 to receive the second bias signal. The source of the fifth field-effect transistor M5 and the drain of the sixth field-effect transistor M6 serve as the delayed clock signal output terminal of the variable delay module 131 and are connected to the first frequency divider 132 to output the delayed clock signal. The control terminals of the n switch transistors Ki serve as the delay control signal input terminal of the variable delay module 131 to receive the delay control signal.

[0071] The variable delay module 131 changes the size of the capacitor connected to the circuit by turning on the switch tube, thereby adjusting the circuit delay time. The more capacitors are connected in parallel, the longer the delay time. The first field effect tube M1 and the fourth field effect tube M4 determine the size of the circuit charge and discharge current, which can be adjusted by the first bias signal and the second bias signal. It should be emphasized that in this application, the function of the variable delay module 131 can be realized without setting the first bias signal and the second bias signal, but in order to further improve the flexibility of circuit adjustment, the first bias signal and the second bias signal can be set to realize the control of the charge and discharge current according to the requirements of the circuit design.

[0072] Continue to refer Figure 7 , the detection circuit 15 includes a D flip-flop U5.

[0073] The data input terminal of the D flip-flop U5 serves as the external input reference clock signal input terminal of the detection circuit 15 to access the external input reference clock signal; the clock terminal of the D flip-flop U5 serves as the internal clock signal input terminal of the detection circuit 15 and is connected to the delay circuit 13 to access the internal clock signal; the data output terminal of the D flip-flop U5 and the reset terminal of the D flip-flop U5 serve together as the detection signal output terminal of the delay circuit 13 and are connected to the selection circuit 11 to output the detection signal.

[0074] In the detection circuit 15, the data input terminal of the D flip-flop U5 is connected to the external input reference clock signal, the clock terminal of the D flip-flop U5 is connected to the internal clock signal, and the data output terminal of the D flip-flop U5 is the output terminal of the detection circuit 15, and is connected to the reset terminal of the D flip-flop U5. Therefore, when the signal output by the D flip-flop U5 changes, that is, when the reset terminal changes from low to high, a set occurs, and the output state of the detection circuit 15 is locked.

[0075] The selection circuit 11 includes a first transmission gate U6 , a second transmission gate U7 , a fourth inverter U8 , and a fifth inverter U9 .

[0076] The input of the first transmission gate U6 serves as the internal clock signal input of the selection circuit 11 and is connected to the delay circuit 13 to receive the internal clock signal. The input of the second transmission gate U7 serves as the external reference clock signal input of the selection circuit 11 to receive the external reference clock signal. The input of the fourth inverter U8 serves as the detection signal input of the selection circuit 11 and is connected to the detection circuit 15 to receive the detection signal. The output of the fourth inverter U8 is connected to the input of the fifth inverter U9, the positive phase control terminal of the first transmission gate U6, and the negative phase control terminal of the second transmission gate U7. The output of the fifth inverter U9 is connected to the negative phase control terminal of the first transmission gate U6 and the positive phase control terminal of the second transmission gate U7. The output of the first transmission gate U6 and the output of the second transmission gate U7 serve as the internal clock signal output or the external reference clock signal output of the selection circuit 11 and are connected to the phase-locked loop circuit 12 to output the internal clock signal or the external reference clock signal.

[0077] The following is combined with the working principle Figure 7 As shown for further explanation:

[0078] The working process of the clock generation circuit is divided into the following three stages:

[0079] 1. Phase-Locked Loop Establishment Phase. At this point, the external input reference clock signal is input from the clock terminal SCL of the I2C interface to the input terminal of the second transmission gate U7. The data input terminal of the D-type flip-flop U5 receives the external input reference clock signal, but the clock terminal of the D-type flip-flop U5 does not receive the internal clock signal. The detection circuit 15 does not output a detection signal, i.e., the detection circuit 15 outputs a low-level signal. The eighth inverter U8 and the ninth inverter U9 invert the low-level signal output by the detection circuit 15 to obtain a pair of first transmission control signals with opposite polarities. Based on these first transmission control signals with opposite polarities, the second transmission gate U7 connects the external input reference clock signal to the phase-locked loop circuit 12 as a reference clock.

[0080] 2. Self-calibration signal generation stage. The phase-locked loop circuit 12 (including the frequency detector 121, charge pump 122, main loop filter 123, and voltage-controlled oscillator 124) tracks the frequency and phase of the external input reference clock signal it receives to output a first output clock signal to the delay circuit 13 and feed back a second output clock signal to the input of the phase-locked loop circuit 12. It should be noted that the frequency detector 121 detects the phase difference between the external input reference clock signal and the second output clock signal and generates a first control signal. The charge pump 122 charges and discharges according to the first control signal to output a first control voltage. The main loop filter 123 filters the first control voltage to generate a modulation voltage. The modulation voltage is applied to the power supply terminals of the three inverters through the operational amplifier U1 to control the ring oscillation frequency. The output of the third inverter U4 outputs the first output clock signal, and the output of the second inverter U3 outputs the second output clock signal. After a certain period of time, the phase-locked loop circuit 12 is locked. At this time, the phase-locked loop circuit 12 outputs two signals with a phase difference (a first output clock signal and a second output clock signal).

[0081] The judgment circuit 161 outputs a trigger signal; when the counter 162 receives the trigger signal, it counts and outputs a counting result; the digital circuit 163 outputs a delay control signal according to the counting result.

[0082] The first output clock signal is input to the gate of the second field-effect transistor M2 and the gate of the third field-effect transistor M3. The delay control signal is input to the control terminals of the n switching transistors Ki. By turning on the switching transistors Ki, the size of the capacitor connected to the circuit is changed, thereby adjusting the circuit delay time. The delayed clock signal is output from the source of the fifth field-effect transistor M5 and the drain of the sixth field-effect transistor M6. The first frequency divider 132 divides the delayed clock signal.

[0083] 3. Phase-locked loop output stabilization stage. In detection circuit 15, the data input of D-type flip-flop U5 is connected to the external input reference clock signal, and the clock input of D-type flip-flop U5 is connected to the divided delayed clock signal. When the phase of the external input reference clock signal and the delayed clock signal are the same, a set occurs when the reset terminal changes from low to high, and the output state of detection circuit 15 is locked and a high-level detection signal is output.

[0084] When receiving a high-level detection signal, judgment circuit 161 turns off the trigger signal output. Counter 162 stops counting when the trigger signal turns off, locking the count result. Digital circuit 163 outputs a locked delay control signal based on the locked count result. At this point, delay circuit 13 generates an internal clock signal that is in phase with the second output clock signal.

[0085] At this point, the eighth inverter U8 and the ninth inverter U9 invert the high-level detection signal output by the detection circuit 15, generating a pair of second transmission control signals with opposite polarities. Based on these second transmission control signals with opposite polarities, the first transmission gate U6 connects the internal clock signal to the phase-locked loop circuit 12 as a reference clock. The output frequency of the phase-locked loop circuit 12 is then stable and no longer relies on the clock terminal SCL to connect to the external input reference clock signal.

[0086] The waveforms of the key nodes of the above clock generation circuit are as follows: Figure 9 As shown in the figure, the first output clock signal A and the second output clock signal B have been stably established, but the internal clock signal has not yet been fully established. At this time, the phase difference between the first output clock signal A and the second output clock signal B is determined (for Figure 8 The three-stage ring oscillation in the waveform is 2π / 3). The delayed clock signal A_delay is the waveform of the first output clock signal A after being delayed by the delay circuit 13. The second output clock signal B and the delayed clock signal A_delay are passed through a frequency divider with the same division ratio to generate the divided second output clock signal clk_fb and the internal clock signal, respectively. At this time, the reference clock clk_ref of the phase-locked loop uses the external input reference clock. The first output clock signal A and the second output clock signal B have been stably established. Therefore, there is no phase difference between the divided second output clock signal clk_fb and the external input reference clock. As can be seen from the figure, the output of the detection circuit 15 is low at this time, indicating that the delay time is insufficient, so the delay circuit 13 increases the delay time.

[0087] When the delay circuit 13 is added to delay the delayed clock signal A_delay and the second output clock signal B, the waveform of the key nodes of the circuit is as follows: Figure 10 As shown. At this point, there is no phase difference between the internal clock signal and the external input reference clock, indicating that the internal self-calibration clock has been established. The output of detection circuit 15 becomes high, locking the output state of detection circuit 15. This also locks the state of delay circuit 13, determining the delay time from the first output clock signal A to A_delay. Reference clock selection circuit 11 connects the internal clock signal as the reference clock for the phase-locked loop circuit. At this point, the clock generation circuit no longer requires an external reference clock.

[0088] After the self-calibration clock is established, if the output frequency of the phase-locked loop circuit is offset, the frequencies of the first output clock signal A and the second output clock signal B will change synchronously, but the delay from the first output clock signal A to the delayed clock signal A_delay is fixed. Therefore, a phase difference is generated between the internal clock signal and the divided second output clock signal clk_fb, thereby adjusting the frequency of the voltage-controlled oscillator 124 to return it to the circuit state after self-calibration, thereby achieving stability of the phase-locked loop output frequency.

[0089] It should be noted that Figure 11 The diagram below shows the four-port structure of the micro camera module. It has four interfaces: power supply VDD, clock SCL, data SDA, and ground VSS.

[0090] An embodiment of the present invention further provides an image sensor, which includes the above-mentioned clock generating circuit.

[0091] In an embodiment of the present invention, the phase-locked loop circuit tracks the frequency and phase of the input clock signal it receives to output a first output clock signal to the delay circuit, and feeds back a second output clock signal to the input end of the phase-locked loop circuit; the delay circuit delays the first output clock signal to output a delayed clock signal; the detection circuit receives an external input reference clock signal and a delayed clock signal, and outputs a detection signal based on the frequency and / or phase of the two; the delay circuit adjusts the delay time of the first output clock signal based on the detection signal, and establishes an internal clock signal based on the delayed clock signal and the delay time, and the internal clock signal has the same phase as the second output clock signal; the selection circuit receives the external input reference clock signal and the internal clock signal, and selects to output the external input reference clock signal or the internal clock signal to the phase-locked loop circuit based on the detection signal; therefore, when the internal clock signal is aligned with the external input reference clock signal, the internal clock signal is used as the reference clock, and the clock terminal SCL no longer needs to be connected to the external input reference clock signal. At this time, the clock terminal SCL can be used to transmit data, thereby improving data transmission efficiency.

[0092] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0093] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A clock generating circuit, characterized in that: include: Phase-locked loop circuit, delay circuit, selection circuit and detection circuit; The phase-locked loop circuit is configured to track the frequency and phase of the input clock signal it receives, so as to output a first output clock signal to the delay circuit, and feed back a second output clock signal to the input end of the phase-locked loop circuit; The delay circuit is configured to delay the first output clock signal to output a delayed clock signal; The detection circuit is configured to receive an external input reference clock signal and the delayed clock signal, and output a detection signal based on the frequency and / or phase of the two; The delay circuit adjusts the delay time of the first output clock signal based on the detection signal, and establishes an internal clock signal based on the delayed clock signal and the delay time, wherein the internal clock signal has the same phase as the second output clock signal; The selection circuit is configured to receive the external input reference clock signal and the internal clock signal, and select to output the external input reference clock signal or the internal clock signal to the phase-locked loop circuit based on the detection signal.

2. The clock generating circuit according to claim 1, wherein: Also includes: a logic circuit, electrically connected to the detection circuit and the delay circuit, and configured to output a delay control signal to the delay circuit according to the detection signal, so as to control the delay time of the delay circuit; The logic circuit comprises: a judgment circuit, connected to the detection circuit, configured to output a trigger signal, and maintain or disconnect the output of the trigger signal based on the detection signal; a counter connected to the judgment circuit, configured to count and output a counting result when the trigger signal is received, and stop counting and lock the counting result when the trigger signal is disconnected; The digital circuit is connected to the counter and the delay circuit and is configured to output the delay control signal according to the counting result.

3. The clock generating circuit according to claim 1, wherein: The phase-locked loop circuit comprises: a phase frequency detector connected to the selection circuit, configured to detect a phase difference between the input clock signal and the second output clock signal, and generate a first control signal; a charge pump connected to the phase and frequency detector and configured to charge and discharge according to the first control signal to output a first control voltage; a main loop filter connected to the charge pump and configured to filter the first control voltage to generate a modulation voltage; A voltage-controlled oscillator is connected to the main loop filter and the delay circuit, and is configured to output the first output clock signal and the second output clock signal, the frequency of which is proportional to the modulation voltage.

4. The clock generating circuit according to claim 3, wherein: The delay circuit includes a first frequency divider and a variable delay module, wherein the variable delay module delays the first output clock signal based on a detection signal and outputs the delayed clock signal to the first frequency divider to expand the frequency range of the delayed clock signal; The phase-locked loop circuit further includes a second frequency divider connected to the voltage-controlled oscillator and the phase frequency detector, and configured to divide the frequency of the second output clock signal to output the divided second output clock signal to an input end of the phase frequency detector; The first frequency divider and the second frequency divider have the same frequency division ratio.

5. The clock generating circuit according to claim 4, wherein: The voltage-controlled oscillator includes an operational amplifier, a first inverter, a second inverter, and a third inverter; The non-inverting input terminal of the operational amplifier serves as the modulation voltage input terminal of the voltage-controlled oscillator and is connected to the main loop filter to receive the modulation voltage; The inverting input terminal of the operational amplifier is connected to the output terminal of the operational amplifier, the power supply terminal of the first inverter, the power supply terminal of the second inverter, and the power supply terminal of the third inverter; The input end of the first inverter and the output end of the third inverter serve together as a first output clock signal output end of the voltage-controlled oscillator, and are connected to the delay circuit to output the first output clock signal; The output terminal of the second inverter and the input terminal of the third inverter serve together as the second output clock signal output terminal of the voltage-controlled oscillator, and are connected to the second frequency divider to output the second output clock signal; The output terminal of the first inverter is connected to the input terminal of the second inverter.

6. The clock generating circuit according to claim 4, wherein: The variable delay module includes a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, n capacitors, and n switch transistors; wherein n is a natural number greater than 0, and i is a positive integer less than or equal to n; The drain of the first field effect transistor and the drain of the fifth field effect transistor are commonly connected to the first power supply, and the gate of the first field effect transistor serves as the first bias signal input terminal of the variable delay module to receive the first bias signal; the source of the first field effect transistor is connected to the drain of the second field effect transistor, and the gate of the second field effect transistor and the gate of the third field effect transistor serve as the first output clock signal input terminal of the variable delay module, and are connected to the phase-locked loop circuit to receive the first output clock signal; the source of the second field effect transistor is connected to the drain of the third field effect transistor, the first input and output terminals of the n switching transistors, the gate of the fifth field effect transistor, and the gate of the sixth field effect transistor, and the i-th switching transistor is connected to the gate of the sixth field effect transistor. The second input and output ends of the transistor are connected to the first end of the i-th capacitor, the second ends of the n capacitors, the source of the fourth field-effect transistor, and the source of the sixth field-effect transistor are commonly connected to the power ground, the source of the third field-effect transistor is connected to the drain of the fourth field-effect transistor, and the gate of the fourth field-effect transistor serves as the second bias signal input end of the variable delay module to receive the second bias signal; the source of the fifth field-effect transistor and the drain of the sixth field-effect transistor jointly serve as the delayed clock signal output end of the variable delay module and are connected to the first frequency divider to output the delayed clock signal; the control ends of the n switching transistors jointly serve as the delay control signal input end of the variable delay module to receive the delay control signal.

7. The clock generating circuit according to claim 1, wherein: The detection circuit includes a D flip-flop; The data input terminal of the D flip-flop serves as the external input reference clock signal input terminal of the detection circuit to receive the external input reference clock signal; the clock terminal of the D flip-flop serves as the internal clock signal input terminal of the detection circuit, and is connected to the delay circuit to receive the internal clock signal; The data output terminal of the D flip-flop and the reset terminal of the D flip-flop serve together as the detection signal output terminal of the delay circuit, and are connected to the selection circuit to output the detection signal.

8. The clock generating circuit according to claim 1, wherein: The selection circuit includes a first transmission gate, a second transmission gate, a fourth inverter and a fifth inverter; The input end of the first transmission gate serves as the internal clock signal input end of the selection circuit and is connected to the delay circuit to receive the internal clock signal; The input end of the second transmission gate serves as the external input reference clock signal input end of the selection circuit to receive the external input reference clock signal; The input end of the fourth inverter serves as a detection signal input end of the selection circuit and is connected to the detection circuit to receive the detection signal; The output terminal of the fourth inverter is connected to the input terminal of the fifth inverter, the positive phase control terminal of the first transmission gate, and the negative phase control terminal of the second transmission gate; An output terminal of the fifth inverter is connected to the inverting control terminal of the first transmission gate and the non-inverting control terminal of the second transmission gate; The output end of the first transmission gate and the output end of the second transmission gate serve together as the internal clock signal output end or the external input reference clock signal output end of the selection circuit, and are connected to the phase-locked loop circuit to output the internal clock signal or the external input reference clock signal.

9. A method for controlling a clock generating circuit according to any one of claims 1 to 8, characterized in that: The clock generating circuit includes a clock signal establishment state and a clock signal stable output state; In the clock signal establishment state, the external input reference clock signal is connected to the detection circuit and the selection circuit, and the selection circuit outputs the external input reference clock signal to the phase-locked loop circuit as the input clock signal of the phase-locked loop circuit; The phase-locked loop circuit outputs the first output clock signal and the second output clock signal having a constant phase difference based on the external input reference clock signal; The delay circuit delays the first output clock signal and outputs the delayed clock signal; the detection circuit compares the frequency and phase of the external input reference clock signal and the delayed clock signal and outputs the detection signal; the delay circuit adjusts the delay time based on the detection signal to output the internal clock signal with the same frequency and phase as the second output clock signal; When the clock signal is in a stable output state, the connection of the external input reference clock signal is disconnected, and the selection circuit outputs the internal clock signal to the phase-locked loop circuit as the input clock signal of the phase-locked loop circuit.

10. An image sensor, characterized in that: The image sensor includes the clock generating circuit according to any one of claims 1 to 8 and the control method of the clock generating circuit according to claim 9.

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