Hybrid IC Architecture

Abstract

An electronic assembly comprises: a carrier wafer having a wafer top surface and a wafer bottom surface; an electronic integrated circuit formed in the carrier wafer and including an integrated circuit contact pad on the wafer top surface; the carrier wafer comprising a through-wafer cavity having a wall, the wall connecting the wafer top surface to the wafer bottom surface; a component chip having a component chip top surface, a component chip bottom surface and a component chip side surface, the component chip being retained in the through-wafer cavity by direct contact of at least the side surface of the component chip with an attachment metal filling at least a portion of the through-wafer cavity; the component chip comprising at least one component contact pad on the component chip bottom surface; and a conductor connecting the integrated circuit contact pad and the component contact pad.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Provisional Application No. 62 / 610,099, which is hereby incorporated by reference. This application claims priority to U.S. Application No. 17 / 214,374, which is hereby incorporated by reference. This application is a continuation-in-part of U.S. Non-Provisional Application No. 16 / 158,212, which is hereby incorporated by reference.

[0003] Statement Regarding Government-Sponsored Research or Development

[0004] This invention was made with Government support under Contract No. HR0011-19-C-0006 awarded by DARPA. The Government has certain rights in this invention. Technical Field

[0005] The present disclosure relates to electronic assemblies, and in particular to electronic assemblies including one or more microelectronic components integrated into a separately fabricated microelectronic wafer. Background Art

[0006] An electronic assembly or hybrid circuit includes microelectronic circuits that are individually manufactured and assembled together to form a single component, which itself can be encapsulated in an electronic circuit package. Assembling individually manufactured microelectronic circuits allows, for example, all of the microelectronic circuits to be individually tested before they are assembled, which in turn enables improved manufacturing yields for the final component. This ability is particularly important if some of the individually manufactured microelectronic circuits are difficult and / or expensive to manufacture. Assembling individually manufactured microelectronic circuits also allows microelectronic circuits that themselves utilize different materials and different manufacturing processes to be combined into a single final component. This ability can result in higher circuit performance.

[0007] Reference "P. Chinoy, N. Jain, Ping Li, J. Goodrich and C. Souchuns, "Manufacture of low-loss microwave circuits using HMIC technology", 1994 IEEE MTT-S International Microwave Symposium Digest (Cat. No. 94CH3389-4), San Diego, California, USA, 1994, pp. 1137-1140, Vol. 2, doi: 10.1109 / MWSYM.1994.335544" discloses a low-cost, batch-processed, surface-mountable microwave manufacturing technology that provides hybrid flexibility with monolithic passive components with repeatability and precision. The reference particularly discloses power amplifier circuits with high power added efficiency and reduced size, paving the way for low-cost, high-performance circuits for the wireless communications market.

[0008] U.S. Patent No. 8,617,927 and U.S. Patent No. 9,214,404, which are incorporated herein by reference in their entirety, disclose a method and apparatus for mounting microelectronic chips to a heat sink. The chips are arranged in a desired configuration with their active surfaces all facing a common direction and their active surfaces defining a common plane for all of the chips. A metallic material is applied to the chips, preferably by electroplating onto the backside of the chips, the metallic material being electroformed onto the chips and forming a gap-free contact with the backside of the chips.

[0009] U.S. Patent No. 9,508,652, which is incorporated herein by reference in its entirety, discloses a method for wafer-level packaging, comprising: forming one or more dies; forming a plated metal ring (PMR) on each die; forming a cover wafer (CW) having one or more plated seal rings; forming a body wafer (BW) having a cavity and a metal layer on a first side of the BW; aligning respective dies with the CW such that the PMRs on the respective dies are aligned with respective plated seal rings (PSRs) on the CW; bonding the PMRs on the respective dies to the respective PSRs; aligning the BW with the CW such that the respective cavities of the BW surround respective dies bonded to the CW and such that the metal layer on the BW is aligned with at least one PSR on the CW; and bonding the metal layer on the first side of the BW to the PSRs on the CW. Each PMR has a first height, and each PSR has a second height.

[0010] U.S. Patent Nos. 9,837,372 and 9,385,083, which are incorporated herein by reference in their entirety, disclose an interconnect and a method for manufacturing pads formed on adjacent chips (or on packaging material adjacent to the chips), wherein a conductive heat sink is disposed between the pads, and the interconnect includes a metal film layer disposed between two adjacent pads and disposed or bridged over the conductive heat sink to avoid electrical contact with the conductive heat sink. An electroplated metal layer is disposed on the metal film layer. Multiple interconnects can be formed in parallel using manufacturing techniques compatible with wafer-level fabrication of the interconnects. The interconnects preferably follow a smooth curve to electrically connect adjacent pads, and following the smooth curve, they bridge over the intervening conductive heat sink material in a predictable manner.

[0011] U.S. Patent No. 9,337,124, which is incorporated herein by reference in its entirety, discloses a method for forming a wafer-level heat spreader, comprising: providing a grid wafer having a plurality of openings and a grid area between the openings; bonding the grid wafer to a backside of an integrated circuit (IC) wafer, the IC wafer including a plurality of circuits; and electroplating a heat sink material through the plurality of openings and onto the backside of the IC wafer.

[0012] There remains a need for an electronic assembly or hybrid component that is easier and more economical to manufacture at high manufacturing yields than currently known electronic assemblies or hybrid components. Summary of the Invention

[0013] Embodiments of the present disclosure include an electronic assembly or hybrid circuit in which a microelectronic circuit in a wafer is connected to a microelectronic circuit in a chip; the chip is embedded in a metal-filled cavity of the wafer, wherein the microelectronic circuit in the wafer and the microelectronic circuit in the chip have contact pads on opposing surfaces of the assembly, and wherein a conductor connects the contact pads.

[0014] For example, Figures 1 to 6As shown, the embodiments described herein include an electronic assembly (e.g., 10) having: a carrier wafer (e.g., 12) having a wafer top surface (e.g., 14) and a wafer bottom surface (e.g., 16); an electronic integrated circuit formed in the carrier wafer (e.g., 12) and including first integrated circuit contact pads (e.g., 18) on the wafer top surface (e.g., 14); the carrier wafer (e.g., 12) including a through-wafer cavity (e.g., 20) having walls (e.g., 22) connecting the wafer top surface (e.g., 14) to the wafer bottom surface (e.g., 16); a first component chip (e.g., 24) having a first component chip top surface (e.g., 26), a first component chip bottom surface (e.g., 16), and a first component chip contact pad (e.g., 18). such as 28) and a side surface (such as 30) of a first component chip, the first component chip (such as 24) being retained in the through-wafer cavity (such as 20) by direct contact of at least a side surface (such as 30) of the first component chip (such as 24) with an attachment metal (such as 32) filling at least a portion of the through-wafer cavity (such as 20); the first component chip (such as 24) including at least one first component contact pad (such as 34) on the bottom surface (such as 28) of the first component chip; and a first conductor (such as 36, 38; 37, 32) connecting the first integrated circuit contact pad (such as 18) and the first component contact pad (such as 34).

[0015] According to an embodiment of the present invention, the carrier wafer (e.g., 12) and the first component chip (e.g., 24) have the same thickness, and wherein the first conductor (e.g., 36, 38; 37, 32) includes a via (e.g., 38) passing through the first component chip (e.g., 24).

[0016] According to an embodiment of the present invention, the first conductor (e.g., 36, 38; 37, 32) includes a metal strip or wire (e.g., 36) that connects the first integrated circuit contact pad (e.g., 18) to the top of the via (e.g., 38) through the first component chip (e.g., 24).

[0017] According to an embodiment of the present invention, the carrier chip (e.g., 12) and the first component chip (e.g., 24) have the same thickness, wherein the attachment metal (e.g., 32) fills at least a portion of the through-chip cavity (e.g., 20) along the entire height of the through-chip cavity (e.g., 20); and wherein the first conductor (e.g., 36, 38; 37, 32) includes the attachment metal (e.g., 32).

[0018] According to the presently described embodiment, the first conductor (eg, 36, 38; 37, 32) comprises a metal strip or line (eg, 37) connecting the first integrated circuit contact pad (eg, 18) to the top of the attachment metal (eg, 32).

[0019] According to the presently described embodiment, the attachment metal (eg, 32) covers at least a portion of the first component chip bottom surface (eg, 28) and the first component contact pads (eg, 34).

[0020] For example, Figure 4 and Figure 6 As shown, according to an embodiment of the present invention, the carrier chip (e.g., 12) is thicker than the first component chip (e.g., 24), the adhesion metal (e.g., 32) holds the first component chip (e.g., 24) so ​​that the top surface of the first component chip (e.g., 26) is flush with the top surface of the chip (e.g., 14), and the first conductor (e.g., 36, 38; 37, 32) includes the adhesion metal (e.g., 32).

[0021] For example, Figure 6 As shown, according to an embodiment of the present invention, the attachment metal (e.g., 32) fills at least a portion of the through-wafer cavity (e.g., 20) along the entire height of the through-wafer cavity (e.g., 20); wherein the first conductor (e.g., 36, 38; 37, 32) includes a metal strip or wire (e.g., 37) that connects the first integrated circuit contact pad (e.g., 18) to the top of the attachment metal (e.g., 32).

[0022] For example, Figure 6 As shown, according to the presently described embodiment, the attachment metal (eg, 32) covers at least a portion of the first component chip bottom surface (eg, 28) and the first component contact pad (eg, 34).

[0023] For example, Figure 4 As shown, according to the embodiment of the present invention, the first conductor (eg, 36, 38; 37, 32) includes the attachment metal (eg, 32) and a via (eg, 40) passing through the first carrier wafer (eg, 12).

[0024] For example, Figure 4 As shown, according to the embodiment described herein, the attachment metal (eg, 32) covers at least a portion of the bottom surface (eg, 28) of the first component chip and passes through the bottom of the via (eg, 40) of the first carrier wafer (eg, 12).

[0025] For example, Figure 3As shown, according to an embodiment of the present invention, the carrier wafer (e.g., 12) is thicker than the first component chip (e.g., 24), wherein the attachment metal (e.g., 32) holds the first component chip (e.g., 24) so ​​that the top surface of the first component chip (e.g., 26) is flush with the top surface of the wafer (e.g., 14), and wherein the first conductor (e.g., 36, 38; 37, 32) includes a via (e.g., 38) passing through the first component chip (e.g., 24).

[0026] For example, Figure 3 As shown, according to the embodiment of the present invention, the first conductor (e.g., 36, 38; 37, 32) includes a metal strip or wire (e.g., 36) that connects the first integrated circuit contact pad (e.g., 18) to the top of the via (e.g., 38) passing through the first component chip (e.g., 24).

[0027] For example, Figure 6 As shown, according to an embodiment of the present disclosure, a wall (eg, 22) of a through-wafer cavity (eg, 20) is covered with a dielectric layer (42).

[0028] According to the presently described embodiment, the carrier wafer (eg, 12) and the first component chip (eg, 24) are made of different materials.

[0029] According to an embodiment of the present disclosure, the first component chip (eg, 24) is an integrated circuit chip including one or more transistors.

[0030] For example, Figure 5 and Figure 6 As shown, according to the embodiment of the present invention, the electronic component includes a second component chip (e.g., 24'), which is also held in the through cavity (e.g., 20) by direct contact between at least one side surface (e.g., 30') of the second component chip (e.g., 24') and the attachment metal (e.g., 32); the second component chip (e.g., 24') includes at least one second component contact pad (e.g., 34') on one of the top surface (e.g., 26') and the bottom surface (e.g., 28') of the second component chip (e.g., 24'); the electronic integrated circuit formed in the carrier wafer includes second integrated circuit contact pads (e.g., 18'; 18) on one of the wafer top surface (e.g., 14) and the wafer bottom surface (e.g., 16); wherein second conductors (e.g., 36', 38'; 32, 37) connect the second integrated circuit contact pad (e.g., 34') and the second component contact pads (e.g., 18', 18).

[0031] For example, Figure 5As shown, according to the embodiment of the present introduction, at least one of the first component chip (e.g., 24) and the second component chip (e.g., 24') is thinner than the wafer, and the attachment metal (e.g., 32) holds the first component chip and the second component chip (e.g., 24, 24') so that the top surface of the first component chip and the top surface of the second component chip (e.g., 26, 26') are flush with the top surface of the wafer.

[0032] Other embodiments of the present disclosure relate to a method of manufacturing an electronic assembly, the method comprising: providing a first component chip (e.g., 24) having a first component chip top surface (e.g., 26), a first component chip bottom surface (e.g., 28), and a first component chip side surface (e.g., 30); the first component chip (e.g., 24) including at least one first component contact pad (e.g., 34) on the first component chip bottom surface (e.g., 28) and a via (e.g., 38) providing an electrical path between the first component chip top surface (e.g., 26) and the first component contact pad (e.g., 34); providing a handle wafer (e.g., 44) having a first surface (e.g., 46); attaching (e.g., 50) the first component chip top surface (e.g., 26) to the first surface (e.g., 46) of the handle wafer (e.g., 44); providing a carrier wafer (e.g., 12) having a wafer top surface (e.g., 14) and a wafer bottom surface (e.g., 16); forming an electronic integrated circuit (e.g., 48) in the carrier wafer (e.g., 12), the electronic integrated circuit having a first component contact pad (e.g., 34) on the wafer bottom surface (e.g., 28); a first integrated circuit contact pad (e.g., 18) on a top surface (e.g., 14) of the wafer; forming a through-wafer cavity (e.g., 20) having walls (e.g., 22) in a carrier wafer, the walls connecting the wafer top surface (e.g., 14) to the wafer bottom surface (e.g., 16); attaching the wafer top surface (e.g., 14) to the first surface of the handle wafer (e.g., 44) such that the first component chip (e.g., 24) is disposed within the through-wafer cavity (e.g., 20); filling at least a portion of the through-wafer cavity (e.g., 20) with an attachment metal (e.g., 32) so as to retain the first component chip (e.g., 24) in the through-wafer cavity (e.g., 20) by direct contact of at least a side surface (e.g., 30) of the first component chip with the attachment metal (e.g., 32); separating the handle wafer (e.g., 44) from the first component chip top surface (e.g., 26) and the wafer top surface (e.g., 14); and forming a first conductor (e.g., 36) between the first integrated circuit contact pad (e.g., 18) and the via (e.g., 38).

[0033] Other embodiments of the present disclosure relate to a method of manufacturing an electronic assembly, the method comprising: providing a first component chip (e.g., 24) having a first component chip top surface (e.g., 26), a first component chip bottom surface (e.g., 28), and a first component chip side surface (e.g., 30); the first component chip (e.g., 24) including at least one first component contact pad (e.g., 34) on the first component chip bottom surface (e.g., 28); providing a handle wafer (e.g., 44) having a first surface (e.g., 46); attaching the first component chip top surface (e.g., 26) to the first surface (e.g., 46) of the handle wafer (e.g., 44); providing a carrier wafer (e.g., 12) having a wafer top surface (e.g., 14) and a wafer bottom surface (e.g., 16); forming an electronic integrated circuit (e.g., 48) in the carrier wafer, the electronic integrated circuit having the first integrated circuit contact pad (e.g., 18) on the wafer top surface (e.g., 14); forming a wafer having a wall (e.g., 22) in the carrier wafer (e.g., 12); a through-wafer cavity (e.g., 20) having a wall connecting the wafer top surface (e.g., 14) to the wafer bottom surface (e.g., 16); attaching the wafer top surface (e.g., 14) to the first surface (e.g., 46) of the handle wafer (e.g., 44) such that the first component chip (e.g., 24) is disposed within the through-wafer cavity (e.g., 20); filling at least a portion of the through-wafer cavity (e.g., 20) with an attachment metal (e.g., 32) so as to retain the first component chip (e.g., 24) in the through-wafer cavity (e.g., 20) by direct contact of at least a side surface (e.g., 30) of the first component (e.g., 24) with the attachment metal (e.g., 24), wherein a first portion of the attachment metal (e.g., 32) contacts the carrier wafer (e.g., 44) and a second portion of the attachment metal electrically contacts the first component contact pad (e.g., 34); separating the handle wafer (e.g., 44) from the first component chip top surface (e.g., 26) and the wafer top surface (e.g., 14); and

[0034] A first conductor (eg, 37) is formed between a first integrated circuit contact pad (eg, 18) and the first portion of the attachment metal (eg, 32). BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a cross-section of an electronic component according to an embodiment of the present invention.

[0036] Figure 2 is a cross-section of an electronic component according to an embodiment of the present invention.

[0037] Figure 3 is a cross-section of an electronic component according to an embodiment of the present invention.

[0038] Figure 4is a cross-section of an electronic component according to an embodiment of the present invention.

[0039] Figure 5 is a cross-section of an electronic component according to an embodiment of the present invention.

[0040] Figure 6 is a cross-section of an electronic component according to an embodiment of the present invention.

[0041] Figure 7 is an elevation view of a component chip that may be used in an electronic assembly according to an embodiment of the present disclosure.

[0042] Figures 8A to 8C The steps of a method of manufacturing an electronic component according to an embodiment of the present invention are illustrated.

[0043] Figures 9A to 9C The steps of a method of manufacturing an electronic component according to an embodiment of the present invention are illustrated. DETAILED DESCRIPTION

[0044] The following description is presented to enable one of ordinary skill in the art to make and use the teachings of this introduction and to incorporate them in the context of a particular application. Various modifications and uses in different applications will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Thus, the present invention is not intended to be limited to the embodiments presented, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0045] In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the embodiments of the present invention. However, it will be apparent to those skilled in the art that such embodiments may be practiced without being limited to these specific details.

[0046] All features disclosed in this introduction (including any accompanying claims, abstracts, and drawings) may be replaced by alternative features serving the same, equivalent, or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is only one example of a generic series of equivalent or similar features.

[0047] Furthermore, any element in a claim that does not explicitly recite a “means” for performing a specified function or a “step” for performing a specified function is not to be construed as a “means” or “step” clause as specified in 35 U.S.C. § 112, paragraph 6. Specifically, the use of “step” or “act” in the claims herein is not intended to invoke the provisions of 35 U.S.C. § 112, paragraph 6.

[0048] The electronic assembly according to the presently described embodiments integrates high-performance integrated circuits such as GaN RF MMICs into a carrier wafer having integrated circuits such as silicon-based integrated circuits in a cost-effective manner with high manufacturing yields and short manufacturing cycles.

[0049] According to embodiments of the present disclosure, high performance integrated circuits or components may include III-nitride transistors or integrated circuits, and they may ultimately be integrated into a carrier wafer along with resistors, inductors, capacitors, and matching networks.

[0050] Figure 1 A cross-sectional view of an electronic assembly 10 according to an embodiment of the present invention is illustrated, the electronic assembly comprising: a carrier wafer 12 having a wafer top surface 14 and a wafer bottom surface 16; an electronic integrated circuit (not shown) formed in the carrier wafer and including at least one first integrated circuit contact pad 18 on the wafer top surface 14. According to the embodiment of the present invention, the carrier wafer 12 includes at least one through-wafer cavity 20 having walls 22 connecting the wafer top surface 14 to the wafer bottom surface 16. According to the embodiment of the present invention, a first component chip 24 having a top surface 26, a bottom surface 28, and side surfaces 30 is retained in the through-wafer cavity 20 by an attachment material 32 that attaches at least one wall 22 of the through-wafer cavity 20 to at least one of the bottom surface 28 and the side surfaces 30. According to the embodiment of the present invention, the attachment material 32 is metal and holds the first component chip (24) in the through-wafer cavity (20) by directly contacting at least the side surface (30) of the first component chip (24). According to the presently described embodiments, electronic integrated circuits of the carrier wafer 12 may be formed within the wafer top surface 14 using known integrated circuit fabrication processes, including but not limited to photolithography, epitaxial growth, oxidation of exposed layers, and the like.

[0051] According to the embodiment of the present invention, carrier wafer 12 and first component chip 24 have the same thickness. Optionally, attachment metal 32 can fill cavity 20, thereby attaching most of the side surfaces of first component chip 24 to wall 22 of through-wafer cavity 20. "Same thickness" means that the difference in thickness between the carrier wafer and the component chip is negligible.

[0052] According to the present embodiment, the first component chip 24 includes at least one first component contact pad 34 on the bottom surface 28 of the first component chip, and first conductors 36, 38 connect the first integrated circuit contact pad 18 to the first component contact pad 34. According to the present embodiment, the first conductors 36, 38 include vias 38 that pass through the first component chip 24 from the top surface 26 to the bottom surface 28 thereof, wherein the vias 38 contact the contact pads 34. According to the present embodiment, the first conductors 36, 38 also include metal strips or lines 36 that connect the first integrated circuit contact pad 18 to the top of the vias 38 on the top surface 26 of the first component chip. According to the present embodiment, the metal strips or lines 36 are formed using a top metal fabrication process that is compatible with the fabrication process of the electronic integrated circuits (e.g., CMOS) of the carrier wafer 12. The fabrication process may include passivating the top surface of the component, masking and etching contact openings, and forming the metal strips or lines 36 by masking and sputtering.

[0053] According to the presently described embodiment, first component chip 24 may include at least one vertical transistor having a top contact pad (not shown) on top surface 26 , for example connected to the gate and source of the transistor, and wherein contact pad 34 is connected to the drain of the transistor.

[0054] Figure 2 An electronic arrangement 10' is illustrated according to an embodiment of the present invention, which is similar to the embodiment of the present invention except that the first component chip 24 does not include a via 38. Figure 1 . Instead, to connect the top integrated circuit contact pad 18 to the bottom component chip contact pad 34, the attachment metal 32 fills at least a portion of the cavity 20 along the entire height of the cavity wall 22 so that the top of the attachment metal 32 is flush with the top surface 14 of the carrier wafer 12. The attachment metal 32 also covers at least a portion of the bottom side 28 of the component chip 24 and is in contact with the contact pad 34. In addition, a metal strip or line 37 connects the contact pad 18 to the top of the attachment metal 32 flush with the top surface 14 of the carrier wafer 12. The metal strip or line 37 can be formed in the same manner as the metal strip or line 36 using a top metal manufacturing process that is compatible with the manufacturing process of the electronic integrated circuit of the carrier wafer 12. According to the embodiments of the present introduction, the top of the metal 32 is "flush" with the top surface 14 of the wafer should be understood to mean that the two surfaces are in the same plane, or have a small or negligible height difference relative to each other. As Figure 2 For example, according to embodiments of the present disclosure, attachment metal 32 may extend along portions of bottom surface 16 of carrier wafer 12 and portions of bottom surface 28 of component chip 24. Metal etching may be used to separate portions of attachment metal 32 on the bottom surface of arrangement 10' to electrically isolate the portions from each other.

[0055] According to the embodiment of the present invention, the component chip 24 can also be thinner than the carrier wafer 12, for example Figure 6 Example.

[0056] Figure 3 An electronic arrangement 10" according to an embodiment of the present invention is illustrated, which is similar to the embodiment of the present invention except that the first component chip 24 is thinner than the carrier wafer 12. Figure 1 The same as the embodiment in . According to an embodiment, the contact metal 32 can attach the component chip 24 by directly contacting one or more side surfaces 30 and the wall 22 of the through-wafer cavity 20. According to the embodiment of the present introduction, the attachment metal 32 holds the first component chip 24 so that the first component chip top surface 26 is flush with the wafer top surface 14. According to the embodiment of the present introduction, the first component chip top surface 26 is "flush" with the wafer top surface 14 to mean that the two surfaces are in the same plane, or have a small or negligible height difference relative to each other, such as can be produced by the following process: the first component chip 24 is permanently attached to the wall 22 of the through-wafer cavity 20, while the first component chip top surface 26 and the wafer top surface 14 are both temporarily attached to the same operating wafer, such as according to the process exemplified below. At this particular moment, it must be emphasized that, for the sake of clarity, the drawings are not drawn to scale.

[0057] According to the embodiment of this introduction, Figure 3 For example, the conductors connecting the top integrated circuit contact pads 18 to the bottom component chip contact pads 34 are as shown. Figure 1 The die is shown as including a via 38 through the first component die 24. The attachment metal 32 fills at least a portion of the through-wafer cavity so as to directly contact at least a portion of the wall 30 of the component die 24, but it may alternatively contact at least a portion of the bottom surface 28 of the component die 24 (and contact at least a portion of the contact pad 34), as shown. Figure 3 Example.

[0058] Figure 4 An electronic arrangement 10'' is illustrated according to an embodiment of the present disclosure, which is similar to the embodiment of the present disclosure, except that to connect the top integrated circuit contact pads 18 to the bottom component chip contact pads 34, the carrier wafer 12 includes vias 40 connecting the contact pads 18 to the bottom surface 16 of the carrier wafer 12. Figure 2 Further, the attachment metal 32 fills at least a portion of the cavity 20 and covers a portion of the bottom surface 16 so that it contacts both the bottom of the via 40 and the bottom contact pad 34. Optionally and as Figure 4 As illustrated, first component chip 24 is thinner than carrier wafer 12 .

[0059] Figure 51 , an electronic arrangement 100 is illustrated according to an embodiment of the present disclosure, which is similar to the embodiment of the present disclosure except that it includes a second component chip 24' having a top surface 26', a bottom surface 28', sidewalls 30', a bottom contact pad 34', and a via 38' connecting the contact pad 34' to the top surface 26' held in the through-wafer cavity 20. Figure 1 . Further, carrier wafer 12 includes a second top contact pad 18' connected to an electronic integrated circuit (not shown) formed in the carrier wafer, and conductors 36' similar to conductors 36 connect integrated circuit contact pad 18' to the top of via 38' and through the via to component contact pad 34'. Like component chip 24, component chip 24' is held in through-wafer cavity 20 by direct contact with attachment metal 32. Attachment metal 32 can fill the wall 22 of cavity 20 with one component chip ( Figure 1 ) or multiple chips ( Figure 5 ) part or all of the space between the walls. Figure 1 and Figure 5 In the illustrated embodiment, the component chips 24 , 24 ′ have the same thickness as the carrier wafer 12 , but they may alternatively be thinner than the carrier wafer 12 .

[0060] Figure 6 An electronic arrangement 100' according to an embodiment of the present invention is illustrated, which is similar to the embodiment of the present invention except that it includes a second component chip 26' held in the through-wafer cavity 20. Figure 2 The second component chip 26' has a top surface 26', a bottom surface 28', sidewalls 30' and bottom contact pads 34', but no vias 38'. Figure 2 Similarly, adhesion metal 32 fills at least a portion of cavity 20 along the entire height of cavity wall 22, such that the top of adhesion metal 32 is flush with top surface 14 of carrier wafer 12. Adhesion metal 32 also covers at least a portion of bottom sides 28 and 28' of component chips 24 and 24' and contacts contact pads 34 and 34'. In addition, metal strips or wires 37 connect contact pad 18 to the top of adhesion metal 32, which is flush with top surface 14 of carrier wafer 12, thereby contacting top contact pad 18 to bottom pads 34 and 34'.

[0061] like Figure 6 By way of example, component chips 24, 24' may also include top contact pads 102, 102' connected to top contact pads 104 of carrier wafer 12 using metal wires or filaments 106. Such top contact connections may also occur at Figures 1 to 5 In the embodiment, for example Figure 3 and Figure 4 Example.

[0062] According to the embodiment of this introduction, Figure 6 For example, the wall 22 of the through-wafer cavity 20 can be covered with a dielectric 42. According to the presently described embodiment, the carrier wafer 12 and the component chip 24 are made of different materials. For example, the carrier wafer can be a silicon wafer having integrated circuits manufactured using known CMOS technology, and the component chip 24 can include a III-V material substrate having one or more III-V HEMT transistors.

[0063] Figure 7 FIG2 is a schematic elevational view of a component chip 24 according to an embodiment of the present invention, which includes three vertical HEMT transistors 108, each transistor having a trench gate electrode 110, a top surface source region 112 on either side of the gate trench, and a bottom surface drain region 114. According to the embodiment of the present invention, contact pads 34 are in electrical contact with drain region 114. Contact pads for the gate and source of component chip 24 may be present on top surface 26, but may be located on the bottom surface 26. Figure 7 Such a top contact pad may be such as Figure 3 、 Figure 4 or Figure 6 Component chip 24 may also include passive circuit elements (not shown).

[0064] Figures 8A to 8C The steps of the method for manufacturing an electronic component according to the embodiment of the present invention are illustrated. Figure 8A As an example, the first step of the method includes providing a first component chip 24 having a first component chip top surface 26, a first component chip bottom surface 28, and first component chip sides / walls 30; the first component chip 24 includes at least one first component contact pad 34 on the first component chip bottom surface 28, and also includes a via 38 that provides an electrical path between the first component chip top surface 26 and the first component contact pad 34. The method also includes providing a handle wafer 44 having a top surface 46; and attaching the top surface 26 of the component chip 24 (upside down) to the top surface 46 of the handle wafer 44, for example, using a temporary adhesive layer 50. Still referring to Figure 8A The method further includes providing a carrier wafer 12 having a wafer top surface 14 and a wafer bottom surface 16; forming an electronic integrated circuit 48 in the carrier wafer 12 (e.g., using known photolithographic fabrication processes) having first integrated circuit contact pads 18 on the wafer top surface 14; forming a through-wafer cavity 20 in the carrier wafer having walls 22 connecting the wafer top surface 14 to the wafer bottom surface 16; and attaching the wafer top surface 14 of the carrier wafer 12 (upside down) to the top surface 46 of the handle wafer 44 such that the first component chip 24 is disposed within the through-wafer cavity 20. According to the presently described embodiment, the wafer 12 may be thinned at this stage, for example, by polishing the bottom surface 16.

[0065] like Figure 8B Illustratively, the method further includes filling at least a portion of the through-wafer cavity 20 with a conductive adhesive material 32, preferably a metal, so that the first component chip 24 is retained in the through-wafer cavity 20 by direct contact between at least one side 30 of the first component 24 and the adhesive metal 32. According to embodiments of the present invention, when the adhesive material 32 is metal, an electrometallurgical process (electroforming, electroplating, or electrodeposition) can be used to fill at least a portion of the space in the cavity 20 between the component chip wall 30 and the cavity wall. If electroforming is used, a metal film can be deposited on the wall 22 of the through-wafer cavity 20 and on the exposed surface of the component chip 24 prior to the electroforming. According to embodiments of the present invention, a dielectric layer can be deposited on the wall 22 before depositing such a metal film.

[0066] According to the presently described embodiment, attaching component chip 24 to through-wafer cavity wall 22 ensures that top surfaces 14 , 26 of carrier wafer 12 and component chip 24 are flush when both are temporarily attached to surface 46 of handle wafer 44 .

[0067] like Figure 8C As illustrated, the method further includes separating handle wafer 44 from first component chip top surface 26 and wafer top surface 14; and (after flipping carrier wafer 12 and attached component chip 24) forming a conductor, such as a metal line or strip 36, between first integrated circuit contact pad 18 and the top of via 38. According to the presently described embodiment, metal line or strip 36 may be fabricated using a top metal fabrication process step in the fabrication process steps used to fabricate integrated circuit 48.

[0068] Figures 9A to 9C The steps of the method for manufacturing an electronic component according to the embodiment of the present invention are illustrated. Figure 9A As an example, the first step of the method includes providing a first component chip 24 having a first component chip top surface 26, a first component chip bottom surface 28, and first component chip sides / walls 30; the first component chip 24 includes at least one first component contact pad 34 on the first component chip bottom surface 28, and also includes a via 38 that provides an electrical path between the first component chip top surface 26 and the first component contact pad 34. The method also includes providing a handle wafer 44 having a top surface 46; and attaching the top surface 26 of the component chip 24 (upside down) to the top surface 46 of the handle wafer 44, for example, using a temporary adhesive layer 50. Still referring to Figure 9AThe method further includes providing a carrier wafer 12 having a wafer top surface 14 and a wafer bottom surface 16; forming an electronic integrated circuit 48 in the carrier wafer 12 (e.g., using known photolithographic manufacturing processes), the electronic integrated circuit having a first integrated circuit contact pad 18 on the wafer top surface 14; forming a through-wafer cavity 20 in the carrier wafer having a wall 22 connecting the wafer top surface 14 to the wafer bottom surface 16; and attaching the wafer top surface 14 of the carrier wafer 12 (upside down) to the top surface 46 of the handle wafer 44 such that the first component chip 24 is arranged within the through-wafer cavity 20.

[0069] like Figure 9B Illustratively, the method further comprises: filling at least a portion of the through-wafer cavity 20 with a conductive attachment material 32, which is preferably a metal, so that the first component chip 24 is retained in the through-wafer cavity 20 by direct contact of at least one side surface 30 of the first component 24 with the attachment metal 32, and also bonding the pads 34 to the conductive attachment material 32 in contact. According to an embodiment of the present invention, when the attachment material 32 is a metal, an electrometallurgical process may be used to fill at least a portion of the space in the cavity 20 between the component chip wall 30 and the cavity wall. According to an embodiment of the present invention, attaching the component chip 24 to the wall 22 of the through-wafer cavity 20 allows ensuring that the top surfaces 14, 26 of the carrier wafer 12 and the component chip 24 are flush when both are temporarily attached to the surface 46 of the handle wafer 44. As Figure 9B As illustrated, conductive material 32 preferably fills cavity 20 such that the surface of conductive material 32 is flush with top surface 14 of carrier wafer 12. According to the presently described embodiment, wafer 12 may be thinned at this stage, for example, by polishing bottom surface 16.

[0070] like Figure 9C As illustrated, the method further includes separating handle wafer 44 from first component chip top surface 26 and wafer top surface 14; and (after flipping carrier wafer 12 and attached component chip 24) forming a conductor, such as a metal line or strip 37, between first integrated circuit contact pads 18 and a surface of conductive material 32 flush with top surface 14 of carrier wafer 12. According to the presently described embodiment, metal line or strip 37 may be fabricated using a top metal fabrication process step in a fabrication process step for fabricating integrated circuit 48.

[0071] Preferably, component chips 24, 24' are pre-tested before assembly to verify their functionality. As a result, the yield of a final device comprising multiple component chips 24, 24' is improved compared to manufacturing components of the circuits in component chips 24, 24' on the same wafer.

[0072] The inventors have noted that embedding component chip 24 (including a single chip or multiple component chips 24, 24', etc., as described above) in a metal-filled cavity allows for significant removal of any chip-generated heat, which in turn limits any dimensional changes due to temperature changes and allows any mechanical strains due to such dimensional changes to remain modest, even if the metal is not elastic. Note that material 32 may also be non-metallic, in which case it may be selected to have greater flexibility, albeit at the expense of having reduced thermal conductivity.

[0073] According to embodiments of the present disclosure, component chip 24 may include GaN, InP, or GaAs components and may be fabricated on a substrate such as Si, SiGe, InP, GaAs, alumina, or diamond.

[0074] According to embodiments of the present disclosure, integrated circuits 48 of carrier wafer 12 may include metal wiring and passive components fabricated at the wafer level.

[0075] According to the embodiments of the present invention, the conductors 36, 37 can be made of thin films, thick, plated interconnects, multilayers, etc. For example, the interconnects can be made using back-end steps of a CMOS manufacturing process.

[0076] According to embodiments of the present disclosure, either component chip 24 or carrier wafer 12 may include integrated circuits on both top and bottom surfaces thereof, including active and / or passive circuitry, thereby allowing for the fabrication of compact assemblies.

[0077] Having now described the present invention in accordance with the requirements of the patent statutes, those skilled in the art will understand how to change and modify the present invention to meet their specific requirements or conditions. Such changes and modifications can be made without departing from the scope and spirit of the present invention as disclosed herein.

[0078] The foregoing detailed description of exemplary and preferred embodiments is presented for purposes of illustration and disclosure, as required by law. It is not intended to be exhaustive or to limit the invention to the precise forms described, but rather to enable others skilled in the art to understand how the invention may be adapted for a particular use or implementation. The possibility of modifications and variations will be apparent to those skilled in the art. The description of the exemplary embodiments is not intended to be limiting, as these embodiments may have included tolerances, feature dimensions, specific operating conditions, engineering specifications, etc., and may vary between implementations or as the prior art changes, and no limitation should be implied therefrom.

[0079] Applicants have made this disclosure with respect to the current state of the art, but advances are also anticipated, and future adaptations may take these advances into account, i.e., in light of the then current state of the art. It is intended that the scope of the invention be defined by the written claims and their equivalents, if applicable. Reference to a claim element in the singular is not intended to mean "one and only one" unless expressly stated as such. Moreover, regardless of whether an element, component, method, or process step in this disclosure is expressly enumerated in a claim, the element, component, or step is not intended to be dedicated to the public. None of the claim elements herein are to be construed under the provisions of 35 U.S.C. Chapter 112, sixth paragraph, unless the element is expressly recited using the phrase "means for...", and none of the method or process steps herein are to be construed under these provisions unless the step is expressly recited using the phrase "comprising the step..."

[0080] All elements, parts and steps described herein are preferably included. It should be understood that any one of these elements, parts and steps can be replaced by other elements, parts and steps or deleted completely, as will be apparent to those skilled in the art.

Claims

1. An electronic component comprising: a carrier wafer having a wafer top surface and a wafer bottom surface; an electronic integrated circuit formed in the carrier wafer and including a first integrated circuit contact pad on the wafer top surface; the carrier wafer including a through-wafer cavity having a wall connecting the wafer top surface to the wafer bottom surface; a first component chip having a first component chip top surface, a first component chip bottom surface, and a first component chip side surface, the first component chip being retained in the through-wafer cavity by direct contact of at least the side surface of the first component chip with a bonding metal filling at least a portion of the through-wafer cavity; The first component chip includes at least one first component contact pad on a bottom surface of the first component chip; and A first conductor connects the first integrated circuit contact pad and the first component contact pad; wherein the first conductor comprises the attachment metal that holds the first component chip in the through-wafer cavity.

2. The electronic component according to claim 1, wherein: The carrier wafer and the first component chip have the same thickness, wherein the attachment metal fills the at least a portion of the through-wafer cavity along the entire height of the through-wafer cavity.

3. The electronic component according to claim 2, wherein: The first conductor comprises a metal strip or line connecting the first integrated circuit contact pad to a top portion of the attachment metal.

4. The electronic component according to claim 3, wherein: The attachment metal covers at least a portion of the first component chip bottom surface and the first component contact pads.

5. The electronic component according to claim 1, wherein: The carrier wafer is thicker than the first component chip, wherein the attachment metal holds the first component chip such that the first component chip top surface is flush with the wafer top surface.

6. The electronic component according to claim 5, wherein: The attachment metal fills the at least a portion of the through-wafer cavity along an entire height of the through-wafer cavity; wherein the first conductor comprises a metal strip or wire connecting the first integrated circuit contact pad to a top of the attachment metal.

7. The electronic component according to claim 6, wherein: The attachment metal covers at least a portion of the first component chip bottom surface and the first component contact pads.

8. The electronic component according to claim 5, wherein: The first conductor includes the attachment metal and a via through the carrier wafer.

9. The electronic component according to claim 8, wherein: The attachment metal covers at least a portion of the bottom surface of the first component chip and passes through the bottom of the via of the carrier wafer.

10. The electronic component according to claim 1, wherein The wall of the through-wafer cavity is covered by a dielectric layer.

11. The electronic component according to claim 1, wherein: The carrier wafer and the first component chip are made of different materials.

12. The electronic component according to claim 1, wherein: The first component chip is an integrated circuit chip including one or more transistors.

13. The electronic assembly of claim 1, comprising a second component chip also held in the through-wafer cavity by direct contact of at least a side of the second component chip with the attachment metal; the second component chip comprising at least one second component contact pad on one of a top surface and a bottom surface of the second component chip; The electronic integrated circuit formed in the carrier wafer includes a second integrated circuit contact pad on one of the wafer top surface and the wafer bottom surface; wherein, A second conductor connects the second integrated circuit contact pad and the second component contact pad.

14. The electronic component according to claim 13, wherein: At least one of the first component chip and the second component chip is thinner than the wafer, and wherein, The attachment metal holds the first component chip and the second component chip such that the first component chip top surface and the second component chip top surface are flush with the wafer top surface.

15. A method of manufacturing an electronic component, comprising: providing a first component chip having a first component chip top surface, a first component chip bottom surface, and a first component chip side surface; The first component chip includes at least one first component contact pad on a bottom surface of the first component chip; providing a handle wafer having a first surface; attaching the first component chip top surface to the first surface of the handle wafer; providing a carrier wafer having a wafer top surface and a wafer bottom surface; forming an electronic integrated circuit in the carrier wafer, the electronic integrated circuit having first integrated circuit contact pads on the top surface of the wafer; forming a through-wafer cavity in the carrier wafer, the through-wafer cavity having walls connecting the wafer top surface to the wafer bottom surface; attaching the wafer top surface to the first surface of the handle wafer such that the first component chip is disposed within the through-wafer cavity; filling at least a portion of the through-wafer cavity with an attachment metal so as to retain the first component chip in the through-wafer cavity by direct contact of at least a side of the first component with the attachment metal, wherein a first portion of the attachment metal contacts the carrier wafer and a second portion of the attachment metal electrically contacts the first component contact pad; separating the handle wafer from the first component chip top surface and the wafer top surface; as well as A first conductor is formed between the first integrated circuit contact pad and the first portion of the attachment metallization.

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