Vertical oxide semiconductor transistor and method of manufacturing the same

Abstract

A vertical oxide semiconductor transistor and a method of fabricating the same are disclosed. The vertical oxide semiconductor transistor includes an insulating substrate, a source electrode in the insulating substrate, a gate electrode on the insulating substrate, wherein the gate electrode surrounds the source electrode to form a recess above the source electrode, an inner spacer on an inner wall of the gate electrode in the recess, an oxide semiconductor layer on the inner spacer and the source electrode and directly contacting the source electrode, a filling oxide on the oxide semiconductor layer and filling the recess, and a drain electrode on the oxide semiconductor layer and the filling oxide and directly contacting the oxide semiconductor layer, wherein the drain electrode completely covers the source electrode and partially overlaps the gate electrode.

Description

Technical Field

[0001] This invention relates to an oxide-semiconductor transistor, and more specifically, to a vertical oxide-semiconductor transistor. Background Technology

[0002] Oxide semiconductors are compound semiconductor materials composed of metals and oxygen. Compared to conventional semiconductor materials (such as silicon, germanium, and gallium arsenide), oxide semiconductors are mostly ionic crystals with larger band gaps, better light transmittance, and more complex chemical properties. The amount of dopants and oxygen vacancies affects the carrier concentration in oxide semiconductors; when the carrier concentration is high enough, it becomes a conductor, and it also exhibits n-type and p-type characteristics. Due to its light transmittance, relatively high carrier mobility, low fabrication temperature, and high uniformity on large scales, oxide semiconductors are considered a promising alternative to low-temperature polycrystalline silicon (LTPS) as the channel layer material for thin-film transistors (TFTs), especially the currently popular amorphous indium gallium zinc oxide (IGZO) material, which can be used in flexible display panels or high-resolution large-size display panels.

[0003] With the advent of the metaverse era, the market demand for micro-display devices is increasing. These devices require extremely high resolution to achieve an immersive experience similar to that of the naked eye. However, regardless of the type of display device, its pixel density is limited by the size of the driving transistors used, even when using oxide semiconductor transistors. Currently, the area of ​​horizontal oxide semiconductor transistors is still too large for the aforementioned high-end display applications, failing to meet their requirements. Furthermore, in operation, large-size or high-resolution display devices also require TFTs with faster response times. Therefore, how to reduce the load capacitance of TFTs to achieve faster switching speeds has become a research and development topic that those skilled in the art need to work hard on. Summary of the Invention

[0004] In view of the current market demand for high-end display devices, this invention proposes a novel vertical oxide semiconductor transistor design, characterized by a vertical channel design that significantly reduces the transistor's area size. Furthermore, compared to other vertical transistor designs, the gate design of this invention results in a smaller overlap area between the transistor and its source or drain, significantly reducing the transistor's Miller capacitance (between the input and output terminals) and improving response speed.

[0005] One aspect of this invention is to provide a vertical oxide semiconductor transistor, comprising an insulating substrate, a source electrode located in the insulating substrate, a gate electrode located on the insulating substrate, wherein the gate electrode surrounds the source electrode and forms a groove above the source electrode, an inner spacer wall is located on the inner sidewall of the gate electrode in the groove, an oxide semiconductor layer is located on the inner spacer wall and the source electrode and is in direct contact with the source electrode, a filling oxide is located on the oxide semiconductor layer and fills the groove, and a drain electrode is located on the oxide semiconductor layer and the filling oxide and is in direct contact with the oxide semiconductor layer, wherein the drain electrode completely covers the source electrode and partially overlaps the gate electrode.

[0006] Another aspect of the present invention is to provide a method for fabricating a vertical oxide semiconductor transistor, the steps of which include providing an insulating substrate, forming a source electrode in the insulating substrate, forming a gate electrode on the insulating substrate surrounding the source electrode, wherein the gate electrode forms a groove above the source electrode, forming a spacer wall on the sidewall of the gate electrode, forming an oxide semiconductor layer on the spacer wall in the groove and on the source electrode, and the oxide semiconductor layer directly contacts the source electrode, forming a filling oxide on the oxide semiconductor layer to fill the groove, and forming a drain electrode on the oxide semiconductor layer and the filling oxide electrode, and the drain electrode directly contacts the oxide semiconductor layer, wherein the drain electrode completely covers the source electrode and partially overlaps the gate electrode.

[0007] These and other objects of the present invention should become more apparent to the reader after reading the detailed description of the preferred embodiments, which are illustrated in various figures and drawings below. Attached Figure Description

[0008] This specification includes accompanying drawings, which form part of the document, to provide the reader with a further understanding of embodiments of the invention. These drawings depict some embodiments of the invention and, together with the description herein, illustrate its principles. In these drawings:

[0009] Figure 1 This is a cross-sectional schematic diagram of a vertical oxide semiconductor transistor according to a preferred embodiment of the present invention;

[0010] Figure 2A , Figure 3A , Figure 4A , Figure 5A as well as Figure 6A This is a cross-sectional schematic diagram of the fabrication process of a vertical oxide semiconductor transistor in a preferred embodiment of the present invention; and

[0011] Figure 2B , Figure 3B , Figure 4B , Figure 5B as well as Figure 6BThis is a plan view of the fabrication process of a vertical oxide semiconductor transistor in a preferred embodiment of the present invention.

[0012] It should be noted that all illustrations in this specification are for illustrative purposes. For clarity and ease of illustration, the size and scale of the components in the illustrations may be exaggerated or reduced. Generally, the same reference symbols in the illustrations are used to indicate corresponding or similar component features in modified or different embodiments.

[0013] Symbol Explanation

[0014] 100 Insulating Substrate

[0015] 100a Groove

[0016] 102 Source Pole

[0017] 104 Insulation Layer

[0018] 106 gate

[0019] 108 Hard Mask Layers

[0020] 109 Grooves

[0021] 110 partition wall

[0022] 110a Inner partition wall

[0023] 114 Filled Oxide

[0024] 116 Oxide Semiconductor Layer

[0025] 118 Drain Detailed Implementation

[0026] Exemplary embodiments of the present invention will now be described in detail below, with reference to the accompanying drawings illustrating the described features to enable the reader to understand and achieve the technical effects. The reader will understand that the descriptions herein are by way of illustration only and are not intended to limit the scope of the invention. Various embodiments of the invention and various features in the embodiments that do not conflict with each other can be combined or rearranged in various ways. Modifications, equivalents, or improvements to the invention will be understood by those skilled in the art without departing from the spirit and scope of the invention, and are intended to be included within the scope of the invention.

[0027] Readers should readily understand that the meanings of "on," "above," and "above" in this context should be interpreted broadly. "On" implies not only being "directly" on something but also includes being "on" something with an intervening feature or layer. Similarly, "above" or "above" implies not only being "above" or "above" something but also being "above" or "above" something without an intervening feature or layer (i.e., directly on something). Furthermore, spatially related terms such as "below," "under," "lower part," "above," and "upper part" are used herein for descriptive convenience to describe the relationship between one element or feature and one or more other elements or features, as shown in the accompanying drawings.

[0028] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a extent smaller than that of the structure below or above. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any horizontal faces at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along an inclined surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0029] Readers can generally understand terms at least partially from their usage in context. For example, depending at least partially on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partially on the context, terms such as "a," "an," "the," or "the" can also be understood to convey either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least partially on the context.

[0030] Readers will better understand that when words such as "comprising" and / or "containing" are used in this specification, they expressly define the presence of the stated features, areas, wholes, steps, operations, elements and / or components, but do not preclude the possibility of the presence or addition of one or more other features, areas, wholes, steps, operations, elements, components and / or combinations thereof.

[0031] First, please refer to... Figure 1 This is a cross-sectional schematic diagram of a vertical oxide semiconductor transistor according to a preferred embodiment of the present invention. Figure 1 As shown, the vertical oxide semiconductor transistor of the present invention generally includes an insulating substrate 100, a source 102, a gate 106, an oxide semiconductor layer 116, and a drain 118. In this embodiment, the insulating substrate 100 serves as the basis for the various components of the transistor and can be a plastic substrate made of materials such as polyimide (PI), polycarbonate (PC), polyethylene naphthalate (PEN), or polyethylene terephthalate (PET), providing good insulation and flexibility, suitable for flexible display device applications. In other embodiments, the insulating substrate 100 can also be a non-flexible glass substrate or a silicon oxide (SiO2) substrate. In this embodiment, the source 102 is embedded in and exposed from the insulating substrate 100, and its exposed surface is flush with the surrounding surface of the insulating substrate 100. The source electrode 102 can be made of a low-resistance metal, such as titanium (Ti), molybdenum (Mo), chromium (Cr), aluminum (Al), gold (Au), or an alloy of the above materials.

[0032] Rereference Figure 1 In this embodiment of the invention, the gate 106 is disposed on the insulating substrate 100 and surrounds the source 102 (e.g., Figure 3B As shown, a recess 109 is thus defined above the source 102. An insulating layer 104, such as a silicon dioxide (SiO2) layer, can be formed between the gate 106 and the insulating substrate 100 to improve the insulating properties of the subsequent layer structure formed on the insulating substrate 100. A hard mask layer 108, which may be made of silicon nitride, may also be provided above the gate 106 as a hard mask used in the gate patterning process. In this embodiment of the invention, the gate 106 does not contact the source 102, and the two do not overlap in the vertical direction and are separated by a spacer 110. The spacer 110 may be made of insulating materials such as silicon oxide, silicon nitride, or aluminum oxide (Al2O3). Spacers 110 can be formed on the inner and outer sidewalls of the gate 106, wherein the inner spacer 110a located in the recess 109 is used as a gate insulating layer in this invention, which preferably partially overlaps with the source 102 in the vertical direction, and its thickness is sufficient to suppress leakage current and improve the voltage tolerance of the transistor.

[0033] Rereference Figure 1A conformal oxide semiconductor layer 116 is formed along the entire surface of the recess 109. In this embodiment, the oxide semiconductor layer 116 is in direct contact with the source 102 at the bottom of the recess 109 and extends upward along the inner spacer wall 110a in the recess 109 to the outside of the recess 109, covering part of the hard mask layer 108. That is, the oxide semiconductor layer 116 and the gate 106 partially overlap in the vertical direction. The material of the oxide semiconductor layer 116 may include oxide semiconductor materials such as titanium oxide (TiO2), zinc oxide (ZnO), niobium oxide (Nb2O5), tungsten oxide (WO3), tin oxide (SnO2), zirconium oxide (ZrO2), or indium gallium zinc oxide (IGZO). The oxide semiconductor layer 116 exhibits resistive properties similar to those of a semiconductor, so it can be used as the channel layer of a transistor. Since its band gap width is mostly greater than the energy of visible light, it also has light-transmitting properties, making it suitable as a thin-film transistor (TFT) for transparent displays. The remaining space in the groove 109 is filled with a filler oxide 114, which may be made of silicon oxide. In this embodiment of the invention, the top surface of the filler oxide 114 is preferably lower than the top surface of the hard mask layer 108 or the gate 106, so as to achieve the self-alignment effect between the source 102 and the subsequently formed drain 118.

[0034] Rereference Figure 1 In this embodiment of the invention, the drain 118 is formed on the filled oxide 114, completely covering the source 102 below. The material of the drain 118 can be a low-resistivity metal, such as titanium (Ti), molybdenum (Mo), chromium (Cr), aluminum (Al), gold (Au), or an alloy of the above materials. In this embodiment of the invention, the drain 118 also extends towards the surrounding gate 106 and directly contacts the surrounding oxide semiconductor layer 116, and can overlap with a portion of the gate 106 and the hard mask layer 108 in the vertical direction. Thus, the oxide semiconductor layer 116 located on the inner spacer 110a serves as the channel of the transistor of the present invention, connecting the lower source 102 and the upper drain 118, and controlling its switching through the surrounding gate 106. This is a vertical oxide semiconductor transistor design, and the length of the transistor channel is determined by the height of the gate 106, which can significantly reduce the layout area required for the transistor compared to the existing horizontal channel layer design. Furthermore, compared to the prior art, the overlap area between the gate 106 and the source 102 or the drain 118 of the transistor in this invention is very small, which can significantly reduce the load capacitance from the gate to the source / drain of the TFT, thereby achieving a faster transistor switching speed.

[0035] The preferred embodiments described below will now be based on Figure 2A , Figure 3A , Figure 4A , Figure 5A as well as Figure 6AThe cross-sectional schematic diagram illustrates the fabrication process of the vertical oxide semiconductor transistor of the present invention, which can also be referred to... Figure 2B , Figure 3B , Figure 4B , Figure 5B as well as Figure 6B The planar schematic diagrams are used to understand the planar layout of transistors during the manufacturing process, and these cross-sectional views are drawn from the corresponding cross-sections A-A' in the planar diagram.

[0036] First, please refer to... Figure 2A and Figure 2B An insulating substrate 100 is provided as the basis for mounting the various components of the transistor of the present invention. This substrate can be a plastic substrate made of materials such as polyimide (PI), polycarbonate (PC), polyethylene naphthalate (PEN), or polyethylene terephthalate (PET), or a silicon dioxide substrate. Then, a patterning process is performed on the insulating substrate 100 to form a groove 100a on the insulating substrate 100. This patterning process can be a photolithography etching process. After the groove 100a is formed, a source electrode 102 is then formed in the groove 100a. In this embodiment of the invention, the source electrode 102 can be a low-resistance metal material, such as titanium (Ti), molybdenum (Mo), chromium (Cr), aluminum (Al), gold (Au), tungsten (W), or an alloy of the above materials. It can be formed on the groove 100a and the insulating substrate 100 by chemical vapor deposition (CVD), physical vapor deposition (PVD), or sputtering processes. Then, a planarization process (such as CMP) is performed to remove part of the source electrode material, so that the exposed surface of the source electrode 102 is flush with the surface of the surrounding insulating substrate 100.

[0037] Please refer to Figure 3B and Figure 3B After the source electrode 102 is formed, a thin insulating layer 104, such as a silicon dioxide layer, is formed on the surface of the insulating substrate 100. This layer can be formed by PECVD or similar methods to improve the insulating properties of subsequent layer structures formed on the insulating substrate 100. Next, a gate electrode 106 is formed on the insulating layer 104. The fabrication steps of the gate electrode 106 may include: first, sequentially forming a gate material layer and a hard mask material layer on the insulating layer 104; then, performing a photolithography process to pattern the hard mask material layer, forming a hard mask layer 108 with a gate pattern. This gate pattern is as follows: Figure 3BAs shown, the gate 106 surrounds the source 102 from a planar perspective but does not contact it, with a gap between them. Then, an etching process is performed using a hard mask layer 108 as an etching mask to pattern the underlying gate material layer, thus forming a gate 106 surrounding the source 102. The patterned gate 106 defines a groove 109 above the source 102. In this embodiment of the invention, the gate 106 can be made of a low-resistivity metal material, such as titanium, molybdenum, chromium, aluminum, gold, or an alloy of the above materials, and can be formed by physical vapor deposition or sputtering processes. The hard mask layer 108 can be made of silicon nitride and can be formed by PECVD processes.

[0038] Please refer to Figure 4A and Figure 4B After the gate 106 is formed, a spacer 110 is then formed on the sidewall of the gate 106. The fabrication steps for this spacer 110 may include: first forming a conformal spacer layer on the gate 106 and the insulating layer 104; then performing an anisotropic etching process to remove a certain thickness of the spacer layer, thus forming the spacer 110 on the sidewall of the gate 106 and exposing the hard mask layer 108 above the gate 106. It should be noted that the insulating layer 104 not covered by the gate 106 and the spacer 110 is also removed in this etching step, thus exposing the source electrode 102 buried in the insulating substrate 100. The inner spacer 110a formed in the recess 109 preferably overlaps with the source electrode 102 in the vertical direction. In this embodiment of the invention, the spacer 110 can be made of insulating materials such as silicon oxide, silicon nitride, or aluminum oxide, and can be formed using a CVD fabrication process.

[0039] Please refer to Figure 5A and Figure 5BAfter the spacer 110 is formed, an oxide semiconductor layer 116 is then formed on the inner spacer 110a and the source 102. The step of forming the oxide semiconductor layer 116 may include: forming a conformal oxide semiconductor material on the surfaces of the hard mask layer 108, the spacer 110, the source 102, and the insulating substrate 100, and then performing a photolithography process to remove the oxide semiconductor material layer located outside the recess 109, leaving only the oxide semiconductor material layer on the source 102, the inner spacer 110a, and part of the hard mask layer 108. As shown in the figure, the oxide semiconductor layer 116 is in direct contact with the source 102 at the bottom of the recess 109, and extends upward along the inner spacer 110a and covers part of the hard mask layer 108, that is, the oxide semiconductor layer 116 and the gate 106 partially overlap in the vertical direction. The oxide semiconductor layer 116 may be made of oxide semiconductor materials such as titanium oxide (TiO2), zinc oxide (ZnO), niobium oxide (Nb2O5), tungsten oxide (Nb2O5), tin oxide (SnO2), zirconium oxide (ZrO2), or indium gallium zinc oxide (IGZO), and may be formed by sputtering or atomic layer deposition (ALD) processes.

[0040] Rereference Figure 5A and Figure 5B After the oxide semiconductor layer 116 is formed, the remaining space in the recess 109 is filled with filler oxide 114. The filler oxide 114 can be made of silicon oxide, which can be formed by CVD fabrication and then a planarization (e.g., CMP) process is performed to remove the filler oxide 114 located outside the recess 109. In this embodiment of the invention, an etching process can be performed again to remove part of the filler oxide 114, so that its top surface is lower than the top surface of the hard mask layer 108 or the gate 106, so that the subsequent step of forming the drain 118 can achieve a self-alignment effect between the source 102 and the drain 118.

[0041] Finally, please refer to... Figure 6A and Figure 6B After the oxide semiconductor layer 116 and the filling oxide 114 are formed, a drain 118 is then formed on the oxide semiconductor layer 116 and the filling oxide 114. The drain 118 can be made of a low-resistivity metal material, such as titanium (Ti), molybdenum (Mo), chromium (Cr), aluminum (Al), gold (Au), or an alloy of the above materials. It can be formed by physical vapor deposition (PVD) or sputtering processes, and patterned by photolithography to completely cover the underlying source 102 and extend to the surrounding gate 106 to directly contact the surrounding oxide semiconductor layer 116. In this way, the fabrication of the vertical oxide semiconductor transistor of the present invention is completed.

[0042] In summary, the vertical oxide semiconductor transistor structure proposed in this invention, besides significantly reducing the required transistor layout area due to its vertical channel design, also achieves self-alignment in the fabrication process for both the oxide semiconductor layer (channel layer) and the drain. Furthermore, due to this design, compared to other vertical transistor designs, the overlap area between the gate and source or drain of the transistor in this invention is smaller, significantly reducing the Miller capacitance (between the input and output terminals) and improving the transistor's response speed.

[0043] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A vertical oxide semiconductor transistor, comprising: Insulating substrate; The source electrode is located within the insulating substrate; A gate is located on the insulating substrate, wherein the gate forms a groove above the source electrode around the source electrode; The inner partition wall is located on the inner wall of the gate in the groove; An oxide semiconductor layer is located on the inner spacer and the source electrode and is in direct contact with the source electrode; A filling oxide, located on the oxide semiconductor layer and filling the groove; and The drain is located on the oxide semiconductor layer and the filling oxide, and is in direct contact with the oxide semiconductor layer, wherein the drain completely covers the source and partially overlaps with the gate.

2. The vertical oxide semiconductor transistor of claim 1, further comprising a hard mask layer located on the gate, and a portion of the oxide semiconductor layer extending from the inner spacer wall onto the hard mask layer.

3. The vertical oxide semiconductor transistor of claim 1, wherein the source electrode overlaps with the inner spacer wall.

4. The vertical oxide semiconductor transistor of claim 1, wherein the source and the gate do not overlap.

5. The vertical oxide semiconductor transistor of claim 1, further comprising an insulating layer located between the gate and the insulating substrate.

6. The vertical oxide semiconductor transistor of claim 1, wherein the material of the oxide semiconductor layer includes titanium oxide (TiO2), zinc oxide (ZnO), niobium oxide (Nb2O5), tungsten oxide (WO3), tin oxide (SnO2), zirconium oxide (ZrO2), or indium gallium zinc oxide (IGZO).

7. The vertical oxide semiconductor transistor of claim 1, wherein the gate, the source, and the drain are made of titanium (Ti), molybdenum (Mo), chromium (Cr), aluminum (Al), gold (Au), tungsten (W), or alloys of the above materials.

8. The vertical oxide semiconductor transistor of claim 1, wherein the spacer wall material is silicon oxide (SiO2) or silicon nitride (SiN). X It could be aluminum oxide (Al2O3).

9. The vertical oxide semiconductor transistor of claim 1, wherein the insulating substrate is made of polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), or silicon dioxide (SiO2).

10. The vertical oxide semiconductor transistor of claim 1, wherein the filling oxide is made of silicon oxide (SiO2).

11. A method for fabricating a vertical oxide semiconductor transistor, comprising: Provide an insulating substrate; The source electrode is formed in the insulating substrate; A gate is formed on the insulating substrate surrounding the source, wherein the gate forms a groove above the source; Spacer walls are formed on the sidewalls of the gate; An oxide semiconductor layer is formed on the spacer wall in the groove and on the source electrode, and the oxide semiconductor layer is in direct contact with the source electrode; A filling oxide is formed on the oxide semiconductor layer to fill the groove; as well as A drain is formed on the oxide semiconductor layer and the filled oxide, and the drain directly contacts the oxide semiconductor layer, wherein the drain completely covers the source and partially overlaps the gate.

12. The method of fabricating a vertical oxide semiconductor transistor as claimed in claim 11, wherein the step of forming the gate comprises: A gate material layer and a hard mask material layer are sequentially formed on the insulating substrate; The hard mask material layer is patterned using a photolithography process to form a hard mask layer with a gate pattern; as well as Using the hard mask layer as an etching mask, an etching process is performed to pattern the gate material layer into the gate.

13. The method of fabricating a vertical oxide semiconductor transistor as claimed in claim 12, wherein the step of forming the spacer wall comprises: A conformal spacer layer is formed on the gate and the insulating substrate; and An anisotropic etching process is used to remove the spacer layer of a certain vertical thickness, so that the spacer layer becomes the spacer on the sidewall of the gate and exposes the hard mask layer.

14. The method of fabricating a vertical oxide semiconductor transistor as described in claim 13, further comprising forming an insulating layer on the insulating substrate before forming the gate, and the insulating layer on the source being removed in the anisotropic etching process to expose the source.

15. The method of fabricating a vertical oxide semiconductor transistor as claimed in claim 14, wherein the step of forming the oxide semiconductor layer comprises: A conformal oxide semiconductor material layer is formed on the surfaces of the hard mask layer, the spacer, the source electrode, and the insulating substrate; and A photolithography process is used to remove part of the oxide semiconductor material layer, leaving only the oxide semiconductor material layer located in the spacer wall in the groove, on the source electrode, and on part of the hard mask layer.

16. The method of fabricating a vertical oxide semiconductor transistor as claimed in claim 11, wherein the step of forming the fill oxide includes performing an etch-back fabrication process such that the top surface of the fill oxide is lower than the top surface of the gate.

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