A particle detector data processing system and method

Abstract

The application relates to the technical field of data processing, and discloses a particle detector data processing system and method, which comprises an analog-digital conversion board, an FPGA board and a server; the analog-digital conversion board realizes analog signal input and digital signal conversion output; the FPGA board comprises a JESD204B protocol module, a digital decoding assembly module, a DDR3 data cache module, a TCP_RoCEv2 module, a high-speed Ethernet transmission module, an SPI configuration module, an AXI4 configuration module, an analysis control module and an SFP+ gigabit optical module; the server is provided with an Ethernet card with the SFP+ gigabit optical module, and the internal high-speed Ethernet data receiving logic is mainly designed to receive data processed in real time by the FPGA. The disclosed data processing system and method can improve data transmission efficiency and server data processing efficiency, and can realize high-speed, dead-time-free and real-time data processing.

Description

A particle detector data processing system and method Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to a particle detector data processing system and method. Background Technology

[0002] With the improvement of particle detector resolution and accuracy, as well as the development of electronic architecture, the ever-increasing data volume poses greater challenges to the design of electronic data processing systems. For example, the electronic readout architecture of superconducting edge-switching detectors based on μMux (microwave multiplexing) currently uses a multiplexing ratio greater than 1000:1 internationally. This means that each electronic readout path needs to process data from thousands of detectors through multiplexing, and the overall data rate of a single readout path can reach close to 100Gbps, while the entire detector array will exceed 400Gbps.

[0003] For data processing, when dealing with small amounts of data and performing simple, fixed calculations, the traditional method is to use the internal logic computing units of an FPGA to perform the calculations. However, when dealing with larger amounts of data and performing more complex logic calculations, the FPGA's internal logic functions are predetermined during programming, and it lacks the instruction set of CPUs and GPUs, making it difficult to meet the requirements. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a particle detector data processing system and method to achieve high-speed, dead-time-free, and real-time data processing.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows:

[0006] A particle detector data processing system includes an analog-to-digital converter board, an FPGA board, and a server; the FPGA board includes a JESD204B protocol module, a digital decoding assembly module, a DDR3 data cache module, a TCP_RoCEv2 module, a high-speed Ethernet transmission module, an SPI configuration module, an AXI4 configuration module, an analysis and control module, and an SFP+ 10 Gigabit optical module.

[0007] The JESD204B protocol module is used to decode the digital signal output by the ADC and output the decoded data to the digital decoding assembly module;

[0008] The digital decoding assembly module is used to rearrange the bit order of ADC sampling data so that the data can be directly analyzed or stored on the server side, and to add timestamps to mark the data packets.

[0009] The DDR3 data cache module is based on the AXI4 data transmission protocol and is used to cache decoded data;

[0010] The TCP_RoCEv2 module is based on the TCP / IP protocol or the RoCEv2 protocol and is used to package the decoded data into data packets in the form of protocol specifications. The packaged data is then transmitted to the high-speed Ethernet transmission module.

[0011] The high-speed Ethernet transmission module is used to further encapsulate data packets into Ethernet data frames, and uses an SFP+ 10 Gigabit optical module to convert electrical signals into optical signals, which are then transmitted to the optical port of the server through 10 Gigabit optical fiber.

[0012] The SPI configuration module is based on the SPI serial port transmission protocol and is used for the transmission of register configuration signals between the FPGA board and the ADC and clock frequency multiplier debouncing unit.

[0013] The AXI4 configuration module is based on the AXI4-Lite protocol and is used to configure the JESD204B protocol module.

[0014] The analysis and control module is based on the integrated logic analyzer and virtual input / output resources inside the FPGA board. It is used to monitor the operation of each module inside the FPGA board and control the generation of reset signals for each module, the establishment of TCP master-slave server connections, and the start of signal transmission.

[0015] In the above scheme, the analog-to-digital converter board includes an ADC, a clock frequency multiplier and debouncing unit, a differential crystal oscillator, a voltage-controlled oscillator, a linear regulator, a power connector, a transformer, a differential amplifier, a bidirectional level converter, an FMC connector, and an SMA connector.

[0016] The ADC is used to digitize the analog signal from the front end;

[0017] The clock frequency multiplier and debouncing device is used to provide the ADC and FPGA board with a reference input clock and a reference synchronization signal specified by the protocol.

[0018] The differential crystal oscillator and voltage-controlled oscillator provide the input reference clock for the clock frequency multiplier and debouncing unit;

[0019] The output of the linear regulator is used to provide the necessary stable power to the ADC and the clock frequency multiplier debouncing device.

[0020] The power connector provides a stable DC power input to the linear regulator;

[0021] The transformer converts a single-ended signal into a differential signal.

[0022] The differential amplifier is used to amplify the differential signal;

[0023] The bidirectional level converter performs level conversion for signals of different level standards transmitted between the FPGA board and the analog-to-digital converter board.

[0024] The FMC connector is used to connect the analog-to-digital converter board and the FPGA board;

[0025] The SMA connector is used for analog signal input to the ADC.

[0026] In the above solution, the server is equipped with an Ethernet card with an SFP+ 10 Gigabit optical module and has internal high-speed Ethernet data receiving logic to receive data processed in real time by the FPGA board, ensuring the real-time performance of the system data processing.

[0027] A particle detector data processing method, employing a particle detector data processing system as described above, includes the following steps:

[0028] The analog-to-digital converter board connects to the particle detector via the SMA connector and to the FPGA board at the back end via the FMC connector, enabling the input of analog signals and the conversion and output of digital signals.

[0029] Digital signals are input to the FPGA board. The analysis and control module is responsible for issuing control and configuration commands, as well as monitoring and analyzing the internal signal status of the FPGA board. Under the control of this module, the AXI4 configuration module configures the JESD204B protocol module based on the AXI4-Lite protocol. With the help of the analysis and control module, the SPI configuration module outputs the required clock signal and synchronization reference signal to configure the analog-to-digital converter to the required working ready state. When both the JESD204B protocol module and the analog-to-digital converter are configured to be in JESD204B protocol mode and simultaneously receive the synchronization reference signal from the SPI configuration module, the digitized signal from the analog-to-digital converter board will begin to be transmitted according to the JESD204B protocol. It is transmitted to the FPGA board through the FMC connector. The serial signal is parallelized by the JESD204B protocol module, and the 8b / 10b encoded signal is digitally decoded to obtain the information acquired by the ADC.

[0030] The parallel data is reordered and corrected bit by bit by the digital decoding and assembly module to restore the real analog signal. The corrected data awaits control commands from the server and the FPGA board, and is cached sequentially into the DDR3 data cache module. The control data is then transmitted from the FPGA board to the server. The data output from the DDR3 data cache module is packaged by the TCP_RoCEv2 module to form a data packet format that conforms to the protocol. The packet is further encapsulated by the high-speed Ethernet transmission module to form an Ethernet frame, which is then uploaded to the server via the SFP+ 10 Gigabit optical module to complete the data transmission.

[0031] In the above scheme, the analog signal output by the particle detector is input to the transformer through the SMA connector to realize the conversion of single-ended signal to differential signal. Then the differential signal is input to the differential amplifier for amplification. After that, it enters the ADC for analog-to-digital conversion. The converted signal enters the FPGA board through the FMC connector.

[0032] Differential crystal oscillator and VCXO provide input clock for clock frequency multiplier and debouncing device. The output of clock frequency multiplier and debouncing device provides reference input clock for ADC and synchronization reference signal specified by JESD204B protocol. It also provides core clock, high-speed transceiver reference clock and synchronization reference signal for JESD204B protocol module of FPGA board.

[0033] The differential crystal oscillator provides the clock input for the first-stage PLL of the clock frequency multiplier and debouncing device, and the VCXO provides the clock input for the second-stage PLL of the clock frequency multiplier and debouncing device, while also providing a feedback signal for the first-stage PLL, ensuring the homogeneity of the clocks in the system.

[0034] The automatic bidirectional level conversion module performs level standard conversion for the configuration signals of the SPI protocol specification between the FPGA board and the ADC and clock frequency multiplier debouncing unit to prevent level standard mismatch problems.

[0035] In the above scheme, the server receives the uploaded data through an SFP+10 Gigabit optical module; for TCP / IP protocol data, the internal socket logic is designed, with the server acting as the client of the TCP connection and the FPGA board acting as the server of the TCP connection; the client sends a connection establishment request to the server, and the server receives the request and agrees to establish the connection.

[0036] After the connection is established, the analysis and control module in the FPGA board turns on the data transmission switch, and the data begins to be buffered in the DDR3 data cache module and transmitted to the server. TCP / IP protocol data transmission consumes CPU resources, and parallel data processing increases thread scheduling, which can easily lead to dead time when the server data reception is temporarily suspended.

[0037] At this point, the data in the FPGA board stops being sent to the server and is only cached in the DDR3 data cache module, waiting for the CPU to resume receiving data before the data is sent to the server again from the DDR3 data cache module.

[0038] In the above scheme, when the experiment requires more CPU resources, the RoCEv2 protocol can be used to replace the TCP / IP protocol to achieve data upload.

[0039] In the above scheme, the server monitors the correctness of the data and the full / empty status of the server's receiving buffer in real time during the data receiving process, and promptly feeds back the status information to the FPGA board to control the data transmission and ensure data correctness.

[0040] In the above scheme, the server data is processed by the CPU or GPU through parallel computing. The calculation results are stored on the server along with timestamp information to facilitate subsequent offline packet splitting and further physical data analysis.

[0041] The particle detector data processing system and method provided by the present invention, through the above technical solution, have the following beneficial effects:

[0042] This invention uses an ADC (Analog-to-Digital Converter) to digitize analog signals, and an FPGA board to perform simple real-time reception, decoding, and buffering of digital signals. For data rates of 10Gbps, 40Gbps, or even 100Gbps, high-speed data transmission from the FPGA to the server is achieved using TCP / IP or RoCEv2 protocols. Since the CPU and GPU in the server are not real-time devices, dead time can occur due to thread scheduling issues during data processing, leading to data loss. This invention optimizes the multi-threaded data processing logic on the server side, using protocols such as TCP / IP and RoCEv2 to improve data transmission and server data processing efficiency. Furthermore, it utilizes the memory resources on the FPGA board as a buffer during data transmission to alleviate the pressure on server-side data processing, thereby eliminating dead time in the entire data transmission process and ensuring real-time and accurate data transmission. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0044] Figure 1 is a schematic diagram of a particle detector data processing system disclosed in an embodiment of the present invention.

[0045] Figure 2 is a schematic diagram of the composition of the analog-to-digital converter board disclosed in the embodiment of the present invention.

[0046] Figure 3 is a schematic diagram of the FPGA board composition disclosed in the embodiment of the present invention.

[0047] Figure 4 is a schematic diagram of the server composition disclosed in the embodiment of the present invention. Detailed Implementation

[0048] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0049] The present invention provides a particle detector data processing system, as shown in Figure 1, which includes an analog-to-digital converter board, an FPGA board and a server.

[0050] I. Analog-to-Digital Converter Board

[0051] As shown in Figure 2, the analog-to-digital converter board includes an ADC, a clock multiplier and debouncing unit, a differential crystal oscillator, a voltage-controlled oscillator (VCXO), a linear regulator (LDO), a power connector, a transformer, a differential amplifier, a bidirectional level shifter, an FMC connector, and an SMA connector. The functions of each component are as follows:

[0052] An ADC is used to digitize analog signals from the front end. In this embodiment, an analog-to-digital converter chip is selected. A single chip supports 16 analog signal inputs and 4 high-speed digital signal outputs. This module supports the JESD204B transmission protocol, and the data rate can reach 10 gigabits per second or even higher for a single chip and single channel.

[0053] The clock frequency multiplier and debouncing device, conforming to the JESD204B transmission protocol, is used to provide the reference input clock and the reference synchronization signal specified in the protocol for the ADC and FPGA board. In this embodiment, a dual phase-locked loop (PLL) chip is selected, which, with the help of its internal cascaded PLL and integrated VCO (voltage-controlled oscillator), can achieve a maximum clock frequency multiplication output of 3080MHz. In this embodiment, the clock frequency multiplier and debouncing device is an ultra-low noise clock frequency multiplier and debouncing device.

[0054] The differential crystal oscillator and VCXO provide the input reference clock for the clock multiplier and debouncing unit.

[0055] LDOs, whose outputs are used to provide stable power supplies of different standards such as 1.0V, 1.8V, and 3.3V to ADCs and clock multipliers / debouncing devices.

[0056] The power connector provides a stable 5V DC power input to the linear regulator.

[0057] Transformers convert single-ended signals into differential signals.

[0058] A differential amplifier is used to amplify differential signals.

[0059] The bidirectional level converter is an automatic bidirectional level converter used to convert the levels of signals of different level standards transmitted between the FPGA board and the analog-to-digital converter board.

[0060] FMC connectors are used to connect analog-to-digital converter boards to FPGA boards.

[0061] The SMA connector is used for the analog signal input of the ADC.

[0062] 2. FPGA board

[0063] As shown in Figure 3, the FPGA board includes a JESD204B protocol module, a digital decoding and assembly module, a DDR3 data cache module, a TCP_RoCEv2 module, a high-speed Ethernet transmission module, an SPI configuration module, an AXI4 configuration module, an analysis and control module, and an SFP+ 10 Gigabit optical module. The functions of each module are as follows:

[0064] The JESD204B protocol module is used to decode the digital signals output by the ADC in 8b / 10b mode and output the decoded data to the digital decoding assembly module.

[0065] The digital decoding assembly module is used to rearrange the bit order of ADC sampling data so that the data can be directly analyzed or stored on the server side, and to add timestamps to mark the data packets.

[0066] The DDR3 data cache module is based on the AXI4 data transmission protocol and is used to cache decoded data, especially when dead time occurs in the system.

[0067] The TCP_RoCEv2 module, based on the TCP / IP or RoCEv2 protocol, is used to package decoded data into data packets conforming to the protocol specifications, and then transmit the packaged data to the high-speed Ethernet transmission module.

[0068] The high-speed Ethernet transmission module is used to further encapsulate data packets into Ethernet data frames. With the help of the SFP+ 10 Gigabit optical module, the electrical signal is converted into an optical signal and transmitted to the optical port of the server through the 10 Gigabit optical fiber.

[0069] The SPI configuration module is based on the SPI serial port transmission protocol and is used for the transmission of register configuration signals between the FPGA board and the ADC and clock frequency multiplier debouncing unit.

[0070] The AXI4 configuration module is based on the AXI4-Lite protocol and is used to configure the JESD204B protocol module.

[0071] The analysis and control module is based on the ILA (Integrated Logic Analyzer) and VIO (Virtual Input / Output) resources inside the FPGA board. It is used to monitor the operation of each module inside the FPGA board and control the generation of reset signals for each module, the establishment of TCP master-slave server connections, and the start of signal transmission.

[0072] III. Server

[0073] As shown in Figure 4, the server is equipped with an Ethernet card featuring an SFP+ 10 Gigabit optical module. Its internal design incorporates high-speed Ethernet data receiving logic to receive data processed in real-time by the FPGA board, ensuring the real-time performance of the system's data processing. While the uploaded data is received by the server in real-time, the server simultaneously sends handshake feedback information to the FPGA to confirm data accuracy. Real-time data computation, analysis, and storage typically involve flexibly selecting either a CPU or GPU device based on the data rate and the server's own performance. The server can monitor or control data transmission at the FPGA end while processing data in real-time, improving the system's flexibility. The results of real-time computation are stored in packets for subsequent offline analysis.

[0074] This invention also discloses a particle detector data processing method, which employs the particle detector data processing system described above and includes the following processes:

[0075] (1) The analog-to-digital converter board is connected to the particle detector via the SMA connector and to the FPGA board at the back end via the FMC connector, so as to realize the input of analog signals and the conversion and output of digital signals.

[0076] The analog-to-digital converter (ADC) board uses an external independent power supply, connected to an external DC power supply via a power connector. An LDO provides the necessary operating voltage to components such as the ADC, clock multiplier / deboiler, and bidirectional level conversion module. The ADC, as the core component of the ADC board, is exemplarily selected as a Σ-Δ ADC, supporting up to 16 analog signal inputs and 4 digital signal outputs. The maximum bandwidth for a single analog signal is 125MHz, and the maximum speed for a single digital signal is 16Gbps. Due to the high digital signal rate, to reduce crosstalk, the design should adhere to the principle of three times the linewidth between signal paths. The ADC also features a multi-stage filtering structure, resulting in good noise performance. A transformer is connected to the input terminal to convert single-ended signals to differential signals. A differential amplifier is connected before the transformer to amplify the differential signals.

[0077] The analog signal output by the particle detector is input to the transformer via the SMA connector to convert the single-ended signal into a differential signal. The differential signal is then input to the differential amplifier for amplification. After that, it enters the ADC for analog-to-digital conversion. The converted signal enters the FPGA board via the FMC connector.

[0078] The differential crystal oscillator and VCXO provide the input clock for the clock frequency multiplier and debouncing unit. The output of the clock frequency multiplier and debouncing unit provides the reference input clock for the ADC and the synchronization reference signal specified by the JESD204B protocol. It also provides the core clock, high-speed transceiver reference clock, and synchronization reference signal for the JESD204B protocol module of the FPGA board. The differential crystal oscillator provides the clock input for the first-stage PLL of the clock frequency multiplier and debouncing unit, and the VCXO provides the clock input for the second-stage PLL of the clock frequency multiplier and debouncing unit. At the same time, it provides the feedback signal for the first-stage PLL, ensuring the clock homogeneity in the system. The automatic bidirectional level conversion module performs level standard conversion for the configuration signals of the SPI protocol specification between the FPGA board and the ADC and the clock frequency multiplier and debouncing unit to prevent level standard mismatch problems.

[0079] (2) FPGA board, for example, Xilinx KC705, the internal logic design is shown in Figure 3.

[0080] Digital signals are input to the FPGA board. The analysis and control module is responsible for issuing control and configuration commands, as well as monitoring and analyzing the internal signal status of the FPGA board. Under the control of this module, the AXI4 configuration module configures the JESD204B protocol module based on the AXI4-Lite protocol. With the help of the analysis and control module, the SPI configuration module outputs the required clock signal and synchronization reference signal to configure the analog-to-digital converter to the required working ready state. When both the JESD204B protocol module and the analog-to-digital converter are configured to be in JESD204B protocol mode and simultaneously receive the synchronization reference signal from the SPI configuration module, the digitized signal from the analog-to-digital converter board will begin to be transmitted according to the JESD204B protocol. It is transmitted to the FPGA board through the FMC connector. The serial signal is parallelized by the JESD204B protocol module, and the 8b / 10b encoded signal is digitally decoded to obtain the information acquired by the ADC.

[0081] The parallel data is reordered and corrected bit by bit by the digital decoding and assembly module to restore the real analog signal. The corrected data awaits control commands from the server and the FPGA board, and is cached sequentially into the DDR3 data cache module. The control data is then transmitted from the FPGA board to the server. The data output from the DDR3 data cache module is packaged by the TCP_RoCEv2 module to form a data packet format that conforms to the protocol. The packet is further encapsulated by the high-speed Ethernet transmission module to form an Ethernet frame, which is then uploaded to the server via the SFP+ 10 Gigabit optical module to complete the data transmission.

[0082] (3) The server receives the uploaded data through the SFP+ 10 Gigabit optical module; for TCP / IP protocol data, the internal socket logic is designed, the server acts as the client of the TCP connection, and the FPGA board acts as the server of the TCP connection; the client sends a connection establishment request to the server, and the server receives the request and agrees to establish the connection.

[0083] After the connection is established, the analysis and control module in the FPGA board turns on the data transmission switch, and the data begins to be buffered in the DDR3 data cache module and transmitted to the server. TCP / IP protocol data transmission consumes CPU resources, and parallel data processing increases thread scheduling, which can easily lead to dead time when the server data reception is temporarily suspended.

[0084] At this point, the data in the FPGA board stops being sent to the server and is only cached in the DDR3 data cache module, waiting for the CPU to resume receiving data. Then, the data is sent to the server again from the DDR3 data cache module. This ensures that no data loss occurs when dead time occurs at high data rates.

[0085] The key to the above process is to set the read and write control logic in the DDR3 data cache module so that when the CPU resumes receiving data, the average write rate of the DDR3 data cache module is less than the average read rate. This ensures that the DDR3 data cache module can clear its space at any time and prevent dead time from happening again.

[0086] The TCP / IP protocol consumes significant CPU resources. When experiments require even more CPU resources, the RoCEv2 protocol can be used as an alternative to TCP / IP for data uploading. RoCEv2 enables direct data exchange between the FPGA and server memory, thus greatly freeing up CPU resources. Due to the limitations of CPU cores, using a GPU for parallel computation of high-speed data ensures higher data processing efficiency and also effectively reduces the CPU load.

[0087] During data reception, the server monitors the data's correctness and the fullness / emptiness of its receive buffer in real time, promptly feeding back status information to the FPGA and controlling data transmission to ensure data integrity. Uploaded data is processed by the CPU or GPU through parallel computing, and the calculation results, along with timestamp information, are stored on the server for subsequent offline packet segmentation and further physical data analysis.

[0088] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A particle detector data processing system, characterized in that, It includes an analog-to-digital converter board, an FPGA board, and a server; the FPGA board includes a JESD204B protocol module, a digital decoding assembly module, a DDR3 data cache module, a TCP_RoCEv2 module, a high-speed Ethernet transmission module, an SPI configuration module, an AXI4 configuration module, an analysis and control module, and an SFP+ 10 Gigabit optical module; the JESD204B protocol module is used to decode the digital signal output by the ADC and output the decoded data to the digital decoding assembly module; The digital decoding assembly module is used to rearrange the bit order of the ADC sampling data so that the data can be directly analyzed or stored on the server side, and to add timestamps to mark the data packets; the DDR3 data cache module is based on the AXI4 data transmission protocol and is used to cache the decoded data; the TCP_RoCEv2 module is based on the TCP / IP protocol or the RoCEv2 protocol and is used to package the decoded data into data packets in the form of protocol specifications, and the packaged data is transmitted to the high-speed Ethernet transmission module. The high-speed Ethernet transmission module further encapsulates data packets into Ethernet data frames, converts electrical signals into optical signals using an SFP+ 10 Gigabit optical module, and transmits them to the server's optical port via 10 Gigabit fiber. The SPI configuration module, based on the SPI serial port transmission protocol, is used for transmitting register configuration signals between the FPGA board and the ADC and clock frequency multiplier / debouncing unit. The AXI4 configuration module, based on the AXI4-Lite protocol, is used for configuring the JESD204B protocol module. The analysis and control module, based on the integrated logic analyzer and virtual input / output resources within the FPGA board, monitors the operation of various modules within the FPGA board and controls the generation of reset signals for each module, as well as TCP transmission master-slave server connections. The establishment of the circuit and the start of signal transmission are described. The analog-to-digital converter board includes an ADC, a clock frequency multiplier and debouncing unit, a differential crystal oscillator, a voltage-controlled oscillator (VCO), a linear regulator, a power connector, a transformer, a differential amplifier, a bidirectional level converter, an FMC connector, and an SMA connector. The ADC is used to digitize the analog signals from the front end. The clock frequency multiplier and debouncing unit provides a reference input clock and a protocol-defined reference synchronization signal for the ADC and the FPGA board. The differential crystal oscillator and the VCO provide an input reference clock for the clock frequency multiplier and debouncing unit. The linear regulator's output provides the necessary stable power to the ADC and the clock frequency multiplier and debouncing unit. The power connector provides a stable DC power input to the linear regulator. The transformer converts single-ended signals to differential signals. The differential amplifier is used to amplify the differential signal; the bidirectional level converter performs level conversion for signals of different level standards transmitted between the FPGA board and the analog-to-digital converter board; the FMC connector is used to connect the analog-to-digital converter board and the FPGA board; the SMA connector is used for the analog signal input of the ADC.

2. The particle detector data processing system according to claim 1, characterized in that, The server is equipped with an Ethernet card featuring an SFP+ 10 Gigabit optical module and has internal high-speed Ethernet data receiving logic to receive data processed in real time by the FPGA board, ensuring the real-time performance of the system's data processing.

3. A particle detector data processing method, employing a particle detector data processing system as described in any one of claims 1-2, characterized in that, The process includes the following steps: the analog-to-digital converter (ADC) board is connected to the particle detector via the SMA connector and to the FPGA board at the back end via the FMC connector, enabling the input of analog signals and the conversion and output of digital signals; the digital signals are input to the FPGA board, and the analysis and control module is responsible for issuing control and configuration commands, as well as monitoring and analyzing the internal signal status of the FPGA board. Under the control of this module, the AXI4 configuration module configures the JESD204B protocol module based on the AXI4-Lite protocol. With the help of the analysis and control module, the SPI configuration module outputs the required clock signal and synchronization reference signal to configure the analog-to-digital converter (ADC) to the required working ready state. When both the JESD204B protocol module and the ADC are configured to be in JESD204B protocol mode and simultaneously receive the synchronization reference signal from the SPI configuration module, the digitized signal from the ADC board will begin to be transmitted according to the JESD204B protocol. It will be transmitted to the FPGA board through the FMC connector. The serial signal is parallelized by the JESD204B protocol module, and the 8b / 10b encoded signal is digitally decoded to obtain the information acquired by the ADC. The parallel data is reordered and corrected bit by bit by the digital decoding and assembly module to restore the real analog signal. The corrected data awaits control commands from the server and the FPGA board, and is cached sequentially into the DDR3 data cache module. The control data is then transmitted from the FPGA board to the server. The data output from the DDR3 data cache module is packaged by the TCP_RoCEv2 module to form a data packet format that conforms to the protocol. The packet is further encapsulated by the high-speed Ethernet transmission module to form an Ethernet frame, which is then uploaded to the server via the SFP+ 10 Gigabit optical module to complete the data transmission.

4. The particle detector data processing method according to claim 3, characterized in that, The analog signal output from the particle detector is input to the transformer via an SMA connector to convert the single-ended signal to a differential signal. The differential signal is then input to a differential amplifier for amplification. After that, it enters the ADC for analog-to-digital conversion. The converted signal enters the FPGA board via an FMC connector. The differential crystal oscillator and VCXO provide the input clock for the clock frequency multiplier and debouncing unit. The output of the clock frequency multiplier and debouncing unit provides the reference input clock for the ADC and the synchronization reference signal specified by the JESD204B protocol. It also provides the core clock, high-speed transceiver reference clock, and synchronization reference signal for the JESD204B protocol module on the FPGA board. The differential crystal oscillator provides the clock input for the first-stage PLL of the clock frequency multiplier and debouncing unit, and the VCXO provides the clock input for the second-stage PLL of the clock frequency multiplier and debouncing unit, while also providing a feedback signal to the first-stage PLL, ensuring the clock homogeneity in the system. The automatic bidirectional level conversion module performs level standard conversion for the configuration signals of the SPI protocol specification between the FPGA board and the ADC and clock frequency multiplier debouncing unit to prevent level standard mismatch problems.

5. The particle detector data processing method according to claim 3, characterized in that, The server receives uploaded data via an SFP+10 Gigabit optical module. For TCP / IP protocol data, the internal design incorporates Socket logic, with the server acting as the TCP client and the FPGA board as the TCP server. The client sends a connection request to the server, which receives and agrees to establish the connection. Once the connection is established, the analysis and control module on the FPGA board turns on the data transmission switch, and data begins to be buffered in the DDR3 data buffer module and transmitted to the server. TCP / IP protocol data transmission consumes CPU resources, and parallel data processing increases thread scheduling, which can easily lead to dead time when server data reception is temporarily interrupted. In this case, the data in the FPGA board is stopped from being transmitted to the server, and only buffered in the DDR3 data buffer module, waiting for the CPU to resume reception before data is transmitted to the server again from the DDR3 data buffer module.

6. The particle detector data processing method according to claim 3, characterized in that, When experiments require more CPU resources, the RoCEv2 protocol can be used to replace the TCP / IP protocol for data uploading.

7. The particle detector data processing method according to claim 3, characterized in that, During the data reception process, the server monitors the correctness of the data and the full / empty status of the server's receive buffer in real time, promptly feeding back status information to the FPGA board, controlling data transmission, and ensuring data correctness.

8. The particle detector data processing method according to claim 3, characterized in that, The server's data is processed by the CPU or GPU through parallel computing. The calculation results, along with timestamp information, are stored on the server to facilitate subsequent offline packet splitting and further physical data analysis.

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