GaN hermetic device

Abstract

The application discloses a GaN hybrid encapsulation device, which comprises a frame, a cascade GaN HEMT device, a Si MOSFET arranged on a first base island, a GaN HEMT arranged on a second base island and cascaded with the Si MOSFET, a control chip arranged in a flip-chip mode, a plurality of pins of the control chip connected with a gate of the cascade GaN HEMT device and a third base island through copper columns, a ceramic substrate arranged above the cascade GaN HEMT device and the control chip, a first copper layer arranged on a lower surface of the ceramic substrate and corresponding to the cascade GaN HEMT device, plastic encapsulation material and a bare upper surface of the ceramic substrate exposed outside the plastic encapsulation material. The technical scheme disclosed by the application realizes double-side heat dissipation through the top copper-clad ceramic substrate and the bottom frame, thereby improving the heat dissipation efficiency of the GaN hybrid encapsulation device, reducing internal heat accumulation and improving the reliability of the GaN hybrid encapsulation device.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and more particularly to a GaN encapsulated device. Background Technology

[0002] A high-voltage depletion-mode GaN HEMT (gallium nitride high electron mobility transistor) and a low-voltage enhancement-mode Si MOSFET (silicon-based metal-oxide-semiconductor field-effect transistor) are packaged together using a common-gate, common-source configuration to form a normally closed cascaded GaN HEMT. This cascaded GaN HEMT is then co-packaged with a PWM (pulse width modulation) control chip within the same package structure to obtain a GaN co-packaged device. This GaN co-packaged device achieves superior performance and has a smaller package size, which is beneficial for product miniaturization design.

[0003] Currently, GaN-encapsulated devices are made by bonding GaN HEMT, Si MOSFET and control chip onto a frame substrate island using conductive adhesive, and the chips are electrically connected to each other. This method results in relatively concentrated heat and poor heat dissipation efficiency.

[0004] In summary, improving the heat dissipation efficiency of GaN encapsulated devices is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a GaN encapsulated device for improving the heat dissipation of GaN encapsulated devices.

[0006] To achieve the above objectives, this application provides the following technical solution:

[0007] A GaN encapsulated device, comprising:

[0008] A frame comprising a first base island, a second base island, and a third base island; the third base island is connected to a first frame pin on the frame;

[0009] A cascaded GaN HEMT device is configured with its source connected to a second frame pin on the frame and its drain connected to a third frame pin on the frame. The GaN HEMT device includes a SiMOSFET disposed on the first base island and a GaN HEMT disposed on the second base island and cascaded with the Si MOSFET.

[0010] A flip-chip control chip; multiple pins of the control chip are respectively connected to the gate of the cascaded GaNHEMT device and the third base island via copper pillars;

[0011] A ceramic substrate is disposed above the cascaded GaN HEMT device and the control chip; a first copper layer corresponding to the cascaded GaN HEMT device is disposed on the lower surface of the ceramic substrate.

[0012] The molding compound is used to encapsulate the frame, the cascaded GaN HEMT device, and the control chip; the upper surface of the ceramic substrate is exposed outside the molding compound.

[0013] Optionally, the source of the Si MOSFET, the gate of the GaN HEMT, and the second frame pin are connected by a first copper plate, the drain of the Si MOSFET and the source of the GaN HEMT are connected by a second copper plate, and the drain of the GaNHEMT is connected to the third frame pin by a third copper plate.

[0014] Optionally, the first copper layer disposed on the lower surface of the ceramic substrate includes a first sub-copper layer corresponding to the first copper sheet, a second sub-copper layer corresponding to the second copper sheet, and a third sub-copper layer corresponding to the third copper sheet.

[0015] Optionally, the upper surfaces of the first copper sheet, the second copper sheet, and the third copper sheet are flush with the upper surface of the control chip.

[0016] Optionally, the first copper sheet, the second copper sheet, and the third copper sheet are of the same size.

[0017] Optionally, a second copper layer corresponding to the control chip is further disposed on the lower surface of the ceramic substrate.

[0018] Optionally, a first trench corresponding to the Si MOSFET is provided at the first base island, and a second trench corresponding to the GaN HEMT is provided at the second base island.

[0019] Optionally, the upper surface of the Si MOSFET is flush with the upper surface of the frame.

[0020] Optionally, the Si MOSFET is disposed in the first tank using conductive adhesive, and the GaN HEMT is disposed in the second tank using conductive adhesive.

[0021] Optionally, the first copper layer is disposed above the cascaded GaN HEMT device using conductive adhesive, and the second copper layer is disposed above the control chip using conductive adhesive.

[0022] This application provides a GaN encapsulated device, comprising: a frame including a first base island, a second base island, and a third base island; the third base island being connected to a first frame pin on the frame; a cascaded GaN HEMT device with its source connected to a second frame pin on the frame and its drain connected to a third frame pin on the frame and mounted upright; the GaN HEMT device including a Si MOSFET disposed on the first base island and a GaN HEMT disposed on the second base island and cascaded with the Si MOSFET; a flip-chip control chip; multiple pins of the control chip being connected to the gate of the cascaded GaN HEMT device and the third base island respectively through copper pillars; a ceramic substrate disposed above the cascaded GaN HEMT device and the control chip; a first copper layer corresponding to the cascaded GaN HEMT device being disposed on the lower surface of the ceramic substrate; a molding compound for encapsulating the frame, the cascaded GaN HEMT device, and the control chip; and the upper surface of the ceramic substrate being exposed outside the molding compound.

[0023] The technical solution disclosed in this application involves a cascaded GaN HEMT mounted upright and a control chip mounted flip-chip, so that the pins on the control chip can be connected to the gate and the third base island on the frame of the cascaded GaN HEMT device through copper pillars. This reduces the use of bonding wires, thereby reducing self-inductance and improving the switching efficiency of the GaN packaged device. It also makes the upper surface of the control chip a flat surface, so as to facilitate the placement of a ceramic substrate on top of the cascaded GaN HEMT device and the control chip. The ceramic substrate above the cascaded GaN HEMT device and control chip has a first copper layer corresponding to the cascaded GaN HEMT device on its lower surface, and the upper surface of the ceramic substrate is exposed outside the molding compound used to encapsulate the GaN packaged device. This allows for double-sided heat dissipation through the copper-clad ceramic substrate above the cascaded GaN HEMT device and the frame below the cascaded GaN HEMT device, thereby improving the heat dissipation efficiency of the GaN packaged device, reducing heat accumulation within the GaN packaged device, improving the reliability and stability of the GaN packaged device, and making the GaN packaged device suitable for high-voltage, high-power electronic devices.

[0024] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0025] Figure 1 This is a schematic cross-sectional view of a known GaN encapsulated device;

[0026] Figure 2 A top view of a GaN encapsulated device provided in an embodiment of this application;

[0027] Figure 3 for Figure 2 A schematic diagram of the cross-section along the AA direction;

[0028] Figure 4 This is a circuit diagram of a cascaded GaN HEMT device;

[0029] Figure 5 This is a schematic diagram of the copper layer distribution on the lower surface of a ceramic substrate provided in an embodiment of this application.

[0030] The reference numerals in the attached figures are as follows:

[0031] 01-PWM control chip, 02-Frame base island, 03-Lead wire, 04-Pin, 05-Encapsulation material;

[0032] 1-Si MOSFET, 2-Conductive adhesive, 3-Frame, 31-First base island, 32-Second base island, 33-First frame pin, 34-Second frame pin, 35-Third frame pin, 4-GaN HEMT, 5-Control chip, 6-Copper pillar, 7-Ceramic substrate, 71-First copper layer, 711-First sub-copper layer, 712-Second sub-copper layer, 713-Third sub-copper layer, 72-Second copper layer, 8-Molding compound, 9-First copper sheet, 10-Second copper sheet, 11-Third copper sheet. Detailed Implementation

[0033] GaN HEMTs are characterized by high mobility, high breakdown field strength, and wide bandgap. Based on their operating characteristics, they are mainly divided into enhancement-mode devices and depletion-mode devices. A high-voltage depletion-mode GaN HEMT and a low-voltage enhancement-mode Si MOSFET are packaged together using a common-gate, common-source configuration to form a normally closed Cascode GaN HEMT. The drive power supply can be compatible with the Si MOSFET device, simplifying drive circuit design, significantly reducing costs and design complexity, and meeting the demands of higher voltage and higher power applications. Furthermore, co-packaging the Cascode GaN HEMT with a PWM control chip in the same package structure achieves even better performance, with a small package area, facilitating product miniaturization, and resulting in low package resistance.

[0034] See Figure 1The diagram shows a cross-sectional schematic of a known GaN encapsulated device. Currently known GaN encapsulated devices consist of a GaN HEMT, a Si MOSFET1, and a PWM control chip01, which are bonded to a corresponding frame substrate 02 using conductive adhesive 2. Electrical connections between the chips are then formed via leads 03, with corresponding pins 04 led out from the leads 03. Finally, the chips are encapsulated using molding compound 05. Because current GaN HEMT chips have a planar structure, the heat generated during operation is primarily dissipated through the chip substrate, conductive adhesive 2, and frame. This results in a long heat conduction path and low heat dissipation efficiency. Furthermore, the increased thermal resistance after encapsulation of multiple chips leads to greater heat concentration. This heat is mainly dissipated through the frame, resulting in low heat dissipation efficiency. Therefore, heat accumulation can occur, potentially causing the GaN encapsulated device to fail due to excessive internal heat.

[0035] Therefore, this application provides a GaN encapsulated device to improve the heat dissipation efficiency of the GaN encapsulated device, thereby reducing the heat accumulation inside the GaN encapsulated device and thus facilitating the improvement of the reliability and stability of the GaN encapsulated device.

[0036] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0037] See Figures 2 to 4 ,in, Figure 2 This paper shows a top view of a GaN encapsulated device according to an embodiment of this application. Figure 3 for Figure 2 A schematic diagram of the cross-section along the AA direction. Figure 4 A circuit diagram of a cascaded GaN HEMT device is shown. An embodiment of this application provides a GaN encapsulated device that may include:

[0038] A frame 3 includes a first base island 31, a second base island 32, and a third base island; the third base island is connected to the first frame pin 33 on the frame 3;

[0039] A cascaded GaN HEMT device with its source connected to the second frame pin 34 on frame 3 and its drain connected to the third frame pin 35 on frame 3, and mounted upright; the GaN HEMT device may include a SiMOSFET1 disposed on the first base island 31 and a GaN HEMT4 disposed on the second base island 32 and cascaded with the SiMOSFET1.

[0040] The control chip 5 is flip-chip configured; multiple pins of the control chip 5 are connected to the gate and the third base island of the cascaded GaN HEMT device through copper pillars 6 respectively.

[0041] A ceramic substrate 7 is disposed above the cascaded GaN HEMT device and control chip 5; a first copper layer 71 corresponding to the cascaded GaN HEMT device is disposed on the lower surface of the ceramic substrate 7.

[0042] Molding compound 8 is used for molding the molded frame 3, cascaded GaN HEMT devices and control chips 5; the upper surface of the ceramic substrate 7 is exposed outside the molding compound 8.

[0043] The GaN encapsulated device provided in this application embodiment may include a frame 3, a cascaded GaN HEMT device, a control chip 5 (specifically a PWM control chip), a ceramic substrate 7, and a molding compound 8. The GaN encapsulated device provided in this application embodiment can withstand a breakdown voltage of 650V or higher.

[0044] Frame 3 may include a first base island 31, a second base island 32, a third base island, a first frame pin 33, a second frame pin 34, and a third frame pin 35. The first base island 31, the second base island 32, and the third base island are isolated from each other (i.e., these three base islands are insulated from each other). The first frame pin 33, the second frame pin 34, and the third frame pin 35 can be located on different inner sides of frame 3. For example, the first frame pin 33 can be located on the first inner side of frame 3, the second frame pin 34 can be located on the second inner side of frame 3, and the third frame pin 35 can be located on the third inner side. The first and second inner sides can be parallel, and the third inner side can be perpendicular to the first and second inner sides. Alternatively, the first frame pin 33, the second frame pin 34, and the third frame pin 35 can be located at other positions within frame 3. The first base island 31, the second base island 32, and the third base island are used for electrical connection with corresponding chips in GaN encapsulated devices. It should be noted that the frame 3 provided in this application embodiment can specifically be a QFN (Quad Flat No-lead Package) frame.

[0045] The cascaded GaN HEMT device includes a Si MOSFET1 and a GaN HEMT4 cascaded with the Si MOSFET1. The Si MOSFET1 is mounted upright on the first base island 31, and the GaN HEMT4 is mounted upright on the second base island 32. The Si MOSFET1 has a vertical structure. Specifically, the drain of the Si MOSFET1 can be located on its lower surface (the side facing the first base island 31) and electrically connected to the first base island 31 via conductive adhesive 2 (specifically, conductive silver paste, etc.). The source and gate of the Si MOSFET1 can be located on its upper surface (i.e., the Si MOSFET1 is mounted upright on the frame 3). The GaN HEMT4 has a planar structure. The lower surface of the GaN HEMT4 is mounted on the second base island 32 via conductive adhesive 2. The source, gate, and drain of the GaN HEMT4 are all located on its upper surface (i.e., the GaN HEMT4 is mounted upright on the frame 3). The drain of Si MOSFET1 is connected to the source of GaN HEMT4, and the source of Si MOSFET1 is connected to the gate of GaN HEMT4. The drain of GaN HEMT4 serves as the drain of the cascaded GaN HEMT device, the source of Si MOSFET1 (or the gate of GaN HEMT4) serves as the source of the cascaded GaN HEMT device, and the gate of Si MOSFET1 serves as the gate of the cascaded GaN HEMT device. The source of the cascaded GaN HEMT device is connected to the second frame pin 34 on frame 3, and the drain of the cascaded GaN HEMT device is connected to the third frame pin 35 on frame 3. That is, the second frame pin 34 on frame 3 is the source pin of frame 3, and the third frame pin 35 on frame 3 is the drain pin of frame 3.

[0046] The control chip 5 is flip-chip mounted on the frame 3, meaning the side of the control chip 5 with pins faces the frame 3 (this side is called the lower surface of the control chip 5), and the side of the control chip 5 without pins faces away from the frame 3 (this side is called the upper surface of the control chip 5). The control chip 5 includes a control pin (DRV, power transistor drive output), which is connected to the gate of the cascaded GaN HEMT device via a copper pillar 6 (specifically, this connection can be fixed by soldering). In other words, the control pin of the control chip 5 can be led out via the copper pillar 6 and connected to the gate of the Si MOSFET 1. The control pin of the control chip 5 can be flip-chip mounted with its pin aligned with the gate of the Si MOSFET 1, meaning the control chip 5 can be positioned above the gate of the Si MOSFET 1. Furthermore, several other pins of the control chip 5 are also led out via the copper pillar 6 and connected to the third base island. The number of third base islands corresponds to the number of other pins of the control chip 5, and each third base island is connected to a first frame pin 33. The control chip 5 typically contains 6 pins, one of which is a control pin. In this case, the remaining pins are the other 5 pins. Figure 2 For example, the first frame pins 33 include a CS (current detection) pin, a GND (ground) pin, an FB (optocoupler feedback) pin, a PRT (auxiliary winding feedback) pin, and a VDD (power supply) pin. By flipping the control chip 5 and connecting each pin on the control chip 5 to the gate and the third base island of the cascaded GaN HEMT device through copper pillars 6 (the third base island is connected to the first frame pins 33 of the frame 3, therefore, the pins on the control chip 5 are connected to the corresponding first frame pins 33 through the third base island), the electrical connection distance between the control pins of the control chip 5 and the gate of the cascaded GaN HEMT device can be shortened, and the electrical connection distance between the remaining pins of the control chip 5 and the corresponding third base island can also be shortened. Furthermore, since the copper pillars 6 have a large conductive area, the internal self-inductance of the GaN encapsulated device can be reduced in the above manner, reducing switching losses and greatly reducing the impact on the switching speed of the GaN HEMT4, thereby improving the switching speed and efficiency of the device. Furthermore, since the control chip 5 is positioned so that the side without pins is away from the frame 3, i.e., the flat side of the control chip 5 faces upwards away from the frame 3, it is convenient to place the ceramic substrate 7 above the control chip 5.

[0047] The ceramic substrate 7 is specifically disposed above the cascaded GaN HEMT device and control chip 5, that is, the ceramic substrate 7 is disposed above the Si MOSFET 1, GaN HEMT 4, and control chip 5, which means the ceramic substrate 7 is disposed on top of the GaN encapsulated device. A first copper layer 71 corresponding to the cascaded GaN HEMT device is disposed on the lower surface of the ceramic substrate 7 (i.e., the surface near the frame 3). The first copper layer 71 can be disposed at the cascaded GaN HEMT device using conductive adhesive 2 or the like. In other words, the ceramic substrate 7 is a copper-clad ceramic substrate. The ceramic substrate 7 can be disposed above the cascaded GaN HEMT device and control chip 5 using conductive adhesive 2 or the like. The ceramic substrate 7 can be an aluminum nitride ceramic substrate or other ceramic substrates; this embodiment does not limit the specific type of ceramic substrate. Since both the ceramic substrate 7 and the copper layer have good thermal conductivity, the copper-clad ceramic substrate 7 at the top, and the copper-clad layer of the ceramic substrate 7 corresponding to the cascaded GaN HEMT device, can achieve double-sided heat dissipation using the bottom frame 3, the copper-clad layer on the lower surface of the ceramic substrate 7, and the ceramic substrate 7. This allows the heat generated by the Si MOSFET1 and GaN HEMT4 in the cascaded GaN HEMT device to be dissipated from both the top and bottom surfaces of the GaN encapsulated device, effectively shortening the heat dissipation path, improving the heat dissipation capacity and efficiency of the GaN encapsulated device, reducing heat accumulation within the GaN encapsulated device, achieving lower power dissipation, and thus improving the reliability and stability of the GaN encapsulated device.

[0048] In GaN encapsulated devices, the molding compound 8 is used to encapsulate the frame 3 (specifically, the base island and frame pins of the frame 3), cascaded GaN HEMT devices, and control chip 5. The upper surface of the ceramic substrate 7 is outside the molding compound 8; that is, the molding compound 8 does not encapsulate the upper surface of the ceramic substrate 7. This allows heat to be effectively transferred from the lower surface of the ceramic substrate 7 to the upper surface and dissipated, thereby enhancing the heat dissipation capacity and efficiency of the GaN encapsulated device and reducing heat accumulation within it.

[0049] The above-disclosed technical solution of this application involves a cascaded GaN HEMT 4 mounted upright and a control chip 5 mounted flip-chip, so that the pins on the control chip 5 can be connected to the gate of the cascaded GaN HEMT device and the third base island on the frame 3 through copper pillars 6. This reduces the use of bonding wires, thereby reducing self-inductance and improving the switching efficiency of the GaN packaged device. It also makes the upper surface of the control chip 5 a flat surface, so that a ceramic substrate 7 can be placed above the cascaded GaN HEMT device and the control chip 5. The ceramic substrate 7, which is positioned above the cascaded GaN HEMT device and control chip 5, has a first copper layer 71 on its lower surface corresponding to the cascaded GaN HEMT device. The upper surface of the ceramic substrate 7 is exposed outside the molding compound 8 used to encapsulate the GaN encapsulated device. This allows for double-sided heat dissipation through the copper-clad ceramic substrate 7 above the cascaded GaN HEMT device and the frame 3 below the cascaded GaN HEMT device. This improves the heat dissipation efficiency of the GaN encapsulated device, reduces heat accumulation within the GaN encapsulated device, enhances the reliability and stability of the GaN encapsulated device, and makes the GaN encapsulated device suitable for high-voltage, high-power electronic devices.

[0050] See Figure 2 and Figure 3 The present application provides a GaN encapsulated device in which the source of Si MOSFET1, the gate of GaNHEMT4 and the second frame pin 34 are connected by a first copper sheet 9, the drain of Si MOSFET1 and the source of GaN HEMT4 are connected by a second copper sheet 10, and the drain of GaN HEMT4 is connected to the third frame pin 35 by a third copper sheet 11.

[0051] In this embodiment, the source of the Si MOSFET1, the gate of the GaN HEMT4, and the second frame pin 34 can be electrically connected via a first copper sheet 9. The drain of the Si MOSFET1 and the source of the GaN HEMT4 can be electrically connected via a second copper sheet 10. The drain of the GaN HEMT4 can be electrically connected to the third frame pin 35 via a third copper sheet 11. Specifically, the corresponding copper sheets can be electrically connected to the corresponding electrodes and pins via conductive adhesive 2. Taking the first copper sheet 9 as an example, it can be electrically connected to the source of the Si MOSFET1, the gate of the GaN HEMT4, and the second frame pin 34 via conductive adhesive 2. Of course, the corresponding copper sheets can also be electrically connected to the corresponding electrodes and pins via other electrical connection methods.

[0052] As can be seen from the above, the embodiments of this application use copper clips to cascade Si MOSFET1 and GaN HEMT4 and to make electrical connections with the corresponding frame pins, without the need for leads for electrical connections. This reduces the thermal resistance of the GaN packaged device, achieves lower power dissipation, and further reduces the package self-inductance of the GaN packaged device, thereby improving the performance of the GaN packaged device.

[0053] See Figure 5 This illustration shows a schematic diagram of the copper layer distribution on the lower surface of a ceramic substrate provided in an embodiment of this application. The GaN encapsulated device provided in this application includes a first copper layer 71 disposed on the lower surface of a ceramic substrate 7, which may include a first sub-copper layer 711 corresponding to a first copper sheet 9, a second sub-copper layer 712 corresponding to a second copper sheet 10, and a third sub-copper layer 713 corresponding to a third copper sheet 11.

[0054] In this embodiment, the first copper layer 71 disposed on the lower surface of the ceramic substrate 7 may specifically include a first sub-copper layer 711, a second sub-copper layer 712, and a third sub-copper layer 713. The first sub-copper layer 711 corresponds to the first copper sheet 9 (i.e., the first sub-copper layer 711 is disposed above the first copper sheet 9), the second sub-copper layer 712 corresponds to the second copper sheet 10 (i.e., the second sub-copper layer 712 is disposed above the second copper sheet 10), and the third sub-copper layer 713 corresponds to the third copper sheet 11 (i.e., the third sub-copper layer 713 is disposed above the third copper sheet 11). The area of ​​each sub-copper layer is larger than the area of ​​the corresponding copper sheet, so that the corresponding sub-copper layer can completely cover the corresponding copper sheet, thereby improving heat transfer and heat dissipation.

[0055] It should be noted that the first sub-copper layer 711, the second sub-copper layer 712, and the third sub-copper layer 713 are isolated from each other to ensure the reliability of the GaN encapsulated device.

[0056] The embodiments of this application provide a GaN encapsulated device in which the upper surfaces of the first copper sheet 9, the second copper sheet 10, and the third copper sheet 11 are flush with the upper surface of the control chip 5.

[0057] In this embodiment, the upper surfaces of the three copper sheets 9, 10 and 11 can be flush with the upper surface of the control chip 5. That is, the upper surfaces of these three copper sheets and the upper surface of the control chip 5 can be located on the same horizontal plane, so as to facilitate the setting of the ceramic substrate 7 and avoid the ceramic substrate 7 from tilting.

[0058] Of course, the upper surfaces of the three copper sheets mentioned above do not have to be flush with the upper surface of the control chip 5. Instead, when setting the ceramic substrate 7, the thickness of the conductive adhesive 2 at different positions can be adjusted to make the ceramic substrate 7 as flat as possible, so as to avoid the ceramic substrate 7 from tilting.

[0059] The embodiments of this application provide a GaN encapsulated device in which the first copper sheet 9, the second copper sheet 10, and the third copper sheet 11 are of the same size.

[0060] In the embodiments of this application, the first copper sheet 9, the second copper sheet 10, and the third copper sheet 11 can be the same size, so that it is not necessary to use copper sheets of multiple sizes in the GaN encapsulation device, thereby facilitating the reduction of the cost and complexity of the GaN encapsulation device.

[0061] See Figure 5 The GaN encapsulated device provided in this application embodiment has a second copper layer 72 corresponding to the control chip 5 disposed on the lower surface of the ceramic substrate 7.

[0062] In this embodiment, considering that the control chip 5 will also generate a certain amount of heat during use, in order to improve the heat dissipation of the control chip 5 and minimize the heat accumulation inside the GaN encapsulated device, a second copper layer 72 (covered with a copper layer) corresponding to the control chip 5 can be provided on the lower surface of the ceramic substrate 7. This allows for double-sided heat dissipation by utilizing the frame 3 below the control chip 5, the corresponding copper layer above it, and the ceramic substrate 7. This effectively dissipates the heat generated by the control chip 5, reduces the heat accumulation inside the GaN encapsulated device, and improves the reliability and stability of the GaN encapsulated device.

[0063] This application provides a GaN encapsulated device in which a first trench corresponding to a Si MOSFET1 is provided on a first base island 31, and a second trench corresponding to a GaN HEMT4 is provided on a second base island 32.

[0064] In this embodiment of the application, trenching can be performed on the first base island 31 on the frame 3 at the location where Si MOSFET1 is set and on the second base island 32 at the location where GaN HEMT4 is set, so that the first base island 31 is provided with a first trench corresponding to Si MOSFET1 and the second base island 32 is provided with a second trench corresponding to GaN HEMT4. Si MOSFET1 is set in the first trench and GaN HEMT4 is set in the second trench. The upper surface of Si MOSFET1 can be flush with the upper surface of GaN HEMT4.

[0065] By setting a first trench at the first base island 31 and a second trench at the second base island 32, the distance between SiMOSFET1 and the bottom of frame 3 and the distance between GaN HEMT4 and the bottom of frame 3 can be shortened accordingly. This not only makes the thickness of GaN encapsulated devices smaller, but also shortens the heat dissipation distance at the bottom, improves heat dissipation capacity and efficiency, and reduces heat accumulation inside GaN encapsulated devices.

[0066] This application provides a GaN encapsulated device in which the upper surface of the Si MOSFET1 is flush with the upper surface of the frame 3.

[0067] In this embodiment, the upper surface of the Si MOSFET1 can be flush with the upper surface of the frame 3, so that the upper surface of the Si MOSFET1 and the upper surface of the frame 3 are on the same horizontal plane, so as to avoid the control chip 5 from tilting during the mounting process, thereby ensuring the reliability of the GaN encapsulated device.

[0068] This application provides a GaN encapsulated device in which a Si MOSFET1 is disposed in a first tank via conductive adhesive 2, and a GaN HEMT4 is disposed in a second tank via conductive adhesive 2.

[0069] In this embodiment, the Si MOSFET1 can be disposed in the first tank using conductive adhesive 2, and the GaN HEMT4 can be disposed in the second tank using conductive adhesive 2, so that the Si MOSFET1 and GaN HEMT4 can be better electrically connected to their respective base islands.

[0070] This application provides a GaN encapsulated device in which a first copper layer 71 is disposed above a cascaded GaN HEMT4 device via conductive adhesive 2, and a second copper layer 72 is disposed above a control chip 5 via conductive adhesive 2.

[0071] In this embodiment, the first copper layer 71 can be disposed above the cascaded GaN HEMT4 device using conductive adhesive 2. When the first copper layer 71 includes a first sub-copper layer 711, a second sub-copper layer 712, and a third sub-copper layer 713, these sub-copper layers 711, 712, and 713 can be respectively disposed above the first copper sheet 9, the second copper sheet 10, and the third copper sheet 11 using conductive adhesive 2. The second copper layer 72 can be disposed above the control chip 5 using conductive adhesive 2, and the thickness of the conductive adhesive 2 can be used to ensure that the ceramic substrate 7 is as flat as possible, thereby improving the reliability of the GaN encapsulated device.

[0072] It should be noted that, in the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0073] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0074] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0075] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A GaN encapsulated device, characterized in that, include: The framework includes a first base island, a second base island, and a third base island; The third base island is connected to the first frame pin on the frame; A cascaded GaN HEMT device is configured with its source connected to a second frame pin on the frame and its drain connected to a third frame pin on the frame. The GaN HEMT device includes a SiMOSFET disposed on the first base island and a GaN HEMT disposed on the second base island and cascaded with the Si MOSFET. The source of the Si MOSFET, the gate of the GaN HEMT, and the second frame pin are connected by a first copper sheet. The drain of the Si MOSFET and the source of the GaN HEMT are connected by a second copper sheet. The drain of the GaN HEMT is connected to the third frame pin by a third copper sheet. A flip-chip control chip; multiple pins of the control chip are respectively connected to the gate of the cascaded GaN HEMT device and the third base island via copper pillars; A ceramic substrate is disposed above the cascaded GaN HEMT device and the control chip; a first copper layer corresponding to the cascaded GaN HEMT device is disposed on the lower surface of the ceramic substrate; the first copper layer includes a first sub-copper layer corresponding to the first copper sheet, a second sub-copper layer corresponding to the second copper sheet, and a third sub-copper layer corresponding to the third copper sheet; the first sub-copper layer, the second sub-copper layer, and the third sub-copper layer are isolated from each other; the areas of the first sub-copper layer, the second sub-copper layer, and the third sub-copper layer are respectively larger than the areas of the first copper sheet, the second copper sheet, and the third copper sheet, so that the corresponding sub-copper layer completely covers the corresponding copper sheet; The molding compound is used to encapsulate the frame, the cascaded GaN HEMT device, and the control chip; the upper surface of the ceramic substrate is exposed outside the molding compound.

2. The GaN encapsulated device according to claim 1, characterized in that, The upper surfaces of the first copper sheet, the second copper sheet, and the third copper sheet are flush with the upper surface of the control chip.

3. The GaN encapsulated device according to claim 1, characterized in that, The first copper sheet, the second copper sheet, and the third copper sheet are all the same size.

4. The GaN encapsulated device according to any one of claims 1 to 3, characterized in that, The lower surface of the ceramic substrate is also provided with a second copper layer corresponding to the control chip.

5. The GaN encapsulated device according to claim 4, characterized in that, The first base island is provided with a first trench corresponding to the SiMOSFET, and the second base island is provided with a second trench corresponding to the GaN HEMT.

6. The GaN encapsulated device according to claim 5, characterized in that, The upper surface of the Si MOSFET is flush with the upper surface of the frame.

7. The GaN encapsulated device according to claim 5, characterized in that, The Si MOSFET is disposed in the first tank using conductive adhesive, and the GaN HEMT is disposed in the second tank using conductive adhesive.

8. The GaN encapsulated device according to claim 4, characterized in that, The first copper layer is disposed on top of the cascaded GaN HEMT device using conductive adhesive, and the second copper layer is disposed on top of the control chip using conductive adhesive.

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