Semiconductor device fabrication method

Abstract

The application discloses a semiconductor device manufacturing method, which comprises the following steps: providing a semiconductor substrate; forming a well region and a gate region on the semiconductor substrate; forming a local doping region on the surface of the well region near both sides of the gate region; etching the well region; forming a groove on both sides of the gate region; and forming an embedded epitaxial layer in the groove. By optimizing the growth process of the embedded epitaxial layer, the surface of the well region on both sides of the gate region is doped by ion implantation to form a local doping region before the trench is formed, the local doping region can reduce the side etching of the upper opening position of the trench during the growth of the embedded epitaxial layer, and the performance of the semiconductor device is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor-related technologies, and in particular to a method for fabricating a semiconductor device. Background Technology

[0002] As integrated circuits continue to evolve towards smaller linewidths, higher carrier mobility is required to improve device performance. Embedding SiGe strained material in the source and drain regions of PMOS transistors can achieve this. <110> Compressive stress is generated in the channel along the crystal orientation, thereby increasing the migration rate of carriers in the channel. In addition, the shape of the trench in the PMOS source and drain regions has changed from U-shaped to a diamond-shaped profile, that is, embedding SiGe strained material in the diamond-shaped trench is more conducive to stress concentration in the channel direction.

[0003] The current method of embedding SiGe strain material in source / drain trenches typically employs epitaxial growth technology. However, this epitaxial growth process requires a pre-cleaning step of the trench before the SiGe strain material is epitaxially grown inside and outside the trench. Unfortunately, the pre-cleaning step during epitaxial growth can lead to varying degrees of over-etching on the sides of the upper opening of the diamond-shaped trench, thus affecting the performance of the semiconductor device.

[0004] Therefore, how to provide a novel semiconductor device fabrication method that can reduce the side etching of the upper opening position of the diamond trench during the pre-cleaning step, thereby improving the performance of the semiconductor device, has become an urgent problem to be solved in this field. Summary of the Invention

[0005] The purpose of this application is to provide a semiconductor device fabrication method that improves the performance of the semiconductor device by forming a local doped region between the trench and the gate region to reduce the side etching of the well region at the upper opening position of the trench during the embedded epitaxial layer growth step.

[0006] In a first aspect, embodiments of this application provide a method for fabricating a semiconductor device, which includes the following steps:

[0007] A semiconductor substrate is provided, and a well region and a gate region are formed on the semiconductor substrate;

[0008] Doped ions are implanted into the surface of the well region near both sides of the gate region to form a localized doped region;

[0009] The etched trap region forms trenches on both sides of the gate region, and the locally doped region includes the area between the trench and the gate region and extends below the gate region.

[0010] An epitaxial layer is filled in the trench to form an embedded epitaxial layer, and source and drain doping is performed in the embedded epitaxial layer to form source and drain regions.

[0011] In one possible implementation, the dopant ion implantation type in the localized doped region includes boron or boron difluoride implantation, the dopant ion implantation angle is 0–45°, and the boron doping concentration in the localized doped region ranges from 3E14 to 3E16 atoms / cm². 2 .

[0012] In one possible implementation, prior to the step of etching the well region and forming trenches in the well regions on both sides of the gate region, the following step is further included:

[0013] A hard mask layer is formed on the surface of the well region and the gate region, and the trench formation region is defined by the hard mask layer.

[0014] In one possible implementation, prior to the hard mask layer formation step, doped ions are implanted into the surface of the well region near both sides of the gate region to form a localized doped region.

[0015] Alternatively, after forming the hard mask layer, doped ions are implanted into the surface of the well region near both sides of the gate region to form a localized doped region.

[0016] In one possible implementation, the step of etching the well region and forming trenches in the well regions on both sides of the gate region specifically includes:

[0017] Using a hard mask layer as a mask, the well region is first etched to form a U-shaped groove on both sides of the gate region through self-alignment.

[0018] Using a hard mask layer as a mask, a second trench etching is performed on the groove to increase the volume of the groove and make the groove shape diamond-shaped.

[0019] In one possible implementation, the second trench etching is performed using wet etching with TMAN as the etching solution.

[0020] In one possible implementation, the trench is pre-cleaned before the step of filling the trench with an epitaxial layer to form an embedded epitaxial layer.

[0021] In one possible implementation, the pre-cleaning step involves etching and cleaning the trenches with process gases including SF6 and Cl2.

[0022] In one possible implementation, the SF6 gas flow rate ranges from 1 to 100 sccm, the time of gaseous action is 3 to 30 s, and the time of plasma action is 3 to 30 s; the Cl2 gas flow rate ranges from 1 to 100 sccm, the time of gaseous action is 3 to 30 s, and the time of plasma action is 3 to 30 s.

[0023] In one possible implementation, the embedded epitaxial layer is an embedded SiGe epitaxial layer, and the source and drain regions are P-type doped.

[0024] Compared with the prior art, the beneficial effects of this application are at least as follows:

[0025] This application provides a method for fabricating a semiconductor device, including providing a semiconductor substrate, forming a well region and a gate region on the semiconductor substrate, forming locally doped regions on the surface of the well region near both sides of the gate region, etching the well region, forming trenches on both sides of the gate region, and forming an embedded epitaxial layer within the trenches. By optimizing the growth process of the embedded epitaxial layer, before forming the trenches, doped ions are implanted onto the surface of the well region on both sides of the gate region to form locally doped regions. The locally doped regions can reduce the side etching at the opening position of the trench during the growth of the embedded epitaxial layer, thereby improving the performance of the semiconductor device. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic flowchart illustrating a semiconductor device fabrication method according to an embodiment of this application;

[0028] Figures 2-5 This is a schematic diagram illustrating the structure of a semiconductor device at different fabrication stages according to embodiments of this application;

[0029] Figure 6A This is a cross-sectional view of a diamond-shaped groove structure of a semiconductor device according to an embodiment of the application;

[0030] Figure 6B This is a cross-sectional view of an embedded epitaxial layer structure for a semiconductor device formed according to existing technology;

[0031] Figure 6C This is a cross-sectional view of an embedded epitaxial layer structure for a semiconductor device according to an embodiment of this application.

[0032] Illustration:

[0033] 10 Semiconductor substrate; 20 Well region; 210 Locally doped region; 30 Gate region; 40 Gate insulating layer; 50 Hard mask layer; 60 Trench; 610 U-shaped groove; 620 Diamond groove; 70 Embedded epitaxial layer. Detailed Implementation

[0034] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or operated through other different specific embodiments, and various details in this application can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application.

[0035] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances. Furthermore, the terms "first" and "second," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0036] The mobility of charge carriers in the channel affects the magnitude of the channel current. A decrease in carrier mobility not only reduces the switching speed of the transistor but also reduces the resistance difference between on and off states. For PMOS devices, applying compressive stress in the direction of channel current flow is beneficial to hole mobility; therefore, introducing compressive stress along the channel direction can improve hole mobility in the channel. Embedded silicon-germanium technology was proposed to address the hole mobility issue in PMOS devices. It uses selective epitaxial growth techniques to grow silicon-germanium in the source and drain regions, introducing stress into the channel region. Trenches with a diamond-shaped cross-section are particularly beneficial for stress concentration in the channel direction.

[0037] Selective epitaxial growth techniques typically include a pre-cleaning process for the trenches, such as using plasma formed by introducing SF6 and Cl2 to etch and clean the trenches. However, trenches with a diamond-shaped cross-section may experience uncontrolled over-etching at the upper opening of the trench during the pre-cleaning process, leading to leakage current between the subsequently formed source / drain and gate electrodes, thus degrading the performance of the semiconductor device.

[0038] Analysis suggests that localized boron ion implantation on the sidewalls before trench formation can effectively reduce the etching rate of Si in the trench sidewalls during the pre-cleaning process. The atomic radius of boron is... The atomic radius of silicon is Boron atoms have a smaller radius than silicon atoms; therefore, boron ion doping creates tensile stress in the silicon lattice, thus reducing the silicon etching rate. Furthermore, boron ions react with fluoride and chloride ions (F ions) in the pre-cleaning plasma. - / Cl - The Coulomb repulsion between the two can also inhibit the etching rate of silicon to a certain extent.

[0039] Based on the above analysis, according to one aspect of this application, a method for fabricating a semiconductor device is provided. See also... Figure 1 It includes the following steps:

[0040] S1, a semiconductor substrate 10 is provided, and a well region 20 and a gate region 30 are formed on the semiconductor substrate 10.

[0041] See Figure 2 A semiconductor substrate 10 is provided. In one embodiment, the semiconductor substrate 10 may be a silicon substrate or a silicon-on-insulator substrate. Here, the semiconductor substrate 10 is described using a silicon substrate as an example.

[0042] Ion implantation is performed on the upper region of the semiconductor substrate 10 to form a well region 20. In one embodiment, N-type dopant ions are implanted into the semiconductor substrate 10 to form a well region 20 with N-type dopant ions. The N-type dopant ions can be, for example, phosphorus (P) ions, arsenic (As) ions, or antimony (Sb) ions, and the P-type dopant ions can be, for example, boron (B) ions, boron difluoride (BF2+) ions, gallium (Ga) ions, or indium (In) ions.

[0043] A gate insulating layer 40 is formed on the aforementioned well region 20, and a polysilicon layer is formed on the gate insulating layer 40. The polysilicon layer is etched using photolithography and etching processes to form the gate region 30. In one embodiment, the gate region 30 further includes an oxide layer formed on the sidewalls of the polysilicon, and a nitride layer formed on the oxide layer. The oxide layer is preferably a silicon oxide layer, and the nitride layer is preferably a silicon nitride layer.

[0044] S2, doped ions are implanted into the surface of the well region 20 near both sides of the gate region 30 to form a local doped region 210.

[0045] An ion implantation process is used to dope the surface of the well region 20 near both sides of the gate region 30 to form a localized doped region 210 on the surface of the well region 20. In one embodiment, the dopant ions can be boron (B) ions or boron difluoride (BF2+) ions, the dopant ion implantation angle is 0–45°, and the boron doping concentration in the locally doped region 210 formed after doping ranges from 3E14 to 3E16 atoms / cm². 2 .

[0046] Before or after forming the local doped region 210 in step S2, a hard mask layer 50 is formed on the surfaces of the well region 20 and the gate region 30. The hard mask layer 50 can be used to protect the polysilicon of the gate, preventing it from being affected by the subsequent trench 60 formation process; secondly, by patterning the hard mask layer 50, the formation range of the subsequent trench 60 can be defined. The hard mask layer 50 is preferably a silicon nitride layer.

[0047] In one embodiment, see Figure 3A The surface of the well region 20 near both sides of the gate region 30 is ion-doped to form a locally doped region 210 on the surface of the well region 20. Then, a hard mask layer 50 is formed on the surface of the well region 20 (including the locally doped region 210) and the gate region 30. In another embodiment, see... Figure 3B A hard mask layer 50 is formed on the surface of the well region 20 and the gate region 30 before the local doped region 210. Then, the surface of the well region 20 near both sides of the gate region 30 is ion-doped with the hard mask layer 50 in between to form the local doped region 210.

[0048] S3, etch the trap region 20, form trenches 60 on both sides of the gate region 30, and the locally doped region 210 includes the area between the trenches 60 and the gate region 30 and extends below the gate region.

[0049] See Figures 4A-4B The trench 60 can be formed using processes known in the art, such as dry etching, wet etching, or a combination of dry and wet etching. The depth of the trench 60 can be determined based on the required depth of the source and drain regions. The shape of the trench 60 can be, but is not limited to, diamond-shaped, and can also be designed as a rectangle, inverted trapezoid, or other shapes as needed.

[0050] In one embodiment, the etched trench 60 is diamond-shaped, i.e., the industry-recognized "∑" shape. It should be noted that diamond-shaped means that the cross-section of the trench 60 has a shape similar to that of a diamond. The specific steps for forming the diamond-shaped groove 620 are as follows: First, the patterned hard mask layer 50 is etched for the first time to form a U-shaped groove 610 in the well region 20; then, the U-shaped groove 610 is etched for the second time to expand the volume of the U-shaped groove 610, forming a diamond-shaped groove 620 with a diamond cross-section. The sidewall of the diamond-shaped groove 620 near the gate region 30 is a locally doped region 210.

[0051] In one embodiment, the first etching is dry etching, and the second etching is wet etching. The etchant used for wet etching is selective for crystal orientation; for example, an etchant containing tetramethylammonium hydroxide (TMAN) is used to initiate etching from within the U-shaped groove 610 provided by the dry etching process. <111> The etching rate of the crystal orientation is lower than that of other crystal orientations, so that the U-shaped groove 610 is etched into a diamond-shaped groove 620.

[0052] S4, fill the trench 60 with an epitaxial layer to form an embedded epitaxial layer 70, and perform source and drain doping in the embedded epitaxial layer 70 to form source and drain regions.

[0053] See Figure 5An embedded epitaxial layer 70 is formed within the diamond-shaped groove 620 using epitaxial growth techniques, including high-vacuum chemical vapor deposition, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, rapid thermal chemical vapor deposition, or molecular beam epitaxy. In one embodiment, the embedded epitaxial layer 70 is formed using high-vacuum chemical vapor deposition. The embedded epitaxial layer 70 can be an embedded SiGe epitaxial layer, and the source and drain regions can be P-type doped.

[0054] The epitaxial growth process also includes a pre-cleaning process for the trench 60. In one embodiment, the pre-cleaning process involves etching and cleaning the trench 60 with process gases containing SF6 and Cl2, wherein the SF6 gas flow rate ranges from 1 to 100 sccm, the gaseous action time is 3 to 30 seconds, and the plasma action time is 3 to 30 seconds; the Cl2 gas flow rate ranges from 1 to 100 sccm, the gaseous action time is 3 to 30 seconds, and the plasma action time is 3 to 30 seconds.

[0055] It is important to note that the typical pre-cleaning process can cause over-etching of the Si on the sidewalls of the diamond-shaped trench 620, especially the sidewalls near the gate region 30. Over-etching of the sidewalls of the diamond-shaped trench 620 can lead to leakage in the gate region 30, affecting device performance. Before forming the trench 60, boron ion doping is performed on the surface of the well region 20 near the gate region 30 to form a localized doped region 210, which can effectively reduce over-etching of the sidewalls of the diamond-shaped trench 620 near the gate region 30 during the pre-cleaning process. (See Figure 6.) Figure 6A This is a structural diagram of the diamond-shaped groove 620 before the pre-cleaning step. Figure 6B The diagram shows an embedded SiGe epitaxial layer structure formed using existing technology. The Si over-etching amount near the gate region 30 is... Figure 6C This is a diagram of the embedded SiGe epitaxial layer structure formed in an embodiment of this application. The Si over-etching amount near the gate region 30 is... Compared with the prior art, the sidewall Si over-etching of the embedded SiGe epitaxial layer in the embodiment of this application is reduced by more than 50%.

[0056] Preferably, before step S3, i.e., before the etching process, the locally doped region 210 should include not only the area between the trench 60 and the gate region 30, but also the area enclosed by the top opening of the trench 60, thereby providing complete protection for the opening edge of the subsequent diamond-shaped recess 620. The locally doped region 210 located within the area enclosed by the opening of the trench 60 will be partially removed during the first etching and subsequent pre-cleaning of the trench 60, thus not affecting the device performance. The locally doped region 210 located around the outer edge of the top opening of the diamond-shaped recess 620 is then retained. It should be understood that, in this case, for the final device structure, the locally doped region 210 should also include the entire top opening area of ​​the diamond-shaped recess 620, and not just the area between the trench and the gate region.

[0057] As can be seen from the above technical solutions, the semiconductor device fabrication method provided in this application includes providing a semiconductor substrate, forming a well region and a gate region on the semiconductor substrate, forming locally doped regions on the surface of the well region near both sides of the gate region, etching the well region, forming trenches on both sides of the gate region, and forming an embedded epitaxial layer in the trenches. By optimizing the growth process of the embedded epitaxial layer, before forming the trench, doped ions are implanted onto the surface of the well region on both sides of the gate region to form locally doped regions. The locally doped regions can reduce the side etching and cleaning of the upper opening position of the trench before the growth of the embedded epitaxial layer, thereby improving the performance of the semiconductor device.

[0058] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and substitutions can be made without departing from the technical principles of this application, and these improvements and substitutions should also be considered within the scope of protection of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A semiconductor substrate is provided, and a well region and a gate region are formed on the semiconductor substrate; Doped ions are implanted into the surface of the well region near both sides of the gate region to form a localized doped region; The well region is etched to form trenches on both sides of the gate region. The locally doped region includes the area between the trench and the gate region and extends below the gate region. The trench is pre-cleaned, and the locally doped region is used to reduce the etching of the upper opening position of the trench during the cleaning process. An epitaxial layer is filled in the trench to form an embedded epitaxial layer, and source and drain doping is performed in the embedded epitaxial layer to form source and drain regions.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The dopant ion implantation type of the localized doped region includes boron or boron difluoride implantation, with an implantation angle of 0~45°, and the boron doping concentration in the localized doped region ranges from 3E14 to 3E16 atoms / cm². 2 .

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, Before the step of etching the well region and forming trenches in the well regions on both sides of the gate region, the method further includes the following step: A hard mask layer is formed on the surface of the well region and the gate region, and the trench formation region is defined by the hard mask layer.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, Prior to the step of forming the hard mask layer, doped ions are implanted into the surface of the well region near both sides of the gate region to form a localized doped region; Alternatively, after the step of forming the hard mask layer, doped ions are implanted into the surface of the well region near both sides of the gate region to form a localized doped region.

5. The method for fabricating a semiconductor device according to any one of claims 3 to 4, characterized in that, The step of etching the well region and forming trenches in the well regions on both sides of the gate region specifically includes: Using the hard mask layer as a mask, the well region is first etched to form a U-shaped groove on both sides of the gate region through self-alignment. Using the hard mask layer as a mask, a second trench etching is performed on the groove to increase the volume of the groove and make the groove shape diamond-shaped.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The second trench etching is performed using wet etching, with TMAN as the etching solution.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The pre-cleaning step involves using process gases including SF6 and Cl2 to etch and clean the trench.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, The SF6 gas flow rate ranges from 1 to 100 sccm, with a gaseous action time of 3 to 30 seconds and a plasma action time of 3 to 30 seconds; the Cl2 gas flow rate ranges from 1 to 100 sccm, with a gaseous action time of 3 to 30 seconds and a plasma action time of 3 to 30 seconds.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The embedded epitaxial layer is an embedded SiGe epitaxial layer, and the source and drain regions are P-type doped.

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