Adaptive analog control circuit for high-speed serdes equalization system

Abstract

The application provides a kind of adaptive analog control circuit for high-speed serdes equalization system, comprising error amplifier circuit, sampling signal generation circuit, sample-and-hold circuit;Sampling signal generation circuit, through negative feedback network, circuit sampling signal only appears when the input signal pulse width of high-speed serdes equalization circuit is the longest, so that the adaptive analog control circuit only collects the rising and falling edge information on the signal with the longest pulse width to realize adaptive control function, reduces the response speed requirement of the equalization system to operational amplifier, improves the highest speed that the circuit can support, and at the same time can reduce the power consumption of the circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, and in particular to an adaptive analog control circuit for a high-speed serdes equalization system. BACKGROUND

[0002] In high-speed serdes signal transmission, a serdes equalization circuit is usually required to modulate the serdes signal. With the continuous increase of transmission rate, the response speed of the serdes equalization circuit is required to be higher and higher. The response speed of the conventional design operational amplifier circuit determines the response speed of the serdes equalization circuit, thereby determining the highest transmission rate of the serdes signal, which limits the further improvement of the serdes circuit rate. SUMMARY

[0003] The present application provides an adaptive analog control circuit, which aims to overcome the limitation of the response speed of the operational amplifier on the transmission rate of the serdes signal, so as to improve the highest rate speed that the circuit can support, while reducing the power consumption of the circuit.

[0004] In a first aspect, an adaptive analog control circuit is provided, comprising:

[0005] an error amplifier circuit configured to receive an external equalization circuit signal and generate a standard signal according to the external equalization circuit signal, and generate an error signal by comparing rising and falling edge speeds of the standard signal;

[0006] a sampling signal generation circuit configured to receive the external equalization circuit signal, and not generate a sampling signal when a pulse width of the external equalization circuit signal is less than a preset pulse width, and generate the sampling signal when the pulse width of the external equalization circuit signal is greater than the preset pulse width;

[0007] a sample-and-hold circuit configured to receive the error signal from the error amplifier circuit, and perform sample-and-hold according to the error signal when the sampling signal is received from the sampling signal generation circuit.

[0008] In combination with the first aspect, in some implementations of the first aspect, the sampling signal generation circuit comprises a first operational amplifier, a common-mode adjustment circuit, a first capacitor, a second capacitor, a first NAND gate, a second NAND gate, and an inverter.

[0009] two differential input terminals of the first operational amplifier are connected to two output terminals of the external equalization circuit, respectively, and two differential output terminals of the first operational amplifier are connected to two differential input terminals of the common-mode adjustment circuit, respectively.

[0010] The positive terminal of the differential output terminal of the common mode adjusting circuit is connected with the positive terminal of the first capacitor and the positive terminal of the first NAND gate, the negative terminal of the first capacitor is grounded, the negative terminal of the differential output terminal of the common mode adjusting circuit is connected with the positive terminal of the second capacitor and the negative terminal of the first NAND gate, and the negative terminal of the second capacitor is grounded;

[0011] The output terminal of the first NAND gate is connected with the input terminal of the second NAND gate, another input terminal of the second NAND gate is connected with an external enable signal ENN, the output terminal of the second NAND gate is connected with the input terminal of the inverter and the first input terminal of the sample and hold circuit, the output terminal of the inverter is connected with the second input terminal of the sample and hold circuit, the sample signal is generated when the level of the first input terminal is lower than the level of the second input terminal, and the sample signal is not generated when the level of the second input terminal is lower than the level of the first input terminal;

[0012] The common mode adjusting circuit is configured to switch the charging and discharging states of the first capacitor and the second capacitor according to the differential input of the external equalization circuit, so that one of the first capacitor and the second capacitor receives charging from the common mode adjusting circuit, and the other discharges to the common mode adjusting circuit, the common mode adjusting circuit is configured to make the charging speed of the first capacitor faster than the discharging speed of the first capacitor, and make the charging speed of the second capacitor faster than the discharging speed of the second capacitor.

[0013] In combination with the first aspect, in some implementations of the first aspect, the common mode adjusting circuit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first resistor, and a second resistor.

[0014] The positive terminals of the differential output terminals of the first operational amplifier are respectively connected with the gate terminals of the first PMOS transistor and the third PMOS transistor, the negative terminals of the differential output terminals of the first operational amplifier are respectively connected with the gate terminals of the second PMOS transistor and the fourth PMOS transistor, the source terminals of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are respectively connected with a power supply VCC, the drain terminal of the first PMOS transistor is connected with the drain terminal and the gate terminal of the first NMOS transistor and the gate terminal of the fourth NMOS transistor, the drain terminal of the second PMOS transistor is connected with the drain terminal and the gate terminal of the second NMOS transistor and the gate terminal of the third NMOS transistor, the source terminals of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are respectively grounded, the drain terminal of the third PMOS transistor is connected with the positive terminal of the first capacitor, the positive terminal of the first NAND gate, and the positive terminal of the first resistor, the drain terminal of the fourth PMOS transistor is connected with the positive terminal of the second capacitor, the negative terminal of the first NAND gate, and the positive terminal of the second resistor, the negative terminal of the first resistor is connected with the drain terminal of the third NMOS transistor, and the negative terminal of the second resistor is connected with the drain terminal of the fourth NMOS transistor.

[0015] With reference to the first aspect, in some implementations of the first aspect, the first resistance and the second resistance are 1k-3k Ohms.

[0016] With reference to the first aspect, in some implementations of the first aspect, the width-length ratios of the first PMOS transistor 202, the second PMOS transistor 203, the third PMOS transistor 204, and the fourth PMOS transistor 205 are greater than the width-length ratios of the first NMOS transistor 206, the second NMOS transistor 207, the third NMOS transistor 208, and the fourth NMOS transistor 209.

[0017] With reference to the first aspect, in some implementations of the first aspect, the width-length ratios of the first PMOS transistor 202, the second PMOS transistor 203, the third PMOS transistor 204, and the fourth PMOS transistor 205 are equal to 150-250; and the width-length ratios of the first NMOS transistor 206, the second NMOS transistor 207, the third NMOS transistor 208, and the fourth NMOS transistor 209 are equal to 50-80.

[0018] With reference to the first aspect, in some implementations of the first aspect, the error amplification circuit includes a second operational amplifier, a band-pass network, and an addition amplifier; the output of the external equalization circuit passes through the second operational amplifier to generate the standard waveform, the output of the external equalization circuit and the standard waveform pass through the band-pass network respectively and are output to the addition amplifier, and the addition amplifier is configured to compare the time difference of rising and falling edges of the output of the external equalization circuit and the standard waveform and generate the error signal.

[0019] With reference to the first aspect, in some implementations of the first aspect, the band-pass network includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first resistance, a second resistance, a third resistance, a fourth resistance, a fifth resistance, a sixth resistance, a seventh resistance, an eighth resistance, a ninth resistance, a tenth resistance, and an eleventh resistance.

[0020] The second operational amplifier input end is connected with the positive pole of the third capacitor and the positive pole of the fourth capacitor respectively, and is connected with the output of the external equalization circuit; the output of the second operational amplifier is connected with the positive pole of the first capacitor and the positive pole of the second capacitor respectively; the negative pole of the first capacitor, the negative pole of the second capacitor, the negative pole of the third capacitor and the negative pole of the fourth capacitor are connected with the positive pole of the first resistor, the positive pole of the second resistor, the positive pole of the third resistor and the positive pole of the fourth resistor respectively, the negative pole of the first resistor, the negative pole of the second resistor, the negative pole of the third resistor and the negative pole of the fourth resistor are connected with the positive pole of the fifth resistor, the positive pole of the sixth resistor, the positive pole of the seventh resistor and the positive pole of the eighth resistor respectively, and are connected with the four input ends of the summing amplifier respectively; the positive pole of the ninth resistor is connected with the power supply, and the negative pole is connected with the negative pole of the fifth resistor, the negative pole of the sixth resistor and the positive pole of the tenth resistor; the negative pole of the tenth resistor is connected with the negative pole of the seventh resistor, the negative pole of the eighth resistor and the positive pole of the eleventh resistor; the negative pole of the eleventh resistor is connected with the ground; the output end of the summing amplifier is output to the sample-and-hold circuit.

[0021] In combination with the first aspect, in some implementations of the first aspect, the sample-and-hold circuit includes a fifth PMOS tube, a fifth NMOS tube, a resistor and a capacitor. The gate of the fifth PMOS tube is connected with the output of the sampling signal generation circuit; the source of the fifth PMOS tube is connected with the source of the fifth NMOS tube and the output of the error amplification circuit; the drain of the fifth PMOS tube is connected with the drain of the fifth NMOS tube and the positive end of the resistor; the gate of the fifth NMOS tube is connected with the output of the sampling signal generation circuit; the source of the fifth NMOS tube is connected with the output of the error amplification circuit; the drain of the fifth NMOS tube is connected with the positive end of the resistor; the negative end of the resistor is connected with the positive end of the capacitor and the output end; and the negative end of the capacitor is connected with the ground.

[0022] The second aspect provides a serdes equalization system, which includes the adaptive analog control circuit as described in any one of the implementations of the first aspect.

[0023] Compared with the prior art, the scheme provided by the present application has at least the following beneficial technical effects:

[0024] The present application provides an adaptive analog control circuit for a high-speed serdes equalization system, the working rate of which is 6.25 Gbps, and the sampling signal of the circuit only appears when the pulse width of the input signal of the high-speed serdes equalization circuit is the longest, so that the adaptive analog control circuit only collects the rising and falling edge information on the signal with the longest pulse width to realize the adaptive control function, the response speed requirement of the equalization system to the operational amplifier is reduced, the highest speed rate that the circuit can support is improved, and the power consumption of the circuit is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 The present application provides an adaptive analog control circuit structure diagram.

[0026] Figure 2 The present application provides an error amplification circuit structure diagram.

[0027] Figure 3 A sampling signal generation circuit structure diagram is provided for the present application.

[0028] Figure 4 A sample-and-hold circuit structure diagram is provided for the present application. DETAILED DESCRIPTION

[0029] The present application is described in further detail below in conjunction with the accompanying drawings and specific embodiments.

[0030] Figure 1 A schematic structure diagram of an adaptive analog control circuit is shown according to an embodiment of the present application. The adaptive analog control circuit can be used in a high-speed serdes equalization circuit. The working frequency of the circuit can be, for example, 6.25 Gbps.

[0031] The adaptive analog control circuit can include an error amplifier circuit, a sampling signal generation circuit, and a sample-and-hold circuit. The error amplifier circuit can be used to receive an external equalization circuit signal, compare the rising and falling edge speeds of the signal with a standard signal generated by internal amplification, and generate an error signal output to the sample-and-hold circuit. The sampling signal generation circuit can be used to receive the external equalization circuit signal, not generate a sampling signal when the pulse is narrow (e.g., 1.25 GHz to 3.125 GHz and above), and generate a sampling signal and output it to the sample-and-hold circuit when the pulse is wide (e.g., 1.25 GHz and below). The sample-and-hold circuit can be used to sample and hold the error signal when receiving the sampling signal from the sampling signal generation circuit, and output the result to the external equalization circuit to modulate the equalization circuit and achieve adaptive functionality.

[0032] Figure 2 A schematic structure diagram of an error amplifier circuit is shown according to an embodiment of the present application.

[0033] The error amplifier circuit includes an operational amplifier 101, a bandpass network, and an addition amplifier 107. The bandpass network can be a resistance-capacitance frequency selection network. The working frequency of the bandpass network can be 50 MHz to 3.5 GHz.

[0034] The external equalization circuit output passes through the operational amplifier 101 inside the error amplifier circuit to generate a standard waveform. The external equalization circuit output and the standard waveform pass through the resistance-capacitance frequency selection network and are output to the addition amplifier. The addition amplifier 107 can be used to compare the time difference of the rising and falling edges of the external equalization circuit output and the standard waveform. The addition amplifier 107 can generate an error signal and output it to the sample-and-hold circuit.

[0035] If the rising and falling edge time of the output waveform of the external equalization circuit is longer than that of the standard waveform, the error amplifier circuit outputs a high-level error signal to the sample-and-hold circuit to increase the high-frequency gain of the equalization circuit; if the rising and falling edge time of the output waveform of the external equalization circuit is shorter than that of the standard waveform, the error amplifier circuit outputs a low-level control signal to the sample-and-hold circuit to decrease the high-frequency gain of the equalization circuit.

[0036] In Figure 2 In the embodiment shown, the band-pass network can include a first capacitor 102, a second capacitor 105, a third capacitor 108, a fourth capacitor 111, a first resistor 103, a second resistor 106, a third resistor 109, a fourth resistor 112, a fifth resistor 104, a sixth resistor 107, a seventh resistor 110, an eighth resistor 113, a ninth resistor 114, a tenth resistor 115, and an eleventh resistor 116.

[0037] The input end of the operational amplifier 101 is connected to the positive pole of the third capacitor 108 and the fourth capacitor 111, and the output of the external equalization circuit; the output end of the operational amplifier 101 is connected to the positive pole of the first capacitor 102 and the second capacitor 105; the negative pole of the first capacitor 102, the second capacitor 105, the third capacitor 108, and the fourth capacitor 111 is connected to the positive pole of the first resistor 103, the second resistor 106, the third resistor 109, and the fourth resistor 112, respectively; the negative pole of the first resistor 103, the second resistor 106, the third resistor 109, and the fourth resistor 112 is connected to the positive pole of the fifth resistor 104, the sixth resistor 107, the seventh resistor 110, and the eighth resistor 113, respectively, and is connected to the four input ends of the summing amplifier 117; the positive pole of the ninth resistor 114 is connected to the power supply, and the negative pole is connected to the negative pole of the fifth resistor 104, the negative pole of the sixth resistor 107, and the positive pole of the tenth resistor 115; the negative pole of the tenth resistor 115 is connected to the negative pole of the seventh resistor 110, the negative pole of the eighth resistor 113, and the positive pole of the eleventh resistor 116; the negative pole of the eleventh resistor 116 is connected to the ground; and the output end Vout3 of the summing amplifier 117 is connected to the sample-and-hold circuit.

[0038] Figure 3 A schematic structural diagram of a sampling signal generation circuit is shown.

[0039] The sampling signal generation circuit can include an operational amplifier 201, a common-mode adjustment circuit, a first capacitor 212, a second capacitor 213, a first NAND gate 214, a second NAND gate 215, and an inverter 216.

[0040] The differential input ends of the operational amplifier 201 are connected to the output ends of the external equalization circuit respectively; the differential output ends of the operational amplifier 201 are connected to the differential input ends of the common-mode adjustment circuit respectively, the positive end of the differential output end of the common-mode adjustment circuit is connected to the positive end of the first capacitor 212 and the positive end of the first NAND gate 214, the negative end of the first capacitor 212 is grounded, the negative end of the differential output end of the common-mode adjustment circuit is connected to the positive end of the second capacitor 213 and the negative end of the first NAND gate 214, and the negative end of the second capacitor 213 is grounded.

[0041] The common-mode adjustment circuit is used to switch the charging and discharging states of the first capacitor 212 and the second capacitor 213 according to the differential input of the external equalization circuit, so that one of the first capacitor 212 and the second capacitor 213 receives charging from the common-mode adjustment circuit, and the other discharges to the common-mode adjustment circuit.

[0042] The common-mode adjustment circuit is used to make the charging speed of the first capacitor 212 faster than the discharging speed of the first capacitor 212, and to make the charging speed of the second capacitor 213 faster than the discharging speed of the second capacitor 213. The output end of the first NAND gate 214 is connected to the input end of the second NAND gate 215; the other input end of the second NAND gate 215 is connected to the external enable signal ENN (which can be high level); the output end Vout1 of the second NAND gate 215 is connected to the input end of the inverter 216 and is output to the sample and hold circuit; and the output end Vout2 of the inverter 216 is output to the sample and hold circuit. When the ENN enable signal is low, the circuit output is fixed at high level, and at this time the circuit is in standby state. When the ENN enable signal is high, this part of the circuit is in working state.

[0043] In the case of a narrow pulse input signal, the positive end and the negative end of the differential output end of the common-mode adjustment circuit are used to output the same type of level (for example, both high level), which includes two cases: the positive end of the differential output end of the common-mode adjustment circuit quickly charges the first capacitor 212, so that the positive end of the first capacitor 212 is high level, and the second capacitor 213 slowly discharges to the negative end of the differential output end of the common-mode adjustment circuit for a short time, so that the positive end of the second capacitor 213 is also high level; the first capacitor 212 slowly discharges to the positive end of the differential output end of the common-mode adjustment circuit for a short time, so that the positive end of the first capacitor 212 is high level, and the negative end of the differential output end of the common-mode adjustment circuit quickly charges the second capacitor 213, so that the positive end of the second capacitor 213 is also high level.

[0044] In one possible case of a narrow pulse input signal, since the inputs of the first NAND gate 214 are both high level, the output of the first NAND gate 214 can be low level, and the output of the second NAND gate 215 can be high level, so that the output end Vout1 of the second NAND gate 215 outputs high level, and the output end Vout2 of the inverter 216 outputs low level.

[0045] In the case that the input signal is a relatively wide pulse, the positive terminal and the negative terminal of the differential output end of the common-mode adjusting circuit are used to output different types of levels (high level and low level respectively, in this application, high level is explained as being higher than a preset level, and low level is explained as being lower than the preset level), which specifically includes two cases: the positive terminal of the differential output end of the common-mode adjusting circuit is rapidly charged to the first capacitor 212, so that the positive terminal of the first capacitor 212 is at a high level, and the second capacitor 213 is slowly discharged to the negative terminal of the differential output end of the common-mode adjusting circuit for a long time, so that the positive terminal of the second capacitor 213 is at a low level; the first capacitor 212 slowly discharges to the positive terminal of the differential output end of the common-mode adjusting circuit for a long time, so that the positive terminal of the first capacitor 212 is at a low level, and the negative terminal of the differential output end of the common-mode adjusting circuit is rapidly charged to the second capacitor 213, so that the positive terminal of the second capacitor 213 is at a high level.

[0046] In the case that the input signal is a relatively wide pulse, the positive terminal and the negative terminal of the differential output end of the common-mode adjusting circuit are used to output different types of levels (high level and low level respectively, in this application, high level is explained as being higher than a preset level, and low level is explained as being lower than the preset level), which specifically includes two cases: the positive terminal of the differential output end of the common-mode adjusting circuit is rapidly charged to the first capacitor 212, so that the positive terminal of the first capacitor 212 is at a high level, and the second capacitor 213 is slowly discharged to the negative terminal of the differential output end of the common-mode adjusting circuit for a long time, so that the positive terminal of the second capacitor 213 is at a low level; the first capacitor 212 slowly discharges to the positive terminal of the differential output end of the common-mode adjusting circuit for a long time, so that the positive terminal of the first capacitor 212 is at a low level, and the negative terminal of the differential output end of the common-mode adjusting circuit is rapidly charged to the second capacitor 213, so that the positive terminal of the second capacitor 213 is at a high level.

[0047] In some embodiments, the capacitances of the first capacitor 212 and the second capacitor 213 are 10-20 fF, for example, 13.5 fF.

[0048] In Figure 3 In the embodiment shown, the common-mode adjusting circuit can include a first PMOS tube 202, a second PMOS tube 203, a third PMOS tube 204, a fourth PMOS tube 205, a first NMOS tube 206, a second NMOS tube 207, a third NMOS tube 208, a fourth NMOS tube 209, a first resistor 210, and a second resistor 211. The first resistor 210 and the second resistor 211 can not only help to reduce the discharge rate of the first capacitor 212 and the second capacitor 213, but also help to raise the input level of the first NAND gate 214 in the narrow pulse scenario, i.e., to raise the common-mode voltage output by the third PMOS tube 204 and the fourth PMOS tube 205.

[0049] The positive terminal of the differential output end of the operational amplifier 201 is connected to the gate of the first PMOS tube 202 and the gate of the third PMOS tube 204 respectively; the negative terminal of the differential output end of the operational amplifier 201 is connected to the gate of the second PMOS tube 203 and the gate of the fourth PMOS tube 205 respectively; the source of the first PMOS tube 202, the source of the second PMOS tube 203, the source of the third PMOS tube 204 and the source of the fourth PMOS tube 205 are connected to the power supply VCC respectively; the drain of the first PMOS tube 202 is connected to the drain and the gate of the first NMOS tube 206 and the gate of the fourth NMOS tube 209; the drain of the second PMOS tube 203 is connected to the drain and the gate of the second NMOS tube 207 and the gate of the third NMOS tube 208; the source of the first NMOS tube 206, the source of the second NMOS tube 207, the source of the third NMOS tube 208 and the source of the fourth NMOS tube 209 are connected to the ground GND respectively; the drain of the third PMOS tube 204 is connected to the positive terminal of the first resistor 210, the positive terminal of the first capacitor 212 and the input terminal of the first NAND gate 214; the drain of the fourth PMOS tube 205 is connected to the positive terminal of the second resistor 211, the positive terminal of the second capacitor 213 and the other input terminal of the first NAND gate 214; the negative terminal of the first resistor 210 is connected to the drain of the third NMOS tube 208; the negative terminal of the second resistor 211 is connected to the drain of the fourth NMOS tube 209.

[0050] When the output Vin1 of the external equalization circuit is high level, the output Vin2 of the external equalization circuit is low level, the gate voltage of the first PMOS tube 202 is high level, the first PMOS tube 202 is off, the gate voltage of the third PMOS tube 204 is high level, the third PMOS tube 204 is off, the gate voltage of the fourth PMOS tube 205 is low level, and the fourth PMOS tube 205 is on. Thus the first capacitor 212 can be discharged through the first resistor 210 and the third NMOS tube 208, and the discharge is slowed down due to the existence of the first resistor 210, and the first input terminal of the first NAND gate 214 is high level for a short time. The power supply VCC can charge the second capacitor 213 through the fourth PMOS tube 205, and the other input terminal of the first NAND gate 214 is high level.

[0051] When the output Vin1 of the external equalization circuit is low, the output Vin2 of the external equalization circuit is high, the gate voltage of the second PMOS transistor 203 is high, the second PMOS transistor 203 is off, the gate voltage of the third PMOS transistor 204 is low, the third PMOS transistor 204 is on, and the gate voltage of the fourth PMOS transistor 205 is high, the fourth PMOS transistor 205 is off. Thus, the second capacitor 213 can discharge through the second resistor 211 and the fourth NMOS transistor 209, and the discharge is slowed down due to the second resistor 211, and the second input of the first NAND gate 214 is high for a short time. The power supply VCC can charge the first capacitor 212 through the third PMOS transistor 204, and the first input of the first NAND gate 214 is high.

[0052] In some embodiments, the resistance of the first resistor 210 and the second resistor 211 can be 1k-3k ohms, for example, 2k ohms.

[0053] In some embodiments provided in the present application, the width-length ratio of the first PMOS transistor 202, the second PMOS transistor 203, the third PMOS transistor 204, and the fourth PMOS transistor 205 is greater than that of the first NMOS transistor 206, the second NMOS transistor 207, the third NMOS transistor 208, and the fourth NMOS transistor 209, so that the resistance of the first PMOS transistor 202, the second PMOS transistor 203, the third PMOS transistor 204, and the fourth PMOS transistor 205 can be slightly smaller than that of the first NMOS transistor 206, the second NMOS transistor 207, the third NMOS transistor 208, and the fourth NMOS transistor 209, so as to increase the charging rate of the first capacitor 212 and the second capacitor 213 and reduce the discharging rate of the first capacitor 212 and the second capacitor 213.

[0054] In some embodiments, the width-length ratio of the first PMOS transistor 202, the second PMOS transistor 203, the third PMOS transistor 204, and the fourth PMOS transistor 205 is equal to 150-250, for example, 36 / 0.13; and the width-length ratio of the first NMOS transistor 206, the second NMOS transistor 207, the third NMOS transistor 208, and the fourth NMOS transistor 209 is equal to 50-80, for example, 12 / 0.13.

[0055] Figure 4A schematic structural diagram of a sample-and-hold circuit is shown. The sample-and-hold circuit comprises a PMOS transistor 301, an NMOS transistor 302, a resistor 303, and a capacitor 304. The gate of the PMOS transistor 301 is connected to an output Vout1 of a sample signal generation circuit; the source of the PMOS transistor 301 is connected to the source of the NMOS transistor 302 and an output Vout3 of an error amplifier circuit; the drain of the PMOS transistor 301 is connected to the drain of the NMOS transistor 302 and the positive terminal of the resistor 303; the gate of the NMOS transistor 302 is connected to an output Vout2 of the sample signal generation circuit; the source of the NMOS transistor 302 is connected to the output Vout3 of the error amplifier circuit; the drain of the NMOS transistor 302 is connected to the positive terminal of the resistor 303; the negative terminal of the resistor 303 is connected to the positive terminal and an output terminal Vout of the capacitor 304; and the negative terminal of the capacitor 304 is connected to a ground GND.

[0056] Vout1 and Vout2 are sample signals. When the Vout1 signal changes from high to low, the Vout2 signal changes from low to high, the PMOS transistor 301 and the NMOS transistor 302 are both turned on, the sample-and-hold circuit samples the value of the error signal Vout3, and the sample-and-hold result of the resistor 303 and the capacitor 304 is output to an external equalization circuit to control the gain of the external equalization circuit. If the error signal is high, the gain of the external equalization circuit is increased; if the error signal is low, the gain of the external equalization circuit is decreased. Thus, the gain of the external equalization circuit automatically reaches the best state according to different input signals, and the purpose of adaptive control is achieved. The sample-and-hold circuit samples and holds the output of the error amplifier circuit through the sample signal, and realizes the adaptive control function.

[0057] The output of the external equalization circuit passes through an operational amplifier 201 inside the sample signal generation circuit to generate a standard waveform; and then passes through a resistor-capacitor common-mode modulation network designed to, in a possible scenario, make an NAND gate 215 output a high level only when the serdes code specifies the longest 5-bit continuous 0 or 1 (i.e., when the two inputs of the first NAND gate 214 are low and high, respectively, when the first NAND gate 214 has 5-bit continuous 0 or 1, and when the two inputs of the first NAND gate 214 are the same level when the first NAND gate 214 has 4-bit continuous 0 or 1), and further generate a sample signal. The sample signal is output to the sample-and-hold circuit through Vout1 and Vout2. The sample signal generation circuit can realize output of the sample signal only when the pulse width of the input signal of the high-speed serdes equalization circuit is the longest through a negative feedback network. Therefore, the adaptive analog control circuit provided by the present application can be applied to the response speed of a traditional operational amplifier circuit, realizes the adaptive control function in the case of a wide pulse, reduces the response speed requirement of the equalization system on the operational amplifier, improves the maximum speed that the circuit can support, and reduces the power consumption of the circuit.

[0058] Although the present application is disclosed with reference to the preferred embodiments above, it is not intended to limit the present application, and any person skilled in the art can make possible variations and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application should be defined by the scope of the claims.

Claims

1. An adaptive analog control circuit, characterized by, The application relates to an error amplifier circuit, a sampling signal generation circuit and a sample-and-hold circuit. The error amplifier circuit receives an external equalization circuit signal and generates a standard signal according to the external equalization circuit signal, and generates an error signal by comparing the rising and falling edge speeds of the standard signal. The sampling signal generation circuit receives the external equalization circuit signal, and does not generate a sampling signal when the pulse width of the external equalization circuit signal is less than a preset pulse width, and generates a sampling signal when the pulse width of the external equalization circuit signal is greater than the preset pulse width. The sample-and-hold circuit receives the error signal from the error amplifier circuit, and performs sample-and-hold according to the error signal when the sampling signal is received from the sampling signal generation circuit. The sampling signal generation circuit comprises a first operational amplifier (201), a common-mode adjustment circuit, a first capacitor (212), a second capacitor (213), a first NAND gate (214), a second NAND gate (215) and an inverter (216). Two differential input ends of the first operational amplifier (201) are connected to two output ends of the external equalization circuit, and two differential output ends of the first operational amplifier (201) are connected to two differential input ends of the common-mode adjustment circuit. The positive end of the differential output end of the common-mode adjustment circuit is connected to the positive end of the first capacitor (212) and the positive end of the first NAND gate (214), the negative end of the first capacitor (212) is grounded, the negative end of the differential output end of the common-mode adjustment circuit is connected to the positive end of the second capacitor (213) and the negative end of the first NAND gate (214), and the negative end of the second capacitor (213) is grounded. The output end of the first NAND gate (214) is connected to the input end of the second NAND gate (215), the other input end of the second NAND gate (215) is connected to an external enable signal ENN, the output end of the second NAND gate (215) is connected to the input end of the inverter (216) and the first input end (Vout1) of the sample-and-hold circuit, the output end of the inverter (216) is connected to the second input end (Vout2) of the sample-and-hold circuit, the sampling signal is generated when the level of the first input end (Vout1) is lower than the level of the second input end (Vout2), and the sampling signal is not generated when the level of the second input end (Vout2) is lower than the level of the first input end (Vout1). The common-mode adjustment circuit is used for switching the charging and discharging states of the first capacitor (212) and the second capacitor (213) according to the differential input of the external equalization circuit, so that one of the first capacitor (212) and the second capacitor (213) receives charging from the common-mode adjustment circuit, and the other discharges to the common-mode adjustment circuit, the common-mode adjustment circuit is used for making the charging speed of the first capacitor (212) faster than the discharging speed of the first capacitor (212), and making the charging speed of the second capacitor (213) faster than the discharging speed of the second capacitor (213).

2. The adaptive analog control circuit of claim 1, wherein, The common mode adjusting circuit comprises a first PMOS tube (202), a second PMOS tube (203), a third PMOS tube (204), a fourth PMOS tube (205), a first NMOS tube (206), a second NMOS tube (207), a third NMOS tube (208), a fourth NMOS tube (209), a first resistor (210), and a second resistor (211). The positive terminal of the differential output end of the first operational amplifier (201) is connected to the gate of the first PMOS tube (202) and the gate of the third PMOS tube (204) respectively; the negative terminal of the differential output end of the first operational amplifier (201) is connected to the gate of the second PMOS tube (203) and the gate of the fourth PMOS tube (205) respectively; the source of the first PMOS tube (202), the source of the second PMOS tube (203), the source of the third PMOS tube (204), and the source of the fourth PMOS tube (205) are connected to the power supply VCC respectively; the drain of the first PMOS tube (202) is connected to the drain and the gate of the first NMOS tube (206) and the gate of the fourth NMOS tube (209); the drain of the second PMOS tube (203) is connected to the drain and the gate of the second NMOS tube (207) and the gate of the third NMOS tube (208); the source of the first NMOS tube (206), the source of the second NMOS tube (207), the source of the third NMOS tube (208), and the source of the fourth NMOS tube (209) are connected to the ground GND respectively; the drain of the third PMOS tube (204) is connected to the positive terminal of the first resistor (210), the positive terminal of the first capacitor (212), and the input terminal of the first NAND gate (214); the drain of the fourth PMOS tube (205) is connected to the positive terminal of the second resistor (211), the positive terminal of the second capacitor (213), and the other input terminal of the first NAND gate (214); the negative terminal of the first resistor (210) is connected to the drain of the third NMOS tube (208); and the negative terminal of the second resistor (211) is connected to the drain of the fourth NMOS tube (209).

3. The adaptive analog control circuit of claim 2, wherein, The resistance of the first resistor (210) and the second resistor (211) is 1k-3k ohms.

4. The adaptive analog control circuit of claim 2, wherein, The width-length ratio of the first PMOS tube (202), the second PMOS tube (203), the third PMOS tube (204), and the fourth PMOS tube (205) is greater than the width-length ratio of the first NMOS tube (206), the second NMOS tube (207), the third NMOS tube (208), and the fourth NMOS tube (209).

5. The adaptive analog control circuit of claim 4, wherein, The width-length ratio of the first PMOS tube (202), the second PMOS tube (203), the third PMOS tube (204), and the fourth PMOS tube (205) is equal to 150-250; and the width-length ratio of the first NMOS tube (206), the second NMOS tube (207), the third NMOS tube (208), and the fourth NMOS tube (209) is equal to 50-80.

6. The adaptive analog control circuit of claim 1, wherein, The error amplifier circuit comprises a second operational amplifier (101), a band-pass network and an addition amplifier (117); the output of the external equalization circuit generates the standard signal through the second operational amplifier (101), and the output of the external equalization circuit and the standard signal are respectively output to the addition amplifier (117) through the band-pass network, and the addition amplifier (117) is used for comparing the time difference of rising and falling edges of the output of the external equalization circuit and the standard signal, and generating the error signal.

7. The adaptive analog control circuit of claim 6, wherein, The band-pass network comprises a third capacitor (102), a fourth capacitor (105), a fifth capacitor (108), a sixth capacitor (111), a third resistor (103), a fourth resistor (106), a fifth resistor (109), a sixth resistor (112), a seventh resistor (104), an eighth resistor (107), a ninth resistor (110), a tenth resistor (113), an eleventh resistor (114), a twelfth resistor (115) and a thirteenth resistor (116); The input end of the second operational amplifier (101) is connected to the positive poles of the fifth capacitor (108) and the sixth capacitor (111) respectively, and is connected to the output of the external equalization circuit; the output end of the second operational amplifier (101) is connected to the positive poles of the third capacitor (102) and the fourth capacitor (105) respectively; the negative poles of the third capacitor (102), the fourth capacitor (105), the fifth capacitor (108) and the sixth capacitor (111) are connected to the positive poles of the third resistor (103), the fourth resistor (106), the fifth resistor (109) and the sixth resistor (112) respectively, and the negative poles of the third resistor (103), the fourth resistor (106), the fifth resistor (109) and the sixth resistor (112) are connected to the positive poles of the seventh resistor (104), the eighth resistor (107), the ninth resistor (110) and the tenth resistor (113) respectively, and are connected to the four input ends of the addition amplifier (117) respectively; the positive pole of the eleventh resistor (114) is connected to a power supply, and the negative pole is connected to the negative poles of the seventh resistor (104), the eighth resistor (107) and the positive pole of the twelfth resistor (115); the negative pole of the twelfth resistor (115) is connected to the negative poles of the ninth resistor (110), the tenth resistor (113) and the positive pole of the thirteenth resistor (116); the negative pole of the thirteenth resistor (116) is connected to a ground; and the output end (Vout3) of the addition amplifier (117) is output to a sample-and-hold circuit.

8. The adaptive analog control circuit of claim 1, wherein, The sample-and-hold circuit comprises a fifth PMOS tube (301), a fifth NMOS tube (302), a fourteenth resistor (303) and a seventh capacitor (304). The fifth PMOS tube (301) gate is connected with the first output end (Vout1) of the sampling signal generating circuit; the fifth PMOS tube (301) source is connected with the source of the fifth NMOS tube (302) and the output end (Vout3) of the error amplifier circuit; the fifth PMOS tube (301) drain is connected with the drain of the fifth NMOS tube (302) and the positive end of the fourteenth resistance (303); the fifth NMOS tube (302) gate is connected with the second output end (Vout2) of the sampling signal generating circuit; the fifth NMOS tube (302) source is connected with the output end (Vout3) of the error amplifier circuit; the fifth NMOS tube (302) drain is connected with the positive end of the fourteenth resistance (303); the negative end of the fourteenth resistance (303) is connected with the positive end of the seventh capacitance (304) and the output end; the negative end of the seventh capacitance (304) is connected with the ground.

9. An adaptive analog control circuit, characterized by Comprise: an error amplifier circuit for receiving an external equalization circuit signal and generating a standard signal according to the external equalization circuit signal, and generating an error signal by comparing the rising and falling edge speeds of the standard signal; a sampling signal generating circuit for receiving the external equalization circuit signal, not generating a sampling signal when the pulse width of the external equalization circuit signal is less than a preset pulse width, and generating a sampling signal when the pulse width of the external equalization circuit signal is greater than the preset pulse width; a sample and hold circuit for receiving the error signal from the error amplifier circuit, and performing sample and hold according to the error signal when the sampling signal is received from the sampling signal generating circuit; the error amplifier circuit comprises a second operational amplifier (101), a band-pass network and an addition amplifier (117); the output of the external equalization circuit passes through the second operational amplifier (101) to generate the standard signal, and the output of the external equalization circuit and the standard signal pass through the band-pass network and output to the addition amplifier (117) respectively, the addition amplifier (117) is used for comparing the rising and falling edge time differences of the output of the external equalization circuit and the standard signal, and generating the error signal; the band-pass network comprises a third capacitance (102), a fourth capacitance (105), a fifth capacitance (108), a sixth capacitance (111), a third resistance (103), a fourth resistance (106), a fifth resistance (109), a sixth resistance (112), a seventh resistance (104), an eighth resistance (107), a ninth resistance (110), a tenth resistance (113), an eleventh resistance (114), a twelfth resistance (115) and a thirteenth resistance (116); The second operational amplifier (101) is connected with the positive poles of the fifth capacitor (108) and the sixth capacitor (111) respectively, and is connected with the output of the external equalization circuit; the output of the second operational amplifier (101) is connected with the positive poles of the third capacitor (102) and the fourth capacitor (105) respectively; the negative poles of the third capacitor (102), the fourth capacitor (105), the fifth capacitor (108) and the sixth capacitor (111) are connected with the positive poles of the third resistor (103), the fourth resistor (106), the fifth resistor (109) and the sixth resistor (112) respectively, the negative poles of the third resistor (103), the fourth resistor (106), the fifth resistor (109) and the sixth resistor (112) are connected with the positive poles of the seventh resistor (104), the eighth resistor (107), the ninth resistor (110) and the tenth resistor (113) respectively, and are connected with the four input terminals of the summing amplifier (117) respectively; the positive pole of the eleventh resistor (114) is connected with the power supply, the negative pole is connected with the negative poles of the seventh resistor (104) and the eighth resistor (107), and is connected with the positive pole of the twelfth resistor (115); the negative pole of the twelfth resistor (115) is connected with the negative poles of the ninth resistor (110) and the tenth resistor (113), and is connected with the positive pole of the thirteenth resistor (116); the negative pole of the thirteenth resistor (116) is connected with the ground; the output terminal (Vout3) of the summing amplifier (117) is connected with the sample and hold circuit.

10. A serdes equalization system, comprising: The serdes equalization system includes the adaptive analog control circuit of any one of claims 1-9.

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