Multi-port multi-domain time synchronization chip and method

Abstract

The application provides a multi-port multi-domain time synchronization chip and method. The chip comprises a CPU and a protocol software module, which is used for determining time deviation according to the transmission time of protocol messages in each time domain and time correction domains; a message forwarding circuit, which is used for forwarding the protocol messages in each time domain between each port and between each port and the CPU; a central timing node module, which is used for providing a reference time, receiving time deviation of each time domain, and adjusting the reference time to synchronize the time of each time domain with a master clock in a network; and a plurality of port modules, which are used for receiving the reference time and the time deviation of each time domain, and synchronizing the time of each time domain of the port. The application does not need to set PTP / gPTP timing information and calibration information of each port of each domain according to the time synchronization result of each domain PTP / gPTP protocol, but only needs to configure the related information in a central timing node, so that each port in the chip can be accurately timed in real time.

Description

Technical Field

[0001] This invention relates to the technical field of electronic device upgrades, and more particularly to multi-port multi-domain time synchronization chips and methods, computing devices, and computer-readable storage media. Background Technology

[0002] Precision time synchronization protocols such as IEEE 1588 (Precision Timing Protocol, PTP) or IEEE 8021.AS (General Precision Time Protocol, gPTP) are used for precise time synchronization among multiple network devices in a network.

[0003] Existing network devices generally only support a single PTP / gPTP time domain and lack support for multiple time domains. Current network chips provide independent timing and calibration registers for each port's timing and calibration control. During runtime, the PTP / gPTP protocol software needs to manually set these registers for each port to perform register timing and calibration control. In scenarios with many ports, this results in complex software and a high software workload. Because each port has its own independent timing and calibration circuits and registers, each port has a corresponding circuit instance, increasing the circuit size and chip area. Summary of the Invention

[0004] In view of the above problems of the prior art, this application provides a multi-port multi-domain time synchronization chip to solve the problem that each port independently sets timing and calibration circuits and registers, and each port has a corresponding circuit instance, which increases the scale of the circuit and the area of ​​the chip.

[0005] To achieve the above objectives, the first aspect of this application provides a multi-port, multi-domain time synchronization chip, comprising:

[0006] The CPU and protocol software module are used to determine the time deviation based on the transmission and reception time of protocol messages in each time domain and the time correction domain.

[0007] The message forwarding circuit is used to forward protocol messages in each time domain between ports and between ports and the CPU.

[0008] The central timing node module is used to provide a reference time, receive the time deviations of each time domain sent by the CPU and protocol software module, and adjust the reference time to synchronize the time of each time domain with the master clock in the network.

[0009] Multiple port modules are used to receive the reference time and the time deviation of each time domain provided by the central timing node module, and to synchronize the time of each time domain of the port.

[0010] This application does not require setting the PTP / gPTP timing and calibration information for each port individually based on the time synchronization results of each domain's PTP / gPTP protocol. Instead, it only requires configuration at a central timing node, allowing each port in the chip to keep accurate time in real time.

[0011] To achieve the above objectives, a second aspect of this application provides a multi-port, multi-domain time synchronization method, comprising:

[0012] The message forwarding circuit forwards protocol messages in each time domain between ports and between ports and the CPU.

[0013] The CPU and protocol software modules determine the time deviation based on the transmission and reception time and time correction domain of the protocol messages in each time domain.

[0014] The central timing node module provides a reference time, receives the time deviations of each time domain sent by the CPU and protocol software module, and adjusts the reference time to synchronize the time of each time domain with the master clock in the network.

[0015] Multiple port modules receive the reference time and the time deviation of each time domain provided by the central timing node module, and perform time synchronization of each time domain of the port.

[0016] This application does not require setting the PTP / gPTP timing and calibration information for each port individually based on the time synchronization results of each domain's PTP / gPTP protocol. Instead, it only requires configuration at a central timing node, allowing each port in the chip to keep accurate time in real time.

[0017] A third aspect of this application provides a computing device, comprising:

[0018] Communication interface;

[0019] At least one processor connected to the communication interface; and

[0020] At least one memory, connected to the processor and storing program instructions, which, when executed by the at least one processor, cause the at least one processor to perform any of the methods described in the first aspect above.

[0021] A fourth aspect of this application provides a computer-readable storage medium having program instructions stored thereon, which, when executed by a computer, cause the computer to perform any of the methods described in the first aspect above.

[0022] These and other aspects of the invention will become more apparent from the following description of several embodiments. Attached Figure Description

[0023] The various features of the present invention and the relationships between them are further explained below with reference to the accompanying drawings. The drawings are exemplary; some features are not shown to scale, and some drawings may omit conventional features in the field of this application that are not essential to this application, or additional features that are not essential to this application may be shown. The combination of features shown in the drawings is not intended to limit the present application. Furthermore, throughout this specification, the same reference numerals refer to the same things. Specific descriptions of the drawings are as follows:

[0024] Figure 1 A schematic diagram of the structure of an embodiment of the multi-port multi-domain time synchronization chip provided in this application;

[0025] Figure 2 A schematic diagram of the structure of an embodiment of the single-port multi-domain time synchronization chip provided in this application;

[0026] Figure 3 This is a schematic diagram of the computing device used in this application. Detailed Implementation

[0027] The terms "first, second, third, etc." or similar terms such as module A, module B, module C, etc., used in the specification and claims are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that a specific order or sequence may be interchanged where permitted so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0028] In the following description, the labels of the steps, such as S110, S120, etc., do not necessarily mean that the steps will be executed in this way. The order of the steps can be interchanged or executed simultaneously if permitted.

[0029] The term "comprising" as used in the specification and claims should not be construed as limiting itself to what follows; it does not exclude other elements or steps. Therefore, it should be interpreted as specifying the presence of the mentioned feature, integral, step, or component, but does not exclude the presence or addition of one or more other features, integrals, steps, or components, or groups thereof. Thus, the statement "device comprising means A and B" should not be limited to a device consisting solely of components A and B.

[0030] The term "an embodiment" or "an embodiment" as used in this specification means that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in at least one embodiment of the invention. Therefore, the terms "in one embodiment" or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment, but may refer to the same embodiment. Furthermore, in one or more embodiments, the particular features, structures, or characteristics can be combined in any suitable manner, as will be apparent to those skilled in the art from this disclosure.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. In case of any inconsistency, the meaning set forth in this specification or derived from the content described herein shall prevail. Furthermore, the terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application. To accurately describe the technical content of this application and to accurately understand the invention, the following explanations or definitions of the terms used in this specification are provided before describing specific embodiments:

[0032] 1. Ordinary Clock (OC): In IEEE 1588, an OC is a single-port device. The OC's port can participate in the election of the Grand Master clock in the network. After the Grand Master is elected, all OC devices belonging to a network within a time domain eventually synchronize with the Grand Master for that domain. An OC corresponds to an End System in IEEE 802.1AS, and it is a single-port device.

[0033] 2. Boundary Clock (BC): In IEEE 1588, the BC is a multi-port device. The BC's ports participate in the election of the Grand Master clock within the network. After the Grand Master is elected, all BC devices belonging to a given time domain eventually synchronize with that domain's Grand Master. The BC corresponds to the relay system in IEEE 802.1AS, and is also a multi-port device.

[0034] 3. Transparent Clock (TC): In IEEE 1588, the TC is a multi-port device. TCs are further divided into end-to-end (E2E) and peer-to-peer (P2P) types. The TC device connects to the ports of various Open Controller (OC) or Base Controller (BC) devices in the network, providing a data forwarding channel. When sending and receiving PTP protocol event-type messages, the TC device must accurately design stamp information to calculate the dwell time of the protocol message within the TC device (the protocol message forwarding delay within the TC device) and related link delays. The TC corresponds to the Relay System in IEEE 802.1AS, and it is a multi-port device.

[0035] Precise time synchronization in a network requires support for multiple time synchronization domains, each with its own GrandMaster. Ports of devices (OC, BC, TC) in the network can belong to multiple time synchronization domains. Each device port needs to process the sampling of timestamps for event-type protocol messages within multiple time synchronization domains and handle protocol message processing. However, existing network devices generally only support a single PTP / gPTP time domain and lack support for multiple time domains. Based on this, this application provides a multi-port, multi-domain time synchronization chip and method, supporting multi-port chips (TC or BC). With this implementation, the precise time synchronization protocol software does not need to individually set the PTP / gPTP timing and calibration information for each port based on the time synchronization results of each PTP / gPTP protocol domain. Instead, it only needs to perform the relevant configuration at a central timing node, allowing each port in the chip to accurately keep time in real time.

[0036] This application can be applied to any type of switching chip.

[0037] [Example of a multi-port, multi-domain time synchronization chip]

[0038] Figure 1 This is a schematic diagram of the structure of an embodiment of the multi-port multi-domain time synchronization chip provided in this application. The following refers to... Figure 1 The first embodiment of multi-port multi-domain time synchronization of this application will be introduced.

[0039] This multi-port, multi-domain time synchronization chip includes:

[0040] The CPU and protocol software module are used to determine the time deviation based on the transmission and reception time of protocol messages in each time domain and the time correction domain.

[0041] The message forwarding circuit is used to forward protocol messages in each time domain between ports and between ports and the CPU.

[0042] The central timing node module is used to provide a reference time, receive the time deviations of each time domain sent by the CPU and protocol software module, and adjust the reference time to synchronize the time of each time domain with the master clock in the network.

[0043] Multiple port modules are used to receive the reference time and the time deviation of each time domain provided by the central timing node module, and to synchronize the time of each time domain of the port.

[0044] In some embodiments, the message forwarding circuit forwards data packets and protocol packets (including PTP / gPTP protocol packets) between service ports. The message forwarding circuit can also redirect or forward data packets or protocol packets received by each service port to the CPU (port) or copy packets to the CPU (port).

[0045] In some embodiments, the CPU and protocol software modules can directly obtain the transmission and reception times of protocol messages from multiple port modules. Alternatively, they can access multiple port modules through register access paths to obtain the transmission and reception times of protocol messages from these port modules. Register access paths provide access for the CPU to access the registers or RAM entries of various modules within the chip.

[0046] Based on this, such as Figure 1 As shown, the multi-port multi-domain time synchronization chip further includes: a register access path for accessing and reading the transmission and reception times of protocol messages from the port module and providing them to the CPU and protocol software module; and accessing the central timing node module to write the time deviation into the central timing node module.

[0047] In some embodiments, such as Figure 1 As shown, the CPU and protocol software module include a multi-time domain clock analysis and synchronization processing unit, a multi-time domain protocol message transmission and reception driver unit, and a chip configuration management driver unit.

[0048] The multi-time-domain clock analysis and synchronization processing unit is used to: determine the time deviation based on the transmission and reception time and time correction domain of the protocol messages in each time domain;

[0049] The protocol message transmission and reception driver unit is used to drive the message forwarding circuit to realize the reception and transmission of protocol messages in each time domain between ports and between ports and CPU.

[0050] The chip configuration management driver unit is used to drive the register access path to access the port module and the central timing node module.

[0051] The chip configuration management driver unit is also used to configure the reference time for the central timing node module.

[0052] In this embodiment, the multi-time-domain clock analysis and synchronization processing unit, i.e., the multi-domain PTP / gPTP protocol software, runs on the CPU and periodically or as needed receives and sends protocol messages through the message forwarding circuit, sending them to other devices through ports. The PTP / gPTP protocol software parses the received protocol messages (which may carry the sending timestamp of the previous-level device's output port), reads the receiving timestamp of event-type messages at the input port (attached to the end of the protocol message at the input port, forwarded to the CPU via the message forwarding circuit, or reads the receiving timestamp of the event message through the register access path), and reads the sending timestamp of the protocol message at the output port through the register access path. The PTP / gPTP protocol, through the message sending and receiving timestamp information of the network node (this chip) and other network nodes (other chips), and the time correction field (correlation field) carried in the protocol message generated by the TC device, can calculate the time offset (using a known method) of the network node relative to the previous hop BC node or Grand Master node in each time domain. Each domain PTP / gPTP sets a central timing node based on its local time offset and calibrates the local time deviation of the central timing node. The time deviation is then sent to the central timing node module for time adjustment. This hardware-based adjustment is performed by the central timing node module. Simultaneously, the CPU and protocol software modules also need to adjust the reference time recorded in their respective modules based on the time deviation; this software-based adjustment is the primary time adjustment.

[0053] The CPU and protocol software module controls the central timing node module to perform time calibration through software. The CPU and protocol software only includes one operating load, namely the central timing node module, and does not include multiple port modules. This results in a low operating load for the software, which can reduce the operating cost of the CPU and protocol software.

[0054] In some embodiments, such as Figure 1 As shown, the central timing node module includes timing control and calibration circuits for multiple time domains (domain 0 to domain N). Each timing control and calibration circuit includes: timing control and register, calibration control and register, and time loading and storage control and register.

[0055] The timing control and register are used for: timing control and storage based on the reference time;

[0056] The calibration control and register are used to: store the time deviation, and control the timing control and register to adjust the reference time according to the time deviation to synchronize the time of each time domain with the master clock in the network;

[0057] The time loading storage control and register is used to: load the reference time into the timing control and register, and load the time deviation into the calibration control and register.

[0058] The time loading storage control and register is also used to: store a snapshot of the current time stored in the timing control and register.

[0059] In this embodiment, the timing control and register includes a timing control circuit and a timing register. The timing control circuit controls the timing register to perform timing, and the timing register accumulates the timing time every clock cycle according to the chip's operating clock frequency (for example, if the operating clock frequency is 500MHz, the timing accumulates 2ns per clock cycle). That is, the timing register provides the network reference clock for the switching chip.

[0060] In this embodiment, the calibration control and register includes a calibration control circuit and a calibration register. The calibration register stores the time deviation. The calibration control circuit sends control signal pulses to the timing control circuit of the timing control and register. The control signal pulses include an enable control adjust_en and a direction control adjust_dir. When adjust_en is valid, adjust_dir is 0 or 1, and the clock cycle timing register stops accumulating once (deducting time). When adjust_dir is 1 or 0, the clock cycle timing register accumulates the time of two clock cycles (taking a main frequency of 500MHz as an example, the clock cycle timing accumulates by 4ns, increasing the time).

[0061] Based on this, the calibration control and register proposed in this application is specifically used to: send control signal pulses to the timing control and register, the control signal pulses including enable control signal pulses and direction control signal pulses (i.e., used to determine whether the calibration time is increased or decreased), when the enable control signal pulse is valid and the direction control signal pulse is a first preset value (0 or 1), then the timing register in the timing control and register is controlled to stop accumulating a first preset number of times, and when the enable control signal pulse is valid and the direction control signal pulse is a second preset value (1 or 0), then the timing register in the timing control and register is controlled to accumulate a second preset number of times.

[0062] In this embodiment, the time load / store control and register, also known as the time load / store control and register, includes a time load circuit and a load register, and a time store circuit and a store register. The time load circuit can be configured by external input or by the PTP / gPTP software in the chip configuration management driver unit of the CPU and protocol software module to load the time value into the load register. Then, the time load circuit controls the timing control circuit in the timing control and register to receive the time value stored in the load register and store it in the timing register. The time store circuit can be triggered by external signals or set by the PTP / gPTP software in the chip configuration management driver unit of the CPU and protocol software module, taking a snapshot of the current time in the timing register and storing it in the store register before outputting it.

[0063] In some embodiments, such as Figure 1 As shown, the multi-port multi-domain time synchronization chip further includes: a time information input / output interface, used to load the set reference time into the time loading storage control and register; and to output the current time after the snapshot, i.e., the time of the current timing register stored in the store register.

[0064] Specifically, the time information input / output interface outputs a time value.

[0065] In some embodiments, such as Figure 1 As shown, the timing control and calibration circuits in each time domain also include: a synchronization pulse input / output circuit;

[0066] The multi-port multi-domain time synchronization chip also includes: an inter-chip timing synchronization pulse input / output interface;

[0067] The synchronization pulse input / output circuit receives external synchronization pulse signals through the inter-chip timing synchronization pulse input / output interface and resets the timing register in the timing control register (to a specified initial value); the synchronization pulse input / output circuit outputs synchronization pulse signals to the outside of the chip through the inter-chip timing synchronization pulse input / output interface.

[0068] Specifically, the synchronization pulse input / output circuit outputs a synchronization pulse signal to the external chip (i.e., the external switching chip) at a specified time based on the configuration and timing register values. The configuration refers to setting the timing of the output synchronization pulse signal; the output is a synchronization pulse signal used to prompt the external switching chip to start timing from the time it receives this synchronization pulse signal.

[0069] The chip-to-chip timing synchronization pulse input / output interface is designed for time synchronization between multiple switching chips.

[0070] In some embodiments, such as Figure 1 As shown, the timing control and calibration circuits in each time domain also include: a synchronous clock output circuit;

[0071] The multi-port multi-domain time synchronization chip also includes: a synchronization clock output interface;

[0072] The synchronous clock output circuit outputs a synchronous clock to the outside of the chip through the synchronous clock output interface.

[0073] Specifically, the synchronous clock output circuit outputs a synchronous clock waveform to the external switching chip to provide a reference time for the external switching chip, so that the external switching chip can use the synchronous clock as a reference for timing.

[0074] Among them, the time information input / output interface, the chip-to-chip timing synchronization pulse input / output interface, and the synchronization clock output interface are three interfaces.

[0075] In some embodiments, such as Figure 1 As shown, the multi-port multi-domain time synchronization chip further includes: a domain timing calibration synchronization control circuit, used to obtain the reference time and timing calibration control information from the central timing node module and synchronize it to the multiple port modules. The timing calibration control information is determined according to the reference time and the time deviation of each time domain. The timing calibration control information is used to control the port modules to perform timing calibration.

[0076] In this embodiment, the central timing node module can directly provide the reference time and time deviation to the port modules via a single circuit. However, this requires multiple buses, increasing circuit complexity. Alternatively, a timing calibration control message can be generated based on the reference time and time deviation. This message controls both `adjust_en` and `adjust_dir`. When `adjust_en` is active, `adjust_dir` is 0 or 1, causing the clock cycle timing register to stop incrementing once (deducting time). When `adjust_dir` is 1 or 0, the clock cycle timing register increments by two clock cycles (for example, at a 500MHz clock frequency, the clock cycle timing increments by 4ns). This timing calibration control message is then provided to each port module via a domain timing calibration synchronization control circuit. This approach uses only a few buses, reducing costs. The central timing node module controls the time calibration of each port module via hardware circuitry.

[0077] In some embodiments, such as Figure 1 As shown, the port module includes a message transceiver unit and a port timing node;

[0078] The message transceiver unit is used to: receive and send protocol messages in various time domains from the port; forward the protocol messages to the ports of other port modules through the message forwarding circuit, or redirect them to the CPU and protocol software module through the message forwarding circuit, or forward them to other port modules through the message forwarding circuit and simultaneously copy them to the CPU and protocol software module.

[0079] The port timing node is used to: receive the protocol message, determine the transmission and reception time based on the protocol message; receive the reference time and timing calibration control information provided by the central timing node module, perform timing based on the reference time, and adjust the reference time based on the timing calibration control information to synchronize the time of each time domain of the port.

[0080] The port timing node includes multiple time domain units and the protocol message domain parsing circuit; each time domain unit includes a timestamp sampling circuit and a domain timing control and calibration circuit.

[0081] The protocol message field parsing circuit is used to: parse the time field to which the received or sent protocol message belongs, and trigger the timestamp sampling circuit in the corresponding time field unit according to the time field to sample the received timestamp and sent timestamp of the protocol message;

[0082] The domain timing control and calibration circuit is used to: receive the reference time and timing calibration control information provided by the central timing node module, perform timing based on the reference time, and adjust the reference time based on the timing calibration control information to synchronize the time of each time domain of the port.

[0083] The timestamp sampling circuit includes a receive timestamp register and a transmit timestamp register;

[0084] The receive timestamp register is used to: store the receive timestamp;

[0085] The transmission timestamp register is used to store the transmission timestamp.

[0086] The domain timing control and calibration circuit includes a timing register and a calibration control circuit;

[0087] The timing register is used to: store the reference time;

[0088] The calibration control circuit is used to: perform timing based on the reference time, and adjust the reference time based on the timing calibration control information to synchronize the time of each time domain of the port.

[0089] In this embodiment, such as Figure 1 As shown, the message transceiver unit receives and sends messages from external service ports. Messages received by the port are forwarded to other ports for transmission via message forwarding circuits, or redirected to the CPU port, or forwarded to other ports while simultaneously copying the message to the CPU port. When sending and receiving event-type PTP / gPTP protocol messages, the port simultaneously sends the message to the port timing node.

[0090] The timestamp sampling circuit samples and stores the values ​​of the timing registers at the time of receiving and sending evnet messages into the receive or transmit register group, respectively. The port timing and calibration control circuit, controlled by the receive domain timing calibration synchronization control circuit, performs timing and real-time calibration, generating timing information (timing register) for the port module. The protocol message domain parsing circuit, i.e., the PTPEvent protocol message PTP domain parsing circuit, parses the PTP / gPTP time domain to which the received or transmitted message belongs, triggering the timestamp sampling circuits of each domain to sample the receive and transmit timestamps of the message.

[0091] Figure 2 This is a schematic diagram of the structure of an embodiment of the single-port multi-domain time synchronization chip provided in this application; as shown. Figure 2 As shown, in terminal chips (i.e., single-port devices), Figure 1 The functions of the port module and the central timing node are combined, eliminating the need for message forwarding circuits and domain timing and calibration synchronization circuits, thus enabling single-port multi-domain time synchronization.

[0092] After the merger, the single-port multi-domain time synchronization chip includes: CPU and protocol software module, port timing node circuit and message transceiver module.

[0093] The CPU and protocol software module are used to provide a reference time and determine the time deviation based on the transmission and reception time of protocol messages in each time domain and the time correction domain.

[0094] The port timing node circuit is used to receive the reference time and the time deviation of each time domain sent by the CPU and the protocol software module, and adjust the reference time to synchronize the time of each time domain with the master clock in the network.

[0095] The message transceiver module is used to receive and send protocol messages in various time domains.

[0096] Specifically, compared to the multi-port multi-domain time synchronization chip, the CPU and protocol software modules of this single-port multi-domain time synchronization chip retain the same functional units and functions. The port timing node circuit, however, includes all the functions of the central timing node in the multi-port multi-domain time synchronization chip and the PTPEvent protocol message PTP domain parsing circuit of the port module in the multi-port multi-domain time synchronization chip. This port timing node circuit can directly perform time synchronization.

[0097] When this application is specifically applied to a TSN Ethernet switching chip, the central timing node can be implemented in the chip management module, and the timing of the port module can be implemented on the MAC or PHY of each Ethernet port. Each module can support multiple domains.

[0098] [First Specific Implementation Method of Multi-Port Multi-Domain Time Synchronization Method]

[0099] The multi-port, multi-domain time synchronization method provided in this application includes the following steps:

[0100] The message forwarding circuit forwards protocol messages in each time domain between ports and between ports and the CPU.

[0101] The CPU and protocol software modules determine the time deviation based on the transmission and reception time and time correction domain of the protocol messages in each time domain.

[0102] The central timing node module provides a reference time, receives the time deviations of each time domain sent by the CPU and protocol software module, and adjusts the reference time to synchronize the time of each time domain with the master clock in the network.

[0103] Multiple port modules receive the reference time and the time deviation of each time domain provided by the central timing node module, and perform time synchronization of each time domain of the port.

[0104] [Examples of the computing device in this application]

[0105] Figure 3 This is a schematic structural diagram of a computing device 900 provided in an embodiment of this application. The computing device 900 includes: a processor 910, a memory 920, and a communication interface 930.

[0106] It should be understood that Figure 3 The communication interface 930 in the computing device 900 shown can be used to communicate with other devices.

[0107] The processor 910 can be connected to the memory 920. The memory 920 can be used to store the program code and data. Therefore, the memory 920 can be a storage unit inside the processor 910, an external storage unit independent of the processor 910, or a component that includes both the storage unit inside the processor 910 and the external storage unit independent of the processor 910.

[0108] Optionally, the computing device 900 may also include a bus. The memory 920 and communication interface 930 can be connected to the processor 910 via the bus. The bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc.

[0109] It should be understood that in the embodiments of this application, the processor 910 may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor. Alternatively, the processor 910 may employ one or more integrated circuits to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0110] The memory 920 may include read-only memory and random access memory, and provides instructions and data to the processor 910. A portion of the processor 910 may also include non-volatile random access memory. For example, the processor 910 may also store device type information.

[0111] When the computing device 900 is running, the processor 910 executes the computer execution instructions in the memory 920 to perform the operation steps of the above method.

[0112] It should be understood that the computing device 900 according to the embodiments of this application can correspond to the corresponding subject in executing the methods according to the various embodiments of this application, and the above and other operations and / or functions of each module in the computing device 900 are respectively for implementing the corresponding processes of the methods of this embodiment. For the sake of brevity, they will not be described in detail here.

[0113] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0114] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0115] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0116] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0117] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0118] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0119] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, is used to perform the above-described method, which includes at least one of the schemes described in the above embodiments.

[0120] The computer storage medium in this application embodiment can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. For example, a computer-readable storage medium can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0121] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0122] The program code contained on a computer-readable medium may be transmitted using any suitable medium, including, but not limited to, wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0123] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0124] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present application has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, all of which fall within the scope of protection of the present invention.

Claims

1. A multi-port, multi-domain time synchronization chip, characterized in that, include: The CPU and protocol software module are used to determine the time deviation based on the transmission and reception time and time correction domain of the protocol message in each time domain; wherein, the time correction domain is the dwell time generated by the transparent clock device when transmitting and receiving the protocol message; each time domain has its own master clock or previous hop edge clock, and the time deviation is the time deviation between each time domain and the corresponding master clock or previous hop edge clock. The message forwarding circuit is used to forward protocol messages in each time domain between ports and between ports and the CPU. The central timing node module is used to provide the reference time for each time domain, receive the time deviation of each time domain sent by the CPU and protocol software module, and adjust the reference time to synchronize the time between each time domain and the corresponding master clock or the previous hop edge clock. Multiple port modules, each port having multiple time domains, are used to receive the reference time and the time deviation of each time domain provided by the central timing node module, and to synchronize the time between each time domain of the port and the corresponding master clock or the previous hop edge clock.

2. The multi-port multi-domain time synchronization chip according to claim 1, characterized in that, The multi-port multi-domain time synchronization chip further includes: a register access path for accessing and reading the transmission and reception times of protocol messages from the port module and providing them to the CPU and protocol software module; and accessing the central timing node module to write the time deviation into the central timing node module.

3. The multi-port multi-domain time synchronization chip according to claim 2, characterized in that, The CPU and protocol software module includes a multi-time domain clock analysis and synchronization processing unit, a multi-time domain protocol message transmission and reception driver unit, and a chip configuration management driver unit. The multi-time-domain clock analysis and synchronization processing unit is used to: determine the time deviation based on the transmission and reception time and time correction domain of the protocol messages in each time domain; The protocol message transmission and reception driver unit is used to drive the message forwarding circuit to realize the reception and transmission of protocol messages in each time domain between ports and between ports and CPU. The chip configuration management driver unit is used to drive the register access path to access the port module and the central timing node module.

4. The multi-port multi-domain time synchronization chip according to claim 3, characterized in that, The chip configuration management driver unit is also used to configure the reference time for the central timing node module.

5. The multi-port multi-domain time synchronization chip according to claim 1, characterized in that, The central timing node module includes timing control and calibration circuits for multiple time domains. Each timing control and calibration circuit includes: timing control and register, calibration control and register, and time loading and storage control and register. The timing control and register are used for: timing control and storage based on the reference time; The calibration control and register are used to: store the time deviation, and control the timing control and register to adjust the reference time according to the time deviation to synchronize the time between each time domain and the corresponding master clock or the previous hop edge clock; The time loading storage control and register is used to: load the reference time into the timing control and register, and load the time deviation into the calibration control and register.

6. The multi-port multi-domain time synchronization chip according to claim 5, characterized in that, The calibration control and register is specifically used to: send control signal pulses to the timing control and register, the control signal pulses including enable control signal pulses and direction control signal pulses; when the enable control signal pulse is valid and the direction control signal pulse is a first preset value, the timing register in the timing control and register is controlled to stop accumulating a first preset number of times; when the enable control signal pulse is valid and the direction control signal pulse is a second preset value, the timing register in the timing control and register is controlled to accumulate a second preset number of times.

7. The multi-port multi-domain time synchronization chip according to claim 5, characterized in that, The time loading storage control and register is also used to: store a snapshot of the current time stored in the timing control and register.

8. The multi-port multi-domain time synchronization chip according to claim 7, characterized in that, The multi-port multi-domain time synchronization chip further includes: a time information input / output interface, used to load the set reference time into the time loading storage control and register; and to output the current time after the snapshot.

9. The multi-port multi-domain time synchronization chip according to claim 5, characterized in that, The timing control and calibration circuits for each time domain also include: a synchronization pulse input / output circuit; The multi-port multi-domain time synchronization chip also includes: an inter-chip timing synchronization pulse input / output interface; The synchronization pulse input / output circuit receives external synchronization pulse signals through the inter-chip timing synchronization pulse input / output interface and resets the timing register in the timing control register; the synchronization pulse input / output circuit outputs synchronization pulse signals to the outside of the chip through the inter-chip timing synchronization pulse input / output interface.

10. The multi-port multi-domain time synchronization chip according to claim 5, characterized in that, The timing control and calibration circuits for each time domain also include: a synchronous clock output circuit; The multi-port multi-domain time synchronization chip also includes: a synchronization clock output interface; The synchronous clock output circuit outputs a synchronous clock to the outside of the chip through the synchronous clock output interface.

11. The multi-port multi-domain time synchronization chip according to claim 1, characterized in that, The multi-port multi-domain time synchronization chip further includes: a domain timing calibration synchronization control circuit, used to obtain the reference time and timing calibration control information from the central timing node module and synchronize it to the multiple port modules. The timing calibration control information is determined based on the reference time and the time deviation of each time domain. The timing calibration control information is used to control the port modules to perform timing calibration.

12. The multi-port multi-domain time synchronization chip according to claim 1 or 11, characterized in that, The port module includes a message transceiver unit and a port timing node; The message transceiver unit is used to: receive and send protocol messages in various time domains from the port; forward the protocol messages to the ports of other port modules through the message forwarding circuit, or redirect them to the CPU and protocol software module through the message forwarding circuit, or forward them to other port modules through the message forwarding circuit and simultaneously copy them to the CPU and protocol software module. The port timing node is used to: receive the protocol message and determine the transmission and reception time according to the protocol message; receive the reference time and timing calibration control information provided by the central timing node module, perform timing based on the reference time, and adjust the reference time based on the timing calibration control information to synchronize the time between each time domain of the port and the corresponding master clock or the previous hop edge clock.

13. The multi-port multi-domain time synchronization chip according to claim 12, characterized in that, The port timing node includes multiple time domain units and the protocol message domain parsing circuit; each time domain unit includes a timestamp sampling circuit and a domain timing control and calibration circuit. The protocol message field parsing circuit is used to: parse the time field to which the received or sent protocol message belongs, and trigger the timestamp sampling circuit in the corresponding time field unit according to the time field to sample the received timestamp and sent timestamp of the protocol message; The domain timing control and calibration circuit is used to: receive the reference time and timing calibration control information provided by the central timing node module, perform timing based on the reference time, and adjust the reference time based on the timing calibration control information to synchronize the time between each time domain of the port and the corresponding master clock or the previous hop edge clock.

14. The multi-port multi-domain time synchronization chip according to claim 13, characterized in that, The timestamp sampling circuit includes a receive timestamp register and a transmit timestamp register; The receive timestamp register is used to: store the receive timestamp; The transmission timestamp register is used to store the transmission timestamp.

15. The multi-port multi-domain time synchronization chip according to claim 13, characterized in that, The domain timing control and calibration circuit includes a timing register and a calibration control circuit; The timing register is used to: store the reference time; The calibration control circuit is used to: perform timing based on the reference time, and adjust the reference time based on the timing calibration control information to synchronize the time between each time domain of the port and the corresponding master clock or the previous hop edge clock.

16. A multi-port, multi-domain time synchronization method, characterized in that, include: The message forwarding circuit forwards protocol messages in each time domain between ports and between ports and the CPU. The CPU and protocol software module determine the time deviation based on the transmission and reception time and time correction domain of the protocol messages in each time domain; wherein, the time correction domain is the dwell time generated by the transparent clock device when transmitting and receiving the protocol messages; each time domain has its own master clock or previous hop edge clock, and the time deviation is the time deviation between each time domain and the corresponding master clock or previous hop edge clock. The central timing node module provides the reference time for each time domain, receives the time deviation of each time domain sent by the CPU and protocol software module, and adjusts the reference time to synchronize the time between each time domain and the corresponding master clock or the previous hop edge clock. Multiple port modules receive the reference time and the time deviation of each time domain provided by the central timing node module, and perform time synchronization between each time domain of the port and the corresponding master clock or the previous hop edge clock, wherein each port has multiple time domains.

17. A single-port multi-domain time synchronization method, characterized in that, include: The CPU and protocol software module are used to provide the reference time for each time domain and determine the time deviation based on the transmission and reception time of the protocol message in each time domain and the time correction domain. The time correction domain is the dwell time generated by the transparent clock when transmitting and receiving the protocol message. Each time domain has its own master clock or previous hop edge clock, and the time deviation is the time deviation between each time domain and the corresponding master clock or previous hop edge clock. A port timing node circuit is used to receive the reference time and the time deviation of each time domain sent by the CPU and the protocol software module, and adjust the reference time to synchronize the time between each time domain and the corresponding master clock or the previous hop edge clock; wherein, the port has multiple time domains; The message transceiver module is used to receive and send protocol messages in various time domains.

18. A computing device, characterized in that, include: Communication interface; At least one processor connected to the communication interface; as well as At least one memory connected to the processor and storing program instructions that, when executed by the at least one processor, cause the at least one processor to perform the method of claim 16.

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