Method for running a robot controller program of a multi-processor architecture and control device

Abstract

The application provides a mechanical arm controller program running method and control device of a multi-processor architecture, the running method comprises processor program starting and updating, the starting sequence of the processor program is FPGA, CPU and DSP in turn, and a multi-stage control and verification starting mode is adopted in the starting process, so that the mechanical arm is ensured not to be incorrectly triggered to move or to be misreported with an error state due to different starting times of multiple processors and reception of a host computer instruction during the starting process; the updating of the processor program depends on the scheduling of the CPU BOOT, so that the software of multiple processors can be quickly updated and upgraded.

Description

Technical Field

[0001] This invention belongs to the field of software control technology, and specifically relates to a method for starting and updating a robotic arm controller program with a multiprocessor architecture. Background Technology

[0002] A robot is a mechanical device that can be programmed to perform certain tasks under automatic control. In industrial production, robotic arms were the first type of robot to be used. Initially, robotic arms were well-suited for material handling, equipment maintenance, lifting, and transporting materials, greatly improving industrial production efficiency. With the continuous development of robot-related technologies, robotic arms are no longer just considered "labor force" in industrial production; various types of software and algorithms have endowed them with the ability to think.

[0003] The robotic arm controller is the nerve center and brain of the robotic arm system, responsible for crucial functions such as task planning and management, data processing, and motion planning. The robotic arm controller mainly consists of two parts: software and hardware. The hardware establishes the electrical connection between the robotic arm and the equipment management system, while the software issues task commands to the robotic arm, enabling task planning and management.

[0004] The current software upgrade process for multi-processor architecture robotic arm controllers uses a power-on full startup method, which carries the risk of robotic arm malfunction due to data uncertainty during the initialization of multiple CPUs. Furthermore, the robotic arm controller contains multiple software programs, and current software upgrades are basically carried out by upgrading each software program separately, resulting in a complex and error-prone software upgrade process.

[0005] Therefore, it is necessary to provide a method for starting and updating the software of a multi-processor architecture robotic arm controller to achieve stable and reliable operation of the controller, while enabling rapid software updates and upgrades for multiple processors. Summary of the Invention

[0006] In order to overcome the shortcomings of the existing technology, the inventors have conducted intensive research and provided a method for starting and updating a robotic arm controller program with a multi-processor architecture. By constructing the controller startup sequence logic, the stable and reliable operation of the controller is achieved, while the software of multiple processors can be updated and upgraded quickly.

[0007] The technical solution provided by this invention is as follows:

[0008] In a first aspect, a method for running a program of a robotic arm controller with a multi-processor architecture is provided. The robotic arm controller with the multi-processor architecture is mainly composed of an FPGA, a DSP, and a CPU. The program of the CPU includes a BOOT program and an application program APP with three modes of redundancy, which are stored in different areas of the first FLASH. The program of the DSP includes a BOOT program and an application program APP with three modes of redundancy, which are stored in different areas of the second FLASH.

[0009] The running method includes a program startup step, the startup process of which is as follows:

[0010] After the FPGA program starts and completes its self-test, the FPGA controls the CPU to start a copy of the CPU BOOT program in the first FLASH memory area. The CPU BOOT program runs in the SRAM mounted on the CPU and performs a triple redundancy check on the CPU's APP. If the check is successful, the CPU BOOT program guides the CPU APP to start. After the CPU APP starts, the startup address of the DSP BOOT program is specified, and the DSP automatically reads a copy of the DSP BOOT program in the second FLASH to start it. After the DSP BOOT program runs and completes its hardware self-test, it performs a triple redundancy check on the DSP APP program. If the check is successful, it guides the DSP to start, and finally completes the startup of the robotic arm controller program.

[0011] Secondly, a multi-processor architecture robotic arm controller program execution device, characterized in that it includes:

[0012] The FPGA startup module is used to implement the FPGA program startup and self-test. After the startup and self-test are completed, it controls the CPU to select and start one copy of the CPU BOOT program in the first FLASH memory area.

[0013] The CPU boot module is used to read a copy of the CPU BOOT program from the first FLASH storage area to start the CPU. The CPU BOOT program runs in the SRAM mounted on the CPU and performs a triple redundancy check on the CPU APP. After the check is successful, the CPU BOOT program guides the CPU APP to start. After the CPU APP starts, the boot address of the DSP BOOT program is specified.

[0014] The DSP boot module is used to read a copy of the DSP BOOT program from the second FLASH storage area to start the DSP. After the DSP BOOT program runs and performs a self-test on the hardware device, it performs a triple redundancy check on the DSP APP program. If the check is correct, it will boot the DSP.

[0015] The update module is used to receive instructions from the host computer and update the CPU BOOT program, CPU APP program, DSP BOOT program, or DSP APP program.

[0016] The multiprocessor architecture robotic arm controller program execution method and control device provided by the present invention have the following beneficial effects:

[0017] (1) The present invention provides a method for running a multi-processor architecture robotic arm controller program. The startup order of the processor program in the robotic arm controller is FPGA, CPU, DSP, and a multi-level control and verification startup method is adopted during the startup process to ensure that the robotic arm will not erroneously trigger the robotic arm action or falsely report an error state after receiving the host computer instruction due to the different startup times of multiple processors during the startup process.

[0018] (2) The present invention provides a method for running a multi-processor architecture robotic arm controller program, which adopts a unified management approach to update the programs of multiple software in the controller, thereby improving the software running efficiency and reducing the complexity of software operation. Attached Figure Description

[0019] Figure 1 A schematic diagram of a multi-processor architecture robotic arm controller;

[0020] Figure 2 Storage layout for robotic arm programs in a multi-processor architecture;

[0021] Figure 3 This indicates the execution locations of the CPU's BOOT program and APP program in SRAM and SDRAM, respectively.

[0022] Figure 4 The program update process for the robotic arm controller;

[0023] Figure 5 To control the instruction frame format;

[0024] Figure 6 Update the data frame format for the program. Detailed Implementation

[0025] The features and advantages of the present invention will become clearer and more explicit from the following detailed description.

[0026] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0027] According to a first aspect of the present invention, a method for starting and updating a program for a robotic arm controller with a multi-processor architecture is provided. The multi-processor robotic arm controller mainly consists of three main processors: an FPGA, a DSP, and a CPU. Its peripheral components include a first FLASH, a second FLASH, a communication bus, a power module, SRAM, and SDRAM. The schematic diagram of the architecture is shown below. Figure 1 As shown in the diagram. The power supply module is responsible for supplying power to the three main processors: FPGA, DSP, and CPU. The communication bus enables communication between the robotic arm controller and the host computer. The first and second FLASH memory are used to store the programs for the CPU and DSP, respectively. SRAM is used to provide operating space for the CPU, and SDRAM is used to provide operating space for the DSP.

[0028] The FPGA's program is stored directly inside its processor; the CPU's program, including the BOOT program and the application program (APP), is stored in different areas of the first FLASH memory and employs a triple-modular redundancy approach; the DSP's program, including the BOOT program and the application program (APP), is stored in different areas of the second FLASH memory and also employs a triple-modular redundancy approach. The storage method and format are as follows: Figure 2 As shown. The locations of the CPU's BOOT and APP programs in SRAM and the locations of the DSP's BOOT and APP programs in SDRAM are as follows. Figure 3 As shown.

[0029] Based on the above-described multi-processor architecture robotic arm controller, this invention provides a method for starting a program in a multi-processor architecture robotic arm controller. The startup order of the processor programs in the robotic arm controller is FPGA, CPU, and DSP, respectively. The detailed startup process is as follows:

[0030] The FPGA program first starts and completes a self-test. Then, the FPGA controls the CPU to start a copy of the CPU BOOT program in the first FLASH memory area. The CPU BOOT program runs in the SRAM mounted on the CPU and performs a triple redundancy check on the CPU's APP. If the check is successful, the CPU BOOT program guides the CPU APP to start. After the CPU APP starts, the startup address of the DSP BOOT program is specified, and the DSP automatically reads a copy of the DSP BOOT program in the second FLASH to start. After the DSP BOOT program runs and completes a hardware self-test, it performs a triple redundancy check on the DSP APP program. If the check is successful, it guides the DSP to start, and finally completes the startup of the robotic arm controller program.

[0031] For example, after the robotic arm controller powers on, the FPGA program first starts, completing the self-test of the hardware device interface. Then, it specifies the start address of the CPU BOOT program (randomly selected from three addresses). The CPU BOOT program runs in the SRAM address space of 0x40000000 to 0x40020000. After the hardware interface device self-test is completed, if there is no program update instruction information, it performs a 2-out-of-3 checksum and XOR check on the three copies of the CPU APP program in the first FLASH. If the checksum passes, the CPU APP program is moved to the SRAM address space of 0x40020000 to 0x407FFFFF, and then the CPU APP program in the address space of 0x40020000 to 0x407FFFF is run. The CPU APP performs a 2-out-of-3 checksum and XOR check on the DSP BOOT program. If the checksum passes, it randomly selects an address in the second FLASH and starts the DSP BOOT program. After the DSP BOOT program finishes running, it initializes and self-tests the external interface of the DSP, and then... The APP program performs a 3-out-of-2 checksum and an XOR checksum. After the checksum is successful, the data is moved to address 0x0008000 in SDRAM. The DSP BOOT program stops running and jumps to the DSP APP program for execution.

[0032] The multi-level control and verification startup method ensures that the robotic arm will not erroneously trigger its actions or falsely report an error status when it receives instructions from the host computer due to the different startup times of multiple processors.

[0033] like Figure 4 The update process of the robotic arm controller program with a multiprocessor architecture is shown below:

[0034] (1) After the CPU BOOT program starts, it enters the update determination period (e.g., 10-30s). If the BOOT program correctly receives the control instructions sent by the host computer during the update determination period, it enters the program update mode and prepares to receive program update data. Otherwise, the BOOT program starts the CPU APP program.

[0035] The control command frame information includes key information such as total length, total verification, software type, and programming location. (See below) Figure 5Software type refers to the type of software being updated, including CPU BOOT program update, CPU APP program update, DSP BOOT program update, or DSP APP program update; the programming location refers to the programming location after the update package of the corresponding program has been received. For example, for the CPU BOOT program, the programming location can be any location among CPU BOOT1, CPU BOOT2, or CPU BOOT3 to update the program. The same applies to CPU APP program, DSP BOOT program, or DSP APP program.

[0036] (2) After the CPU BOOT program successfully receives the control instruction frame, it enters the state of waiting for program updates;

[0037] (3) After entering the program update state, the CPU BOOT program receives a program data frame instruction sent by the host computer. The data frame contains the valid data for updating the program, the frame count, the data length, and the frame checksum. See [link to documentation]. Figure 6 ;

[0038] (4) After receiving a data frame, the CPU BOOT program performs frame continuity and XOR check. If the check is correct, the frame data is saved to the temporary storage area of ​​the CPU FLASH program and the number of successfully received frames is displayed in the feedback. If the count is not continuous or the check is incorrect, the program stops receiving new data and uploads the error status.

[0039] (5) The host computer retransmits the data frame from the breakpoint based on the received frame count value;

[0040] (6) After the CPU BOOT program receives the breakpoint resume data frame, it receives the data frame again.

[0041] (7) After the CPU BOOT has received all the data frames fed back to the host computer, the host computer sends an end control command frame to the CPU BOOT.

[0042] (8) After receiving the end control command frame, the CPU BOOT program compares the total length and total verification of the data in the FLASH temporary storage area according to the information of the first frame, and uploads the final verification result for feedback.

[0043] (9) After the verification is passed, the data is burned to the corresponding FLASH area of ​​the program according to the instruction position. After the burning is completed, the FLASH data is read again for total length and total checksum comparison. If the comparison is passed, the FLASH burning is completed; otherwise, the program update task fails.

[0044] According to a second aspect of the present invention, a multiprocessor architecture robotic arm controller program startup and update device is also provided, including an FPGA startup module, a CPU startup module, a DSP startup module and an update module;

[0045] The FPGA startup module is used to implement the FPGA program startup and self-test. After the startup and self-test are completed, it controls the CPU to select and start one copy of the CPU BOOT program in the first FLASH memory area.

[0046] The CPU boot module is used to read a copy of the CPU BOOT program from the first FLASH storage area to start the CPU. The CPU BOOT program runs in the SRAM mounted on the CPU and performs a triple redundancy check on the CPU APP. After the check is successful, the CPU BOOT program guides the CPU APP to start. After the CPU APP starts, the boot address of the DSP BOOT program is specified.

[0047] The DSP boot module is used to read a copy of the DSP BOOT program from the second FLASH storage area to start the DSP. After the DSP BOOT program runs and performs a self-test on the hardware device, it performs a triple redundancy check on the DSP APP program. If the check is successful, it will boot the DSP.

[0048] The update module receives instructions from the host computer and updates the CPU BOOT program, CPU APP program, DSP BOOT program, or DSP APP program. The specific update process is the same as the update process in the first aspect.

[0049] Those skilled in the art will recognize that the modules described in this invention can be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, these modules can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium.

[0050] The present invention has been described in detail above with reference to specific embodiments and exemplary examples; however, these descriptions should not be construed as limiting the present invention. Those skilled in the art will understand that various equivalent substitutions, modifications, or improvements can be made to the technical solutions and embodiments of the present invention without departing from the spirit and scope of the invention, and all such modifications and improvements fall within the scope of the present invention. The scope of protection of the present invention is defined by the appended claims.

[0051] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A method of running a robot controller program in a multi-processor architecture, characterized by, The multi-processor architecture mechanical arm controller is mainly composed of FPGA, DSP and CPU, the program of the CPU includes three-mode redundant BOOT program and application program APP, which are stored in different areas of the first FLASH, the program of the DSP includes three-mode redundant BOOT program and application program APP, which are stored in different areas of the second FLASH; The running method includes a program starting step, and the starting process is as follows: The FPGA program is firstly started and self-checked, then the FPGA controls the CPU to start one copy of the CPU BOOT program in the first FLASH storage area, the CPU BOOT program runs in the SRAM mounted by the CPU, and performs three-mode redundant check on the CPU APP, after the check is successful, the CPU BOOT program guides the CPU APP to start; after the CPU APP is started, the starting address of the DSP BOOT program is specified, the DSP automatically reads one copy of the DSP BOOT program in the second FLASH to realize starting, the DSP BOOT program runs and performs self-check on the hardware device, after the self-check is completed, the program of the DSP APP is checked in three-mode redundancy, if the check is correct, the DSP APP is guided to start, and finally the starting of the program of the mechanical arm controller is completed; The running method includes a program updating step, and the updating process is as follows: After the CPU BOOT program is started, a determination period is entered, if the BOOT program correctly receives the control instruction sent by the upper computer in the determination period, the program updating mode is entered, the program updating data is prepared to be received, otherwise the CPU APP program is started by the BOOT program; After the CPU BOOT program successfully receives the control instruction frame, the state of waiting for program updating is entered; After the CPU BOOT program enters the state of program updating, the program data frame instruction sent by the upper computer is received; After the CPU BOOT program receives the data frame, frame continuity and exclusive or check are performed, if the check is correct, the frame data is saved to the CPU FLASH program temporary storage area and the number of successfully received frames is displayed in the feedback; if the count is discontinuous or the check is incorrect, the reception of new data is stopped, and the error state is uploaded; The upper computer re-sends the data frame from the breakpoint according to the received frame count value; After the CPU BOOT program receives the breakpoint continuous transmission data frame, the data frame is received again; After the CPU BOOT feeds back that the data frame is completely received, the upper computer sends an end control instruction frame to the CPU BOOT; After the CPU BOOT program receives the end control instruction frame, the total length and total check of the data in the FLASH temporary storage area are compared according to the first frame information, and the final check result is uploaded and fed back; After the check is passed, the data is written to the corresponding program starting FLASH area according to the instruction position, after the writing is completed, the FLASH data is read again to compare the total length and total check sum, if the comparison is passed, the FLASH writing is completed, otherwise the program updating task fails.

2. The multi-processor architecture-based robot controller program execution method according to claim 1, characterized by, The determination period is 10-30s.

3. The multi-processor architecture based robot controller program execution method according to claim 1, wherein, The control instruction frame information includes total length, total check, software type and burning position, wherein the software type refers to the type of the updated software, including updating CPU BOOT program, updating CPU APP program, updating DSP BOOT program or updating DSP APP program; the burning position refers to the burning position after the receiving of the update package of the corresponding program.

4. The multi-processor architecture based robot controller program execution method according to claim 1, wherein, The data frame includes valid data of the update program, frame count, data length and frame check sum.

5. A multi-processor architecture robot controller program execution control apparatus characterized by comprising: The method comprises the following steps: The FPGA starting module is used to implement the program starting and self-checking of the FPGA, and control the CPU to select and start the CPU BOOT program in the first FLASH storage area after the starting and self-checking are completed; The CPU starting module is used to read the CPU BOOT program in the first FLASH storage area to realize the starting, so that the CPU BOOT program runs in the SRAM mounted by the CPU, and the APP of the CPU is checked by the three-mode redundancy, and after the check is successful, the CPU BOOT program guides the starting of the CPU APP; after the starting of the CPU APP is completed, the starting address of the DSP BOOT program is specified; The DSP starting module is used to read the DSP BOOT program in the second FLASH storage area to realize the starting, and the DSP BOOT program runs and checks the hardware device, and after the self-checking is completed, the program of the DSP APP is checked by the three-mode redundancy, and if the check is correct, the starting is guided; The update module is used to receive the instruction of the upper computer, and implement the updating of the CPU BOOT program, the CPU APP program, the DSP BOOT program or the DSP APP program; The updating process of the update module to the CPU BOOT program, the CPU APP program, the DSP BOOT program or the DSP APP program comprises the following steps: The CPU BOOT program is used to enter the update determination period after the starting, and if the BOOT program correctly receives the control instruction sent by the upper computer in the update determination period, the program updating mode is entered, and the program update data is prepared to be received, otherwise the CPU APP program is started by the BOOT program; After the CPU BOOT program correctly receives the control instruction frame, the state of waiting for the program update is entered; After the CPU BOOT program enters the state of waiting for the program update, the program data frame instruction sent by the upper computer is received; After the CPU BOOT program receives the data frame, the frame continuity and the exclusive or check are judged, if the judgment is correct, the frame data is saved to the CPU FLASH program temporary storage area and the number of successfully received frames is displayed in the feedback; if the count is not continuous or the check is wrong, the receiving of new data is stopped, and the error state is uploaded; The upper computer re-sends the data frame from the breakpoint according to the received frame count value; After the CPU BOOT program receives the breakpoint continuation data frame, the data frame is received again; After the CPU BOOT feeds back to the upper computer that the data frame is completely received, the upper computer sends the end control instruction frame to the CPU BOOT. After the CPU BOOT program receives the end control instruction frame, the data in the FLASH temporary storage area is compared in total length and total check sum according to the first frame information, and the final check result is uploaded and fed back; After the check passes, the data is written to the corresponding program started FLASH area according to the instruction position, after the writing is completed, the FLASH data is read again to compare the total length and total check sum, if the comparison passes, the FLASH writing is completed, otherwise the program updating task fails.

6. The multi-processor architecture robot controller program execution control apparatus according to claim 5, wherein The control instruction frame information includes total length, total check sum, software type and writing position, wherein the software type refers to the type of the updating software, including updating CPU BOOT program, updating CPU APP program, updating DSP BOOT program or updating DSP APP program; the writing position refers to the writing position after the receiving of the updating package of the corresponding program is completed.

7. The multi-processor architecture based robot controller program execution control apparatus according to claim 5, wherein The data frame includes the effective data of the updating program, frame count, data length and frame check sum.

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