Reference voltage circuit

Abstract

A reference voltage generating circuit includes a first depletion-mode metal oxide semiconductor field effect transistor (MOSFET), a first enhancement-mode MOSFET, a reference voltage output connected between the first depletion-mode MOSFET and the first enhancement-mode MOSFET, and a second depletion-mode MOSFET.

Description

Technical Field

[0001] The present application relates to a reference voltage circuit, and in particular, but not exclusively, to a reference voltage circuit having an additional depletion-mode metal oxide semiconductor field effect transistor (MOSFET) configured to provide current compensation. Background Art

[0002] Voltage reference circuits are used to provide a fixed or constant voltage to a device and are often used to reduce the device's current consumption. Low-current consumption circuits are often implemented in power supplies for smaller, less power-intensive devices, such as wearable electronics.

[0003] like Figure 1 As shown, it is known to provide a voltage reference circuit that includes an enhancement-mode MOSFET and a depletion-mode MOSFET to provide a reference voltage. Each MOSFET includes a source, a drain, and a gate. N-channel (nMOS) and P-channel (pMOS) MOSFETs also have a fourth terminal called the substrate. In a discrete MOSFET, the substrate is connected to the source terminal.

[0004] Figure 2 Shown Figure 1 A graph of the current Id through the depletion-mode and enhancement-mode MOSFETs in the circuit versus the voltage Vgs1 and Vgs2 between the gate and source of each MOSFET. t_DP and V t_EN Represents the voltage across the depletion-mode MOSFET and the enhancement-mode MOSFET when the current through the device is zero.

[0005] When Id = I1, the voltages Vgs1 and Vgs2 between the gate and source of each MOSFET and the provided reference voltage follow the following equation, where L1 and W1 refer to the length and width of the MOS gate:

[0006] Vgs1={I1*(L1 / W1*2 / β1)} 1 / 2 +V t_DP

[0007] =K1*I1 1 / 2 +V t_DP

[0008] Vgs2={I1*(L2 / W2*2 / β2)} 1 / 2 +V t_EN

[0009] =K2*I1 1 / 2 +V t_EN

[0010] Vref=Vgs1+Vgs2

[0011] Vgs1=0

[0012] Vref=Vgs2

[0013] =K2*(Vgs1-V t_DP ) / K1+V t_EN

[0014] The circuit configuration can be adjusted so that K2 = K1. This is usually done by adjusting W and L and can only be performed when the MOSFET is designed or manufactured. Generally, they cannot be changed using circuit design.

[0015] Vref=(V t_EN –V t_DP )

[0016] If V t_EN and V t_DP The temperature coefficients are the same or substantially the same, then

[0017] ΔV t_EN / ΔT≒ΔV t_DP / ΔT,

[0018] And the temperature coefficient of the generated reference voltage will be approximately zero, ΔVref / ΔT≒0.

[0019] However, it is generally found that the generated reference voltage Vref depends on the temperature, and ΔVref

[0020] / ΔT≠0, such as Figure 3 It is proved that Figure 1 The relationship between the reference voltage Vref generated in the circuit and the temperature. The change in the generated reference voltage Vref due to temperature is given as Δvref_t.

[0021] Δvref_t may depend on the process characteristics of the manufacturing process used to make the depletion and enhancement mode MOSFETs, but is typically found to vary by a few %. For low current consumption power supplies, it is desirable to reduce Δvref_t to provide a more reliable and constant reference voltage.

[0022] It is known to introduce additional circuitry to provide compensation for the offset Δvref_t. However, using complex additional circuitry for this purpose increases the current consumption of the reference voltage generating circuit. Summary of the Invention

[0023] Generally speaking, the present disclosure proposes to overcome at least some of the above-mentioned problems by providing a reference voltage circuit having an additional depletion-mode metal-oxide-semiconductor field-effect transistor (MOSFET) configured to provide current compensation.

[0024] For optimal performance of the reference voltage generating circuit, Δvref_t is preferably less than 0.5% to 0.75% of Vref. The present disclosure provides a voltage generating circuit that meets this standard.

[0025] Various aspects and preferred features are set out in the accompanying claims.

[0026] According to a first aspect of the present disclosure, there is provided a reference voltage generating circuit, comprising:

[0027] a first depletion-mode metal oxide semiconductor field effect transistor (MOSFET) having a source, a drain, and a gate, and

[0028] wherein the drain of the first depletion-mode MOSFET is configured to be connected to a power supply potential, and the gate of the first depletion-mode MOSFET is connected to the source of the first depletion-mode MOSFET;

[0029] a first enhancement mode MOSFET having a source, a drain, and a gate, and

[0030] wherein the drain of the first enhancement-mode MOSFET is connected to the source of the first depletion-mode MOSFET, the gate of the first enhancement-mode MOSFET is connected to the drain of the first enhancement-mode MOSFET, and the source of the first enhancement-mode MOSFET is connected to a first reference potential;

[0031] a reference voltage output connected between the source of the first depletion-mode MOSFET and the drain of the first enhancement-mode MOSFET; and

[0032] a second depletion-mode MOSFET having a source, a drain, and a gate, and

[0033] The drain of the second depletion MOSFET is connected between the power supply potential and the drain of the first depletion MOSFET, and the source of the second depletion MOSFET is connected between the source of the first depletion MOSFET and the drain of the first enhancement MOSFET.

[0034] Each of the first depletion-mode MOSFET and the first enhancement-mode MOSFET may include a substrate electrode.

[0035] Each of the first depletion-mode MOSFET and the first enhancement-mode MOSFET may include an N-channel MOSFET. Alternatively, each of the first depletion-mode MOSFET and the first enhancement-mode MOSFET may include a P-channel MOSFET.

[0036] The reference voltage generating circuit may further include a first resistor connected between the source of the first depletion MOSFET and the substrate of the first depletion MOSFET, and a second resistor connected between the source of the first enhancement MOSFET and the substrate of the first enhancement MOSFET.

[0037] A ratio of the resistance of the first resistor to the resistance of the second resistor is configured such that a voltage of the reference voltage output decreases as temperature increases.

[0038] The resistance of the first resistor may be smaller than the resistance of the second resistor

[0039] The second depletion mode MOSFET may include a substrate electrode.

[0040] The second depletion MOSFET may include an N-channel MOSFET. Alternatively, the second depletion MOSFET may include a P-channel MOSFET.

[0041] The reference voltage generating circuit may further include a third resistor connected between the source of the first depletion-mode MOSFET and the substrate of the second depletion-mode MOSFET.

[0042] The gate of the second depletion-mode MOSFET may be connected to a second reference potential.

[0043] The first reference potential and the second reference potential may be the same reference potential.

[0044] The first reference potential and / or the second reference potential may be ground potential.

[0045] The gate of the second depletion-mode MOSFET may be connected to the source of the first enhancement-mode MOSFET.

[0046] The source of the second depletion-mode MOSFET may be connected between the drain of the first enhancement-mode MOSFET and the reference voltage output.

[0047] The reference voltage generating circuit may further include:

[0048] one or more additional first depletion-mode MOSFETs connected in series with the first depletion-mode MOSFET; and / or

[0049] one or more additional first enhancement-mode MOSFETs connected in series with the first enhancement-mode MOSFET;

[0050] One or more additional second depletion-mode MOSFETs connected in parallel with the second depletion-mode MOSFET.

[0051] According to another aspect of the present disclosure, there is provided a method for manufacturing a reference voltage generating circuit, the method comprising:

[0052] forming a first depletion mode metal oxide semiconductor field effect transistor (MOSFET) having a source, a drain, and a gate, and

[0053] wherein the drain of the first depletion-mode MOSFET is configured to be connected to a power supply potential, and the gate of the first depletion-mode MOSFET is connected to the source of the first depletion-mode MOSFET;

[0054] forming a first enhancement mode MOSFET having a source, a drain and a gate, and

[0055] wherein the drain of the first enhancement-mode MOSFET is connected to the source of the first depletion-mode MOSFET, the gate of the first enhancement-mode MOSFET is connected to the drain of the first enhancement-mode MOSFET, and the source of the first enhancement-mode MOSFET is connected to a first reference potential;

[0056] forming a reference voltage output connected between the source of the first depletion-mode MOSFET and the drain of the first enhancement-mode MOSFET; and

[0057] forming a second depletion-mode MOSFET having a source, a drain, and a gate, and

[0058] The drain of the second depletion MOSFET is connected between the power supply potential and the drain of the first depletion MOSFET, and the source of the second depletion MOSFET is connected between the source of the first depletion MOSFET and the drain of the first enhancement MOSFET.

[0059] The proposed device offers the following advantages:

[0060] - the reference voltage generating circuit provides a reference voltage having a reduced temperature coefficient compared to a reference voltage generating circuit of the related art;

[0061] - the reference voltage generation circuit is simplified compared to prior art devices, with only an additional depletion mode MOSFET and resistor, while still providing a reduced Δvref_t;

[0062] - the current consumption of the additional components of the circuit is reduced compared to alternative reference voltage generating circuits;

[0063] - there is only a small increase in current consumption due to the additional components, since the provided compensation is effective at high temperatures;

[0064] The compensation of the reference voltage generating circuit can be achieved by a DC power supply and an additional current having a positive temperature coefficient relative to the reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Some embodiments of the present disclosure will now be described, by way of example only, and with reference to the accompanying drawings, in which:

[0066] Figure 1 Schematically illustrates an example circuit for providing a reference voltage according to the related art;

[0067] Figure 2 shows a graph of current versus voltage for a pair of depletion-mode and enhancement-mode MOSFETs in an example circuit for providing a reference voltage according to the related art;

[0068] Figure 3 A graph showing a generated reference voltage versus temperature of an example circuit for providing a reference voltage according to the related art is shown;

[0069] Figure 4 Schematically illustrates a circuit for providing a reference voltage according to an embodiment of the present disclosure;

[0070] Figure 5 Shown Figure 4 a graph of the current provided by the additional depletion-mode MOSFET, the voltage across the additional depletion-mode MOSFET, and the generated reference voltage versus temperature for the circuit;

[0071] Figure 6 A graph showing current versus voltage for an additional depletion-mode MOSFET of a circuit for providing a reference voltage according to an embodiment of the present disclosure is shown;

[0072] Figure 7 A graph showing a reference voltage generated by a circuit for providing a reference voltage relative to temperature according to an embodiment of the present disclosure is shown;

[0073] Figure 8 schematically illustrates an alternative circuit for providing a reference voltage according to an embodiment of the present disclosure;

[0074] Figure 9 Shown Figure 8 a graph of a reference voltage versus an analog value of temperature and a graph of a current versus an analog value of temperature generated in the circuit;

[0075] Figure 10 Shown Figure 8 a graph of a reference voltage generated by the circuit versus a simulated value of temperature;

[0076] Figure 11 schematically illustrates an alternative circuit for providing a reference voltage according to an embodiment of the present disclosure;

[0077] Figure 12 Shown Figure 11 a graph of the current provided by the additional depletion-mode MOSFET, the voltage across the additional depletion-mode MOSFET, and the generated reference voltage versus temperature for the circuit;

[0078] Figure 13 schematically illustrates an alternative circuit for providing a reference voltage according to an embodiment of the present disclosure;

[0079] Figure 14 Shown Figure 13 a graph of analog values of reference voltage versus temperature and a graph of analog values of current versus temperature generated in a circuit; and

[0080] Figure 15 Shown Figure 13 A graph of the analog value of the circuit that generates the reference voltage versus temperature. DETAILED DESCRIPTION

[0081] Figure 4 A circuit 100 or module for providing a reference voltage according to an embodiment of the present disclosure is shown. The circuit 100 includes a first depletion-mode (also known as normally-on) n-type metal oxide semiconductor field effect transistor (nMOSFET) 110. The first depletion-mode nMOSFET

[0082] 110 has a source, a drain, a gate, and a substrate electrode. The gate of the first depletion-mode nMOSFET 110 is connected to the source of the first depletion-mode nMOSFET 110 at a first node. The voltage measured between the gate and source of the first depletion-mode nMOSFET 110 is given as Vgs1. The drain of the first depletion-mode nMOSFET 110 is connected to a power supply 140. In this example, the power supply is a voltage cell or a battery. The power supply 140 provides a voltage VDD.

[0083] The substrate electrode of the first depletion-mode nMOSFET 110 is also connected to the source of the first depletion-mode nMOSFET 110. In this example, the substrate electrode of the first depletion-mode nMOSFET 110 is also connected to the source of the first depletion-mode nMOSFET 110 at a first node. Alternatively, the substrate electrode of the first depletion-mode nMOSFET 110 may be connected to a reference potential, such as ground potential. A first resistor 115 having a resistance Ra is connected to the source of the first depletion-mode nMOSFET 110. The first resistor 115 is formed between the source of the first depletion-mode nMOSFET 110 and a first node at which both the gate and substrate electrode of the first depletion-mode nMOSFET 110 are connected to the source of the first depletion-mode nMOSFET 110.

[0084] A first enhancement-mode (also known as normally-off) nMOSFET 120 is connected in series with the first depletion-mode nMOSFET 110. The first enhancement-mode nMOSFET 120 has a source, a drain, a gate, and a substrate electrode. The drain of the first enhancement-mode nMOSFET 120 is connected to the source of the first depletion-mode nMOSFET 110. The gate of the first enhancement-mode nMOSFET 120 is connected to the drain of the first enhancement-mode nMOSFET 120 at a second node. Both the first node and the second node are formed between the first depletion-mode nMOSFET 110 and the first enhancement-mode nMOSFET 120.

[0085] The source of the first enhancement mode nMOSFET 120 is connected to a first reference potential 150. In this example, the first reference potential 150 is a ground potential. The voltage between the gate and source of the first enhancement mode nMOSFET 120 is given as Vgs2. The substrate electrode of the first enhancement mode nMOSFET 120 is connected to the source of the first enhancement mode nMOSFET 120 at a third node. The third node is formed between the source of the first enhancement mode nMOSFET 120 and the first reference potential 150.

[0086] The second resistor 125 having a resistance Rb is connected to the source of the first enhancement mode nMOSFET 120. The second resistor 125 is formed between the source of the first enhancement mode nMOSFET 120 and the third node. Figure 2 As shown, for a reference voltage generating circuit having a depletion-mode MOSFET and an enhancement-mode MOSFET connected in series, a voltage Vgs1 between the gate and source of the first depletion-mode nMOSFET 110 and a voltage Vgs2 between the gate and source of the first enhancement-mode nMOSFET 120 similarly depend on the current I1 passing therethrough. Therefore, including the first resistor and the second resistor reduces the current I1 while maintaining the generated reference voltage Vref.

[0087] An output 170 for generating a reference voltage Vref is connected between the first depletion-type nMOSFET 110 and the first enhancement-type nMOSFET 120. In this example, the output 170 is connected to a fourth node located between the first node and the second node.

[0088] Circuit 100 includes additional circuitry 180 including a second depletion-mode nMOSFET 130 connected in parallel with first depletion-mode nMOSFET 110. Second depletion-mode nMOSFET 130 has a source, a drain, a gate, and a substrate electrode. The drain of second depletion-mode nMOSFET 130 is connected to the drain of first depletion-mode nMOSFET 110 and to a power source 140. The drain of second depletion-mode nMOSFET 130 is connected to a fifth node located between the drain of first depletion-mode nMOSFET 110 and power source 140.

[0089] The gate of the second depletion mode nMOSFET 130 is connected to a second reference potential 160. In this example, the second reference potential 160 is ground potential.

[0090] The source of the second depletion-mode nMOSFET 130 is connected to the source of the first depletion-mode nMOSFET 110 and the drain of the first enhancement-mode nMOSFET 120. The source of the second depletion-mode nMOSFET 130 is connected to a sixth node located between the second node and the fourth node. The voltage measured between the gate and source of the second depletion-mode nMOSFET 130 is given as Vgs3.

[0091] The substrate electrode of the second depletion mode nMOSFET 130 is connected to the source of the second depletion mode nMOSFET 130 at a seventh node. The seventh node is formed between the source of the second depletion mode nMOSFET 130 and the sixth node. A third resistor 135 having a resistance Rc is connected to the source of the second depletion mode nMOSFET 130. The third resistor 135 is formed between the source of the second depletion mode nMOSFET 130 and the seventh node.

[0092] The current through the first depletion-type nMOSFET 110 and the first enhancement-type nMOSFET 120 is given as I1. The current through the second depletion-type nMOSFET 130 is given as I2.

[0093] Figure 5 The upper part shows Figure 4In circuit 100, the voltage Vgs3 across the second depletion-mode nMOSFET 130 (herein referred to as M3) and the generated reference voltage Vref are plotted as a function of temperature when the second depletion-mode nMOSFET 130 is turned off at a lower temperature and when M3 is turned on at a higher temperature. If Vref > -Vgs3, M3 is turned off, and if Vref < -Vgs3, M3 is turned on, generating current I2. The dashed line shows the voltage -Vgs3 when no Vref is connected to the circuit. Vgs3 is the voltage measured between the gate and source of the second depletion-mode nMOSFET 130. Since the source node has a higher voltage than the gate node, Vgs3 is negative.

[0094] Figure 5 The lower portion of FIG shows the compensation provided to the generated reference voltage due to the second depletion MOSFET 130 and the current I2 through the second depletion MOSFET 130. If Vref>-Vgs3: then M3 is off and the resistor generates no current, and if Vref<-Vgs3: then M3 is on and the resistor generates current I2. Figure 6 It is shown that for three different temperatures, Figure 4 FIG. 1 is a graph showing a current I2 of the second depletion MOSFET 130 of the circuit with respect to a voltage Vgs3.

[0095] Figure 7 shows the relationship between the generated reference voltage and temperature, including the Figure 4 A second depletion-mode MOSFET is shown to provide compensation.

[0096] Figure 7 (a) shows the relationship between the reference voltage generated by the reference voltage generating circuit without the second depletion MOSFET 130 introducing compensation and the temperature. The change of the reference voltage Vref generated due to temperature is given as Δvref_t;

[0097] Figure 7 (b) shows the Figure 7 The reference voltage shown in (a) of FIG. 1 is similar to the reference voltage shown in FIG. 1 , and the relationship between the generated reference voltage and temperature is adjusted. The magnitude of Δvref_t does not change due to this adjustment, however, the change in the reference voltage Δvref_t due to temperature occurs less at lower temperatures and more at higher temperatures. This adjustment is provided by selecting the values of Ra and Rb and K1 and K2 to provide this adjustment. In general, if Rb / Ra < 1, then Δvref_t will be as Figure 7 (b) is adjusted;

[0098] Figure 7(c) shows the compensation provided to the reference voltage by I2 and the second depletion MOSFET 130. The compensation increases the reference voltage Vref at higher temperatures; and

[0099] Figure 7 (d) shows that by Figure 7 (b) The adjusted reference voltage Vref is added to Figure 7 Vref is obtained by the compensation voltage of (c). Figure 7 The adjusted reference voltage Vref of (b) has a reduced reference voltage Vref at a higher temperature, while Figure 7 The compensation voltage of (c) has an increased voltage at higher temperatures, so Figure 7 The result shown in (d) shows that the magnitude of Δvref_t is significantly reduced.

[0100] Figure 8 Schematically illustrates an alternative circuit for providing a reference voltage according to an embodiment of the present disclosure. Figure 4 The circuits shown are similar and therefore have similar reference numerals. However, in this embodiment, three first depletion mode MOSFETs 210a, 210b, 210c are connected in series instead of Figure 4 The first depletion-mode MOSFET 110 shown in FIG. 1 and the three first enhancement-mode MOSFETs 220a, 220b, and 220c are connected in series to replace Figure 4 The first enhancement mode MOSFET 120 and three second depletion mode MOSFETs 230a, 230b, and 230c are connected in parallel, replacing Figure 4 A second depletion-mode MOSFET 130 is shown. Although the first depletion-mode MOSFETs 210a, 210b, 210c and the enhancement-mode MOSFETs 220a, 220b, 220c are connected in series in the example shown, they may alternatively be connected in parallel. Similarly, although the second depletion-mode MOSFETs 230a, 230b, 230c are connected in parallel in the example shown, they may alternatively be connected in series.

[0101] Figure 9 (a) shows Figure 8 The upper line shows the reference voltage Vref relative to temperature when compensation is provided, and the lower line shows the reference voltage Vref relative to temperature when no compensation is provided.

[0102] Figure 9 (b) shows Figure 8Figure 2 shows simulated values of current versus temperature in a circuit. The bottom line shows the combined current I2 from the second depletion-mode MOSFETs 230a, 230b, and 230c. The middle line shows the current I1 through the first depletion-mode MOSFETs 210a, 210b, and 210c and the first enhancement-mode MOSFETs 220a, 220b, and 220c. The top line shows the total current consumption I1+I2 of the circuit.

[0103] Figure 10 shows that compared with the circuit without compensation, Figure 8 The circuit generates a reference voltage with respect to the simulated value of temperature, where the upper curve shows Figure 8 The circuit generates an analog value of the reference voltage relative to the temperature, and Figure 10 The lower curve shows the reference voltage generated by the circuit without compensation. This shows the magnitude of the reduction in Δvref_t due to compensation, as well as the reduction in Δvref_t as a fraction of Vref itself. This demonstrates that as a result of compensation, accuracy and reliability are improved, while Vref variability is reduced.

[0104] Figure 11 An alternative circuit for providing a reference voltage according to an embodiment of the present disclosure is schematically shown. Many features are similar to Figure 4 The features provided in FIG1 are identical to those provided in FIG1 and have similar functions and therefore have the same reference numerals. In this embodiment, the gate of the second depletion mode MOSFET 130 is connected to the source of the first enhancement mode MOSFET 120.

[0105] The source of the first enhancement mode nMOSFET 120 is connected to a first reference potential 150. In this example, the first reference potential 150 is a ground potential. The substrate electrode of the first enhancement mode nMOSFET 120 is connected to the source of the first enhancement mode nMOSFET 120 at a third node. The third node is formed between the source of the first enhancement mode nMOSFET 120 and the first reference potential 150.

[0106] A second resistor 125 having a resistance Rb is connected in series with the source of the first enhancement mode nMOSFET 120. The second resistor 125 is formed between the first reference potential 150 and the third node. The gate of the second depletion mode MOSFET 130 is connected to the source of the first enhancement mode MOSFET 120 at an eighth node. The eighth node is formed between the third node and the second resistor 125.

[0107] Figure 12 The upper part shows when M3 is turned off at a lower temperature and when M3 is turned on at a higher temperature. Figure 11The relationship between the voltage Vgs3 across the second depletion mode MOSFET 130 and the voltage Vgs3 across the first enhancement mode nMOSFET 120 and temperature in the circuit 100. If Vgs2>-Vgs3: then M3 is turned off, and if Vgs2<-Vgs3: then M3 is turned on, generating current I2.

[0108] Figure 12 The lower portion of φ shows the compensation provided to the generated reference voltage due to the second depletion MOSFET 130 and the current I2 through the second depletion MOSFET 130 .

[0109] Figure 13 Schematically illustrates an alternative circuit for providing a reference voltage according to an embodiment of the present disclosure. Figure 11 The circuit is similar to that shown in FIG. 1 , however, in this embodiment, three first depletion-mode MOSFETs 210a, 210b, 210c are connected in series instead of Figure 11 The first depletion-mode MOSFET 110 shown in FIG. 1 and the three first enhancement-mode MOSFETs 220a, 220b, and 220c are connected in series to replace Figure 11 The first enhancement mode MOSFET 120 and three second depletion mode MOSFETs 230a, 230b, and 230c are connected in parallel, replacing Figure 11 A second depletion mode MOSFET 130 is shown.

[0110] Figure 14 (a) shows Figure 13 FIG. 4 is a diagram showing analog values of the reference voltage Vref generated by the circuit relative to temperature, illustrating the reference voltage Vref relative to temperature when compensation is provided.

[0111] Figure 14 (b) shows Figure 13 Figure 2 shows simulated values of circuit current versus temperature. The upper line shows the combined current I2 from the second depletion-mode MOSFETs 230a, 230b, and 230c. The lower line shows the current I1 through the first depletion-mode MOSFETs 210a, 210b, and 210c and the first enhancement-mode MOSFETs 220a, 220b, and 220c. The middle line shows the total current consumption I1+I2 of the circuit.

[0112] Figure 15 shows that compared with the circuit without compensation, Figure 13 The circuit generates a reference voltage versus temperature analog value, where the above graph shows Figure 13 The circuit generates a reference voltage relative to the analog value of the temperature, and Figure 15The lower graph shows the reference voltage generated in the circuit without compensation. This shows the magnitude of the reduction in Δvref_t due to compensation, as well as the reduction in Δvref_t as a fraction of Vref itself.

[0113] Although specific embodiments have been described above, the claims are not limited to these embodiments.Each feature disclosed herein may be incorporated into any described embodiment, alone or in any appropriate combination with other features disclosed herein.

[0114] Reference numerals

[0115] 100 reference voltage circuit

[0116] 110 First depletion mode MOSFET

[0117] 115 first resistor

[0118] 120 Enhancement Mode MOSFET

[0119] 125 second resistor

[0120] 130 Second depletion mode MOSFET

[0121] 135 third resistor

[0122] 140 power supply

[0123] 150 first reference potential

[0124] 160 Second reference potential

[0125] 170 reference voltage output

[0126] 180 additional circuit system

[0127] 210a-c first depletion-mode MOSFET

[0128] 220a-c enhancement-mode MOSFET

[0129] 230a-c second depletion mode MOSFET

Claims

1. A reference voltage generating circuit, comprising: a first depletion mode metal oxide semiconductor field effect transistor having a source, a drain and a gate, and wherein the drain of the first depletion-mode metal oxide semiconductor field effect transistor is configured to be connected to a power supply potential, and the gate of the first depletion-mode metal oxide semiconductor field effect transistor is connected to the source of the first depletion-mode metal oxide semiconductor field effect transistor; a first enhancement mode metal oxide semiconductor field effect transistor having a source, a drain and a gate, and wherein the drain of the first enhancement mode metal oxide semiconductor field effect transistor is connected to the source of the first depletion mode metal oxide semiconductor field effect transistor, the gate of the first enhancement mode metal oxide semiconductor field effect transistor is connected to the drain of the first enhancement mode metal oxide semiconductor field effect transistor, and the source of the first enhancement mode metal oxide semiconductor field effect transistor is connected to a first reference potential; a reference voltage output connected between the source of the first depletion-mode metal-oxide-semiconductor field-effect transistor and the drain of the first enhancement-mode metal-oxide-semiconductor field-effect transistor; and a second depletion mode metal oxide semiconductor field effect transistor having a source, a drain and a gate, wherein the drain of the second depletion-mode metal oxide semiconductor field effect transistor is connected between the power supply potential and the drain of the first depletion-mode metal oxide semiconductor field effect transistor, and the source of the second depletion-mode metal oxide semiconductor field effect transistor is connected between the source of the first depletion-mode metal oxide semiconductor field effect transistor and the drain of the first enhancement-mode metal oxide semiconductor field effect transistor, and The gate of the second depletion-mode metal oxide semiconductor field effect transistor is connected to a second reference potential.

2. The reference voltage generating circuit according to claim 1, wherein: Each of the first depletion mode metal oxide semiconductor field effect transistor and the first enhancement mode metal oxide semiconductor field effect transistor includes a substrate electrode.

3. The reference voltage generating circuit according to claim 2, wherein: Each of the first depletion mode metal oxide semiconductor field effect transistor and the first enhancement mode metal oxide semiconductor field effect transistor includes an N-channel metal oxide semiconductor field effect transistor.

4. The reference voltage generating circuit according to claim 2, further comprising: a first resistor connected between the source electrode of the first depletion mode metal oxide semiconductor field effect transistor and the substrate electrode of the first depletion mode metal oxide semiconductor field effect transistor; as well as A second resistor is connected between the source of the first enhancement mode metal oxide semiconductor field effect transistor and the substrate electrode of the first enhancement mode metal oxide semiconductor field effect transistor.

5. The reference voltage generating circuit according to claim 4, wherein: A ratio of the resistance of the first resistor to the resistance of the second resistor is configured such that a voltage of the reference voltage output decreases as temperature increases. The reference voltage generating circuit according to claim 5 , wherein: The resistance of the first resistor is smaller than the resistance of the second resistor.

7. The reference voltage generating circuit according to any one of claims 1 to 6, wherein: The second depletion-mode metal-oxide-semiconductor field-effect transistor includes a substrate electrode.

8. The reference voltage generating circuit according to claim 7, wherein: The second depletion-mode metal oxide semiconductor field effect transistor includes an N-channel metal oxide semiconductor field effect transistor. 9 . The reference voltage generating circuit according to claim 7 , further comprising a third resistor connected between a source of the second depletion mode MOSFET and a substrate electrode of the second depletion mode MOSFET.

10. The reference voltage generating circuit according to any one of claims 1 to 6, wherein: The first reference potential and the second reference potential are the same reference potential.

11. The reference voltage generating circuit according to any one of claims 1 to 6, wherein: The first reference potential and / or the second reference potential is ground potential.

12. The reference voltage generating circuit according to any one of claims 1 to 6, wherein: A source of the second depletion-mode metal-oxide-semiconductor field-effect transistor is connected between a drain of the first enhancement-mode metal-oxide-semiconductor field-effect transistor and the reference voltage output.

13. The reference voltage generating circuit according to any one of claims 1 to 6, further comprising: one or more additional first depletion-mode metal-oxide-semiconductor field-effect transistors connected in series with the first depletion-mode metal-oxide-semiconductor field-effect transistor; one or more additional first enhancement mode metal oxide semiconductor field effect transistors connected in series with the first enhancement mode metal oxide semiconductor field effect transistor; One or more additional second depletion mode metal oxide semiconductor field effect transistors are connected in series with the second depletion mode metal oxide semiconductor field effect transistor.

14. A reference voltage generating circuit, comprising: a first depletion mode metal oxide semiconductor field effect transistor having a source, a drain and a gate, and wherein the drain of the first depletion-mode metal oxide semiconductor field effect transistor is configured to be connected to a power supply potential, and the gate of the first depletion-mode metal oxide semiconductor field effect transistor is connected to the source of the first depletion-mode metal oxide semiconductor field effect transistor; a first enhancement mode metal oxide semiconductor field effect transistor having a source, a drain and a gate, and wherein the drain of the first enhancement mode metal oxide semiconductor field effect transistor is connected to the source of the first depletion mode metal oxide semiconductor field effect transistor, the gate of the first enhancement mode metal oxide semiconductor field effect transistor is connected to the drain of the first enhancement mode metal oxide semiconductor field effect transistor, and the source of the first enhancement mode metal oxide semiconductor field effect transistor is connected to a first reference potential; a reference voltage output connected between the source of the first depletion-mode metal-oxide-semiconductor field-effect transistor and the drain of the first enhancement-mode metal-oxide-semiconductor field-effect transistor; and a second depletion mode metal oxide semiconductor field effect transistor having a source, a drain and a gate, wherein the drain of the second depletion-mode metal oxide semiconductor field effect transistor is connected between the power supply potential and the drain of the first depletion-mode metal oxide semiconductor field effect transistor, and the source of the second depletion-mode metal oxide semiconductor field effect transistor is connected between the source of the first depletion-mode metal oxide semiconductor field effect transistor and the drain of the first enhancement-mode metal oxide semiconductor field effect transistor, and The gate of the second depletion-mode metal oxide semiconductor field effect transistor is connected to the source of the first enhancement-mode metal oxide semiconductor field effect transistor.

15. The reference voltage generating circuit according to claim 14, wherein: Each of the first depletion mode metal oxide semiconductor field effect transistor and the first enhancement mode metal oxide semiconductor field effect transistor includes a substrate electrode.

16. The reference voltage generating circuit according to claim 15, wherein: Each of the first depletion mode metal oxide semiconductor field effect transistor and the first enhancement mode metal oxide semiconductor field effect transistor includes an N-channel metal oxide semiconductor field effect transistor.

17. The reference voltage generating circuit according to any one of claims 14 to 16, wherein: The second depletion-mode metal-oxide-semiconductor field-effect transistor includes a substrate electrode.

18. The reference voltage generating circuit according to claim 17, wherein: The second depletion-mode metal oxide semiconductor field effect transistor includes an N-channel metal oxide semiconductor field effect transistor. 19 . The reference voltage generating circuit according to claim 17 , further comprising a third resistor connected between a source of the second depletion mode MOSFET and a substrate electrode of the second depletion mode MOSFET.

20. The reference voltage generating circuit according to any one of claims 14 to 16, wherein: A source of the second depletion-mode metal-oxide-semiconductor field-effect transistor is connected between a drain of the first enhancement-mode metal-oxide-semiconductor field-effect transistor and the reference voltage output.

21. The reference voltage generating circuit according to any one of claims 14 to 16, further comprising: one or more additional first depletion-mode metal-oxide-semiconductor field-effect transistors connected in series with the first depletion-mode metal-oxide-semiconductor field-effect transistor; one or more additional first enhancement mode metal oxide semiconductor field effect transistors connected in series with the first enhancement mode metal oxide semiconductor field effect transistor; One or more additional second depletion mode metal oxide semiconductor field effect transistors are connected in series with the second depletion mode metal oxide semiconductor field effect transistor.

22. A method for manufacturing a reference voltage generating circuit, the method comprising: forming a first depletion mode metal oxide semiconductor field effect transistor having a source, a drain and a gate, and wherein the drain of the first depletion-mode metal oxide semiconductor field effect transistor is configured to be connected to a power supply potential, and the gate of the first depletion-mode metal oxide semiconductor field effect transistor is connected to the source of the first depletion-mode metal oxide semiconductor field effect transistor; forming a first enhancement mode metal oxide semiconductor field effect transistor having a source, a drain and a gate, and wherein the drain of the first enhancement mode metal oxide semiconductor field effect transistor is connected to the source of the first depletion mode metal oxide semiconductor field effect transistor, the gate of the first enhancement mode metal oxide semiconductor field effect transistor is connected to the drain of the first enhancement mode metal oxide semiconductor field effect transistor, and the source of the first enhancement mode metal oxide semiconductor field effect transistor is connected to a first reference potential; forming a reference voltage output connected between the source of the first depletion-mode metal-oxide-semiconductor field-effect transistor and the drain of the first enhancement-mode metal-oxide-semiconductor field-effect transistor; and forming a second depletion mode metal oxide semiconductor field effect transistor having a source, a drain and a gate, wherein the drain of the second depletion-mode metal oxide semiconductor field effect transistor is connected between the power supply potential and the drain of the first depletion-mode metal oxide semiconductor field effect transistor, and the source of the second depletion-mode metal oxide semiconductor field effect transistor is connected between the source of the first depletion-mode metal oxide semiconductor field effect transistor and the drain of the first enhancement-mode metal oxide semiconductor field effect transistor, and The gate of the second depletion-mode metal oxide semiconductor field effect transistor is connected to a second reference potential, or is connected to the source of the first enhancement-mode metal oxide semiconductor field effect transistor.

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