A reduced instruction set processor

Abstract

This invention discloses a simplified dataflow instruction set processor, comprising on-chip memory, a planar arithmetic unit, a cube arithmetic unit, a point arithmetic unit, a tensor arithmetic unit, and an instruction controller. The on-chip memory directly reads and stores computational data from off-chip memory, and this computational data is used for computation by the planar arithmetic unit, the cube arithmetic unit, and the point arithmetic unit. The tensor arithmetic unit directly obtains data from off-chip memory and performs swapping, splitting, aggregation, and reverse aggregation operations on the tensor data according to instruction configuration information from the instruction controller. The instruction controller directly obtains instructions from off-chip memory and sends instruction configuration information to the planar arithmetic unit, the cube arithmetic unit, the point arithmetic unit, or the tensor arithmetic unit according to the instructions. This processor features simplified and limited computational types, maintaining the high efficiency of a dataflow computing architecture while possessing general computing characteristics, thus achieving the advantages of high computing power, high clock speed, and low power consumption.

Description

Technical Field

[0001] This invention relates to the field of general-purpose processors, and particularly to a reduced dataflow instruction set processor that performs efficient computation of tensor data for computational graph models, and is a general-purpose processor that can be used for neural network computation. Background Technology

[0002] Traditional processors such as CPUs, GPUs, and DSPs employ an instruction-stream computing approach, meaning they continuously read instructions and execute corresponding operations. Traditional processors define functionality at the smallest granularity ("instruction") and define processor behavior through "instruction sets." Users program using high-level languages ​​(such as C), and compilers (such as the GCC compiler) translate these high-level languages ​​into instructions, driving traditional processors like CPUs, GPUs, and DSPs to execute these instructions and implement the functions defined by the high-level language.

[0003] Compared to traditional instruction-stream computing, datastream computing employs a completely different operating method: datastream computing configures a small number of instructions to perform specific functions during computation, continuously reading, processing, and writing data to achieve its computational goals. The average number of operations per cycle that a datastream computing system can perform can reach hundreds of thousands, far exceeding that of instruction-stream computing. A more intuitive comparison between instruction-stream and datastream computing is as follows: Figure 1 As shown.

[0004] Instruction-stream computing is well-suited for control-priority tasks, and for a long time, human-made computers have primarily served control-related needs. Therefore, instruction-stream computing technology, represented by CPUs, has made significant progress over the past few decades, giving rise to technical systems such as CISC (Complex Instruction Set Computing) and RISC (Reduced Instruction Set Computing), and producing mature instruction set technologies like x86, ARM, and RISC.

[0005] In recent years, with the development of neural network algorithms, computational tasks have gradually become the primary task requirement for intelligent computers. Therefore, dataflow computing technology, which is more suitable for computationally intensive tasks, has developed rapidly in the past few years. Almost all low-power, high-performance computing processors employ dataflow computing technology; for example, Google's TPU processor is a typical example of this technology.

[0006] Unlike the mature instruction set architecture of instruction stream computing, the instruction set technology of data stream computing is still in its very early stages. When designing data stream computing systems, various institutions and organizations typically define basic computing functions using different "computational granularities" based on their own business needs. For example, data stream computing systems developed for neural network computing tasks usually define computing functions at the "neural network operator" granularity. Typically, Google's TPU and NVIDIA's NVDLA both employ computing schemes with "neural network operator" granularity.

[0007] However, with the number of neural network operators exceeding 100 and continuously increasing, dataflow computing systems using neural network operators as the granularity, while possessing high performance advantages, also have a significant drawback: a lack of versatility. When the operator requirements of the neural network algorithm exceed the design functional range (due to unsupported operators), the dataflow computing system becomes unusable.

[0008] Because chip development cycles can take 1 to 2 years, and neural network algorithms are updated rapidly on a monthly basis, dataflow computing systems designed at the granularity of neural network operators are easily rendered obsolete in the rapidly evolving AI field due to their inability to adapt to the latest algorithms. This is the biggest pain point for most high-performance dataflow architecture AI processors today: poor versatility and inability to adapt to new algorithms. Summary of the Invention

[0009] To address the aforementioned problems, this invention proposes a simplified dataflow instruction set processor. The processor provides 25 basic operation types, and various combinations of these basic operation types can form various high-level computational expressions, thereby creating a Turing-complete, tensor-based, computation graph-oriented general-purpose dataflow computation system.

[0010] The technical solution is as follows:

[0011] A simplified dataflow instruction set processor includes on-chip memory, a planar arithmetic unit, a cubic arithmetic unit, a point arithmetic unit, a tensor arithmetic unit, and an instruction controller;

[0012] The on-chip memory directly reads and stores computational data from off-chip memory, and the computational data is used for calculations by the planar arithmetic unit, the cubic arithmetic unit, and the point arithmetic unit.

[0013] The tensor arithmetic unit directly obtains data from off-chip memory and performs swapping, splitting, aggregation, and reverse aggregation operations on the tensor data according to the instruction configuration information from the instruction controller.

[0014] The instruction controller directly retrieves instructions from off-chip memory and sends instruction configuration information to the planar arithmetic unit, cube arithmetic unit, point arithmetic unit, or tensor arithmetic unit according to the instructions.

[0015] Furthermore, the planar arithmetic unit includes a planar multiplication and accumulation unit, a planar comparison and maximum value operation unit, and a planar interpolation unit. The planar arithmetic unit reads data from on-chip memory, and the data passes through the planar multiplication and accumulation unit, the planar comparison and maximum value operation unit, and the planar interpolation unit in a pipelined manner. According to the instruction configuration information from the instruction controller, one or more of the planar multiplication and accumulation operation, the planar comparison and maximum value operation, or the planar interpolation operation are selected for each data. The calculation result of the planar arithmetic unit is sent to the point arithmetic unit.

[0016] Furthermore, the planar operator is used to perform planar operations, the scope of which is a plane in the tensor data, and the planar calculation refers to the operation of all data in the plane corresponding to the coordinates (h,w) of one or two tensors.

[0017] Furthermore, the cube arithmetic unit includes a cube multiplication and accumulation unit and a cube comparison and maximum value operation unit; the cube arithmetic unit reads data from on-chip memory, and the data passes through the cube multiplication and accumulation unit and the cube comparison and maximum value operation unit in a pipelined manner, and according to the instruction configuration information from the instruction controller, selects to perform one or more of the cube multiplication and accumulation operation and the cube comparison and maximum value operation for each data; the calculation result of the cube arithmetic unit is sent to the point arithmetic unit.

[0018] Furthermore, the cube arithmetic unit performs cube operations; the scope of the cube operation is a cube in the tensor data, and the cube operation refers to the operation of all data within the cube corresponding to the coordinates (c,h,w) in one or two tensors.

[0019] Furthermore, the point arithmetic unit includes a multiplication / division unit, an addition / subtraction unit, a maximum / minimum value operation unit, an AND / OR / XOR operation unit, a left / right shift operation unit, a reciprocal square root operation unit, an upper / lower limit operation unit, and a lookup table operation unit. The point arithmetic unit obtains data from the planar arithmetic unit and the cubic arithmetic unit respectively. The data passes through the multiplication / division unit, addition / subtraction unit, maximum / minimum value operation unit, AND / OR / XOR operation unit, left / right shift operation unit, reciprocal square root operation unit, upper / lower limit operation unit, and lookup table operation unit in a pipelined manner. According to the instruction configuration information from the instruction controller, it selects to perform one or more of the following operations on each data: multiplication / division, addition / subtraction, maximum / minimum value operation, AND / OR / XOR operation, left / right shift operation, reciprocal square root operation, upper / lower limit operation, and lookup table operation. The calculation result of the point arithmetic unit is directly written to the off-chip memory.

[0020] Furthermore, the point operator is used to perform point operations, the scope of which is a point in the tensor data, and the point operation refers to the operation of corresponding coordinate data in one or two tensors.

[0021] Furthermore, the instructions are divided into point operation type instructions, planar operation type instructions, cube operation type instructions, and tensor operation type instructions. The instruction controller configures different arithmetic units according to different types of instructions. Point operation type instructions are used to configure point arithmetic units, planar operation type instructions are used to configure planar arithmetic units, cube operation type instructions are used to configure cube arithmetic units, and tensor operation type instructions are used to configure tensor arithmetic units or instruction controllers. The tensor operation type instructions used to configure the instruction controller include direct jump instructions and unequal branch jump instructions.

[0022] Technical effects:

[0023] The simplified dataflow instruction set processor of the present invention has a simplified and limited number of computing types. While possessing general computing characteristics, it can maintain the high efficiency of the dataflow computing architecture, thus having the advantages of high computing power, high clock frequency, and low power consumption. Attached Figure Description

[0024] Figure 1 This is a comparison diagram of instruction-flow computing architecture and dataflow computing architecture;

[0025] Figure 2 This is a system block diagram of the simplified data stream instruction set processor of the present invention;

[0026] Figure 3 This is a system block diagram of a planar arithmetic unit;

[0027] Figure 4 This is an example of planar operations;

[0028] Figure 5 This is a system block diagram of the cube arithmetic unit;

[0029] Figure 6 This is an example of cube operations;

[0030] Figure 7 This is a system block diagram of the dot arithmetic unit;

[0031] Figure 8 This is an example of point arithmetic. Detailed Implementation

[0032] To further illustrate the various embodiments, the present invention provides accompanying drawings. These drawings are part of the disclosure of the present invention, primarily used to illustrate the embodiments, and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these drawings, those skilled in the art should be able to understand other possible implementations and the advantages of the present invention.

[0033] The present invention will now be further described in conjunction with the accompanying drawings and specific embodiments.

[0034] Example 1

[0035] This embodiment presents a simplified dataflow instruction set processor. For example... Figure 2 As shown, it includes circuit logic units such as on-chip memory, planar arithmetic unit, cube arithmetic unit, point arithmetic unit, tensor arithmetic unit, and instruction controller.

[0036] The on-chip memory directly reads and stores computational data from off-chip memory, and the computational data is used for calculations by the planar arithmetic unit, the cubic arithmetic unit, and the point arithmetic unit.

[0037] like Figure 3 As shown, the planar arithmetic unit includes a planar multiplication-accumulation unit, a planar comparison-maximization unit, and a planar interpolation unit. The planar arithmetic unit reads data from on-chip memory. The data is pipelined through the planar multiplication-accumulation unit, the planar comparison-maximization unit, and the planar interpolation unit. Based on instruction configuration information from the instruction controller, one or more of the following operations are performed for each data item: planar multiplication-accumulation, planar comparison-maximization, or planar interpolation. The calculation result of the planar arithmetic unit is sent to the point arithmetic unit.

[0038] The planar arithmetic unit performs planar operations. The scope of these planar operations is a plane within the tensor data; that is, planar operations on one or two tensors are actually operations on all data within the plane corresponding to the (h, w) coordinates of one or two tensors. Figure 4 As shown.

[0039] like Figure 5 As shown, the cube arithmetic unit includes a cube multiplication and accumulation unit and a cube comparison and maximum value operation unit. The cube arithmetic unit reads data from on-chip memory, and the data is pipelined through the cube multiplication and accumulation unit and the cube comparison and maximum value operation unit respectively. Based on the instruction configuration information from the instruction controller, one or more of the cube multiplication and accumulation operation and the cube comparison and maximum value operation are selected for each data item. The calculation result of the cube arithmetic unit is sent to the point arithmetic unit.

[0040] The cube arithmetic unit performs cube operations. The scope of the cube operation is a cube within the tensor data; that is, a cube operation on one or two tensors actually involves the operation of all data within the cube corresponding to the coordinates (c, h, w) of one or two tensors. Figure 6 As shown.

[0041] like Figure 7 As shown, the point arithmetic unit obtains data from the planar arithmetic unit and the cubic arithmetic unit respectively. The data passes through a pipelined multiplication / division unit, addition / subtraction unit, maximum / minimum value operation unit, AND / OR / XOR operation unit, left shift / right shift operation unit, reciprocal square root operation unit, upper and lower limit operation unit, and lookup table operation unit. Based on the instruction configuration information from the instruction controller, it selects one or more of the following operations for each data point: multiplication / division, addition / subtraction, maximum / minimum value operation, AND / OR / XOR operation, left shift / right shift operation, reciprocal square root operation, upper and lower limit operation, and lookup table operation. The calculation result of the point arithmetic unit is directly written to off-chip memory.

[0042] The point arithmetic unit performs point operations. The scope of the point operation is a point within the tensor data; that is, point operations on one or two tensors are actually operations on the corresponding coordinate data within one or two tensors, such as... Figure 8 As shown.

[0043] The tensor arithmetic unit directly retrieves data from off-chip memory and performs swapping, splitting, aggregation, and reverse aggregation operations on the tensor data according to the instruction configuration information from the instruction controller. Swapping refers to changing the data dimension; for example, swapping a tensor of (c,h,w) dimensions to a tensor of (h,w,c) dimensions. Splitting refers to splitting data from one dimension into N dimensions; for example, splitting a tensor of (c,h,w) dimensions into c tensors of (1,h,w) dimensions. Aggregation refers to aggregating data from N dimensions into one dimension at a higher dimension; for example, aggregating c tensors of (1,h,w) dimensions into one tensor of (c,h,w) dimensions. Reverse aggregation refers to aggregating data from N dimensions into one dimension at a lower dimension; for example, reversing the aggregation of c tensors of (1,h,w) dimensions into one tensor of (h,w,c) dimensions.

[0044] The instruction controller retrieves instructions from off-chip memory. These instructions are divided into four categories, totaling 25 instructions: point operation type, planar operation type, cube operation type, and tensor operation type, as shown in Table 1. The instruction controller configures different arithmetic units according to different instruction types. Point operation type instructions are used to configure point arithmetic units, planar operation type instructions are used to configure planar arithmetic units, cube operation type instructions are used to configure cube arithmetic units, and tensor operation type instructions are used to configure tensor arithmetic units or the instruction controller.

[0045] The instruction controller can perform direct jump and unequal branch jump operations according to the instruction, thereby realizing the instruction jump function.

[0046] Table 1 shows the types of instructions that the instruction controller can recognize.

[0047]

[0048]

[0049] In summary, the simplified dataflow instruction set processor of the present invention has simplified and limited computing types, and can maintain the high efficiency of dataflow computing architecture while possessing general computing characteristics, thus having the advantages of high computing power, high clock frequency and low power consumption.

[0050] Although the invention has been specifically shown and described in conjunction with preferred embodiments, those skilled in the art should understand that various changes in form and detail may be made to the invention without departing from the spirit and scope of the invention as defined in the appended claims, all of which shall be within the scope of protection of the invention.

Claims

1. A reduced dataflow instruction set processor, characterized in that: It includes on-chip memory, planar arithmetic unit, cube arithmetic unit, point arithmetic unit, tensor arithmetic unit, and instruction controller; The on-chip memory directly reads and stores computational data from off-chip memory, and the computational data is used for calculations by the planar arithmetic unit, the cubic arithmetic unit, and the point arithmetic unit. The tensor arithmetic unit directly obtains data from off-chip memory and performs swapping, splitting, aggregation, and reverse aggregation operations on the tensor data according to the instruction configuration information from the instruction controller. The instruction controller directly retrieves instructions from off-chip memory and sends instruction configuration information to the planar arithmetic unit, cube arithmetic unit, point arithmetic unit, or tensor arithmetic unit according to the instructions, or executes jump instructions. The planar operator is used to perform planar operations. The scope of the planar operation is a plane in the tensor data. The planar operation refers to the operation of all data in the plane corresponding to the coordinates (h,w) in one or two tensors. The cube arithmetic unit performs cube operations; the scope of the cube operation is a cube in the tensor data, and the cube operation refers to the operation of all data within the cube corresponding to the coordinates (c,h,w) in one or two tensors. The point operator is used to perform point operations, the scope of which is a point in the tensor data, and the point operation refers to the operation of corresponding coordinate data in one or two tensors.

2. The Reduced Data Stream Instruction Set Processor as described in claim 1, characterized in that: The planar arithmetic unit includes a planar multiplication and accumulation unit, a planar comparison and maximum value operation unit, and a planar interpolation unit. The planar arithmetic unit reads data from on-chip memory, and the data passes through the planar multiplication and accumulation unit, the planar comparison and maximum value operation unit, and the planar interpolation unit in a pipelined manner. According to the instruction configuration information from the instruction controller, one or more of the planar multiplication and accumulation operation, the planar comparison and maximum value operation, or the planar interpolation operation are selected for each data. The calculation result of the planar arithmetic unit is sent to the point arithmetic unit.

3. The Reduced Data Stream Instruction Set Processor as described in claim 1, characterized in that: The cube arithmetic unit includes a cube multiplication and accumulation unit and a cube comparison and maximum value operation unit. The cube arithmetic unit reads data from on-chip memory, and the data passes through the cube multiplication and accumulation unit and the cube comparison and maximum value operation unit in a pipelined manner. According to the instruction configuration information from the instruction controller, one or more of the cube multiplication and accumulation operation and the cube comparison and maximum value operation are selected for each data. The calculation result of the cube arithmetic unit is sent to the point arithmetic unit.

4. The Reduced Data Stream Instruction Set Processor as described in claim 1, characterized in that: The point arithmetic unit includes a multiplication / division unit, an addition / subtraction unit, a maximum / minimum value operation unit, an AND / OR / XOR operation unit, a left / right shift operation unit, a square root operation unit, an upper / lower limit operation unit, and a lookup table operation unit. The point arithmetic unit obtains data from the planar arithmetic unit and the cubic arithmetic unit respectively. The data is pipelined through the multiplication / division unit, addition / subtraction unit, maximum / minimum value operation unit, AND / OR / XOR operation unit, left / right shift operation unit, square root operation unit, upper / lower limit operation unit, and lookup table operation unit. Based on the instruction configuration information from the instruction controller, it selects and performs one or more of the following operations for each data point: multiplication / division, addition / subtraction, maximum / minimum value operation, AND / OR / XOR operation, left / right shift operation, square root operation, upper / lower limit operation, and lookup table operation. The calculation result of the point arithmetic unit is directly written to off-chip memory.

5. The Reduced Data Stream Instruction Set Processor as described in claim 1, characterized in that: The instructions are divided into point operation type, planar operation type, cube operation type, and tensor operation type. The instruction controller configures different arithmetic units according to different types of instructions. Point operation type instructions are used to configure point arithmetic units, planar operation type instructions are used to configure planar arithmetic units, cube operation type instructions are used to configure cube arithmetic units, and tensor operation type instructions are used to configure tensor arithmetic units or instruction controllers. The instructions used to configure the instruction controller for tensor operation type instructions include direct jump instructions and unequal branch jump instructions.

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