Silicon wafer impurity removal method, silicon wafer, and preparation method and application thereof

Abstract

The present invention relates to a method for removing impurities from a silicon wafer, a silicon wafer, a preparation method thereof, and an application thereof. The method for removing impurities from a silicon wafer includes the following steps: performing a first texturing treatment on the silicon wafer to prepare a silicon wafer intermediate with a reflectivity of 11% to 35%; preparing an amorphous silicon layer on the silicon wafer intermediate with a reflectivity of 11% to 35%, and doping phosphorus in the amorphous silicon layer; preparing an oxide layer on the amorphous silicon layer to prepare a first intermediate; performing an annealing treatment on the first intermediate to prepare a second intermediate; and performing a second texturing treatment on the second intermediate. This method has the advantages of high impurity absorption efficiency, mild conditions, simple operation, and low cost. Using the silicon wafer after impurity removal in a device can increase light absorption, improve the short-circuit current, open-circuit voltage, and fill factor, and ultimately improve the photoelectric conversion efficiency of the device.

Description

Technical Field

[0001] The present invention relates to the technical field of photovoltaic devices, and particularly relates to a method for removing impurities from silicon wafers, a silicon wafer, a preparation method thereof, and an application thereof. Background Art

[0002] Photovoltaic power generation is a technology that directly converts light energy into electrical energy by utilizing the photovoltaic effect at the semiconductor interface. The key to this technology is the solar cell. Specifically, sunlight shines on the semiconductor pn junction, forming new hole-electron pairs. Under the action of the built-in electric field in the pn junction, holes flow from the N region to the P region, and electrons flow from the P region to the N region. After the circuit is connected, an electric current is formed. The most basic component of photovoltaic power generation is the solar cell (chip), including single-crystalline silicon, polycrystalline silicon, amorphous silicon, and thin-film batteries. Among them, single-crystalline silicon and polycrystalline silicon batteries are the most widely used.

[0003] As the substrate material for making solar cells, silicon wafers have micro-defects and metal impurities. These defects and impurities introduce multiple deep energy levels in the silicon bandgap, becoming recombination centers for minority carriers, which seriously affect the photoelectric conversion efficiency of solar cells. In single-crystalline silicon, due to the interaction between impurities and impurities, and between impurities and defects, heavy metal impurities or micro-defects will migrate and re-aggregate at a certain temperature. Using this phenomenon, mechanical damage, defects, or deposition of a certain thin film is introduced on the back of the silicon wafer for impurity gettering, which is called external gettering; or defects are introduced in the body to make heavy metal impurities concentrate from the working area of the device to these special areas, which is called internal gettering. Traditional gettering methods have problems such as low gettering efficiency, high energy consumption, cumbersome operation, and high cost. Summary of the Invention

[0004] Based on this, it is necessary to provide a method for removing impurities from silicon wafers with high gettering efficiency, mild conditions, simple operation, and low cost, and further obtain silicon wafers, and apply them to photovoltaic devices.

[0005] The technical solution is as follows:

[0006] In one aspect of the present invention, a method for removing impurities from silicon wafers is provided, including the following steps:

[0007] Perform the first texturing treatment on the silicon wafer to prepare a silicon wafer intermediate with a mechanically damaged layer on the surface and a reflectivity of 11% - 35%;

[0008] Prepare an amorphous silicon layer on the silicon wafer intermediate, and dope phosphorus in the amorphous silicon layer;

[0009] Prepare an oxide layer on the amorphous silicon layer to prepare a first intermediate;

[0010] Perform annealing treatment on the first intermediate to prepare a second intermediate;

[0011] Perform a second texturing treatment on the second intermediate.

[0012] In some embodiments, the first texturing treatment is wet texturing.

[0013] In some embodiments, the step of performing a first texturing treatment on the silicon wafer to prepare a silicon wafer intermediate with a reflectivity of 11% to 35% includes the following steps:

[0014] Mix the silicon wafer with a first alkaline solution and perform the first texturing treatment at 50°C to 85°C.

[0015] In some embodiments, the alkali in the first alkaline solution is selected from at least one of sodium hydroxide and potassium hydroxide.

[0016] In some embodiments, the amorphous silicon layer is prepared by chemical vapor deposition, and the process parameters include:

[0017] The temperature is 300°C to 500°C, the working gas flow rate is 8000 sccm to 15000 sccm, the time is 120 s to 900 s, the deposition power is 8500 w to 15000 w, and the furnace tube pressure is 2000 mbar to 3000 mbar.

[0018] In some embodiments, the thickness of the amorphous silicon layer is 30 nm to 200 nm.

[0019] In some embodiments, the percentage of phosphorus element in the amorphous silicon layer is 2% to 60%.

[0020] In some embodiments, the temperature of the annealing treatment is 800°C to 1000°C, and the time is 10 min to 60 min.

[0021] In some embodiments, the oxide layer is prepared by PECVD, and the process parameters include:

[0022] The temperature is 300°C to 500°C, the working gas flow rate is 5000 sccm to 10000 sccm, the time is 30 s to 100 s, and the furnace tube pressure is 1000 mbar to 2000 mbar.

[0023] In some embodiments, the second texturing treatment is wet texturing.

[0024] In some embodiments, performing a second texturing treatment on the second intermediate includes the following steps:

[0025] Mix the second intermediate with an acid solution to prepare a third intermediate;

[0026] Mix the third intermediate with a second alkaline solution and perform the second texturing treatment at 50°C to 85°C so that the reflectivity of the third intermediate is 10% or less.

[0027] In some embodiments, the acid in the acid solution is selected from at least one of hydrofluoric acid, a mixed acid of hydrofluoric acid and nitric acid, and a mixed acid of hydrofluoric acid and hydrochloric acid.

[0028] In some embodiments, the base in the second alkaline solution is selected from at least one of sodium hydroxide and potassium hydroxide.

[0029] In a second aspect of the present invention, there is provided a method for preparing a silicon wafer, comprising the following steps:

[0030] Provide a silicon wafer;

[0031] Perform impurity removal on the silicon wafer by the silicon wafer impurity removal method as described above;

[0032] Perform at least one of diffusion, deposition of an antireflection passivation film, screen printing, and photo-injection annealing on the impurity-removed silicon wafer.

[0033] In a third aspect of the present invention, there is provided a silicon wafer prepared by the method for preparing a silicon wafer as described above.

[0034] In a fourth aspect of the present invention, there is provided a photovoltaic device comprising the silicon wafer as described above.

[0035] In a fifth aspect of the present invention, there is provided a photovoltaic module comprising the photovoltaic device as described above.

[0036] The present invention has at least the following beneficial effects:

[0037] The silicon wafer impurity removal method provided by the present invention includes: performing a first texturing treatment on the silicon wafer to remove surface oil stains and impurities, partially retaining mechanical damage, with a reflectivity of 11% to 35%, as condition 1 for external gettering; then preparing an amorphous silicon layer and simultaneously doping with a phosphorus source, where the amorphous silicon layer serves as condition 2 for external gettering and the phosphorus source doping serves as the condition for internal gettering; then preparing an oxide layer and performing an annealing treatment. During the annealing process, impurities diffuse and accumulate towards the surface gettering region, and then slowly cool down to capture and precipitate the impurities; after annealing, cooperate with a second texturing treatment to remove impurities, improve the surface fuzzing rate of the silicon wafer, make the surface pyramids of the silicon wafer more uniform, reduce the reflectivity, and use the impurity-removed silicon wafer in a device, which can increase light absorption, improve the short-circuit current (Isc), open-circuit voltage (Uoc), and fill factor (FF), and ultimately improve the photoelectric conversion efficiency of the device. Moreover, this method can provide multiple gettering conditions and improve the gettering efficiency. In addition, this method has the advantages of simple process, mild conditions, and low chemical usage cost. Description of the Drawings

[0038] Figure 1 The flowchart of the silicon wafer impurity removal method shown in an embodiment of the present invention. Detailed implementation manners

[0039] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0041] In the case of using "including", "having", and "comprising" described herein, it is intended to cover non-exclusive inclusion. Unless a clear limiting term is used, such as "only", "consisting of", etc., another component may be added.

[0042] In the present invention, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features.

[0043] The terms "preferably", "more preferably", "more preferably", "even more preferably", etc. in the present invention refer to embodiments of the present invention that can provide certain beneficial effects in certain cases. However, in the same or other cases, other embodiments may also be preferred. In addition, the description of one or more preferred embodiments does not imply that other embodiments are not available, nor is it intended to exclude other embodiments from the scope of the present invention. That is, in the present invention, "preferably", "more preferably", "more preferably", "even more preferably", etc. are only used to describe embodiments or examples with better effects, but do not constitute a limitation on the protection scope of the present invention. In the present invention, "further", "even further", "especially", etc. are used for descriptive purposes and indicate differences in content, but should not be understood as a limitation on the protection scope of the present invention.

[0044] In the present invention, the meaning of "at least one" is more than one, such as one, two or more. The meaning of "multiple" or "several" is at least two, such as two, three, etc. The meaning of "multiple layers" is at least two layers, such as two layers, three layers, etc., unless otherwise specifically defined. In the description of the present invention, the meaning of "a number of" is at least one, such as one, two, etc., unless otherwise specifically defined.

[0045] When a numerical range is disclosed in the present invention, the above range is considered continuous and includes the minimum and maximum values of the range, as well as each value between such minimum and maximum values. Further, when the range refers to integers, it includes each integer between the minimum and maximum values of the range. In addition, when multiple ranges are provided to describe features or characteristics, the ranges can be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all sub-ranges subsumed therein. And only some numerical ranges are specifically disclosed herein. However, any lower limit can be combined with any upper limit to form a range not explicitly recited; and any lower limit can be combined with other lower limits to form a range not explicitly recited, and similarly any upper limit can be combined with any other upper limit to form a range not explicitly recited. In addition, each individually disclosed point or single numerical value itself can be used as a lower or upper limit and combined with any other point or single numerical value or combined with other lower or upper limits to form a range not explicitly recited.

[0046] If there is no special instruction, all steps of the present invention can be carried out in sequence or randomly. For example, the method includes steps (a) and (b), which means that the method can include steps (a) and (b) carried out in sequence, or can also include steps (b) and (a) carried out in sequence. For example, it is mentioned that the method may further include step (c), which means that step (c) can be added to the method in any order. For example, the method can include steps (a), (b) and (c) in sequence, or can also include steps (a), (c) and (b), or can also include steps (c), (a) and (b), etc.

[0047] Unless otherwise mentioned, terms in the singular form may include the plural form and should not be construed as having a quantity of one.

[0048] The temperature parameter in the present invention, unless otherwise specifically limited, allows both constant temperature treatment and treatment within a certain temperature range. The constant temperature treatment allows the temperature to fluctuate within the accuracy range controlled by the instrument.

[0049] In the embodiments of the specification of the present invention, the weight of the relevant components mentioned not only refers to the specific content of each component, but also represents the proportional relationship of the weights between the components. Therefore, as long as the content of the relevant components in the embodiments of the specification of the present invention is scaled up or down in proportion, it is within the scope disclosed in the embodiments of the specification of the present invention. Specifically, the weight described in the embodiments of the specification of the present invention can be mass units well-known in the chemical industry such as μg, mg, g, kg, etc.

[0050] In the present invention, for the unit of the data range, if there is only a unit after the right endpoint, it means that the units of the left endpoint and the right endpoint are the same. For example, 800~850nm means that the units of the left endpoint "800" and the right endpoint "850" are both nm (nanometers).

[0051] In the present invention, "above" or "below" both include the number itself. For example, below 1 means less than or equal to 1 (≤1), and above 1 means greater than or equal to 1 (≥1).

[0052] In the present invention, room temperature refers to 10℃~40℃, preferably 20℃~30℃, and more preferably 25±2℃.

[0053] The gas-phase deposition method described in the present invention is preferably a plasma-enhanced chemical vapor deposition method (PECVD).

[0054] In addition, the drawings are not drawn to a scale of 1:1, and the relative sizes of the components are only drawn exemplarily in the drawings for the convenience of understanding the present invention, but not necessarily drawn according to the actual scale. The scale in the drawings does not constitute a limitation to the present invention.

[0055] The gettering technique is a very effective method to reduce the contamination in the processing of silicon wafers and device processes and improve the performance of devices. By utilizing the characteristic that impurities gather in the region with lattice imperfections to introduce defects to form an impurity-rich region, and then removing this layer of impurity-rich damaged region, the purpose of removing some impurities in the silicon wafer can be achieved, reducing the recombination centers of minority carriers in the silicon wafer, increasing the short-circuit current of the battery, and thus improving the photoelectric conversion efficiency of the solar cell. In order to reduce the cost of silicon wafers and maximize the utilization rate of silicon rods, gettering is performed on the silicon wafers with poor quality after back-cutting, which can reduce the cost at the end of the silicon wafer and improve the battery efficiency at the same time.

[0056] Currently, a scheme for internal gettering of silicon wafers using a phosphorus diffusion process has been reported. It mainly includes putting the cleaned and textured silicon wafers into a diffusion furnace, introducing nitrogen, oxygen, and phosphorus oxychloride, and performing diffusion at high temperature. The diffusion is carried out in three depositions, with a certain time of promotion after each deposition, and then cooling to room temperature. This scheme can improve the average conversion efficiency of solar cells. Or a phosphorus diffusion gettering process for silicon wafers used in manufacturing solar cells mainly includes coating a phosphorus source on the surface of the silicon wafer or carrying POCl3 into the diffusion furnace tube by a carrier gas. Under the atmosphere of a protective gas, the silicon wafer is kept at 800 - 1050 °C for 10 - 60 minutes, then the silicon wafer is kept at 500 - 800 °C for 20 - 60 minutes, and after cooling, the phosphosilicate glass layer is removed. This scheme adopts the method of variable-temperature gettering, combining the advantages that impurities are easily dissolved and released at high temperature and are effectively captured by the gettering layer at a lower temperature, and can effectively reduce the content of metal impurities in the silicon matrix and improve the light conversion efficiency of solar cells. However, the above schemes all use a diffusion process or a coating process for phosphorus source diffusion gettering, and phosphorus diffusion is carried out under high-temperature conditions and the main method is internal gettering, so the preparation process takes a long time and the cost is high.

[0057] Based on this, the present invention provides a method for removing impurities from silicon wafers with high gettering efficiency, mild conditions, simple operation, and low cost.

[0058] The technical solution is as follows:

[0059] See Figure 1 , the method for removing impurities from silicon wafers shown in an embodiment of the present invention includes the following steps:

[0060] Perform a first texturing treatment on the silicon wafer to prepare a silicon wafer intermediate with a mechanically damaged layer on the surface and a reflectivity of 11% - 35%.

[0061] Prepare an amorphous silicon layer on the silicon wafer intermediate and dope phosphorus in the amorphous silicon layer.

[0062] Prepare an oxide layer on the amorphous silicon layer to prepare a first intermediate.

[0063] Perform an annealing treatment on the first intermediate to prepare a second intermediate.

[0064] Perform a second texturing treatment on the second intermediate.

[0065] The silicon wafer is subjected to a first texturing treatment to remove the oil stains and impurities on the surface, and part of the mechanical damage is retained (the reflectivity is 11% - 35%), which serves as condition 1 for external gettering; then an amorphous silicon layer is prepared, and doping with a phosphorus source is carried out synchronously. Among them, the amorphous silicon layer serves as condition 2 for external gettering, and the phosphorus source doping serves as the condition for internal gettering; then an oxide layer is prepared and annealing treatment is carried out. During the annealing process, the impurities diffuse and accumulate towards the gettering area on the surface, and then the temperature is slowly decreased to capture and precipitate the impurities; after annealing, a second texturing treatment is carried out to remove the impurities, improve the surface hairiness rate of the silicon wafer, make the pyramids on the silicon wafer surface more uniform, reduce the reflectivity, and use the impurity-removed silicon wafer in the device, which can increase light absorption, improve the short-circuit current (Isc), open-circuit voltage (Uoc) and fill factor (FF), and finally improve the photoelectric conversion efficiency of the device. Moreover, this method can provide various gettering conditions and improve the gettering efficiency. In addition, this method has the advantages of simple process, mild conditions, and low chemical usage cost.

[0066] The method for removing impurities from the silicon wafer according to the present invention will be further described below.

[0067] S100: Perform a first texturing treatment on the silicon wafer to prepare an intermediate silicon wafer with a mechanically damaged layer on the surface and a reflectivity of 11% - 35%

[0068] In the traditional method for removing impurities from silicon wafers, the reflectivity of the silicon wafer after texturing treatment is usually below 10%, and it is difficult to be used as an external gettering condition subsequently. However, in the present invention, through the first texturing treatment, the oil stains and impurities on the surface are removed, and then a micro-roughened surface is prepared, and part of the mechanically damaged layer (referred to as the micro-roughened surface) is retained, so that the reflectivity of the silicon wafer is 11% - 35%, which serves as condition 1 for external gettering and improves the gettering effect.

[0069] In some embodiments, the first texturing treatment is a wet texturing. The wet texturing mainly includes acid etching and alkaline etching methods. Among them, ① Acid etching method: mainly uses an acid (such as a mixed acid of hydrofluoric acid and nitric acid) to react with the silicon wafer at a certain temperature, the silicon-hydrogen bonds on the silicon wafer surface are broken, and a roughened surface is generated on the silicon wafer surface. ② Alkaline etching method: mainly uses an alkali (such as sodium hydroxide solution) to etch the silicon wafer at a certain temperature.

[0070] In some embodiments, the step of performing a first texturing treatment on the silicon wafer to prepare an intermediate silicon wafer with a mechanically damaged layer on the surface and a reflectivity of 11% - 35% includes the following steps:

[0071] Mix the silicon wafer with a first alkaline solution, and perform the first texturing treatment at 50°C - 85°C to prepare an intermediate silicon wafer with a mechanically damaged layer on the surface and a reflectivity of 11% - 35%.

[0072] Understandably, the temperature of the first texturing treatment includes but is not limited to 50°C, 55°C, 60°C, 65°C, 70°C, 75°C, 80°C or 85°C.

[0073] In some of these embodiments, the base in the first lye is selected from at least one of sodium hydroxide and potassium hydroxide. Preferably, the base in the first lye is sodium hydroxide.

[0074] Understandably, in the present invention, for the silicon wafer after the first texturing treatment, its reflectivity is 11% - 35%, including but not limited to 11%, 12%, 15%, 16%, 18%, 19%, 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29%, 30%, 31%, 32%, 33%, 34% or 35%. Preferably, for the silicon wafer after the first texturing treatment, its reflectivity is 15% - 25%.

[0075] S200: Prepare an amorphous silicon layer on the silicon wafer intermediate, and dope phosphorus in the amorphous silicon layer.

[0076] A phosphorus-doped layer is formed on the silicon wafer surface, and then impurity atoms are absorbed and fixed in the doped layer through migration and diffusion. The amorphous silicon layer serves as the external gettering condition 2, and phosphorus source doping serves as the internal gettering condition to improve the gettering effect.

[0077] In some of these embodiments, an amorphous silicon layer is prepared on the silicon wafer intermediate with a reflectivity of 11% - 35% by chemical vapor deposition. Further, the amorphous silicon layer is prepared by PECVD, and the process parameters include:

[0078] The temperature is 300°C - 500°C, the working gas flow rate is 8000 sccm - 15000 sccm, the time is 120 s - 900 s, the deposition power is 8500 w - 15000 w, and the furnace tube pressure is 2000 mbar - 3000 mbar.

[0079] Compared with conventional phosphorus diffusion, the present invention has a lower temperature. At the same time, due to the preparation of the micro-textured surface, the deposition of the amorphous silicon layer, and the introduction of the phosphorus dopant, multiple conditions are provided for gettering, greatly improving the subsequent gettering effect.

[0080] Understandably, during the preparation of the amorphous silicon layer by PECVD, the temperature includes but is not limited to 300 °C, 350 °C, 400 °C, 450 °C or 500 °C; the working gas flow rate is 8000 sccm, 9000 sccm, 10000 sccm, 11000 sccm, 12000 sccm, 13000 sccm, 14000 sccm or 15000 sccm; the time includes but is not limited to 120 s, 150 s, 200 s, 200 s, 300 s, 400 s, 500 s, 600 s, 700 s, 800 s or 900 s; the deposition power includes but is not limited to 8500 w, 9000 w, 9500 w, 10000 w, 10500 w, 11000 w, 12000 w, 13000 w, 14000 w or 15000 w; the furnace tube pressure includes but is not limited to 2000 mbar, 2200 mbar, 2400 mbar, 2500 mbar, 2600 mbar, 2800 mbar or 3000 mbar.

[0081] In some embodiments, the thickness of the amorphous silicon layer is 30 nm to 200 nm, including but not limited to 30 nm, 40 nm, 50 nm, 70 nm, 80 nm, 90 nm, 100 nm, 120 nm, 150 nm or 200 nm.

[0082] In some embodiments, the percentage of phosphorus element in the amorphous silicon layer is 2% to 60%, including but not limited to 2%, 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55% or 60%.

[0083] S300: Prepare an oxide layer on the amorphous silicon layer to prepare a first intermediate.

[0084] In one embodiment, the material of the oxide layer is silicon oxide.

[0085] In one embodiment, the thickness of the oxide layer is 7 nm to 50 nm, including but not limited to 7 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm or 50 nm.

[0086] In one embodiment, the oxide layer is prepared on the amorphous silicon layer by chemical vapor deposition. Further, the oxide layer is prepared by PECVD, and the process parameters include:

[0087] The temperature is 300 °C to 500 °C, the working gas flow rate is 5000 sccm to 10000 sccm, the time is 30 s to 100 s, and the furnace tube pressure is 1000 mbar to 2000 mbar.

[0088] Understandably, during the process of preparing the oxide layer by PECVD, the temperature includes but is not limited to 300 °C, 350 °C, 400 °C, 450 °C or 500 °C; the working gas flow rate is 5000 sccm, 6000 sccm, 7000 sccm, 8000 sccm, 9000 sccm or 10000 sccm; the time includes but is not limited to 30 s, 50 s, 60 s, 80 s, 90 s or 100 s; the furnace tube pressure includes but is not limited to 1000 mbar, 1200 mbar, 1400 mbar, 12500 mbar, 1600 mbar, 1800 mbar or 2000 mbar.

[0089] S400: Anneal the first intermediate to prepare a second intermediate.

[0090] During the annealing process, impurities diffuse and aggregate towards the surface gettering region, and then the temperature is slowly decreased for impurity capture and precipitation, improving the gettering effect.

[0091] In some embodiments, the temperature of the annealing treatment is 800 °C to 1000 °C, including but not limited to 800 °C, 850 °C, 900 °C, 950 °C or 1000 °C.

[0092] In some embodiments, the time of the annealing treatment is 10 min to 60 min, including but not limited to 10 min, 15 min, 20 min, 25 min, 30 min, 35 min, 40 min, 45 min, 50 min, 55 min or 60 min.

[0093] S500: Perform a second texturing treatment on the second intermediate.

[0094] By the second texturing treatment, impurities are removed, the surface fuzzing rate of the silicon wafer is increased, the pyramids on the silicon wafer surface become more uniform, the reflectivity is reduced. Subsequently, the impurity-removed silicon wafer is used in the device, which can increase light absorption, improve the short-circuit current (Isc), open-circuit voltage (Uoc) and fill factor (FF), and ultimately improve the photoelectric conversion efficiency of the device. Preferably, the reflectivity of the product after the second intermediate is textured is < 10%.

[0095] In some embodiments, the method of the second texturing treatment is wet texturing. Referring to the above, wet texturing mainly includes acid etching and alkaline etching methods.

[0096] In some embodiments, performing the second texturing treatment on the second intermediate includes the following steps:

[0097] Mix the second intermediate with an acid solution to prepare a third intermediate;

[0098] Mix the third intermediate with a second alkaline solution and perform the second texturing treatment at 50°C to 85°C, so that the reflectivity of the third intermediate is 10% or less.

[0099] In some embodiments, the acid in the acid solution is selected from at least one of hydrofluoric acid, a mixed acid of nitric acid and hydrofluoric acid, and a mixed acid of hydrochloric acid and hydrofluoric acid.

[0100] In some embodiments, the base in the second alkaline solution is selected from at least one of sodium hydroxide and potassium hydroxide. Preferably, the base in the second alkaline solution is sodium hydroxide.

[0101] The present invention also provides a method for preparing a silicon wafer, comprising the following steps:

[0102] Dope the silicon wafer by the above-mentioned silicon wafer doping method;

[0103] Perform at least one of diffusion, deposition of an antireflection passivation film, screen printing, and photo-injection annealing on the doped silicon wafer.

[0104] The present invention also provides a silicon wafer prepared by the above-mentioned method for preparing a silicon wafer.

[0105] The present invention also provides a photovoltaic device comprising the above-mentioned silicon wafer.

[0106] The present invention also provides a photovoltaic module comprising the above-mentioned photovoltaic device.

[0107] In order to make the objectives, technical solutions, and advantages of the present invention more concise and clear, the present invention is illustrated by the following specific embodiments, but the present invention is by no means limited to these embodiments. The following described embodiments are only preferred embodiments of the present invention and can be used to describe the present invention, and should not be construed as a limitation on the scope of the present invention. It should be noted that any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention should be included within the protection scope of the present invention.

[0108] The following are specific embodiments:

[0109] Example 1

[0110] This example provides a polycrystalline silicon photovoltaic device and its preparation method, specifically as follows:

[0111] (1) The bare silicon wafer is first alkali-washed with sodium hydroxide to remove the oil and impurities on the surface, and then the preparation of a micro-textured surface is carried out, retaining part of the mechanical damage layer, and the reflectivity of the silicon wafer surface is prepared within the range of 10% to 20% at 80°C; the main purpose of this step is the cleaning of the silicon wafer and the preparation of the micro-textured surface;

[0112] (2) Subsequently, it enters the PECVD machine to prepare an n+ amorphous silicon with a thickness of 50 nm and a phosphorus doping concentration of 5%, and a 30-nm-thick oxide layer. The process parameters for depositing the amorphous silicon layer are as follows: temperature is 400 °C, working gas flow rate is 12000 sccm, time is 300 s, deposition power is 9500 w, and furnace tube pressure is 2500 mbar; the process parameters for depositing the oxide layer are: temperature is 400 °C, working gas flow rate is 7500 sccm, time is 30 s, and furnace tube pressure is 1200 mbar;

[0113] (3) After the film layer preparation is completed, the silicon wafer is sent to an annealing furnace for thermal annealing at 900 °C for 30 min. Under this condition, the internal impurities and defects diffuse and accumulate towards the surface layer of the silicon wafer; subsequently, a slow cooling step is carried out to enable the impurities to remain deposited in the impurity layer;

[0114] (4) The silicon wafer is pickled with hydrofluoric acid to remove the surface oxide impurity layer;

[0115] (5) The pickled silicon wafer is re-textured with sodium hydroxide. During this process, the poly impurity layer on the silicon wafer surface is removed, and at the same time, the secondary texturing of the micro-textured surface is achieved. The reflectivity is controlled at about 9.8%, making the surface texture more uniform, reducing light reflection, and improving the light absorption effect;

[0116] (6) The silicon wafer undergoes the preparation turnover of the normal battery process.

[0117] Example 2

[0118] This example provides a polycrystalline silicon photovoltaic device and its preparation method, which are as follows:

[0119] (1) The bare silicon wafer is first alkali-washed with sodium hydroxide to remove the surface oil and impurities, and then the micro-textured surface is prepared, retaining part of the mechanical damage layer. The reflectivity of the silicon wafer surface is prepared within the range of 20% - 35% at 75 °C; the main purpose of this step is the cleaning and micro-texturing of the silicon wafer;

[0120] (2) Subsequently, it enters the PECVD machine to prepare an n+ amorphous silicon with a thickness of 50 nm and a phosphorus doping concentration of 5%, and a 30-nm-thick oxide layer. The process parameters for depositing the amorphous silicon layer are as follows: temperature is 400 °C, working gas flow rate is 12000 sccm, time is 300 s, deposition power is 9500 w, and furnace tube pressure is 2500 mbar; the process parameters for depositing the oxide layer are: temperature is 400 °C, working gas flow rate is 7500 sccm, time is 30 s, and furnace tube pressure is 1200 mbar;

[0121] (3) After the film layer preparation is completed, the silicon wafer is sent to an annealing furnace for thermal annealing at 900 °C for 30 minutes. Under these conditions, the internal impurities and defects diffuse and aggregate towards the surface layer of the silicon wafer; subsequently, a slow cooling step is carried out to allow the impurities to remain deposited in the impurity layer;

[0122] (4) The silicon wafer is pickled with hydrofluoric acid to remove the surface oxidation impurity layer;

[0123] (5) The pickled silicon wafer is re-textured with sodium hydroxide. During this process, the poly impurity layer on the silicon wafer surface is removed, and at the same time, the secondary texturing of the micro-roughened surface is achieved. The reflectivity is controlled at about 9.6%, making the surface roughened surface more uniform, reducing light reflection, and improving the light absorption effect;

[0124] (6) The silicon wafer undergoes the preparation turnover of the normal battery process.

[0125] Example 3

[0126] This example provides a polycrystalline silicon photovoltaic device and its manufacturing method, as follows:

[0127] (1) The bare silicon wafer is first pickled with sodium hydroxide to remove the surface oil and impurities, and then the micro-roughened surface is prepared, retaining part of the mechanical damage layer. The reflectivity of the silicon wafer surface is prepared within the range of 20% - 35% at 75 °C; the main purpose of this step is the cleaning and micro-roughened surface preparation of the silicon wafer;

[0128] (2) Subsequently, it enters a PECVD machine to prepare an n+ amorphous silicon with a thickness of 50 nm and a phosphorus doping concentration of 5% and an oxide layer with a thickness of 30 nm. The process parameters for depositing the amorphous silicon layer are: temperature 400 °C, working gas flow rate 12000 sccm, time 300 s, deposition power 9500 w, and furnace tube pressure 2500 mbar; the process parameters for depositing the oxide layer are: temperature 400 °C, working gas flow rate 7500 sccm, time 30 s, and furnace tube pressure 1200 mbar;

[0129] (3) After the film layer preparation is completed, the silicon wafer is sent to an annealing furnace for thermal annealing at 840 °C for 30 minutes. Under these conditions, the internal impurities and defects diffuse and aggregate towards the surface layer of the silicon wafer; subsequently, a slow cooling step is carried out to allow the impurities to remain deposited in the impurity layer;

[0130] (4) The silicon wafer is pickled with hydrofluoric acid to remove the surface oxidation impurity layer;

[0131] (5) The pickled silicon wafer is re-textured with sodium hydroxide. During this process, the poly impurity layer on the silicon wafer surface is removed, and at the same time, the secondary texturing of the micro-roughened surface is achieved. The reflectivity is controlled at about 9.3%, making the surface roughened surface more uniform, reducing light reflection, and improving the light absorption effect;

[0132] (6) The silicon wafers are prepared and circulated through the normal cell process.

[0133] Example 4

[0134] This example provides a polysilicon photovoltaic device and its preparation method, which are as follows:

[0135] (1) The bare silicon wafers are first alkali-washed with sodium hydroxide to remove the oil stains and impurities on the surface, and then the micro-textured surface is prepared, retaining part of the mechanical damage layer. The surface reflectivity of the silicon wafers is prepared within the range of 20% - 35% at 75°C; the main purpose of this step is the cleaning of the silicon wafers and the preparation of the micro-textured surface.

[0136] (2) Subsequently, the wafers enter the PECVD machine to prepare an n+-amorphous silicon layer with a thickness of 80 nm and a phosphorus doping concentration of 8% and an oxide layer with a thickness of 30 nm. The process parameters for depositing the amorphous silicon layer are: temperature 400°C, working gas flow rate 12000 sccm, time 500 s, deposition power 9500 w, and furnace tube pressure 2500 mbar; the process parameters for depositing the oxide layer are: temperature 400°C, working gas flow rate 7500 sccm, time 30 s, and furnace tube pressure 1200 mbar.

[0137] (3) After the film layer preparation, the silicon wafers are sent to an annealing furnace for thermal annealing at 900°C for 30 min. Under this condition, the internal impurities and defects diffuse and aggregate towards the surface layer of the silicon wafers; subsequently, a slow cooling step is carried out to enable the impurities to remain deposited in the impurity layer.

[0138] (4) The silicon wafers are pickled with hydrofluoric acid to remove the oxide impurity layer on the surface.

[0139] (5) The pickled silicon wafers are re-textured with sodium hydroxide. During this process, the poly impurity layer on the surface of the silicon wafers is removed, and the secondary texturing of the micro-textured surface is synchronously achieved. The reflectivity is controlled at about 9.5%, making the surface texture more uniform, reducing light reflection, and improving the light absorption effect.

[0140] (6) The silicon wafers are prepared and circulated through the normal cell process.

[0141] Comparative Example 1

[0142] This comparative example provides a polysilicon photovoltaic device and its preparation method, which are as follows:

[0143] (1) The bare silicon wafers are first alkali-washed with sodium hydroxide to remove the oil stains and impurities on the surface, and then the micro-textured surface is prepared, retaining part of the mechanical damage layer. The surface reflectivity of the silicon wafers is prepared at about 20% - 35% at 75°C; the main purpose of this step is the cleaning of the silicon wafers and the removal of part of the mechanical damage layer.

[0144] (2) Subsequently, the silicon wafer is sent to an annealing furnace for thermal annealing at 840 °C for 40 min;

[0145] (4) The silicon wafer is pickled with hydrofluoric acid to remove the surface oxide impurity layer;

[0146] (5) The pickled silicon wafer is re-textured with sodium hydroxide. During this process, the poly impurity layer on the silicon wafer surface is removed, and secondary texturing of the micro-textured surface is synchronously achieved. The reflectivity is controlled at about 9.8%, making the surface texture more uniform, reducing light reflection, and improving the light absorption effect;

[0147] (6) The silicon wafer undergoes the preparation turnover of the normal battery process.

[0148] Comparative Example 2

[0149] This comparative example provides a polycrystalline silicon photovoltaic device and its preparation method, which are as follows:

[0150] (1) The bare silicon wafer is normally textured;

[0151] (2) Subsequently, it enters a PECVD machine to prepare an n+-amorphous silicon with a thickness of 50 nm and a phosphorus doping concentration of 5% and an oxide layer with a thickness of 30 nm. The process parameters for depositing the amorphous silicon layer are: temperature of 400 °C, working gas flow rate of 12000 sccm, time of 300 s, deposition power of 9500 w, and furnace tube pressure of 2500 mbar; the process parameters for depositing the oxide layer are: temperature of 400 °C, working gas flow rate of 7500 sccm, time of 30 s, and furnace tube pressure of 1200 mbar;

[0152] (3) After the film layer preparation is completed, the silicon wafer is sent to an annealing furnace for thermal annealing at 840 °C for 40 min;

[0153] (4) The silicon wafer is pickled with hydrofluoric acid to remove the surface oxide impurity layer;

[0154] (5) The pickled silicon wafer is re-textured with sodium hydroxide. During this process, the poly impurity layer on the silicon wafer surface is removed, and secondary texturing of the micro-textured surface is synchronously achieved. The reflectivity is controlled at about 9.2%, making the surface texture more uniform, reducing light reflection, and improving the light absorption effect;

[0155] (6) The silicon wafer undergoes the preparation turnover of the normal battery process.

[0156] Comparative Example 3

[0157] This comparative example provides a polycrystalline silicon photovoltaic device and its preparation method, which are as follows:

[0158] (1) The bare silicon wafer is first alkali-washed with sodium hydroxide to remove the oil and impurities on the surface. Subsequently, the preparation of a micro-textured surface is carried out, and part of the mechanical damage layer is retained. The reflectivity of the silicon wafer surface is prepared at about 20% - 35% at 75°C. The main purpose of this step is the cleaning of the silicon wafer and the preparation of the micro-textured surface;

[0159] (2) Subsequently, it enters the PECVD machine to prepare an n+-amorphous silicon with a thickness of 50 nm and a phosphorus doping concentration of 5% and an oxide layer with a thickness of 30 nm. The process parameters for depositing the amorphous silicon layer are: temperature is 400°C, working gas flow rate is 12000 sccm, time is 300 s, deposition power is 9500 w, and the furnace tube pressure is 2500 mbar; the process parameters for depositing the oxide layer are: temperature is 400°C, working gas flow rate is 7500 sccm, time is 30 s, and the furnace tube pressure is 1200 mbar;

[0160] (3) After the film layer preparation is completed, the silicon wafer is pickled with hydrofluoric acid to remove the oxide impurity layer on the surface;

[0161] (5) The pickled silicon wafer is re-textured with sodium hydroxide. During this process, the poly impurity layer on the silicon wafer surface is removed, and at the same time, the secondary texturing of the micro-textured surface is achieved. The reflectivity is controlled at about 9.2%, making the surface texture more uniform, reducing light reflection, and improving the light absorption effect;

[0162] (6) The silicon wafer undergoes the preparation and turnover of the normal battery process.

[0163] Comparative Example 4

[0164] The bare silicon wafer without impurity removal treatment is used for the preparation and turnover of the normal battery process.

[0165] Testing

[0166] The electrical performance is tested by simulating light to test the conversion efficiency of the solar cell. The measurement is carried out using a Halm tester under the conditions of a spectral irradiance of 1000 w / m 2 , a spectrum of AM1.5, and a cell temperature of 25°C. The test results are shown in Table 1 below.

[0167] Table 1

[0168]

[0169] As can be seen from Table 1, the solar cell prepared from the gettering-treated silicon wafer has increased light absorption, the short-circuit current has increased, and at the same time, the internal impurities have decreased, and both the bulk passivation effect and the FF have been improved, with a strong efficiency gain.

[0170] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as falling within the scope described in this specification.

[0171] The above-described embodiments merely represent several implementation manners of the present invention, which are convenient for understanding the technical solutions of the present invention specifically and in detail, but should not be construed as a limitation on the protection scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. It should be understood that the technical solutions obtained by those skilled in the art through logical analysis, reasoning or limited experiments based on the technical solutions provided by the present invention are all within the protection scope of the appended claims of the present invention. Therefore, the protection scope of this invention patent shall be subject to the content of the appended claims, and the description and drawings can be used to explain the content of the claims.

Claims

1. A method for removing impurities from a silicon wafer, characterized in that, It includes the following steps: Perform a first texturing treatment on the silicon wafer to prepare a silicon wafer intermediate with a mechanically damaged layer on the surface and a reflectivity of 11% to 35%; Prepare an amorphous silicon layer on the silicon wafer intermediate and dope phosphorus in the amorphous silicon layer; Prepare an oxide layer on the amorphous silicon layer to prepare a first intermediate; Perform an annealing treatment on the first intermediate to prepare a second intermediate; Perform a second texturing treatment on the second intermediate; Among them, performing the second texturing treatment on the second intermediate includes the following steps: Mix the second intermediate with an acid solution to prepare a third intermediate; Mix the third intermediate with a second alkali solution to perform the second texturing treatment.

2. The silicon wafer impurity removal method according to claim 1, wherein The method of the first texturing treatment is wet texturing.

3. The silicon wafer impurity removal method according to claim 2, wherein, Performing the first texturing treatment on the silicon wafer to prepare a silicon wafer intermediate with a reflectivity of 11% to 35% includes the following steps: Mix the silicon wafer with a first alkali solution and perform the first texturing treatment under the condition of 50°C to 85°C.

4. The wafer impurity removal method according to claim 3, wherein, The alkali in the first alkali solution is selected from at least one of sodium hydroxide and potassium hydroxide.

5. The silicon wafer impurity removal method according to claim 1, characterized in that, Prepare the amorphous silicon layer by PECVD method, and the process parameters include: The temperature is 300°C to 500°C, the working gas flow rate is 8000 sccm to 15000 sccm, the time is 120 s to 900 s, the deposition power is 8500 w to 15000 w, and the furnace tube pressure is 2000 mbar to 3000 mbar.

6. The wafer impurity removal method according to claim 1, wherein, Meet at least one of the following (1) to (2): (1) The thickness of the amorphous silicon layer is 30 nm to 200 nm; (2) The percentage of phosphorus element in the amorphous silicon layer is 2% to 60%.

7. The method for removing impurities from a silicon wafer according to claim 1, wherein, The temperature of the annealing treatment is 800°C to 1000°C, and the time is 10 min to 60 min.

8. The silicon wafer impurity removal method according to any one of claims 1 to 7, characterized in that, Prepare the oxide layer by PECVD, and the process parameters include: The temperature is 300°C to 500°C, the working gas flow rate is 5000 sccm to 10000 sccm, the time is 30 s to 100 s, and the furnace tube pressure is 1000 mbar to 2000 mbar.

9. The method for removing impurities from a silicon wafer according to any one of claims 1 to 7, characterized in that, Mix the third intermediate with a second alkali solution, and the temperature for performing the second texturing treatment is 50°C to 85°C.

10. The wafer impurity removal method according to claim 9, wherein After the second texturing treatment, the reflectivity of the third intermediate is 10% or less.

11. The wafer impurity removal method according to any one of claims 1 to 7 and 10, characterized in that, The acid in the acid solution is selected from at least one of hydrofluoric acid, a mixed acid of hydrofluoric acid and nitric acid, and a mixed acid of hydrofluoric acid and hydrochloric acid.

12. The wafer impurity removal method according to any one of claims 1 to 7 and 10, characterized in that, The alkali in the second alkali solution is selected from at least one of sodium hydroxide and potassium hydroxide.

13. A method for preparing a silicon wafer, characterized in that, It includes the following steps: Perform impurity removal on the silicon wafer by the silicon wafer impurity removal method according to any one of claims 1 to 12; Perform at least one of diffusion, deposition of an antireflection passivation film, screen printing, and photo-injection annealing on the silicon wafer after impurity removal.

14. A silicon wafer, characterized in that, Obtained according to the method for preparing a silicon wafer as claimed in claim 13.

15. A photovoltaic device, characterized in that, It includes the silicon wafer as claimed in claim 14.

16. A photovoltaic module, characterized in that, It includes the photovoltaic device as claimed in claim 15.

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