A high-performance phase-locked loop based on dual-enhanced second-order generalized integrators

Abstract

The present invention provides a high-performance phase-locked loop based on a dual-enhanced second-order generalized integrator, which belongs to the technical field related to grid voltage phase signal detection and extraction. In order to solve the problem that traditional phase-locked loops cannot achieve satisfactory performance under unbalanced and distorted grid conditions, the present invention proposes a high-performance phase-locked loop based on a dual-enhanced second-order generalized integrator. In order to enhance the anti-interference performance of the phase-locked loop, the present invention designs an enhanced second-order generalized integrator that can effectively eliminate DC offset voltage, and constructs a dual-enhanced second-order generalized integrator. At the same time, the dual-enhanced second-order generalized integrator and the sliding average filter are integrated into an integrated filter, and finally a high-performance three-phase grid-connected phase-locked loop is designed based on the integrated filter, which achieves the purpose of accurately locking the grid voltage phase under non-ideal grid conditions. The present invention is mainly used in the process of grid-connected synchronous application of renewable energy.

Description

Technical Field

[0001] The present invention belongs to the technical field related to detection and extraction of power grid voltage phase signals, and in particular relates to a high-performance phase-locked loop based on a dual-enhanced second-order generalized integrator. Background Art

[0002] Renewable energy, such as wind and solar power, is growing in popularity due to its environmentally friendly properties. Grid-connected converters (GCs) are used to inject the generated energy into the public grid. However, all GCs must be precisely synchronized with the grid voltage to ensure high-quality integration of renewable energy. Accurately detecting the grid's fundamental positive-sequence voltage component is crucial when synchronizing three-phase grid-connected converters.

[0003] The most common and easily implemented algorithm for grid synchronization is phase-locked loop technology. Phase-locked loops (PLLs) are crucial for many important tasks, including active and reactive power control, voltage regulation, voltage sag and flicker compensation, grid monitoring, smart grid control functions, fault ride-through, and current control. Among existing PLL technologies, the synchronized reference frame phase-locked loop (SRF-PLL) is the most commonly used in power engineering applications due to its simple structure and stable performance. It can accurately obtain information about the grid's essential positive-sequence voltage component.

[0004] However, under conditions of three-phase voltage imbalance, in addition to the grid fundamental positive-sequence voltage component, a fundamental negative-sequence voltage component can also be observed, which directly leads to the generation of second harmonics in the phase signal. To mitigate the impact of the fundamental negative-sequence voltage component, dual second-order generalized integrators (DSOGI-PLLs), dual complex coefficient filters (DCCFs), and several other pre-filtering methods have been developed to improve the overall performance of phase-locked loops (PLLs). While these methods are effective in eliminating the fundamental negative-sequence voltage component, PLLs based on these methods are unable to cope with grid voltage distortion and the introduction of DC offset voltages due to their insufficient anti-interference capabilities. Therefore, it is practical to develop PLLs suitable for harsh conditions such as grid harmonics and DC offset voltages. Summary of the Invention

[0005] The purpose of the present invention is to solve the deficiencies of the above-mentioned technology and provide a high-performance phase-locked loop based on a dual-enhanced second-order generalized integrator.

[0006] In order to achieve the above object, the technical solution provided by the present invention is:

[0007] The present invention proposes a high performance phase locked loop based on a double enhanced second order generalized integrator, which is composed of a Clarke transformation unit of a three-phase grid voltage, an integrated filter, a proportional controller k p, Phase Compensator The integral part is composed of 1 / s.

[0008] Three-phase grid voltage v abc The input end of the coordinate transformation unit is connected, the output end of the Clark transformation unit is connected to the input end of the integrated filter, the output end of the integrated filter is connected to the input end of the inverse tangent operation unit, and the output end of the inverse tangent operation unit is connected to the proportional controller k p The input of the proportional controller k p The output signal and natural frequency ω n After adding, it is input to the input end of the integral link 1 / s, and the output end of the integral link 1 / s outputs the phase estimation value In addition, the proportional controller k p The output signal of the phase compensator The output of the integral link 1 / s is connected to the input of the coordinate transformation unit, and the output of the integral link 1 / s is connected to the input of the coordinate transformation unit. The output of the inverse tangent unit and the phase compensator The output of the sum output phase locked result

[0009] The integrated filter is composed of a double enhanced second-order generalized integrator (DESOGI), a Park transformer and a moving average filter (MAF), wherein the double enhanced second-order generalized integrator (DESOGI) is responsible for suppressing the fundamental negative sequence voltage component and the DC offset component, and the moving average filter (MAF) is responsible for filtering out the harmonic voltages in the grid voltage;

[0010] The dual enhanced second-order generalized integrator (DESOGI) is composed of two enhanced second-order generalized integrators (ESOGI) and a fundamental positive-sequence voltage calculation unit. Its transfer function formula in the stationary coordinate system is:

[0011]

[0012] Where, is the resonant frequency, s represents the s domain, and k is 500.

[0013] The dual-enhanced second-order generalized integrator is responsible for obtaining the grid voltage fundamental positive sequence voltage in the stationary coordinate system, while also suppressing the fundamental negative sequence voltage component and DC offset voltage component;

[0014] The enhanced second-order generalized integrator (ESOGI) is composed of two integrators, three adders, two multipliers and two constant proportional controllers. Its transfer function formula is:

[0015] and

[0016]

[0017] Where u, v′ and qv′ are the input and output of the enhanced second-order generalized integrator respectively;

[0018] The s-domain transfer function of the integrated filter can be obtained by integrating the transfer function of the double enhanced second-order generalized integrator (DESOGI) in the rotating coordinate system and the transfer function of the moving average filter (MAF). The transfer function formula is:

[0019]

[0020] The integrated filter can accurately extract the fundamental positive-sequence voltage component in a relatively harsh power grid environment, comprehensively reduce the impact of the fundamental negative-sequence voltage component, DC offset component and harmonic voltage on the phase-locked loop, and thus achieve the function of efficiently locking the grid voltage phase.

[0021] Beneficial effects of the present invention:

[0022] This invention proposes a high-performance phase-locked loop (PLL) based on a dual-enhanced second-order generalized integrator. This method improves the PLL's steady-state characteristics in the presence of grid harmonic contamination, reduces grid phase tracking error, and enhances its dynamic performance. Compared to other phase-locked methods, this invention offers advantages such as faster adjustment time to grid changes and stronger anti-interference capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a structural diagram of the enhanced second-order generalized integrator (ESOGI) provided by the present invention;

[0024] Figure 2 Bode diagram of the transfer function of the enhanced second-order generalized integrator (ESOGI) provided by the present invention;

[0025] Figure 3 This is a structural diagram of the double-enhanced second-order generalized integrator (DESOGI) provided by the present invention;

[0026] Figure 4 When k provided by the present invention takes different values, G dqDESOGI (s) step response curve;

[0027] Figure 5 The Bode diagram of the transfer function of the double-enhanced second-order generalized integrator (DESOGI) provided by the present invention;

[0028] Figure 6 A structural diagram of a high-performance phase-locked loop provided by the present invention;

[0029] Figure 7The Bode diagram of the transfer function of the integrated filter provided by the present invention;

[0030] Figure 8 This is a frequency estimation diagram when the grid voltage undergoes a +40° phase jump and is mixed with a DC offset voltage in an embodiment of the present invention;

[0031] Figure 9 This is a phase error diagram when the grid voltage undergoes a +40° phase jump and is mixed with a DC offset voltage in an embodiment of the present invention;

[0032] Figure 10 This is a frequency estimation diagram when a two-phase sag occurs in the grid voltage and harmonic voltage is mixed in according to an embodiment of the present invention;

[0033] Figure 11 This is a phase error diagram when the grid voltage experiences a double-phase drop and is mixed with harmonic voltages in an embodiment of the present invention. DETAILED DESCRIPTION

[0034] To make the technical problems solved, the technical solutions adopted, and the technical effects achieved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, rather than all of the contents.

[0035] Aiming at the problem that the negative sequence component and harmonic component of the three-phase grid voltage deteriorate the phase-locked effect of SRF-PLL under abnormal and faulty conditions, a high-performance phase-locked loop based on dual enhanced second-order generalized integrators is proposed.

[0036] The implementation principle of the present invention:

[0037] The high performance phase-locked loop based on dual enhanced second-order generalized integrator is composed of Clarke transformation unit of three-phase grid voltage, integrated filter, proportional controller k p , Phase Compensator The integral part is composed of 1 / s.

[0038] Three-phase grid voltage v abc The input end of the coordinate transformation unit is connected, the output end of the Clark transformation unit is connected to the input end of the integrated filter, the output end of the integrated filter is connected to the input end of the inverse tangent operation unit, and the output end of the inverse tangent operation unit is connected to the proportional controller k p The input of the proportional controller k p The output signal and natural frequency ω n After adding, it is input to the input end of the integral link 1 / s, and the output end of the integral link 1 / s outputs the phase estimation value In addition, the proportional controller k p The output signal of the phase compensator The output of the integral link 1 / s is connected to the input of the coordinate transformation unit, and the output of the integral link 1 / s is connected to the input of the coordinate transformation unit. The output of the inverse tangent unit and the phase compensator The output of the sum output phase locked result

[0039] When the three-phase grid voltage is in an ideal balanced state, the traditional SRF-PLL has good phase and frequency tracking capabilities and high bandwidth. However, the performance of the SRF-PLL will deteriorate significantly under grid voltage distortion or unbalanced grid conditions. In order to obtain satisfactory performance under unbalanced and distorted grid conditions, the present invention proposes a high-performance phase-locked loop based on a dual enhanced second-order generalized integrator. First, an enhanced second-order generalized integrator (ESOGI) is proposed, and a dual enhanced second-order generalized integrator (DESOGI) is designed. At the same time, the dual enhanced second-order generalized integrator (DESOGI) and the moving average filter (MAF) are integrated into an integrated filter. Finally, a high-performance three-phase grid-connected phase-locked loop is designed based on the integrated filter to achieve the purpose of accurately locking the grid voltage phase under non-ideal grid conditions. The specific implementation steps are as follows:

[0040] 1) Implementation of enhanced second-order generalized integrator

[0041] In order to accurately extract and separate the positive and negative sequence signals of the power grid and eliminate the influence of the DC offset component on the phase-locked loop, the present invention proposes an enhanced second-order generalized integrator (ESOGI) structure, which is as follows: Figure 1 shown.

[0042] Depend on Figure 1 The transfer function expression of ESOGI is:

[0043]

[0044]

[0045] When k takes different values, R E (s) and Q E The Bode diagram of (s) is as follows Figure 4 As shown. Figure 4 It can be clearly seen that in the low frequency band, R E The logarithmic amplitude-frequency characteristic of (s) is a straight line with a slope of about 30dB / dec, so it has the ability to suppress DC offset. E(s) is a bandpass filter with a logarithmic amplitude-frequency characteristic of approximately 60 dB / dec, which also has the ability to suppress DC offset. Therefore, the ESOGI proposed in this invention can completely eliminate DC offset voltage.

[0046] 2) Implementation of dual enhanced second-order generalized integrator

[0047] In three-phase grid-connected system applications, PLLs typically use a filtering process that uses two filters combined with a fundamental positive sequence calculator to extract the fundamental positive sequence component of the grid voltage. In this paper, two ESOGI structures are used in conjunction with a fundamental positive sequence calculator to form a DESOGI filter. While extracting the fundamental positive sequence component, DESOGI can also eliminate the fundamental negative sequence component and DC offset. In addition, this structure uses a fixed frequency input method, and the input angular frequency ω n =2π×50rad / s. Figure 2 This is the structural diagram of DESOGI.

[0048] Figure 2 In which v α , v β is the three-phase voltage v a , v b , v c After the abc-αβ coordinate transformation, the voltage signal in the αβ coordinate system is obtained. and After passing through the fundamental positive sequence calculator, the output signal contains only the voltage positive sequence component and

[0049] observe Figure 2 available

[0050]

[0051] Combine Figure 2 And using the real and imaginary part expression method of the complex filter, we can get

[0052] According to formulas (1)-(3), the mathematical expression of the transfer function of DESOGI is:

[0053]

[0054] In order to make DESOGI applicable in the dq coordinate system, it needs to be converted into dqDESOGI. The transfer function of dqDESOGI can be obtained by Instead of G DESOGI (s) is obtained by

[0055]

[0056] The step response study of the dqDESOGI transfer function helps to further determine the k value. dqDESOGI (s), and its unit step response input signal is

[0057]

[0058] Therefore G dqDESOGI The step response expression of (s) is

[0059]

[0060] The time domain expression of the step response can be obtained by the inverse Laplace transform of formula (7). The time domain expression curve can be drawn by selecting different k values, such as Figure 3 As shown in the figure, as the value of k increases, the dynamic convergence time slows down, but the overshoot increases. When the value of k decreases, the dynamic convergence time shortens, but the overshoot first decreases and then increases. In order to balance the dynamic response time and overshoot, k is selected as 500 in the present invention.

[0061] The Bode plots of DESOGI and dqDESOGI are as follows: Figure 7 Grid frequency estimation is 50Hz, k is set to 500. Figure 7 As shown, the DESOGI curve for the fundamental negative-sequence component in the αβ coordinate system corresponds to the 0Hz axis, and the corresponding gain is approximately -50dB. Therefore, DESOGI can be considered to eliminate the fundamental negative-sequence component. The DESOGI curve for the DC component in the αβ coordinate system corresponds to the -50Hz axis, and the corresponding gain is approximately -40dB. Therefore, DESOGI can also be considered to eliminate the DC offset component. Similarly, dqDESOGI can eliminate the DC offset component and the fundamental negative-sequence component corresponding to -100Hz and -50Hz in the dq coordinate system. Meanwhile, the gain and phase of the fundamental positive-sequence component at 0Hz in the dq coordinate system are 0, indicating that it can completely separate the fundamental positive-sequence voltage component.

[0062] 3) High-performance phase-locked loop implementation

[0063] In order to improve the filtering performance of the phase-locked loop, this paper combines DESOGI and MAF into a new integrated filter, and adopts the QT-PLL structure to design a new three-phase grid-connected phase-locked loop. Figure 5 shown.

[0064] Figure 5 In, k p represents the gain of the P controller, is the phase compensation factor, which is used to compensate for the phase offset that occurs when the grid frequency deviates from its nominal value. The MAF transfer function introduced is Where T ω =T / 6=0.0033s.

[0065] observe Figure 4 , the phase shift caused by DESOGI can be approximated as the slope of the phase-frequency characteristic, which is about 50 Hz, as shown below.

[0066]

[0067] The phase compensation factor It can be taken as 0.00399.

[0068] The transfer function of the integrated filter unit composed of DESOGI and MAF is:

[0069]

[0070] According to formula (9), the frequency response curve of the proposed integrated filter is plotted as follows: Figure 6 As shown. It can be seen that when the fundamental negative-sequence component in the dq coordinate system corresponds to the -50Hz axis, the corresponding gain of the G(s) curve is approximately -50dB, thus assuming that G(s) can eliminate the fundamental negative-sequence component. When the DC component in the dq coordinate system corresponds to the -100Hz axis, the corresponding gain of the DESOGI curve is greater than -40dB, thus assuming that G(s) can eliminate the DC offset component. When the harmonic voltages in the dq coordinate system correspond to the -600Hz, -300Hz, 300Hz, 600Hz, and so on axes, the corresponding gain of the dqDESOGI curve is -∞, thus assuming that G(s) can eliminate each harmonic component. When the fundamental positive-sequence component in the dq coordinate system corresponds to the 0Hz axis, the corresponding gain of the G(s) curve is 0, and the phase is also 0, indicating that it can completely extract the fundamental positive-sequence component.

[0071] At this point, the structural design of a high-performance phase-locked loop based on dual enhanced second-order generalized integrators is completed.

[0072] The following are specific implementation cases:

[0073] To verify the effectiveness and superiority of the proposed phase-locked loop, the method was simulated and analyzed using MATLAB / Simulink. To better simulate the grid-connected fault environment, this experiment set up two working conditions, including frequency jump under DC offset conditions and voltage drop under voltage distortion conditions. In the simulation, the grid frequency was 50Hz, the three-phase voltage amplitude was normalized to 1p.u, and the sampling frequency was 10kHz. In order to more comprehensively demonstrate the performance advantages of the PLL proposed in this invention, the PLL was compared with the DSOGI PID -PLL and DIFMAF-PLL were compared and verified by experiments. p The value is 320.

[0074] The specific implementation effects are:

[0075] In order to verify the performance of the three PLLs when the grid voltage is mixed with a DC offset, the present invention injects a 20% DC offset into phase A, a 10% DC offset into phase B, and a -20% DC offset into phase C of the three-phase voltage. Figure 8 and Figure 9 Phase error and frequency estimation diagram when the grid frequency jumps from 50Hz to 56Hz when adding DC offset to the grid voltage. In the figure, the three-phase grid voltage operates normally from 0 to 0.12s, and the frequency of the three-phase voltage increases by 6Hz at 0.12s. As shown in the figure, DSOGI pid -PLL fluctuates violently and cannot be stabilized within a given time, indicating that the DSOGI structure is highly sensitive to frequency jumps and DC offsets, and cannot complete phase locking when the power grid contains a DC offset voltage. Although there is overshoot in the tracking process of DIFMAF-PLL, under the working condition that the power grid contains a DC offset, the steady-state phase errors of the PLL and DIFMAF-PLL proposed in the present invention are both 0, and the estimated frequency can also track the set value of the power grid frequency without static error, achieving accurate frequency locking and phase locking effects. However, the dynamic adjustment time of the PLL proposed in the present invention is about 1 power grid cycle, while the adjustment time of DIFMAF-PLL is about 1.5 power grid cycles, which shows that the dynamic performance of the PLL proposed in the present invention is more advantageous.

[0076] In order to verify the performance of the three PLLs when the grid voltage is unbalanced, the present invention conducts a voltage drop experiment under the condition of grid voltage harmonic distortion. Figure 10 and Figure 11This is a phase error and frequency estimation diagram when the two-phase voltage of the power grid drops by 50% in this case. In the figure, the three-phase power grid voltage operates normally in the period of 0 to 0.12s, and the amplitude of the two-phase voltage drops to 0.5pu at 0.12s. It can be seen from the figure that in the initial stage (that is, when there is no change in the voltage amplitude), it can be seen that the PLL and DIFMAF-PLL proposed in the present invention can accurately lock the frequency and amplitude of the power grid voltage. When the three-phase voltage undergoes an asymmetric mutation, the PLL proposed in the present invention has the fastest dynamic response due to the QT1 structure, the transition process takes less time, and the steady-state characteristics of the phase-locked loop are better when the power grid is polluted by harmonics. Due to DSOGI pid -PLL does not have the ability to work under harmonic conditions, so its frequency estimation and phase error have small amplitude oscillations.

[0077] pass Figures 8-11 By comparison, it can be seen that the high-performance phase-locked loop based on the dual-enhanced second-order generalized integrator proposed in the present invention has excellent filtering and dynamic characteristics, can achieve fast and accurate tracking of the grid voltage in a relatively harsh grid environment, and can be applied to the synchronization process of renewable energy grid connection.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the same. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that they can still modify or replace the technical solutions of the present invention with equivalents, and these modifications or equivalent replacements cannot cause the modified technical solutions to deviate from the spirit and scope of the technical solutions of the present invention.

Claims

1. A high-performance phase-locked loop based on a dual-enhanced second-order generalized integrator, characterized by: A high performance phase locked loop based on dual enhanced second order generalized integrator consists of Clarke transform unit of three-phase grid voltage, integrated filter, proportional controller k p , Phase Compensator The integral link is composed of 1 / s; Three-phase grid voltage v abc The input end of the coordinate transformation unit is connected, the output end of the Clark transformation unit is connected to the input end of the integrated filter, the output end of the integrated filter is connected to the input end of the inverse tangent operation unit, and the output end of the inverse tangent operation unit is connected to the proportional controller k p The input of the proportional controller k p The output signal and natural frequency ω n After adding, it is input to the input end of the integral link 1 / s, and the output end of the integral link 1 / s outputs the phase estimation value In addition, the proportional controller k p The output signal of the phase compensator The output of the integral link 1 / s is connected to the input of the coordinate transformation unit, and the output of the integral link 1 / s is connected to the input of the coordinate transformation unit. The output of the inverse tangent unit and the phase compensator The output of the sum output phase locked result The integrated filter is composed of a double enhanced second-order generalized integrator (DESOGI), a Park transformer and a moving average filter (MAF), wherein the double enhanced second-order generalized integrator (DESOGI) is responsible for suppressing the fundamental negative sequence voltage component and the DC offset component, and the moving average filter (MAF) is responsible for filtering out the harmonic voltages in the grid voltage; The dual enhanced second-order generalized integrator (DESOGI) is composed of two enhanced second-order generalized integrators (ESOGI) and a fundamental positive-sequence voltage calculation unit. Its transfer function formula in the stationary coordinate system is: Where, is the resonant frequency, s represents the s domain, and k is 500; The dual-enhanced second-order generalized integrator is responsible for obtaining the grid voltage fundamental positive sequence voltage in the stationary coordinate system, while also suppressing the fundamental negative sequence voltage component and DC offset voltage component; The enhanced second-order generalized integrator (ESOGI) is composed of two integrators, three adders, two multipliers and two constant proportional controllers. Its transfer function formula is: Where u, v′ and qv′ are the input and output of the enhanced second-order generalized integrator respectively.

2. The high-performance phase-locked loop based on a dual-enhanced second-order generalized integrator according to claim 1, characterized in that : The s-domain transfer function of the integrated filter can be obtained by integrating the transfer function of the double enhanced second-order generalized integrator (DESOGI) in the rotating coordinate system and the transfer function of the moving average filter (MAF). The transfer function formula is: Among them, T w is the time constant, which is 0.0033 seconds; The integrated filter can accurately extract the fundamental positive-sequence voltage component in a relatively harsh power grid environment, comprehensively reduce the impact of the fundamental negative-sequence voltage component, DC offset component and harmonic voltage on the phase-locked loop, and thus achieve the function of efficiently locking the grid voltage phase.

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