Liquid crystal handwriting pad

Abstract

The application discloses a liquid crystal handwriting board and belongs to the technical field of display. The liquid crystal handwriting board comprises a first substrate, a second substrate and a liquid crystal layer. A transistor in the first substrate is electrically connected with a pixel electrode, and the transistor is sensitive to light. Here, the area of the channel region of the transistor is large. Therefore, the transistor is more likely to be turned on after being irradiated by target light, that is, the sensitivity of the liquid crystal handwriting board is high, and thus the erasing effect of the liquid crystal handwriting board is good.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a liquid crystal handwriting tablet. Background Technology

[0002] A handwriting tablet is an electronic device used for writing and drawing. Among them, LCD handwriting tablets have the advantages of low power consumption and clear handwriting, and have gained a significant market share in recent years.

[0003] To enable partial erasure of handwriting displayed on an LCD handwriting tablet, a transistor sensitive to target light needs to be incorporated into the tablet. When an erasing tool (e.g., an eraser emitting strong target light) is used to erase the handwriting, the transistor conducts along the target light's illumination line, creating a voltage difference between the pixel electrode connected to the transistor and the common electrode in the LCD handwriting tablet, thus erasing the handwriting within the illuminated area.

[0004] However, the photosensitive area of ​​the transistors in the LCD handwriting tablet is small, resulting in low transistor sensitivity and consequently poor erasing performance. Summary of the Invention

[0005] This application provides a liquid crystal handwriting tablet. It solves the problem of poor erasing performance in existing liquid crystal handwriting tablets. The technical solution is as follows:

[0006] On one hand, a liquid crystal writing tablet is provided, characterized in that it includes: a first substrate and a second substrate disposed opposite to each other, and a liquid crystal layer located between the first substrate and the second substrate, the liquid crystal layer comprising bistable liquid crystal molecules;

[0007] The first substrate includes: a first substrate, and a transistor and a pixel electrode located on the side of the first substrate near the second substrate, wherein the transistor is electrically connected to the pixel electrode;

[0008] The transistor has a channel region, and the ratio of the area of ​​the channel region to the conduction current of the transistor is greater than the ratio of the area of ​​the channel region of the reference transistor to the conduction current of the reference transistor, and the ratio of the area of ​​the channel region of the reference transistor to the conduction current of the reference transistor is 32.5.

[0009] Optionally, the length of the channel region of the transistor is N times the length of the channel region of the reference transistor, and the width of the channel region of the transistor is also N times the width of the channel region of the reference transistor, where N is greater than 1.

[0010] Optionally, N is less than or equal to 2.

[0011] Optionally, the channel region of the transistor includes: a first sub-communication region and a second sub-channel region that are interconnected, wherein the length of the first sub-channel region is greater than the length of the second sub-channel region;

[0012] Wherein, the length of the second sub-channel region is equal to the length of the channel region of the reference transistor; the sum of the width-to-length ratio of the first sub-channel region and the width-to-length ratio of the second sub-channel region is equal to the width-to-length ratio of the reference transistor.

[0013] Optionally, the channel region is U-shaped, with one of the first sub-channel region and the second sub-channel region having two sub-channel regions, and the two sub-channel regions being arranged on both sides of the other of the first sub-channel region and the second sub-channel region.

[0014] Optionally, both sub-channel regions are strip-shaped, and the other of the first and second sub-channel regions is U-shaped.

[0015] Optionally, the width W1 of the first sub-channel and the width W2 of the second sub-channel region satisfy the following relationship:

[0016] W1 / M + W2 = W3;

[0017] Wherein, W3 represents the width of the channel region of the reference transistor, M represents the ratio of the length of the first sub-channel region to the length of the channel region of the reference transistor, and M is greater than 1.

[0018] Optionally, the transistor includes: K first sub-transistors connected in series, each of the first sub-transistors having a third sub-channel region, and the K third sub-channel regions being separately arranged, where K is an integer greater than 1;

[0019] Wherein, the length of the third sub-channel region is equal to the length of the channel region of the reference transistor, and the width of the third sub-channel region is K times the width of the channel region of the reference transistor.

[0020] Optionally, each of the third sub-channel regions is strip-shaped.

[0021] Optionally, the channel region of the transistor is annular in shape, and the length of the channel region is equal to the length of the channel region of the reference transistor, and the width of the channel region is equal to the width of the channel region of the reference transistor.

[0022] Optionally, the transistor includes: J second sub-transistors connected in parallel, each second sub-transistor having a ring-shaped fourth sub-channel region, and the J fourth sub-channel regions being separately arranged, where J is an integer greater than 1;

[0023] Wherein, the length of the fourth sub-channel region is equal to the length of the channel region of the reference transistor, and the sum of the widths of the J fourth sub-channel regions is equal to the width of the channel region of the reference transistor.

[0024] Optionally, the areas of each of the fourth sub-channel regions are equal, and the width of each of the fourth sub-channel regions is equal to one-J times the width of the channel region of the reference transistor.

[0025] Optionally, the ring is a square in the shape of a ring.

[0026] Optionally, the first substrate further includes: a gate line and a data line, wherein the gate line is electrically connected to the gate of the transistor, the data line is electrically connected to the first electrode of the transistor, and the second electrode of the transistor is electrically connected to the pixel electrode.

[0027] Optionally, the second substrate includes: a second substrate and a common electrode located on the side of the second substrate close to the first substrate, wherein one of the first substrate and the second substrate is a flexible substrate;

[0028] The transistor is configured to turn on under the illumination of target light, so that the data line connected to the transistor can apply a pixel voltage to the pixel electrode connected to the transistor, thereby creating a voltage difference between the pixel electrode to which the pixel voltage is applied and the common electrode.

[0029] Optionally, the difference between the ratio of the channel area of ​​the transistor to the on-current of the transistor and the ratio of the channel area of ​​the reference transistor to the on-current of the reference transistor is greater than or equal to 1.8.

[0030] The beneficial effects of the technical solutions provided in this application include at least the following:

[0031] A liquid crystal writing tablet includes a first substrate, a second substrate, and a liquid crystal layer. A transistor in the first substrate is electrically connected to a pixel electrode, and this transistor is highly sensitive to light. Here, the channel region of the transistor has a large area. Therefore, the transistor is more likely to conduct after being illuminated by target light, resulting in high sensitivity of the liquid crystal writing tablet and thus better erasing performance. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1This is a top view of a transistor in a liquid crystal writing tablet provided by related technologies;

[0034] Figure 2 This is a schematic diagram of the film layer structure of a liquid crystal handwriting tablet provided in an embodiment of this application;

[0035] Figure 3 yes Figure 2 A top view of the first substrate in the liquid crystal writing tablet shown;

[0036] Figure 4 This is a top view of a transistor in a first substrate provided in an embodiment of this application;

[0037] Figure 5 This is a top view of a transistor in a first substrate provided in an embodiment of this application;

[0038] Figure 6 This is a schematic diagram of the equivalent structure of a transistor provided in an embodiment of this application;

[0039] Figure 7 This is a top view of a transistor in a first substrate provided in an embodiment of this application;

[0040] Figure 8 This is a schematic diagram of another equivalent structure of a transistor provided in an embodiment of this application;

[0041] Figure 9 This is a top view of a transistor in a first substrate provided in an embodiment of this application;

[0042] Figure 10 This is a top view of yet another first substrate provided in the embodiments of this application;

[0043] Figure 11 This is a schematic diagram of the equivalent structure of another transistor provided in the embodiments of this application. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0045] Please refer to Figure 1 , Figure 1 This is a top view of a transistor in a liquid crystal writing tablet provided by related technology. The photosensitive area of ​​the transistor in the liquid crystal writing tablet is the area of ​​the channel region 01 of the transistor, and the size of the channel region 01 of the transistor directly affects the sensitivity of the transistor.

[0046] In related technologies, the channel region 01 of a transistor is typically U-shaped, with a width W of 50 micrometers and a length L of 4 micrometers, meaning the width-to-length ratio W / L is 50 / 4. Therefore, the area of ​​the channel region 01 is only 325 square micrometers. This small area makes it difficult for the transistor to conduct when illuminated by target light, resulting in low sensitivity of the LCD handwriting tablet and consequently poor erasing performance.

[0047] Furthermore, in order for the transistor to continue conducting normally after being illuminated by the target light, the gate voltage applied to the transistor's gate needs to be increased. However, when the gate voltage applied to the transistor's gate is too high, even weak ambient light may cause the transistor to conduct, leading to accidental erasing on the LCD handwriting tablet. This, in turn, results in poor erasing performance of the LCD handwriting tablet.

[0048] Please refer to Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of the film layer structure of a liquid crystal handwriting tablet provided in an embodiment of this application. Figure 3 yes Figure 2 The diagram shows a top view of the first substrate in the liquid crystal writing tablet. The liquid crystal writing tablet 000 may include: a first substrate 100 and a second substrate 200 disposed opposite to each other, and a liquid crystal layer 300 located between the first substrate 100 and the second substrate 200. The liquid crystal layer 300 may include bistable liquid crystal molecules, that is, this liquid crystal layer 300 may be a bistable liquid crystal layer.

[0049] The first substrate 100 may include a first substrate 101, and a transistor 102 and a pixel electrode 103 located on the side of the first substrate 101 near the second substrate 200, wherein the transistor 102 and the pixel electrode 103 are electrically connected. The second substrate 200 may include a second substrate 201, and a common electrode 202 located on the side of the second substrate 201 near the first substrate 100. Here, the transistor 102 is a light-sensitive transistor. If the transistor 102 is irradiated by a target light with strong intensity, the transistor 102 will conduct.

[0050] For example, such as Figure 2As shown, transistor 102 may include a gate 1021, a first electrode 1022, a second electrode 1023, and an active layer 1024. In transistor 1012, both the first electrode 1022 and the second electrode 1023 are connected to the active layer 1024, and the active layer 1024 and the gate 1021 are insulated from each other by a gate insulating layer 1025. Here, the first electrode 1022 can be one of the source and the drain, and the second electrode 1023 can be the other of the source and the drain. One of the source and the drain of transistor 102 can be electrically connected to the pixel electrode 103.

[0051] In this application, the active layer 1024 of the transistor 102 in the first substrate 100 has a channel region 102a. This channel region 102a refers to the region in the active layer 1024 located between a first region where the active layer 1024 contacts the first electrode 1022 and a second region where the active layer 1024 contacts the second electrode 1023.

[0052] After transistor 102 is irradiated by target light, carriers can be generated in the channel region 102a of transistor 102, and these carriers can turn on the first electrode 1022 and the second electrode 1023 of transistor 102. It should be noted that this embodiment is illustrated using a bottom-gate thin-film transistor as an example. In other optional implementations, the thin-film transistor can also be a top-gate thin-film transistor, and this embodiment does not limit this to that.

[0053] In this embodiment, when the liquid crystal writing tablet 000 is in writing mode, the second substrate 200 in the liquid crystal writing tablet 000 is subjected to external pressure. Under this pressure, some bistable liquid crystal molecules within the liquid crystal layer 300 of the liquid crystal writing tablet 000 change from a focal conical texture to a planar texture. In this way, the liquid crystal molecules that have changed to a planar texture can reflect light of a certain wavelength (e.g., green light) from the incident ambient light, allowing the liquid crystal writing tablet to display handwriting.

[0054] When the LCD handwriting tablet 000 is in erase mode, the erasing tool (an eraser capable of emitting strong target light) can emit target light towards the area in the LCD handwriting tablet 000 where writing exists. The transistor 102 in the LCD handwriting tablet 000 illuminated by the target light will then conduct. This creates a voltage difference between the pixel electrode 103 connected to this transistor 102 and the common electrode 202 in the LCD handwriting tablet 000. Consequently, the bistable liquid crystal molecules in the area illuminated by the target light rearrange under the influence of this voltage difference; that is, the bistable liquid crystal molecules can change from a planar texture to a focal conical texture, thereby erasing the writing in the area illuminated by the target light.

[0055] In this embodiment, the ratio of the area S2 of the channel region 102a of transistor 102 to the conduction current of transistor 102 is greater than the ratio of the area S1 of the channel region of the reference transistor to the conduction current of the reference transistor. It should be noted that the area of ​​the channel region of the transistor in this embodiment refers to the area of ​​the channel region projected onto the substrate on which the transistor is located.

[0056] It should also be noted that the reference transistor here can be the transistor in the aforementioned related technologies; that is, the structure of this reference transistor can be... Figure 1 The diagram shows the structure of a transistor. The transistor's on-state current refers to the current flowing between the transistor's first and second terminals when the transistor is turned on and not exposed to light.

[0057] In this application, the conduction current of the transistor 102 within the first substrate 100 can be made identical to that of the reference transistor; for example, the conduction current of both transistors can be 10 microamps. This ensures that the electrical performance of the transistor 102 in this application is consistent with that of the reference transistor. Furthermore, since the channel area of ​​this reference transistor is only 325 square micrometers, the ratio of the channel area to the conduction current of the reference transistor is 32.5.

[0058] Thus, when the ratio of the area of ​​the channel region 102a of transistor 102 projected onto the first substrate 101 to the conduction current of transistor 102 is greater than 32.5, it is possible to increase the area of ​​the channel region 102a of transistor 102 projected onto the first substrate 101 while ensuring that the electrical performance of transistor 102 in this application is consistent with that of the reference transistor. That is, the area S2 of the channel region 102a of transistor 102 projected onto the first substrate 101 will be larger than the area S1 of the channel region of the reference transistor.

[0059] In this case, since the area S2 of the channel region 102a of the transistor 102 in this application is relatively large, after the transistor 102 is irradiated by the target light, the active layer 1024 in the channel region 102a generates more charge carriers, and the transistor 102 is easier to conduct. That is, the sensitivity of the liquid crystal handwriting tablet 000 is high, which in turn makes the erasing effect of the liquid crystal handwriting tablet 000 better.

[0060] In summary, the liquid crystal writing tablet provided in this application includes a first substrate, a second substrate, and a liquid crystal layer. The transistor in the first substrate is electrically connected to a pixel electrode, and this transistor is highly sensitive to light. Here, because the channel area of ​​the transistor is relatively large, the transistor is more easily turned on after being illuminated by target light, resulting in high sensitivity of the liquid crystal writing tablet and thus better erasing performance.

[0061] It should be noted that, as Figure 3 As shown, the first substrate 100 in the liquid crystal handwriting tablet 000 may further include: a gate line 104 and a data line 105. The gate line 104 may be electrically connected to the gate 1021 of the transistor 102, the data line 105 may be electrically connected to the first electrode 1022 of the transistor 102, and the first electrode 1023 of the transistor 102 may be electrically connected to the pixel electrode 103. The transistor 102 is configured to conduct under the illumination of target light, enabling the data line 105 connected to the transistor 102 to apply a pixel voltage to the pixel electrode 103 connected to the transistor 102, thereby creating a voltage difference between the pixel electrode 103 with the applied pixel voltage and the common electrode 202.

[0062] In this scenario, when the LCD handwriting pad 000 is in erase mode, voltage is applied to all gate lines 104 and electrical signals are applied to data lines 105. Here, because the area S2 of the channel region 102a of transistor 102 is larger than the area S1 of the channel region of the reference transistor, a smaller voltage can be applied to the gate lines 104, i.e., a smaller gate voltage is applied to the gate 1021 of transistor 102. This ensures that transistor 102 can still conduct even when exposed to strong target light. Thus, when the gate voltage applied to the gate 1021 of transistor 102 is small, transistor 102 will not conduct under weak ambient light. This effectively reduces the probability of accidental erasures on the LCD handwriting pad 000 and improves the erasing effect.

[0063] It should also be noted that one of the first substrate 101 and the second substrate 201 in the liquid crystal writing tablet 000 is a flexible substrate. The flexible substrate is located on the writing side of the liquid crystal writing tablet 000. Here, the writing side of the liquid crystal writing tablet 000 refers to the side of the liquid crystal writing tablet 000 where it is displayed. In this way, when the user applies pressure to the flexible substrate on the writing side of the liquid crystal writing tablet 000, the bistable liquid crystal molecules in the liquid crystal layer 300 change from a focal conical texture to a planar texture, thereby enabling the liquid crystal writing tablet 000 to display handwriting.

[0064] In the embodiments of this application, there are several optional methods to make the area of ​​the channel region 102a of transistor 102 larger than the area of ​​the channel region of the reference transistor. The embodiments of this application only illustrate the following five optional implementation methods:

[0065] It should be noted that, in order to facilitate a more detailed description of the area S2 of the channel region 102a of the transistor 102 in the following embodiments, and to facilitate understanding of the content in the subsequent embodiments, the following embodiments first explain the technical terms involved in this application.

[0066] In this application, the channel region of a transistor refers to the region located between the first region where the active layer contacts the first electrode and the second region where the active layer contacts the second electrode. The length L of the channel region refers to the distance between the first and second regions, and the width W of the channel region refers to the smaller of the lengths of the first region and the second region near the channel region. The width-to-length ratio W / L of the transistor's channel region is the ratio between the width W and the length L of the transistor's channel region. A larger width-to-length ratio W / L results in a smaller resistance between the first and second electrodes and a larger conduction current between them; conversely, a smaller width-to-length ratio W / L results in a smaller conduction current between the first and second electrodes. In other words, the magnitude of the conduction current between the first and second electrodes of the transistor is directly proportional to the width-to-length ratio W / L of the channel region. Furthermore, the on-state current of a transistor is also related to the material of the active layer in the transistor. In the example of this application, the material of the active layer 1024 in transistor 102 can be the same as the material of the active layer in the reference transistor. Thus, the magnitude of the on-state current per W / L in the channel region 102a of transistor 102 in this application example is the same as the magnitude of the on-state current per W / L in the channel region of the reference transistor; for example, both are 0.8 microamps.

[0067] For the first optional implementation method, please refer to... Figure 4 , Figure 4 This is a top view of a transistor in a first substrate provided in an embodiment of this application. The length L of the channel region 102a of the transistor 102 in the first substrate 100 is N times the length of the channel region of the reference transistor, and the width W of the channel region 102a of the transistor 102 is also N times the width of the channel region of the reference transistor, where N is greater than 1. Thus, the area S2 of the channel region 102a of the transistor 102 is equal to N times the area S1 of the channel region of the reference transistor. 2 This results in a larger area S2 for the channel region 102a of transistor 102, leading to better erasing performance of the LCD handwriting tablet.

[0068] In this application, the on-current E1 of the reference transistor is equal to the product of the width-to-length ratio W / L of the channel region of the reference transistor and the current per unit width-to-length ratio of the channel region of the reference transistor. The on-current E2 of transistor 102 is equal to the product of the width-to-length ratio W / L of the channel region of transistor 102 and the current per unit width-to-length ratio of the channel region of transistor 102. For example, when N equals 2, if the width of the channel region of the reference transistor is 50 micrometers and the length of the channel region of the reference transistor is 4 micrometers, then the width of the channel region 102a of transistor 102 is 100 micrometers and the length of the channel region 102a of transistor 102 is 8 micrometers. Thus, the on-current E1 of the reference transistor and the on-current E2 of transistor 102 satisfy the following relationship:

[0069] E1 = (50 / 4) * 0.8;

[0070] E2 = (100 / 8) * 0.8;

[0071] E1 = E2.

[0072] In this case, the area S1 of the channel region of the reference transistor is equal to the product of the length and width of the channel region of the reference transistor. The area S2 of the channel region of transistor 102 is equal to the product of the length and width of the channel region of the transistor. For example, the areas S1 and S2 of the channel region of the reference transistor and transistor 102 satisfy the following relationship:

[0073] S1 = 50 * 40;

[0074] S2 = 100 * 8;

[0075] S2 > S1.

[0076] In this application, N is less than or equal to 2. Here, the region enclosed by any two adjacent data lines 105 and any two adjacent gate lines 104 in the first substrate 100 is the pixel region 100a. Thus, the larger N is, the larger the area S2 of the channel region of the transistor 102 is, resulting in a larger area of ​​the orthographic projection of the transistor 102 onto the first substrate 101. Therefore, as... Figure 3 As shown, since both transistor 102 and pixel electrode 103 are located within the same pixel region 100a, the area of ​​the orthographic projection of transistor 102 onto the first substrate 101 cannot be too large. This is to effectively prevent the area of ​​the orthographic projection of pixel electrode 103 onto the first substrate 101 from being too small, which would result in a small pixel opening in the liquid crystal writing tablet 000 and thus affect the writing and erasing of the liquid crystal writing tablet 000.

[0077] For the second optional implementation method, please refer to... Figure 5 , Figure 5This is a top view of a transistor in a first substrate provided in an embodiment of this application. The channel region 102a of the transistor 102 may include: a first sub-communication region 102a1 and a second sub-channel region 102a2 that are interconnected, wherein the length of the first sub-channel region 102a1 is greater than the length of the second sub-channel region 102a2.

[0078] In this transistor, the length of the second sub-channel region 102a2 is equal to the length of the channel region of the reference transistor. The sum of the aspect ratios of the first sub-channel region 102a1 and the second sub-channel region 102a2 is equal to the aspect ratio of the reference transistor. Therefore, the length of the first sub-channel region 102a1 is greater than the length of the channel region of the reference transistor. The area S2 of the channel region 102a of transistor 102 is equal to the sum of the areas of the first sub-channel region 102a1 and the second sub-channel region 102a2. Thus, the area S2 of the channel region 102a of transistor 102 is larger than the area S1 of the channel region of the reference transistor.

[0079] In this application, as Figure 5 As shown, the channel region of transistor 102 is U-shaped. One of the first sub-channel region 102a1 and the second sub-channel region 102a2 has two sub-channel regions, and the two sub-channel regions are arranged on both sides of the other of the first sub-channel region 102a1 and the second sub-channel region 102a2. Here, Figure 5 The illustration is based on the example of the first sub-channel region 102a1 having two sub-channel regions.

[0080] In this embodiment of the application, both sub-channel regions are strip-shaped, and the other of the first sub-channel region 102a1 and the second sub-channel region 102a2 is U-shaped.

[0081] In this case, please refer to Figure 6 , Figure 6 This is a schematic diagram of the equivalent structure of a transistor provided in an embodiment of this application. The first sub-channel region 102a1, a portion of the first electrode 1022 corresponding to the first sub-channel region 102a1, a portion of the second electrode 1023 corresponding to the first sub-channel region 102a1, and a portion of the gate 1021 corresponding to the first sub-channel region 102a1 in transistor 102 can form a sub-transistor. The second sub-channel region 102a2, a portion of the first electrode 1022 corresponding to the second sub-channel region 102a2, a portion of the second electrode 1023 corresponding to the second sub-channel region 102a2, and a portion of the gate 1021 corresponding to the second sub-channel region 102a2 in transistor 102 can form another sub-transistor. Furthermore, these two sub-transistors are connected in parallel.

[0082] In this application, the on-state current E1 of the reference transistor is equal to the product of the width-to-length ratio W / L of the channel region of the reference transistor and the current per unit width-to-length ratio of the channel region of the reference transistor. The on-state current E2 of transistor 102 is equal to the product of the sum of the width-to-length ratios of the first sub-channel region 102a1 and the second sub-channel region 102a2, and the current per unit width-to-length ratio of the channel region of transistor 102. In other words, the on-state current E2 of transistor 102 is equal to the sum of the on-state currents of the two sub-transistors mentioned above. For example, when the width W3 of the reference transistor's channel region is 50 micrometers and the length of the reference transistor's channel region is 4 micrometers, the length of the first sub-channel region 102a1 of transistor 102 is 8 micrometers, the width W1 of the first sub-channel region 102a1 of transistor 102 is 20 micrometers, the length of the second sub-channel region 102a2 of transistor 102 is 4 micrometers, and the width W2 of the second sub-channel region 102a2 of transistor 102 is 40 micrometers. Thus, the on-state current E1 of the reference transistor and the on-state current E2 of transistor 102 satisfy the following relationship:

[0083] E1 = (50 / 4) * 0.8;

[0084] E2 = ((20 / 8) + (40 / 4)) * 0.8;

[0085] E1 = E2.

[0086] In this case, the area S1 of the channel region of the reference transistor is equal to the product of the length and width of the channel region of the reference transistor. The area S2 of the channel region of transistor 102 is equal to the sum of the length and width of the first sub-channel region 102a1, plus the sum of the length and width of the second sub-channel region 102a2. For example, the areas S1 and S2 of the channel region of the reference transistor and transistor 102 satisfy the following relationship:

[0087] S1 = 50 * 40;

[0088] S2 = 20*8 + 40*4;

[0089] S2 > S1.

[0090] In this application, as Figure 6 As shown, the width W1 of the first sub-channel 102a1 and the width W2 of the second sub-channel region 102a2 also satisfy the following relationship:

[0091] W1 / M + W2 = W3;

[0092] Where W3 represents the width of the channel region of the reference transistor, M represents the ratio of the length of the first sub-channel region 102a1 to the length of the channel region of the reference transistor, and M is greater than 1.

[0093] In this embodiment, when the ratio of the length of the first sub-channel region 102a1 to the length of the channel region of the reference transistor is 2, the length of the first sub-channel region 102a1 is 8 micrometers, and the length of the channel region of the reference transistor can be 4 micrometers. Thus, after the width W1 of the first sub-channel 102a1 and the width W2 of the second sub-channel region 102a2 satisfy the above relationship, it can be guaranteed that the on-state current E1 of the reference transistor is equal to the on-state current E2 of the transistor 102.

[0094] For the third optional implementation method, please refer to... Figure 7 and Figure 8 , Figure 7 This is a top view of a transistor in a first substrate provided in an embodiment of this application. Figure 8 This is a schematic diagram of an equivalent structure of another transistor provided in an embodiment of this application. Transistor 102 may include: K first sub-transistors 1026 connected in series, each first sub-transistor 1026 having a third sub-channel region 1026a, and the K third sub-channel regions 1026a being separately disposed, where K is an integer greater than 1.

[0095] In this transistor, the length of the third sub-channel region 1026a is equal to the length of the channel region of the reference transistor, and the width of the third sub-channel region 1026a is K times the width of the channel region of the reference transistor. Therefore, the area S2 of the channel region 102a of transistor 102 is equal to the sum of the areas of the K third sub-channel regions 1026a. Since the width of the third sub-channel region 1026a is K times the width of the channel region of the reference transistor, the area S2 of the channel region 102a of transistor 102 is relatively large.

[0096] In this application, each third sub-channel region 1026a is strip-shaped. Thus, K third sub-channel regions 1026a can form K first sub-transistors 1026 connected in series.

[0097] In this embodiment, the on-current E1 of the reference transistor is equal to the product of the width-to-length ratio W / L of the channel region of the reference transistor and the current per unit width-to-length ratio of the channel region of the reference transistor. The on-current E2 of transistor 102 is equal to one-K times the product of the width-to-length ratio of the third sub-channel region 1026a and the current per unit width-to-length ratio of the channel region of transistor 102. For example, when the width W3 of the channel region of the reference transistor is 50 micrometers and the length of the channel region of the reference transistor is 4 micrometers, the length of the K third sub-channel regions 1026a is 4 micrometers, and the width W of the K third sub-channel regions 1026a is 100 micrometers. Thus, the on-current E1 of the reference transistor and the on-current E2 of transistor 102 satisfy the following relationship:

[0098] E1 = (50 / 4) * 0.8;

[0099] E2 = ((100 / 4) * 0.8) * 1 / K;

[0100] E1 = E2.

[0101] In this case, the area S1 of the channel region of the reference transistor is equal to the product of the length and width of the channel region of the reference transistor. The area S2 of the channel region of transistor 102 is equal to the sum of the areas of the third sub-channel regions 1026a of the K first sub-transistors 1026. The area of ​​the third sub-channel region 1026a is equal to the product of the length and width of the third sub-channel region 1026a. For example, the area S1 of the channel region of the reference transistor and the area S2 of the channel region of transistor 102 satisfy the following relationship:

[0102] S1 = 50 * 40;

[0103] S2 = K * (100 * 4);

[0104] S2 > S1.

[0105] For the fourth optional implementation method, please refer to... Figure 9 , Figure 9This is a top view of a transistor in a first substrate provided in an embodiment of this application. The channel region 102a of transistor 102 is annular in shape, and the length of the channel region 102a is equal to the length of the channel region of the reference transistor, and the width of the channel region 102a of transistor 102 is equal to the width of the channel region of the reference transistor. Here, the annular shape is a square. Thus, since the channel region 102a of transistor 102 is annular, the area S2 of the channel region 102a of transistor 102 is equal to the product of the length of the second region and the length of the channel region 102a of transistor 102, plus the area of ​​a square equal to the length of the channel regions 102a of four transistors 102. Therefore, the area S2 of the channel region 102a of transistor 102 is larger than the area S1 of the channel region of the reference transistor. Here, the length of the second region refers to the length of the second electrode 1023 near the active layer 1024, which is also the width of the channel region 102a. Thus, the width of channel region 102a is enclosed by four equal-length segments. For example, the width of channel region 102a is equal to 4 times 12.5 micrometers.

[0106] In this application, since the length of the channel region 102a is equal to the length of the channel region of the reference transistor, and the width of the channel region 102a of the transistor 102 is equal to the width of the channel region of the reference transistor, the on-state current E1 of the reference transistor is equal to the on-state current E2 of the transistor 102. For example, when the width W3 of the channel region of the reference transistor is 50 micrometers and the length of the channel region of the reference transistor is 4 micrometers, the width of the annular channel region 102a is 50 micrometers, and the length of the channel region 102a of the transistor 102 is 4 micrometers. It should be noted that the calculation method for the on-state current E2 of the channel region 102a of the transistor 102 can refer to the corresponding content in the above embodiments, and will not be repeated in this application.

[0107] In this case, the channel area S1 of the reference transistor is equal to 325 square micrometers. The channel area S2 of the transistor 102 is equal to 343 square micrometers.

[0108] For the fifth optional implementation method, please refer to... Figure 10 , Figure 10 This is a top view of yet another first substrate provided in the embodiments of this application. The transistor 102 may include J second sub-transistors 1027 connected in parallel, each second sub-transistor 1027 having a ring-shaped fourth sub-channel region 1027a, and the J fourth sub-channel regions 1027a being separately disposed, where J is an integer greater than 1. Here, the ring shape is a square ring.

[0109] In this embodiment, the length of the fourth sub-channel region 1027a is equal to the length of the channel region of the reference transistor, and the sum of the widths of the J fourth sub-channel regions 1027a is equal to the width of the channel region of the reference transistor. Here, the fourth sub-channel regions 1027a of the J second sub-transistors 1027 are all annular; therefore, the area S2 of the channel region 102a of transistor 102 is equal to the sum of the areas of the channel regions of the J second sub-transistors 1027. The area of ​​the channel region of the second sub-transistors 1027 can be described in the fourth optional implementation described above, and will not be repeated here. Thus, the area S2 of the channel region 102a of transistor 102 is larger than the area S1 of the channel region of the reference transistor.

[0110] In this embodiment, the areas of the orthographic projections of each fourth sub-channel region 1027a onto the first substrate 101 are all equal, and the width of each fourth sub-channel region 1027a is equal to one-J parts of the width of the channel region of the reference transistor. Thus, the J second sub-transistors 1027 have the same height. The width of the fourth sub-channel region 1027a in each second sub-transistor 1027 is enclosed by four equal-length portions. For example, the width of each fourth sub-channel region 1027a is equal to 4 times 4.2 micrometers.

[0111] In this case, please refer to Figure 11 , Figure 11 This is a schematic diagram of the equivalent structure of another transistor provided in an embodiment of this application. The on-state current E1 of the reference transistor is equal to the product of the width-to-length ratio W / L of the channel region of the reference transistor and the current per unit width-to-length ratio of the channel region of the reference transistor. The on-state current E2 of transistor 102 is equal to the sum of the on-state currents of the J second sub-transistors 1027. For example, when the width W3 of the channel region of the reference transistor is 50 micrometers and the length of the channel region of the reference transistor is 4 micrometers, the length of the three fourth sub-channel regions 1027a is 4 micrometers, and the width W of the three fourth sub-channel regions 1027a is 50 micrometers. The width W of each fourth sub-channel region 1027a is 16.8 micrometers.

[0112] In this embodiment, the calculation formulas for the channel area S1 of the reference transistor and the channel area S2 of the transistor 102, for the five optional implementations described above, are merely illustrative. Thus, it can be seen from the simplified formulas that the channel area S2 of the transistor 102 is larger than the channel area S1 of the reference transistor. It should be noted that the ratio of the channel area of ​​the reference transistor to the on-state current of the reference transistor is 32.5. This is because the reference transistor is... Figure 3 The U-shaped transistor shown has a channel area of ​​325 square micrometers, which is the actual channel area of ​​the reference transistor in actual production.

[0113] In this application, the difference between the ratio of the channel area S2 of transistor 102 to the on-current E2 of transistor 102 and the ratio of the channel area S1 of the reference transistor to the on-current E1 of the reference transistor is greater than or equal to 1.8. In an embodiment of this application, the difference between the ratio of the channel area S2 of transistor 102 to the on-current E2 of transistor 102 and the ratio of the channel area S1 of the reference transistor to the on-current E1 of the reference transistor is less than or equal to 80. For example, the difference between the ratio of the channel area S2 of transistor 102 to the on-current E2 of transistor 102 and the ratio of the channel area S1 of the reference transistor to the on-current E1 of the reference transistor can be 30. Thus, when the on-current E2 of the transistor and the on-current E1 of the reference transistor are equal to 10 microamps, the channel area S2 of transistor 102 is 300 square micrometers larger than the channel area S1 of the reference transistor. It should be noted that in other possible implementations, the difference between the ratio of the channel area S2 of the body transistor 102 to the conduction current E2 of the transistor 102 and the ratio of the channel area S1 of the reference transistor to the conduction current E1 of the reference transistor can be 40, 60, etc., which will not be elaborated in the embodiments of this application.

[0114] In this scenario, when the on-current E2 of the transistor and the on-current E1 of the reference transistor are both 10 microamps, the channel area S2 of transistor 102 is at least 18 square micrometers larger than the channel area S1 of the reference transistor. Thus, transistor 102 is more easily turned on after being illuminated by the target light, resulting in better erasing performance of the LCD handwriting pad 000.

[0115] In this embodiment, since both transistor 102 and pixel electrode 103 are located within the same pixel region 100a, the area of ​​the orthogonal projection of transistor 102 onto the first substrate 101 cannot be too large. Here, regarding the five optional implementations described above, the area of ​​the orthogonal projection of transistor 102 onto the first substrate 101 in the third optional implementation is larger than the area of ​​the orthogonal projection of transistor 102 onto the first substrate 101 in the first optional implementation. The area of ​​the orthogonal projection of transistor 102 onto the first substrate 101 in the first optional implementation is larger than the area of ​​the orthogonal projection of transistor 102 onto the first substrate 101 in the fourth optional implementation. The area of ​​the orthogonal projection of transistor 102 onto the first substrate 101 in the fourth optional implementation is larger than the area of ​​the orthogonal projection of transistor 102 onto the first substrate 101 in the second optional implementation. The area of ​​the orthogonal projection of transistor 102 onto the first substrate 101 in the second optional implementation is larger than the area of ​​the orthogonal projection of transistor 102 onto the first substrate 101 in the fifth optional implementation. Thus, the area of ​​the orthogonal projection of the pixel electrode 103 onto the first substrate 101 is negatively correlated with the area of ​​the orthogonal projection of the transistor 102 onto the first substrate 101. Furthermore, for the five optional implementations described above, the area of ​​the channel region of the transistor 102 in each implementation is positively correlated with the area of ​​the orthogonal projection of the transistor 102 onto the first substrate 101.

[0116] In this scenario, when the LCD handwriting tablet 000 adopts the transistor 102 structure in the third optional implementation, the LCD handwriting tablet 000 exhibits the highest sensitivity. When the LCD handwriting tablet 000 adopts the transistor 102 structure in the fifth optional implementation, the opening of its pixel electrode 103 is larger while ensuring good sensitivity.

[0117] In summary, the liquid crystal writing tablet provided in this application includes a first substrate, a second substrate, and a liquid crystal layer. The transistor in the first substrate is electrically connected to a pixel electrode, and this transistor is highly sensitive to light. Here, because the channel area of ​​the transistor is relatively large, the transistor is more easily turned on after being illuminated by target light, resulting in high sensitivity of the liquid crystal writing tablet and thus better erasing performance.

[0118] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0119] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0120] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A liquid crystal handwriting tablet, characterized in that, include: A first substrate and a second substrate disposed opposite to each other, and a liquid crystal layer located between the first substrate and the second substrate, the liquid crystal layer comprising bistable liquid crystal molecules; The first substrate includes: a first substrate, and a transistor and a pixel electrode located on the side of the first substrate near the second substrate, wherein the transistor is electrically connected to the pixel electrode; The transistor has a channel region, and the ratio of the area of ​​the channel region to the conduction current of the transistor is greater than the ratio of the area of ​​the channel region of the reference transistor to the conduction current of the reference transistor. The ratio of the area of ​​the channel region of the reference transistor to the conduction current of the reference transistor is 32.

5. The conduction current of the transistor is the same as the conduction current of the reference transistor. The reference transistor is not present in the liquid crystal handwriting tablet. The reference transistor is used to compare with the transistor to define the transistor.

2. The liquid crystal handwriting tablet according to claim 1, characterized in that, The length of the channel region of the transistor is N times the length of the channel region of the reference transistor, and the width of the channel region of the transistor is also N times the width of the channel region of the reference transistor, where N is greater than 1.

3. The liquid crystal handwriting tablet according to claim 2, characterized in that, The N is less than or equal to 2.

4. The liquid crystal handwriting tablet according to claim 1, characterized in that, The channel region of the transistor includes: a first sub-channel region and a second sub-channel region that are interconnected, wherein the length of the first sub-channel region is greater than the length of the second sub-channel region; Wherein, the length of the second sub-channel region is equal to the length of the channel region of the reference transistor; the sum of the width-to-length ratio of the first sub-channel region and the width-to-length ratio of the second sub-channel region is equal to the width-to-length ratio of the reference transistor.

5. The liquid crystal handwriting tablet according to claim 4, characterized in that, The channel area is U-shaped, and one of the first sub-channel area and the second sub-channel area has two sub-channel areas, which are arranged on both sides of the other of the first sub-channel area and the second sub-channel area.

6. The liquid crystal handwriting tablet according to claim 5, characterized in that, Both sub-channel regions are strip-shaped, while the other of the first and second sub-channel regions is U-shaped.

7. The liquid crystal handwriting tablet according to claim 4, characterized in that, The width W1 of the first sub-channel and the width W2 of the second sub-channel region satisfy the following relationship: W1 / M + W2 = W3; Wherein, W3 represents the width of the channel region of the reference transistor, M represents the ratio of the length of the first sub-channel region to the length of the channel region of the reference transistor, and M is greater than 1.

8. The liquid crystal handwriting tablet according to claim 1, characterized in that, The transistor includes: K first sub-transistors connected in series, each of the first sub-transistors having a third sub-channel region, and the K third sub-channel regions being separately arranged, where K is an integer greater than 1; Wherein, the length of the third sub-channel region is equal to the length of the channel region of the reference transistor, and the width of the third sub-channel region is K times the width of the channel region of the reference transistor.

9. The liquid crystal handwriting tablet according to claim 8, characterized in that, Each of the aforementioned third sub-channel regions is strip-shaped.

10. The liquid crystal handwriting tablet according to claim 1, characterized in that, The channel region of the transistor is annular in shape, and the length of the channel region is equal to the length of the channel region of the reference transistor, and the width of the channel region is equal to the width of the channel region of the reference transistor.

11. The liquid crystal handwriting tablet according to claim 1, characterized in that, The transistor includes J second sub-transistors connected in parallel, each second sub-transistor having a ring-shaped fourth sub-channel region, and the J fourth sub-channel regions being separately arranged, where J is an integer greater than 1; Wherein, the length of the fourth sub-channel region is equal to the length of the channel region of the reference transistor, and the sum of the widths of the J fourth sub-channel regions is equal to the width of the channel region of the reference transistor.

12. The liquid crystal handwriting tablet according to claim 11, characterized in that, Each of the fourth sub-channel regions has the same area, and the width of each of the fourth sub-channel regions is equal to one-J times the width of the channel region of the reference transistor.

13. The liquid crystal writing tablet according to any one of claims 10 to 12, characterized in that, The ring is a square ring.

14. The liquid crystal writing tablet according to any one of claims 1 to 12, characterized in that, The first substrate further includes: a gate line and a data line, wherein the gate line is electrically connected to the gate of the transistor, the data line is electrically connected to the first electrode of the transistor, and the second electrode of the transistor is electrically connected to the pixel electrode.

15. The liquid crystal handwriting tablet according to claim 14, characterized in that, The second substrate includes: a second substrate, and a common electrode located on the side of the second substrate close to the first substrate, wherein one of the first substrate and the second substrate is a flexible substrate; The transistor is configured to turn on under the illumination of target light, so that the data line connected to the transistor can apply a pixel voltage to the pixel electrode connected to the transistor, thereby creating a voltage difference between the pixel electrode to which the pixel voltage is applied and the common electrode.

16. The liquid crystal handwriting tablet according to any one of claims 1 to 12, characterized in that, The difference between the ratio of the channel area of ​​the transistor to the on-current of the transistor and the ratio of the channel area of ​​the reference transistor to the on-current of the reference transistor is greater than or equal to 1.8.

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