A trim circuit

Abstract

The present application relates to the field of analog integrated circuit technology, and particularly relates to a trimming circuit. The trimming circuit comprises a first branch, a second branch, and a third branch. The first branch forms a driving signal output under the action of an enable signal. The second branch receives the driving signal and forms a control signal output under the action of the driving signal. The second branch comprises a trimming fuse. The third branch receives the control signal and forms a trimming signal output under the action of the control signal. The third branch comprises a third comparison circuit. The third comparison circuit is formed by a third PMOS transistor and a third NMOS transistor. The gate of the third PMOS transistor is connected to the gate of the third NMOS transistor and the output end of the second branch. The drain of the third PMOS transistor is connected to the source of the third NMOS transistor. The source of the third PMOS transistor is connected to a working voltage. The drain of the third NMOS transistor is connected to the ground. The width-length ratio of the third NMOS transistor is greater than the width-length ratio of the third PMOS transistor.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and more specifically to a tuning circuit. Background Technology

[0002] Integrated circuits, due to their inherent distribution, exhibit varying parameter distributions during manufacturing. In applications requiring high parameter accuracy, trimming techniques are necessary to mitigate this distribution and improve parameter consistency, thus meeting application requirements. Current trimming methods primarily include electrical trimming. The principle of electrical trimming involves applying voltage across a trimming fuse; the current flowing through the fuse generates heat, burning it off and achieving the trimming purpose. Existing trimming circuits mainly fall into three categories: trimming circuits that use high current to burn off metal fuses, trimming circuits that use polysilicon fuses, and trimming circuits that use lasers to burn off metal fuses. In actual chip manufacturing, process errors often lead to discrepancies between the design values ​​and measured values ​​of certain reference voltages. Therefore, during chip calibration (CP) testing, trimming circuits are needed to correct these inaccurate reference values. During testing, theoretically, the fuse should be completely burned out, meaning the voltage of the burned section of the fuse is 0V or Vdd. However, in actual testing, complete burning out is relatively rare. In reality, most of the fuse diameter is burned out, but some wires are still pulled or stuck together. Due to the partial sticking or pulling, the adjustment effect of the adjustment circuit is affected, meaning the adjustment purpose cannot be achieved. On the other hand, the tested chip is judged as a failed chip, which affects the product yield (currently the industry yield is 90%), thereby reducing the company's economic benefits. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention provides a trimming circuit designed to achieve a trimming effect even when the fuse is not completely blown, thereby improving product yield. Specifically:

[0004] On one hand, the present invention provides a trimming circuit, comprising:

[0005] The first branch is used to generate a drive signal output under the action of the enable signal;

[0006] The second branch is connected to the first branch and is used to receive the drive signal and generate a control signal output under the action of the drive signal; the second branch includes a trimming fuse;

[0007] The third branch, connected to the second branch, is used to receive the control signal and output a trimming signal upon the formation of the control signal. The third branch includes a third comparator circuit, which is formed by a third PMOS transistor and a third NMOS transistor. The gate of the third PMOS transistor is connected to the gate of the third NMOS transistor and to the output terminal of the second branch. The drain of the third PMOS transistor is connected to the source of the third NMOS transistor. The source of the third PMOS transistor is connected to the operating voltage, and the drain of the third NMOS transistor is grounded. The aspect ratio of the third NMOS transistor is greater than that of the third PMOS transistor.

[0008] Preferably, in the above-described adjustment circuit, the first branch includes:

[0009] The first processing circuit receives the enable signal and generates a processing signal output based on the enable signal.

[0010] A first control switch, the control terminal of the first control switch is connected to the output terminal of the first processing circuit, for receiving a first processing signal, and generating a first control signal output when the first processing signal matches a first predetermined signal, and generating a second control signal output when the first processing signal does not match the first predetermined signal.

[0011] The first driving circuit is connected to the output terminal of the first control switch and the second processing circuit, and is used to generate a first driving sub-signal output under the action of the second control signal and the bias signal.

[0012] The second processing circuit is connected to the output terminal of the first control switch and the first drive circuit, and is used to receive the second control signal and generate a second processing signal output under the action of the second control signal.

[0013] The first comparison circuit has its input terminal connected to the second processing circuit, and is used to generate a first comparison signal output based on the second processing signal;

[0014] The third processing circuit has a first input terminal connected to the output terminal of the first comparison circuit, a second input terminal for receiving the enable signal, and a third processing circuit for generating the drive signal output under the action of the first comparison signal and the enable signal.

[0015] Preferably, in one of the above-described adjustment circuits, the first processing circuit is formed by an inverter, and the input terminal of the inverter receives the enable signal.

[0016] Preferably, in the above-described adjustment circuit, the first control switch is formed by a first NMOS transistor, the gate of the first NMOS transistor is connected to the output of the first processing circuit, the source of the first NMOS transistor is connected to a common ground, and the drain of the first NMOS transistor forms the output terminal of the first control switch.

[0017] Preferably, in the above-described adjustment circuit, the second processing circuit is formed by a second NMOS transistor, the gate of the second NMOS transistor is connected to the output terminal of the first control switch, and the source of the second NMOS transistor is connected to the drain of the second NMOS transistor and connected to a common ground.

[0018] Preferably, in the above-described adjustment circuit, the third processing circuit is formed by a NAND gate, the first input terminal of the NAND gate is connected to the output terminal of the first comparison circuit, the second input terminal of the NAND gate is connected to the enable signal, and the output terminal of the NAND gate forms the output terminal of the third processing circuit.

[0019] Preferably, in the above-described adjustment circuit, the second branch:

[0020] The second comparator circuit is connected to the output terminal of the first branch to receive the drive signal, and generates a first drive sub-signal output when the drive signal is matched with a first predetermined drive signal; and generates a second drive sub-signal output when the drive signal is matched with a second predetermined drive signal.

[0021] At least one adjustment control branch is provided, and the input terminals of all the adjustment control branches are connected to the second comparator circuit, forming the control signal output under the action of the second drive sub-signal.

[0022] Preferably, in the above-mentioned adjustment circuit, the adjustment control branch is formed by an adjustment resistor and an adjustment fuse connected in series, one end of the adjustment control branch is connected to the second comparator circuit, the other end of the adjustment control branch is connected to a common ground, and the connection point of the adjustment resistor and the adjustment fuse forms the output terminal of the adjustment control branch.

[0023] Preferably, in the above-described adjustment circuit, the third branch includes: the third branch includes at least one third sub-branch, the third sub-branch being matched with the adjustment control branch; the third sub-branch includes:

[0024] The third comparison circuit is connected to the output terminal of the second branch to receive the control signal and generate a third comparison signal output based on the control signal.

[0025] The fourth processing circuit is connected to the output terminal of the third comparison circuit to receive the third comparison signal and generate a fourth processing signal output based on the third comparison signal.

[0026] The fifth processing circuit has a first input terminal connected to the output terminal of the fourth processing circuit and a second output terminal connected to the output terminal of the first processing circuit. It is used to receive the first processing signal and the fourth processing signal, and to form the adjustment signal output based on the first processing signal and the fourth processing signal.

[0027] Preferably, in the above-described adjustment circuit, the fifth processing circuit is formed by an RS flip-flop.

[0028] On the other hand, the present invention also provides an integrated circuit, wherein the integrated circuit includes the above-described adjustment circuit.

[0029] Furthermore, the present invention also provides a trimming circuit, comprising:

[0030] A drive signal circuit is formed to generate a drive signal output under the action of an enable signal;

[0031] A control circuit, connected to the driving signal generating circuit, is used to receive the driving signal and generate a control signal output under the action of the driving signal;

[0032] An adjustment circuit, connected to the control circuit, is used to receive the control signal and output a trimming signal from the formation of the control signal, wherein the adjustment circuit includes:

[0033] The second regulation branch is formed by a third PMOS transistor and at least two fourth PMOS transistors connected in parallel. The third PMOS transistor and the at least two fourth PMOS transistors connected in parallel are connected in parallel with each other so that the width-to-length ratio of the multiple PMOS transistors is greater than that of the PMOS transistor.

[0034] The third adjustment branch includes a fifth NMOS transistor and a sixth NMOS transistor. The gates of the fifth and sixth NMOS transistors are interconnected and connected to the source of the seventh NMOS transistor. The drain of the sixth NMOS transistor is grounded through a resistor and a trim fuse. The width-to-length ratio of the fifth and sixth NMOS transistors is the same.

[0035] Preferably, in the above-described adjustment circuit, the driving signal generating circuit includes a first driving branch and a second driving branch connected to the first driving branch, wherein the first driving circuit contains a capacitor element for generating a pulse signal.

[0036] Preferably, in the above-described adjustment circuit, the control circuit includes a transmission gate control branch, the control terminal of which is connected to the generating drive signal circuit, and the input terminal of which is connected to a constant current signal.

[0037] Compared with the prior art, the beneficial effects of the present invention are:

[0038] This application provides a tuning circuit. Because the aspect ratio of an NMOS transistor is greater than that of a PMOS transistor, the on-resistance of the NMOS transistor is less than that of the PMOS transistor. The NMOS transistor has a stronger driving capability than the PMOS transistor. When the control signal is sufficient to drive the NMOS transistor to its conduction threshold, the NMOS transistor conducts to form a tuning signal output. Specifically, even when the fuse in the tuning circuit is not completely burned out, a corresponding voltage signal can still be generated on the branch containing the tuning resistor and the fuse to drive the NMOS transistor to conduct, thus achieving the tuning purpose. The beneficial effect is that, compared to traditional tuning circuits, the tuning circuit provided by this invention can still perform the function of tuning the reference even when the fuse is not completely burned out. Furthermore, the tuning circuit of this application has a simple structure, requires fewer components, and only consumes power during the process of determining whether the tuning fuse has burned out, i.e., during the generation of the pulse signal; no power consumption is generated when it is not operating. Furthermore, even if stringing or adhesion occurs, the adjustment circuit can still continue to work, increasing the product yield to 95% or even higher, effectively improving the company's economic benefits. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 A block diagram of a trimming circuit provided in an embodiment of the present invention;

[0041] Figure 2 A schematic diagram of the circuit structure of the first branch in a trimming circuit provided in an embodiment of the present invention;

[0042] Figure 3 A schematic diagram of the circuit structure of the second branch in a trimming circuit provided in an embodiment of the present invention;

[0043] Figure 4 A schematic diagram of the circuit structure of the third branch in a trimming circuit provided in an embodiment of the present invention;

[0044] Figure 5 This is a schematic diagram of a trimming circuit provided in an embodiment of the present invention. Detailed Implementation

[0045] Example 1

[0046] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0047] like Figure 1 As shown, in one aspect, the present invention provides a trimming circuit, comprising:

[0048] The first branch is used to generate a drive signal output under the action of the enable signal; the enable signal can be input from an external circuit, and the enable signal can be a high-level signal or a low-level signal. The working state of the adjustment circuit is different under the action of different enable signals.

[0049] The second branch is connected to the first branch and is used to receive the drive signal and generate a control signal output under the action of the drive signal; the second branch includes a trimming fuse;

[0050] The third branch, connected to the second branch, is used to receive the control signal and output a trimming signal in the formation of the control signal.

[0051] The third branch includes a third comparator circuit, which is formed by a third PMOS transistor and a third NMOS transistor. The gate of the third PMOS transistor is connected to the gate of the third NMOS transistor and to the output terminal of the second branch. The drain of the third PMOS transistor is connected to the source of the third NMOS transistor. The source of the third PMOS transistor is connected to the operating voltage, and the drain of the third NMOS transistor is grounded. The width-to-length ratio of the third NMOS transistor is greater than that of the third PMOS transistor.

[0052] The working principle of the above-mentioned adjustment circuit is as follows: a drive signal is generated under the action of an enable signal; a control signal is generated based on the drive signal. In the case where the adjustment fuse in the second branch is not completely blown or is completely blown, a control signal is generated to drive the third NMOS transistor to conduct. Under the conducting state of the third NMOS transistor, an adjustment signal is generated to achieve the adjustment purpose.

[0053] In this application, because the aspect ratio of the NMOS transistor is greater than that of the PMOS transistor, the on-resistance of the NMOS transistor is less than that of the PMOS transistor. Since the NMOS transistor has a stronger driving capability than the PMOS transistor, it conducts when the control signal is sufficient to drive the NMOS transistor to the conduction threshold, thus forming a trimming signal output. Specifically, even when the fuse in the trimming circuit is not completely burned out, a corresponding voltage signal to drive the NMOS transistor to conduct can still be generated on the branch containing the trimming resistor and the fuse to achieve the trimming purpose. The beneficial effect obtained is that, compared with traditional trimming circuits, the trimming circuit provided by this invention can still perform the function of trimming the reference even when the fuse is not completely burned out.

[0054] As a further preferred embodiment, the above-mentioned adjustment circuit, such as Figure 2 As shown, the first branch includes:

[0055] The first processing circuit receives the enable signal and generates a processing signal output based on the enable signal. Schematic, when the enable signal is low, the first processing signal is high; similarly, when the enable signal is high, the first processing signal is low.

[0056] Furthermore, the first processing circuit can be formed by the first inverter I42. The purpose of using an inverter is to make regular adjustments to the enable signal. For example, in analog circuits, the signal is easily affected by components and temperature in the circuit, which can cause the level signal to form "unexpected" harmonic signals. The first inverter I42 converts the irregular level signal into a regular level signal with a 180° phase difference for output, so as to avoid affecting the signals of subsequent circuits.

[0057] A first control switch, the control terminal of which is connected to the output terminal of the first processing circuit, is used to receive a first processing signal and generate a first control signal output when the first processing signal matches a first predetermined signal, and generate a second control signal output when the first processing signal does not match the first predetermined signal. The first predetermined signal may be a high-level signal. Schematic, when the first processing signal is a high-level signal, it is determined that the first processing signal matches the first predetermined signal, and the first control switch operates in the on state, at which time the first control signal is low-level. Conversely, when the first processing signal is a low-level signal, it is determined that the first processing signal does not match the first predetermined signal, and the first control switch operates in the off state, at which time the second control signal is generated, and the second control signal is high-level.

[0058] Furthermore, the first control switch can be formed by a first NMOS transistor NM9. The gate of the first NMOS transistor NM9 is connected to the output of the first processing circuit, the source of the first NMOS transistor NM9 is connected to a common ground, and the drain of the first NMOS transistor NM9 forms the output terminal of the first control switch.

[0059] The first driving circuit has its input terminal connected to the output terminal of the first control switch and the input terminal of the second processing circuit. Its control terminal is used to receive a bias signal. The first driving circuit, upon receiving the second control signal and the bias signal, generates a comparison signal output. Specifically:

[0060] When the first control switch outputs the second control signal, the first control switch is in the off state. At this time, the control terminal receives the bias voltage vbp1 (bias signal), and the bias voltage vbp1 drives the first drive circuit to work in the on state and output a high level.

[0061] The first driving circuit is formed by two PMOS transistors, namely a first driving PMOS transistor PM9 and a second driving PMOS transistor PM12. The gate of the first driving PMOS transistor PM9 is connected to the gate of the second driving PMOS transistor PM12 and is connected to a bias voltage vbp1. The drain of the first driving PMOS transistor PM9 is connected to the source of the second driving PMOS transistor PM12. The drain of the second driving PMOS transistor PM12 forms the output terminal of the first driving circuit, and the source of the first driving PMOS transistor PM9 forms the input terminal of the first driving circuit.

[0062] The second processing circuit is connected to the output terminals of the first control switch and the first driving circuit. The second processing signal is output when the first control switch is in the off state and the first driving circuit outputs a high level. The second processing circuit can be a capacitor element. Further, the second processing circuit can be formed by a second NMOS transistor NM12. Schematically, the gate of the second NMOS transistor NM12 is connected to the output terminal of the first driving circuit, and the source of the second NMOS transistor NM12 is connected to the drain of the second NMOS transistor NM12 and connected to a common ground. The NMOS transistor has a relatively small area, which is beneficial for circuit integration.

[0063] Specifically, when the first driving circuit outputs a high-level signal, this high-level signal charges the second processing circuit to form a charging voltage (or charging voltage drop), which continuously increases over time. This charging voltage is the second processing signal generated by the second processing circuit.

[0064] The first comparator circuit has its input terminal connected to the second processing circuit to generate a first comparator signal output based on the second processing signal. Further, the first comparator circuit is formed by a first comparator NMOS transistor NM10 and a first comparator PMOS transistor PM10. The gates of the first comparator NMOS transistor NM10 and the first comparator PMOS transistor PM10 are connected and connected to the output terminal of the second processing circuit. The drain of the first comparator NMOS transistor NM10 is connected to the drain of the first comparator PMOS transistor PM10. The source of the first comparator NMOS transistor NM10 is connected to a common ground, and the source of the first comparator PMOS transistor PM10 is connected to the power supply voltage VDD.

[0065] When the second processing signal is high, it drives the first comparator NMOS transistor NM10 to turn on and the first comparator PMOS transistor PM10 to turn off. At this time, the output of the first comparator circuit is low (i.e., net2 is a low-level signal). When the second processing signal is low, it drives the first comparator PMOS transistor PM10 to turn on and the first comparator NMOS transistor NM10 to turn off. At this time, the output of the first comparator circuit is high (i.e., net2 is a high-level signal, with a voltage close to VDD).

[0066] It should be noted that the high level of the second processing signal here should be understood as a voltage signal that can drive the first comparator NMOS transistor NM10 to conduct, and not as the low and high levels represented by 0 or 1 in digital circuits. Similarly, the low level of the second processing signal here should be understood as a voltage signal that can drive the first comparator PMOS transistor PM10 to conduct. Since the second processing signal is based on charging the second processing circuit to form a charging voltage, the increase of this voltage is related to the time constant. During this process, the second processing circuit will generate a pulse signal with a very short period of time.

[0067] A third processing circuit has its first input connected to the output of the first comparator circuit, and its second input receiving the enable signal. The third processing circuit is used to generate the drive signal output under the influence of the first comparator signal and the enable signal. Schematably, the third processing circuit can be formed by a NAND gate I43, with its first input connected to the drain of the first comparator NMOS transistor NM10. The second input of the NAND gate I43 is used to receive the enable signal.

[0068] When the first comparison signal or the enable signal is low, the NAND gate I43 outputs a high level (i.e., the drive signal net3 is high). When both the first comparison signal and the enable signal are high, the NAND gate I43 outputs a low level (i.e., the drive signal net3 is low).

[0069] As a further preferred embodiment, the second branch includes:

[0070] The second comparator circuit is connected to the output terminal of the first branch to receive the drive signal and generate a drive sub-signal output under the action of the drive signal; further:

[0071] The second comparator circuit is formed by a second NMOS transistor NM8 and a second PMOS transistor PM0. The gates of the second NMOS transistor NM8 and the second PMOS transistor PM0 are connected and connected to the output terminal of the third processing circuit. The source of the second NMOS transistor NM8 is connected to the source of the second PMOS transistor PM0 and forms the output terminal of the second comparator circuit. The source of the second NMOS transistor NM8 is connected to the common ground, and the source of the second PMOS transistor PM0 is connected to the power supply voltage VDD.

[0072] Specifically: When the drive signal net3 is high, the drive signal turns on the second comparator NMOS transistor NM8 and turns off the second comparator PMOS transistor PM0. At this time, the output of the second comparator circuit is low (i.e., the drive sub-signal net4 is low). When the second processing signal is low, the drive signal net3 turns on the second comparator PMOS transistor PM0 and turns off the second comparator NMOS transistor NM8. At this time, the output of the second comparator circuit is high (i.e., the drive sub-signal net4 is high, and the voltage is close to VDD).

[0073] At least one trimming control branch is provided, and the input terminals of all the trimming control branches are connected to the second comparator circuit, forming the control signal output under the action of the drive sub-signal. Further, each trimming control branch is formed by a trimming resistor and a trimming fuse connected in series. One end of each trimming control branch is connected to the second comparator circuit, and the other end is connected to a common ground. The connection point between the trimming resistor and the trimming fuse forms the output terminal of the trimming control branch.

[0074] Indicatively, such as Figure 3As shown, one adjustment control branch is connected in series with adjustment resistor R1 and adjustment fuse I61, wherein the connection point of adjustment resistor R1 and adjustment fuse I61 forms the output terminal tr(0) of the adjustment control branch, and another adjustment control branch is connected in series with adjustment resistor R13 and adjustment fuse I62, wherein the connection point of adjustment resistor R13 and adjustment fuse I62 forms the output terminal tr(1) of the adjustment control branch.

[0075] like Figure 4 As shown, in a further preferred embodiment, the third branch includes: the third branch includes at least one third sub-branch, and one third sub-branch matches one adjustment control branch; the third sub-branch includes:

[0076] The third comparison circuit is connected to the output terminal of the second branch to receive the control signal and generate a third comparison signal output based on the control signal; further,

[0077] The third comparator circuit is formed by a third comparator NMOS transistor NM0 and a third comparator PMOS transistor PM1. The gates of the third comparator NMOS transistor NM0 and the third comparator PMOS transistor PM1 are connected and connected to the output terminal of the adjustment control branch. The drain of the third comparator NMOS transistor NM0 is connected to the drain of the third comparator PMOS transistor PM1 and forms the output terminal of the third comparator circuit. The source of the third comparator NMOS transistor NM0 is connected to the common ground, and the source of the third comparator PMOS transistor PM1 is connected to the power supply voltage VDD.

[0078] Specifically: When the control signal is high, the control signal drives the third comparator NMOS transistor NM0 to turn on and the third comparator PMOS transistor PM1 to turn off. At this time, the output of the third comparator circuit is low (i.e., the third comparator signal net5 is a low-level signal). When the control signal is low, the control signal drives the third comparator PMOS transistor PM1 to turn on and the third comparator NMOS transistor NM0 to turn off. At this time, the output of the third comparator circuit is high (i.e., the third comparator signal net5 is a high-level signal, and the voltage is close to VDD).

[0079] The fourth processing circuit is connected to the output of the second comparison circuit to receive the third comparison signal and generate a fourth processing signal output based on the third comparison signal; further, the fourth processing circuit is formed by the second inverter I44.

[0080] A fifth processing circuit, whose first input terminal is connected to the output terminal of the fourth processing circuit and whose second output terminal is connected to the output terminal of the first processing circuit, is used to receive the first processing signal and the fourth processing signal, and to generate the adjustment signal output based on the first processing signal and the fourth processing signal. The fifth processing circuit is formed by an RS flip-flop I52. The R input terminal of the RS flip-flop is connected to the output terminal of the first inverter I42, and the S input terminal of the RS flip-flop is connected to the output terminal of the second inverter I44. The Q output terminal of the RS flip-flop forms the output terminal of the fifth processing circuit. The output terminal is left floating.

[0081] like Figure 2 , 3 As shown in Figure 4, the working principle of a tuning circuit is specifically explained:

[0082] When the enable signal en is low, the enable signal forms the first processing signal en_b through the first inverter I42. The first processing signal en_b is high, and the first NMOS transistor NM9 is turned on. The output signal net1 of the first control switch is low. At this time, the first comparator PMOS transistor PM10 is turned on, the output signal net2 of the first comparator circuit is low, and the enable signal en is low. The output signal of the NAND gate I43 is high, that is, net3 is high. At this time, the second comparator PMOS transistor PM0 is in the off state, and the second comparator NMOS transistor NM8 is in the on state. Since the output terminal net4 of the second comparator circuit is low when the second comparator NMOS transistor NM8 is in the on state, the voltage drop of all trimming branches is low. Taking a trimming control branch as an example, the voltage drop of the output terminal tr(0) of a trimming control branch is low. The low level of the output terminal tr(0) of the adjustment control branch drives the third comparator PMOS transistor PM1 to turn on. At this time, the source of the third comparator PMOS transistor PM1 outputs a high level (i.e., net5 is high). After being reversed by the second inverter I44, it outputs a low level. The S input terminal of the RS flip-flop is connected to a low level, the R input terminal is connected to a high level, and the Q terminal outputs a low level signal.

[0083] When the enable signal en is high, it forms the first processing signal en_b through the first inverter I42. When the first processing signal en_b is low, the first NMOS transistor NM9 is turned off. Since the first driving circuit is connected to the bias voltage vbp1, it drives the first driving PMOS transistor PM9 and the second driving PMOS transistor PM12 to conduct. At this time, the voltage of net1 is high (close to VDD). The high level of net1 charges the second MOS transistor NM12. When the charging voltage of the second MOS transistor NM12 is less than the predetermined switching threshold voltage, the first comparator PMOS transistor PM10 is turned on. At this time, the voltage of net2 is pulled high, and both inputs of the NAND gate I43 are high (en is high and net2 is high). At this time, the output of the NAND gate I43 is low, that is, net3 is low. When net3 is low, the second comparator PMOS transistor PM0 is turned on, and net4 is pulled up to a high level. This high level is applied to the trim control sub-branch to form a current in the trim control sub-branch.

[0084] When the current does not blow the fuse, the output terminal tr(0) of the adjustment control sub-branch is at a low level. The low level of tr(0) drives the third comparator PMOS transistor PM1 to turn on. At this time, net5 is at a high level, and the output of the second inverting comparator I44 is at a low level. Then the S input terminal of the RS flip-flop is at a low level, and the R input terminal is also at a low level. The RS flip-flop Q works in the latching state.

[0085] When the fuse is blown by the current, the output terminal tr(0) of the adjustment control sub-branch is at a high level. The high level of tr(0) drives the third comparator PMOS transistor PM1 to be cut off and the third comparator NMOS transistor NM0 to be turned on. At this time, net5 is at a low level and the second inverting comparator I44 outputs a high level. Then the S input terminal of the RS flip-flop is at a high level, the R input terminal is at a low level, and the Q output terminal of the RS flip-flop is at a high level.

[0086] If the current does not completely burn out the fuse, adjust the voltage divider between the resistor and fuse on the control sub-branch and net4. The voltage tr(0) may be near VDD / 2. Since the width-to-length ratio of the third comparator NMOS transistor NM0 is greater than that of the third comparator PMOS transistor PM1, the on-resistance of the third comparator NMOS transistor NM0 is smaller, and its driving capability is stronger than that of the third comparator PMOS transistor PM1. That is, when the voltage tr(0) is greater than the on-threshold of the third comparator NMOS transistor NM0, NM0 will turn on and pull tr(0) low. At this time, the S set signal of the RS flip-flop is high, the R input is low, and the Q output of the RS flip-flop is high.

[0087] Example 2

[0088] This invention provides another integrated circuit, wherein the integrated circuit includes a trimming circuit provided in Embodiment 1.

[0089] Example 3

[0090] like Figure 5 As shown, the present invention further provides an adjustment circuit. The technical concept of the adjustment circuit provided in this embodiment is the same as that of the adjustment circuit provided in Embodiment 1. The technical concept is as follows: the adjustment purpose is achieved by adjusting the width-to-length ratio of the MOS transistors in the adjustment circuit. Embodiment 1 achieves the adjustment purpose by adjusting the width-to-length ratio of the internal MOS transistors without changing the number of MOS transistors. In this embodiment, the width-to-length ratio of the internal MOS transistors is not adjusted (i.e., the width-to-length ratio of each MOS transistor is the same), and the width-to-length ratio of the adjustment circuit is indirectly adjusted by changing the number of MOS transistors to achieve the adjustment purpose. Specifically, it includes:

[0091] A drive signal generating circuit is provided to generate a drive signal output under the action of an enable signal. Further, a processing circuit is included, the input of which receives the enable signal, and the output of which is connected to the drive signal generating circuit. Further, the processing circuit can be formed by a first inverter I82.

[0092] The circuit for forming the driving signal includes a first driving branch and a second driving branch connected to the first driving branch. The first driving branch is connected to the output terminal of the first inverter I82. Schematically, the first driving circuit I58 can be formed by a Pulse_200ns module I58, which contains a capacitor element. The second driving branch can be formed by a second inverter I59.

[0093] Schematic, its working principle is as follows: when the enable signal en is a low-level signal, the first inverter I82 reverses the low-level enable signal en to form a high-level enable processing signal en_b output. The high-level enable processing signal en_b is transmitted to the Pulse_200ns module I58. The Pulse_200ns module I58 forms a low-level drive base signal con and a high-level drive processing signal con_b based on the high-level enable processing signal en_b and outputs them. When the enable signal en changes from low to high, the enable processing signal en_b is a low-level signal. Under the action of the enable processing signal en_b, the Pulse_200ns module I58 generates a pulse signal output (the Pulse_200ns module I58 has an internal protection capacitor element that prevents the signal from decreasing, so the pulse signal is a high-level signal that is maintained for a period of time before decreasing to a low-level signal. The pulse signal is formed during the time the high-level signal is maintained). This pulse signal can be understood as driving the basic signal con.

[0094] A control circuit, connected to the driving signal generating circuit, is used to receive the driving signal and generate a control signal output under the action of the driving signal; further, the control circuit includes a transmission gate control branch, the control terminal of which is connected to the driving signal generating circuit, and the input terminal of which is connected to a constant current signal. Specifically:

[0095] The transmission gate control branch can be formed by a first PMOS transistor M2 and a first NMOS transistor M1. Schematic, the control terminal of the first NMOS transistor M1 receives the drive base signal *con*, and the control terminal of the first PMOS transistor M2 receives the drive processing signal *con_b*. The operating states of the first PMOS transistor M2 and the first NMOS transistor M1 are determined based on the states of the drive base signal *con* and the drive processing signal *con_b*. For example, when the drive base signal *con* is low and the drive processing signal *con_b* is high, both the first NMOS transistor M1 and the first PMOS transistor M2 are off, and the transmission gate control branch operates in a non-conducting state. Conversely, when both the first NMOS transistor M1 and the first PMOS transistor M2 are on, the transmission gate control branch operates in a conducting state. When the transmission gate control branch is in the conducting state, it outputs a constant current signal *ibias* to the subsequent circuitry.

[0096] An adjustment circuit, connected to the control circuit, is used to receive the control signal and output a trim signal from the formation of the control signal, wherein the adjustment circuit includes a first adjustment branch and a second adjustment branch;

[0097] The first adjustment branch is formed by the second NMOS transistor M28. The gate of the second NMOS transistor M28 is connected to the driving signal forming circuit to receive the driving processing signal con_b. When the driving processing signal con_b is low, the second NMOS transistor M28 is in the off state. When the driving processing signal con_b is high, the second NMOS transistor M28 is in the on state.

[0098] The second regulating branch is formed by a third PMOS transistor M27 and at least two fourth PMOS transistors M18 connected in parallel. The third PMOS transistor M27 and the at least two fourth PMOS transistors M18 are connected in parallel with each other, such that the width-to-length ratio of the multiple PMOS transistors M18 is greater than that of the PMOS transistor M27. More preferably, the ratio of the number of fourth PMOS transistors M18 to the number of third PMOS transistors M27 is 3:1.

[0099] The third adjustment branch includes a fifth NMOS transistor M29 and a sixth NMOS transistor M37. The gates of the fifth NMOS transistor M29 and the sixth NMOS transistor M37 are interconnected and connected to the source of the seventh NMOS transistor M40. The drain of the sixth NMOS transistor M37 is grounded through a resistor and a trimming fuse. The fifth NMOS transistor M29 and the sixth NMOS transistor M37 have the same width-to-length ratio. The output terminal of the third PMOS transistor M27 is connected to the input terminal of a trimming sub-branch and the input terminal of the sixth NMOS transistor M37. It should be noted that the resistance value of the resistor matches the resistance value of the trimming fuse in the "drawn or stuck" state. Indicatively, the resistance value is 20KΩ. By setting the resistance value to match the resistance value of the trimming fuse in the "drawn or stuck" state, a voltage output value not exceeding (Vdd / 2) is formed when the trimming fuse is in the "drawn or stuck" state.

[0100] Since each PMOS transistor has the same width-to-length ratio, the ratio of the number of fourth PMOS transistors M18 to the number of third PMOS transistors M27 is 3:1, and the width-to-length ratio of the fifth NMOS transistors M29 and M37 is the same. Therefore, the current drawn by the sixth NMOS transistor M37 is greater than that drawn by the third PMOS transistor M27, meaning that the driving capability of the sixth NMOS transistor M37 is greater than that of the third PMOS transistor M27.

[0101] Here is a specific implementation method for a tuning circuit:

[0102] The enable signal 'en' is input as a pulse signal, which passes through an inverter I58 and is then connected to a Pulse_200ns module I58. The Pulse_200ns module I58, composed of logic units and capacitors, generates a brief pulse signal. During this brief pulse signal, it detects whether the circuit's fuse has been blown by current and allows for corresponding adjustments. Specifically:

[0103] When the enable signal en is low, the enable processing signal en_b is high. Therefore, the drive base signal con is low and the drive processing signal con_b is high. These two signals act on the gates of the first PMOS transistor M2 and the first NMOS transistor M1, respectively, turning off both. At this time, the transmission gate is not conducting. The gate of the second NMOS transistor M28 receives the high-level drive processing signal con_b, which drives the second NMOS transistor M28 to conduct. When the second NMOS transistor M28 is in the ON state, its drain is essentially grounded, and the voltage at node NET1 is pulled low. Since the driving base signal con is low, this level drives the seventeenth NMOS transistor M17 to turn on. The output of the seventeenth NMOS transistor M17 is then pulled high to the input voltage VDD, meaning the voltage at node NET2 is high. The gates of the adjustment processing branch all receive the driving processing signal con_b, which is high, thus the adjustment processing branch is turned on and outputs a low-level signal.

[0104] When the enable signal en changes from low to high, the enable processing signal en_b is low. Because of the capacitor within the Pulse_200ns module, the output drive base signal con remains high for a short period before changing to low, thus generating a pulse. While the drive base signal con is high and the drive processing signal con_b is low, the first PMOS transistor M2 and the first NMOS transistor M1 are turned on, and the constant current signal ibias_1uA flows in. The voltage at node NET1 begins to rise, the gate of the fifth NMOS transistor M29 is connected to a high level, and M29 is turned on. At this time, the voltage at node NET2 is pulled low. Since these transistors have the same width-to-length ratio, the ratio of the number of the fourth PMOS transistor M18 to the number of the third PMOS transistor M27 is 3:1, the ratio of the number of the fifth NMOS transistor M29 to the number of the sixth NMOS transistor M37 is 1:1, and further, the ratio of the number of the fifth NMOS transistor M29, the sixth NMOS transistor M37, and the seventh NMOS transistor M40 is 1:1:1. Therefore, the current obtained by the sixth NMOS transistor M37 is greater than the current obtained by the third PMOS transistor M27, and the driving capability of the sixth NMOS transistor M37 is stronger than that of the third PMOS transistor M27. So at this time, the output current of the trimmer branch tr(0) to tr(6) is pulled low.

[0105] If a fuse is blown during this period, for example, if fuse tr_ov(6) is blown, the source (or output) pin of the sixth NMOS transistor M37 will be floating. Therefore, tr(6) will be pulled high by the conducting third PMOS transistor M27. This high-level signal is transmitted to the RS flip-flop. The reset pin of the RS flip-flop is low, and the set pin is high, so the Q output is high. Schematic, this signal can then control the connected logic unit to change the number of series voltage divider resistors, thereby achieving the purpose of adjusting the reference.

[0106] The judgment can still be made even if the fuse is not completely burned out. When the fuse is not completely burned out, there will be a certain resistance. The source voltage (which can also be understood as the output terminal) of the sixth NMOS transistor M37 will become high. When the voltage between the gate and the source is mismatched and the threshold voltage is turned on, the sixth NMOS transistor M37 will work in the off state. Then tr (6) will still be pulled high by the conducting third PMOS transistor M27 to output a high-level signal.

[0107] It should be noted that the RS flip-flop in Embodiment 3 works on the same principle as the RS flip-flop in Embodiment 1, and will not be explained in detail here.

[0108] Example 4

[0109] Finally, the present invention provides another integrated circuit, which includes a trimming circuit provided in Embodiment 3 above.

[0110] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A trim circuit, characterized by include: The first branch is used to generate a drive signal output under the action of the enable signal; The second branch is connected to the first branch and is used to receive the drive signal and generate a control signal output under the action of the drive signal; the second branch includes a trimming fuse; when the trimming fuse is not completely blown, a control signal is generated to drive the third NMOS transistor to conduct. The third branch, connected to the second branch, is used to receive the control signal and generate a trimming signal output based on the control signal. The third branch includes a third comparator circuit formed by a third PMOS transistor and a third NMOS transistor. The gate of the third PMOS transistor is connected to the gate of the third NMOS transistor and to the output terminal of the second branch. The drain of the third PMOS transistor is connected to the source of the third NMOS transistor. The source of the third PMOS transistor is connected to the operating voltage, and the drain of the third NMOS transistor is grounded. The width-to-length ratio of the third NMOS transistor is greater than that of the third PMOS transistor. A trimming signal output is generated to achieve the trimming purpose when the third NMOS transistor is in the ON state.

2. A trim circuit according to claim 1, wherein The first branch includes: The first processing circuit receives the enable signal and generates a processing signal output based on the enable signal. A first control switch, the control terminal of the first control switch is connected to the output terminal of the first processing circuit, for receiving a first processing signal, and generating a first control signal output when the first processing signal matches a first predetermined signal, and generating a second control signal output when the first processing signal does not match the first predetermined signal. The first driving circuit is connected to the output terminal of the first control switch and the second processing circuit, and is used to generate a first driving sub-signal output under the action of the second control signal and the bias signal. The second processing circuit is connected to the output terminal of the first control switch and the first drive circuit, and is used to receive the second control signal and generate a second processing signal output under the action of the second control signal. The first comparison circuit has its input terminal connected to the second processing circuit, and is used to generate a first comparison signal output based on the second processing signal; The third processing circuit has a first input terminal connected to the output terminal of the first comparison circuit, a second input terminal for receiving the enable signal, and a third processing circuit for generating the drive signal output under the action of the first comparison signal and the enable signal.

3. A trim circuit according to claim 2, wherein The first processing circuit is formed by an inverter, and the input of the inverter receives the enable signal.

4. A trim circuit according to claim 2, wherein The first control switch is formed by a first NMOS transistor. The gate of the first NMOS transistor is connected to the output of the first processing circuit, the source of the first NMOS transistor is connected to a common ground, and the drain of the first NMOS transistor forms the output terminal of the first control switch.

5. A trim circuit according to claim 2, wherein, The second processing circuit is formed by a second NMOS transistor. The gate of the second NMOS transistor is connected to the output terminal of the first control switch, and the source of the second NMOS transistor is connected to the drain of the second NMOS transistor and connected to a common ground. ​ 6. A trim circuit according to claim 2, wherein Second branch: The second comparator circuit is connected to the output terminal of the first branch to receive the drive signal and generate a drive sub-signal output under the action of the drive signal. At least one adjustment control branch, and the input terminals of all said adjustment control branches are connected to the second comparator circuit, and the control signal is output under the action of said drive sub-signal.

7. A trim circuit as claimed in claim 6, characterised in that The third branch includes: the third branch includes at least one third sub-branch, the third sub-branch being matched with the adjustment control branch; the third sub-branch includes: The third comparison circuit is connected to the output terminal of the second branch to receive the control signal and generate a third comparison signal output based on the control signal. The fourth processing circuit is connected to the output terminal of the third comparison circuit to receive the third comparison signal and generate a fourth processing signal output based on the third comparison signal. The fifth processing circuit has a first input terminal connected to the output terminal of the fourth processing circuit and a second output terminal connected to the output terminal of the first processing circuit. It is used to receive the first processing signal and the fourth processing signal, and to form the adjustment signal output based on the first processing signal and the fourth processing signal.

8. A trimming circuit, characterized by include: A drive signal circuit is formed to generate a drive signal output under the action of an enable signal; A control circuit, connected to the driving signal generating circuit, is used to receive the driving signal and generate a control signal output under the action of the driving signal; An adjustment circuit, connected to the control circuit, is used to receive the control signal and output a trimming signal from the formation of the control signal, wherein the adjustment circuit includes: The second regulation branch is formed by a third PMOS transistor and at least two fourth PMOS transistors connected in parallel. The third PMOS transistor and the at least two fourth PMOS transistors connected in parallel are connected in parallel with each other so that the width-to-length ratio of the multiple PMOS transistors is greater than that of the PMOS transistor. The third adjustment branch includes a fifth NMOS transistor and a sixth NMOS transistor. The gates of the fifth NMOS transistor and the sixth NMOS transistor are connected to each other and to the source of the seventh NMOS transistor. The drain of the sixth NMOS transistor is grounded through a resistor and a trimming fuse. The width-to-length ratio of the fifth NMOS transistor and the sixth NMOS transistor is the same. The resistance value is matched to the resistance value formed when the adjustment fuse is not completely melted.

9. A trim circuit as claimed in claim 8, characterised in that, The circuit for generating the driving signal includes a first driving branch and a second driving branch connected to the first driving branch. The first driving branch contains a capacitor element for generating a pulse signal.

10. A trimming circuit according to claim 8, characterized in that, The control circuit includes a transmission gate control branch, the control terminal of which is connected to the generating drive signal circuit, and the input terminal of which is connected to a constant current signal.

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