Simulation method, apparatus, and system

Abstract

The application provides a simulation method, device and system. The method comprises: a first simulation device storing serial numbers of at least one logic gate connected with an output node of a faulty logic gate into a first data structure, the first data structure being capable of storing M serial numbers, the number of logic gates in a fan-out area of the faulty logic gate being N, M < N, the faulty logic gate corresponding to at least one fault; under the condition that it is determined that a first logic gate corresponds to a logic value of a first fault, the first simulation device deleting the serial number of the first logic gate from the first data structure; wherein the first logic gate is one of the at least one logic gate, and the first fault is one of the at least one fault. Through the above method, the application can reduce the order of magnitude of the data that needs to be stored by the simulation device during fault simulation, which can increase the number of test vectors and the number of concurrent threads for fault simulation, thereby enhancing the execution speed of fault simulation and improving the efficiency of fault simulation.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip testing, and more particularly, to a simulation method, device and system. BACKGROUND

[0002] Fault simulation refers to a process of simulating a response of a circuit-under-test (CUT) using at least one set of test vectors in a case of fault modeling, which plays an important role in various applications of very-large-scale integration (VISL) circuit testing, including but not limited to: automatic test pattern generation (ATPG), built-in self-test, etc. The purpose of fault simulation is to select a number of test vectors so as to detect as many possible faults in the circuit as possible.

[0003] The existing technology mainly implements accelerated running of fault simulation by using a highly parallel multi-thread and multi-core processor of a graphics processing unit (GPU), but the simulation efficiency of the existing GPU-based fault simulation is affected by various factors, for example, large memory occupation, etc.

[0004] Therefore, how to improve the fault simulation efficiency based on the GPU is a technical problem to be solved urgently. SUMMARY

[0005] The present application provides a simulation method, device and system, which stores the serial numbers of logic gates connected to the output nodes of fault logic gates into a data structure with limited memory space and supporting deletion of stored serial numbers of logic gates, so that the simulation device can recycle the data structure, can reduce the order of magnitude of data to be stored during fault simulation, thereby increasing the number of test vectors and the number of concurrent threads for fault simulation, and further enhancing the execution speed of fault simulation and improving the fault simulation efficiency.

[0006] In a first aspect, a simulation method is provided, comprising: storing, by a first simulation device, serial numbers of at least one logic gate connected to an output node of a faulty logic gate into a first data structure, the first data structure being capable of storing a number of serial numbers M, a number of logic gates in a fan-out region of the faulty logic gate being N, M being less than N, the faulty logic gate corresponding to at least one fault; and deleting, by the first simulation device, the serial number of a first logic gate from the first data structure on a condition that the first logic gate is determined to correspond to a logic value of a first fault, the first logic gate being one of the at least one logic gate, the first fault being one of the at least one fault.

[0007] It should be understood that the serial number of a logic gate can be understood as an identifier of the logic gate, the identifier of a logic gate being used to uniquely indicate the logic gate.

[0008] In addition, the storing, by the first simulation device, of the serial numbers of the at least one logic gate into the first data structure can be understood as the storing, by the first simulation device, of the serial numbers of the at least one logic gate into a first memory, the first memory being capable of storing the number of serial numbers M.

[0009] In particular, the deleting, by the first simulation device, of the serial number of the first logic gate from the first data structure on the condition that the first logic gate is determined to correspond to the logic value of the first fault can be understood as: the first simulation device taking out the serial number of the first logic gate from the first data structure, deleting the serial number of the first logic gate while performing fault simulation on the first logic gate; or can be understood as: the first simulation device taking out the serial number of the first logic gate from the first data structure, performing fault simulation on the first logic gate, and then deleting the serial number of the first logic gate.

[0010] By storing the serial numbers of the logic gates connected to the output node of the faulty logic gate into the memory-limited data structure supporting deletion of the stored serial numbers of the logic gates, the first simulation device can complete the simulation processing of all the logic gates in the fan-out region of the faulty logic gate in a manner of recycling the data structure, which can reduce the order of magnitude of the data required to be stored during fault simulation, thereby increasing the number of test vectors and the number of concurrent threads for fault simulation, and also enhancing the execution speed of fault simulation and improving the efficiency of fault simulation, for example, more test vectors can be tested, thereby determining more test vectors that can be used for actual testing.

[0011] With reference to the first aspect, in some implementations of the first aspect, the method further includes: when the logic value of the first logic gate corresponding to the first fault is the same as the logic value of the first logic gate not corresponding to the first fault, under the condition that the second logic gate corresponds to the logic value of the first fault, the first simulation device deletes the serial number of the second logic gate from the first data structure, the second logic gate being another logic gate different from the first logic gate among the at least one logic gate; or when the logic value of the first logic gate corresponding to the first fault is different from the logic value of the first logic gate not corresponding to the first fault, the first simulation device stores the serial number of at least one logic gate connected to the output node of the first logic gate into the first data structure.

[0012] It can be understood that the logic value of the first logic gate corresponding to the first fault refers to the logic value of the first logic gate when the fault exists. The logic value of the first logic gate not corresponding to the first fault refers to the logic value of the first logic gate when the fault does not exist.

[0013] Specifically, when it is determined that the logic value of the first logic gate corresponding to the first fault is the same as the logic value of the first logic gate not corresponding to the first fault, the first simulation device starts fault simulation on the second logic gate and deletes the serial number of the second logic gate from the first data structure; when it is determined that the logic value of the first logic gate corresponding to the first fault is different from the logic value of the first logic gate not corresponding to the first fault, the first simulation device stores the serial number of the logic gate connected to the output node of the first logic gate into the first data structure.

[0014] By deleting and adding the serial numbers of the logic gates in the data structure, the first simulation device can recycle the data structure, thereby saving the memory for storing the logic gate information and improving the overall efficiency of fault simulation.

[0015] With reference to the first aspect, in some implementations of the first aspect, when the logic value of the first logic gate corresponding to the first fault is different from the logic value of the first logic gate not corresponding to the first fault, the method further includes: the first simulation device stores the logic value of the first logic gate corresponding to the first fault and the serial number of the first logic gate into the second data structure.

[0016] In this way, the embodiments of the present application can reduce the memory overhead for storing the fault values, and can use the secondary storage mode of simultaneously storing the fault values and the corresponding serial numbers to replace the storage of the fault values of all the logic gates.

[0017] It can be understood that the embodiments of the present application do not make any limitation on the second data structure.

[0018] With reference to the first aspect, in some implementations of the first aspect, after the first simulation device stores the sequence numbers of the at least one logic gate connected to the output node of the first logic gate into the first data structure, the method further includes: under the condition that the third logic gate corresponds to the logic value of the first fault, the first simulation device deletes the sequence number of the third logic gate from the first data structure; wherein the third logic gate is one of the at least one logic gate connected to the output node of the first logic gate.

[0019] With reference to the first aspect, in some implementations of the first aspect, before the first simulation device stores the sequence numbers of the at least one logic gate into the first data structure, the method further includes: the first simulation device acquires the first data structure sent by the second simulation device; wherein the first data structure is determined by the second simulation device according to the total number of the logic gates and the prior information; or the first data structure is determined by the second simulation device according to the number of the logic gates in the fan-out region of the faulty logic gate.

[0020] Specifically, the data structure can be determined by the second simulation device according to the total number of the logic gates, the prior information, or the number of the logic gates in the fan-out region of the faulty logic gate, so that the number of the sequence numbers that can be stored in the data structure can support the first simulation device to perform the fault simulation processing on most of the faulty logic gates when the first simulation device performs the fault simulation.

[0021] With reference to the first aspect, in some implementations of the first aspect, the first data structure includes at least one of the following: a priority queue, a small heap structure; wherein the first logic gate is the logic gate with the highest priority in the fault simulation order among the at least one logic gate.

[0022] By using the priority queue or the small heap structure, and the first logic gate being the logic gate with the highest priority in the fault simulation among the at least one logic gate connected to the output node of the faulty logic gate, the first simulation device will not perform multiple simulations on the same logic gate when performing the fault simulation, so that the power consumption of the first simulation device when performing the fault simulation can be saved.

[0023] With reference to the first aspect, in some implementations of the first aspect, before the first simulation device stores the sequence numbers of the at least one logic gate into the first data structure, the method further includes: the first simulation device acquires the information of the at least one fault sent by the second simulation device.

[0024] By sending the fault information that needs to be simulated by the first simulation device to the first simulation device by the second simulation device, the fault simulation processing can be completed by the first simulation device and the second simulation device in cooperation, so that the overall fault simulation efficiency can be improved.

[0025] With reference to the first aspect, in some implementations of the first aspect, the method further includes: when the number of the at least one logic gate connected to the output node of the first logic gate causes the first data structure to be in an overflow state, the first simulation device sends, to the second simulation device, the sequence number of the first fault.

[0026] The second aspect provides a simulation device, including: a processing module, configured to store the sequence number of the at least one logic gate into a first data structure, the at least one logic gate being connected to an output node of a fault logic gate, the first data structure being capable of storing a number of sequence numbers M, the number of logic gates in a fan-out region of the fault logic gate being N, M being less than N, the fault logic gate corresponding to at least one fault; the processing module is further configured to delete the sequence number of the first logic gate from the first data structure on a condition that the first logic gate corresponds to a logic value of the first fault, the first logic gate being one of the at least one logic gate, the first fault being one of the at least one fault; and a storage module, configured to store the sequence number of the at least one logic gate.

[0027] With reference to the second aspect, in some implementations of the second aspect, the processing module is further configured to: when the logic value corresponding to the first fault of the first logic gate is the same as the logic value not corresponding to the first fault of the first logic gate, delete the sequence number of the second logic gate from the first data structure on a condition that the second logic gate corresponds to the logic value of the first fault, the second logic gate being another logic gate different from the first logic gate among the at least one logic gate; or when the logic value corresponding to the first fault of the first logic gate is different from the logic value not corresponding to the first fault of the first logic gate, store the sequence number of the at least one logic gate connected to the output node of the first logic gate into the first data structure.

[0028] With reference to the second aspect, in some implementations of the second aspect, the processing module is further configured to: when the logic value corresponding to the first fault of the first logic gate is different from the logic value not corresponding to the first fault of the first logic gate, store the logic value corresponding to the first fault of the first logic gate and the sequence number of the first logic gate into a second data structure.

[0029] With reference to the second aspect, in some implementations of the second aspect, the processing module is further configured to: delete the sequence number of the third logic gate from the first data structure on a condition that the third logic gate corresponds to the logic value of the first fault; wherein the third logic gate is one of the at least one logic gate connected to the output node of the first logic gate.

[0030] With reference to the second aspect, in some implementations of the second aspect, the processing module is further configured to: obtain the first data structure sent by the second simulation device; wherein the first data structure is determined by the second simulation device according to the total number of the logic gates and prior information; or the first data structure is determined by the second simulation device according to the number of the logic gates in the fan-out region of the fault logic gate.

[0031] In some implementations of the second aspect, the first data structure comprises at least one of: a priority queue or a small min-heap structure; and the first logic gate is a logic gate with the highest priority of fault emulation among the at least one logic gate.

[0032] In some implementations of the second aspect, the processing module is further configured to: receive the information of the at least one fault from the second emulation device.

[0033] In some implementations of the second aspect, the processing module is further configured to: send the sequence number of the first fault to the second emulation device when the number of the at least one logic gate connected to the output node of the first logic gate causes the first data structure to be in an overflow state.

[0034] In some implementations of the third aspect, the first emulation device sends the sequence number of the first fault to the second emulation device when the number of the at least one logic gate connected to the output node of the first logic gate causes the first data structure to be in an overflow state; and the second emulation device is configured to perform fault emulation of the faulty logic gate under the first fault.

[0035] In some implementations of the third aspect, the first emulation device sends the sequence number of the first fault to the second emulation device when the number of the at least one logic gate connected to the output node of the first logic gate causes the first data structure to be in an overflow state; and the second emulation device is configured to perform fault emulation of the faulty logic gate under the first fault.

[0036] The fourth aspect provides a computer-readable storage medium comprising a computer program or instructions, which, when executed on a computer, cause the computer to perform the emulation method of the first aspect and any possible implementation of the first aspect.

[0037] The fifth aspect provides a computer program product comprising instructions, which, when executed on a computer, cause the computer to perform the emulation method of the first aspect and any possible implementation of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 An application scenario of an embodiment of the present application is shown in the following figure.

[0039] Figure 2 An illustration of a single fixed fault model is shown in the following figure.

[0040] Figure 3 An illustration of the correspondence between a compact fault set and a fan-out region of a logic gate is shown in the following figure.

[0041] Figure 4 Figure 1 is a schematic diagram of a simulation method 100 according to an embodiment of the present application.

[0042] Figure 5 Figure 2 is a schematic diagram of a first data structure according to an embodiment of the present application.

[0043] Figure 6 Figure 3 is a schematic diagram of a simulation method 300 according to an embodiment of the present application.

[0044] Figure 7 Figure 4 is a schematic diagram of a logic gate hierarchy according to an embodiment of the present application.

[0045] Figure 8 Figure 5 is a schematic diagram of a simulation apparatus 800 according to an embodiment of the present application.

[0046] Figure 9 Figure 6 is a schematic diagram of a simulation system 900 according to an embodiment of the present application. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be described below with reference to the drawings.

[0048] In the production and manufacturing of chips, there are various physical defects (also referred to as manufacturing defects), such as short circuits to ground and to power supply, short circuits of wires caused by dust particles, short circuits of transistor source or drain caused by metal spike-through, and the like. These physical defects can affect the function implementation of the chip. Therefore, it is necessary to test the chip to determine whether there are physical defects inside the chip, so as to screen out qualified chips.

[0049] Chip testing mainly establishes a logical model of the physical defects of the chip, i.e., a fault model, and determines whether there are physical defects inside the chip by measuring the behavior of the circuit on the input / output pins. Chip testing mainly relies on test vectors (test vectors can be understood as the input excitation of the circuit) based on scan circuits to complete. Therefore, test vectors are very important for chip mass production and screening in the chip manufacturing process.

[0050] The development of test vectors mainly relies on the use of ATPG tools. ATPG tools complete fault simulation and test vector generation based on certain algorithms and modeling of the physical defects of the chip. For large-scale integrated circuits, it takes several weeks or even months of running time to complete a complete ATPG based on multiple fault models. Among them, the running time of fault simulation can account for at least 30% or more of the total running time of ATPG. As a method of chip testing, fault simulation can be used to screen qualified chips. For details, please refer toFigure 1 .

[0051] Figure 1 is a schematic diagram of an application scenario of an embodiment of the present application. As shown in Figure 1 , a chip to be detected includes a plurality of integrated circuits (ICs), which are IC#1-IC#8 respectively. After a processing process of fault simulation, a plurality of qualified chips can be obtained, for example, IC#1, IC#3, IC#5, IC#6, IC#8, etc. Through the processing of fault simulation, the qualified chips in the chip to be detected can be screened out.

[0052] Specifically, fault modeling refers to simulating physical defects in the chip manufacturing process by a mathematical model, so as to study the impact of faults on circuits or systems, and diagnose the location of faults. In fault modeling, the most common fault model in the chip manufacturing industry is the single stuck-at (SSA) fault model. The SSA fault model assumes that all faults can be represented as a pin (referring to the pin of a logic gate rather than the pin of a chip) or node on the circuit being short-circuited to a high level or a low level, i.e., being fixed to level 1 or level 0. When a pin or node is fixed to level 1 or level 0, it means that the response of the circuit is not associated with the actual input of the circuit. The SSA fault model also assumes that each chip under test has at most one fault, i.e., only one logic gate in the circuit has a fault, and an input line or an output line of the logic gate is fixed to level 1 or level 0.

[0053] For ease of description, embodiments of the present application are described by taking the SSA fault model as an example, but the technical solutions of the embodiments of the present application are not limited to the application in other types of fault models, for example, multiple stuck-at fault (MSAF), bridging fault (BF), and delay fault (DF), etc.

[0054] Figure 2 is a schematic diagram of a single stuck-at fault model. As shown in Figure 2 , (a) in Figure 2 shows a fault model in which the input pin A (or node A) of the logic gate is fixed to level 1, Figure 2 (b) shows a fault model in which the output pin Y (or node Y) of the logic gate is fixed to level 0. Wherein, A / B refers to different inputs of the logic gate, and Y refers to the output of the logic gate.

[0055] Generally, the flow of fault simulation is as follows:

[0056] 1) Obtain the circuit information and fault information of a given circuit, and perform logic simulation, i.e., assume that there is no any fault in the circuit;

[0057] 2) Calculate the true value of each logic gate in the circuit based on a given or randomly generated test vector, and record it as T val ;

[0058] 3) Traverse each fault existing in the circuit, and under the SSA fault model, assume that there is only one fault in the circuit each time, and calculate the fault value of the logic gate involved in the fault simulation process under the same test vector, and record it as F val ;

[0059] 4) Finally, compare whether F val and T val of the primary output (PO) of the circuit are equal, if not, it indicates that the test vector can detect the fault; otherwise, it indicates that the test vector cannot detect the fault.

[0060] The current fault simulation technology mainly uses the multi-thread and multi-core processor characteristics of GPU, and realizes the accelerated operation of fault simulation by compressing faults into multiple compact fault sets (CFS).

[0061] Figure 3 A schematic diagram of the correspondence between the compact fault set and the fanout region of the logic gate. As shown in Figure 3 , CFS(A) includes four faults: f1(a / 1), f2(b / 1), f3(c / 0) and f1(c / 1). Among them, f1(a / 1) indicates that the input pin a of logic gate #A has a physical defect and is fixed at high level 1. f2(b / 1) indicates that the input pin b of logic gate #A has a physical defect and is fixed at high level 1. f3(c / 0) indicates that the output pin c of logic gate #A has a physical defect and is fixed at low level 0. f4(c / 1) indicates that the output pin c of logic gate #A has a physical defect and is fixed at high level 1. The FR of each fault is shown in Figure 3 . Logic gate #A is a fault logic gate, which means that the multiple faults included in CFS occur at logic gate #A.

[0062] Exemplarily, the existing GPU-based fault simulation method is as follows:

[0063] 1) - Denote the logic gate containing CFS as the fault logic gate (which can be understood as...) Figure 3 The logic gate #A is used, and the actual value of the faulty logic gate (which can also be understood as the logic value that does not correspond to the fault) and the fault value (which can also be understood as the logic value that corresponds to the fault) are respectively denoted as T. val With F val Fault logic gate F val It can be set to T val The value obtained by inverting each bit, for example, the T of the fault logic gate. val =1, then F val =0.

[0064] 2) Each thread in each thread block performs fault simulation on all logic gates in the FR of the faulty logic gate in sequence, and records which logic gate's T. val A change can trigger the main output of the circuit (if logic gate #E is connected to an external source, then the main output can be understood as...). Figure 3 The logic value of the output of logic gate #E changes.

[0065] 3) Sequentially determine whether each fault in the CFS triggers a change in the recorded main output fault value. If it does, the physical defect can be detected by the test vector; otherwise, it cannot. See Tables 1 and 2 for details. The examples in Tables 1 and 2 are based on... Figure 3 It's confirmed.

[0066] Table 1

[0067]

[0068] Table 2

[0069]

[0070] Specifically, in Tables 1 and 2, a, b, and d represent the main inputs of the circuit. In Table 1, the true values ​​of all logic gates are the logic values ​​simulating the absence of a fault. In Table 2, the fault values ​​of all logic gates except for gate #A are the logic values ​​assuming the output pin c of gate #A is fixed at level 1. In Table 1, the true value of gate #E is 1 only when a = 1, b = 1, and d = 0. In Table 2, the fault value of gate #E is 0 only when d = 1. Table 2 shows that fixing the output pin c of gate #A at level 1 can cause the fault values ​​of the main outputs in Table 2 to differ from the true values ​​multiple times. Therefore, the presence or absence of a fault in logic gate #A can be detected or verified using the test vector (a = 0, b = 0, d = 0), and the fault is f3(c / 1). In other words, it can be verified using the test vector (a = 0, b = 0, d = 0). Figure 3whether the logic gate A of the circuit shown is faulty.

[0071] On one hand, each thread needs to perform fault simulation on all logic gates in the FR of the faulty logic gate, and the GPU needs to store information of all logic gates in the FR of the faulty logic gate, for example, the number of input and output pins, the true value, the faulty value, and the circuit information, etc. When the circuit scale is large or the FR of the faulty logic gate is large, the memory space for storing the test vectors and threads used for fault simulation will be reduced after the GPU stores the information of all logic gates in the FR of the faulty logic gate due to the small memory, and the GPU needs to reduce the number of test vectors and the number of concurrent threads used for fault simulation, which will reduce the execution speed of fault simulation, and even the fault simulation task may not be completed. On the other hand, the existing GPU-based fault simulation only considers fault simulation on the GPU and does not consider cooperative processing with other processors, which may lead to insufficient utilization of the GPU and slow GPU-based fault simulation. In summary, the simulation efficiency of GPU-based fault simulation is affected by many factors, which leads to the inability to fully exert the simulation capability based on the GPU.

[0072] Therefore, the present application provides a simulation method, device and system, by storing the serial numbers of the logic gates connected to the output nodes of the faulty logic gate into the memory-limited data structure supporting deletion of the stored serial numbers of the logic gates, the first simulation device can complete the simulation processing of all logic gates in the fan-out area of the faulty logic gate in a cyclic utilization manner of the data structure, which can reduce the order of magnitude of the data that needs to be stored during fault simulation, thereby increasing the number of test vectors and the number of concurrent threads used for fault simulation, and also enhancing the execution speed of fault simulation and improving the fault simulation efficiency.

[0073] The following will be described in conjunction with Figure 4 The simulation method of the embodiment of the present application is described.

[0074] Figure 4 FIG. 4 is a schematic diagram of the simulation method 400 of the embodiment of the present application. The execution subject of the method 400 is a first simulation device. The first simulation device can be a GPU, a central processing unit (CPU), or other processors such as a hardware acceleration card, a field-programmable gate array (FPGA), etc., which are not limited by the embodiments of the present application. The method 400 includes:

[0075] S410, the first simulation device stores the serial number of the at least one logic gate connected with the output node of the faulty logic gate into a first data structure, the first data structure can store M serial numbers, the number of logic gates in the fan-out region of the faulty logic gate is N, M is less than N, and the faulty logic gate corresponds to at least one fault.

[0076] It should be understood that the serial number of the logic gate can be understood as the identification of the logic gate, and the identification of one logic gate is used to uniquely indicate one logic gate.

[0077] In addition, the first simulation device stores the serial number of the at least one logic gate into the first data structure” can be understood as that the first simulation device stores the serial number of the at least one logic gate into a first memory, and the first memory can store M serial numbers.

[0078] Specifically, the at least one logic gate is connected with the output node of the faulty logic gate A (i.e., the above-mentioned faulty logic gate) and belongs to the logic gates in the fan-out region of the faulty logic gate A. During the fault simulation, the first simulation device stores the serial number (or the logic gate serial number) of the at least one logic gate mentioned above into the first data structure. The first data structure is used to store the serial number of the logic gate.

[0079] Optionally, the first data structure can also be used to store other information of the logic gate corresponding to the stored logic gate serial number, for example, the number information of the input and output pins, the real value, the fault value, and the circuit information, etc.

[0080] The memory space (or length) of the first data structure in S410 is limited. For example, the first data structure can store M serial numbers of the logic gate. In addition, the number of the logic gates in the fan-out region of the faulty logic gate A is N, and M is less than N. It can be understood that the first simulation device can perform fault simulation processing on the faulty logic gate whose number of logic gates in the fan-out region is within M.

[0081] It can be understood that the number N of the logic gates in the fan-out region of the faulty logic gate A can be considered as the maximum value or the average value of the number of the logic gates in the fan-out region of the faulty logic gate in the entire circuit, etc. This can be set according to the actual situation, and the embodiments of the present application are not limited. When the number of the logic gates in the fan-out region of a certain faulty logic gate is greater than M, the first simulation device terminates the fault simulation processing.

[0082] As an example, the first data structure can be set in a static manner. For example, the first data structure used by the first simulation device is irrelevant to the number of the logic gates in the fan-out region of the faulty logic gate to be processed.

[0083] As an example, the first data structure can also be set in a dynamic manner. For example, the second simulation device determines the first data structure according to the number N of logic gates in the fan-out region of the fault logic gate A to be processed by the first simulation device. As an example, if N = 100, then M = 30. In this way, the first simulation device can flexibly change the number of logic gate serial numbers that the first data structure can store when performing fault simulation, so as to further save the memory space for storing logic gate information, and thus improve the fault simulation efficiency.

[0084] Optionally, the second simulation device can determine the first data structure according to the total number of logic gates and prior information. The first data structure determined by the second simulation device can be used by the first simulation device to store the serial numbers of at least one logic gate connected to the output node of the fault logic gate when performing fault simulation processing, and does not need to store the information of all logic gates in the fan-out region of the fault logic gate.

[0085] Optionally, the second simulation device sends the first data structure determined by it to the first simulation device. Correspondingly, the first simulation device receives the first data structure from the second simulation device. The description of the first data structure can refer to Figure 5 .

[0086] Figure 5 The first data structure of the embodiment of the present application is shown in the following schematic diagram. Figure 5 (a) of FIG. 1 shows the first data structure of a ring priority queue (PQ). The length of the ring PQ is m, that is, the number of logic gate serial numbers that the ring PQ can store is m. In the ring PQ, the m logic gate serial numbers are sorted according to the level numbers of the logic gates. For example, the four logic gate serial numbers stored in the ring PQ are Gate#1, Gate#5, Gate#7 and Gate#10, and the four logic gates are sorted according to the level numbers of the logic gates, that is, the level number of Gate#1 < the level number of Gate#5 < the level number of Gate#7 < the level number of Gate#10.

[0087] Optionally, the first data structure can also include a non-ring PQ. By using the data structure of the priority queue, the embodiment of the present application can realize convenient data insertion and deletion operations.

[0088] Figure 5(b) shows a first data structure of a small top heap structure. Wherein, the heap refers to a one-dimensional array maintained by a structure of a complete binary tree, and the small top heap refers to a value of each node being less than or equal to values of left and right child nodes. By using a one-dimensional array structure after mapping based on the small top heap, the structure of the heap needs to be adjusted each time an element is inserted, so that the small top heap structure still meets the condition limit. When each element is taken out, the top element of the one-dimensional array corresponding to the small top heap structure (i.e., all minimum sequence numbers in the array) is taken out, and the structure of the heap is adjusted to re-establish a new small top heap structure.

[0089] In Figure 5 In (b) of the above, the numbers in the circle represent the sequence numbers of the logic gates, and the numbers outside the circle represent the level numbers of the logic gates. The arrangement of the sequence numbers of the logic gates needs to follow the rules of the complete binary tree, so that faster data insertion and deletion operations can be achieved.

[0090] By using the priority queue or the small top heap structure, and the first logic gate being the logic gate with the highest fault simulation priority among the at least one logic gate to which the output node of the fault logic gate is connected, the first simulation device does not perform multiple simulations on the same logic gate during fault simulation, so that the power consumption of the first simulation device during fault simulation can be saved.

[0091] It can be understood that, before storing the sequence numbers of the at least one logic gate into the first data structure, the first simulation device needs to determine whether the number of the sequence numbers of the at least one logic gate will cause the first data structure to be in an overflow state. If the number of the sequence numbers of the at least one logic gate will cause the first data structure to be in the overflow state, the first simulation device terminates the fault simulation of the fault logic gate A; if the number of the sequence numbers of the at least one logic gate will not cause the first data structure to be in the overflow state, the first simulation device starts the fault simulation of the fault logic gate A after storing the sequence numbers of the at least one logic gate. Wherein, the first data structure being in the overflow state can be understood as: the sum of the number Y of the sequence numbers of the logic gates already stored in the first data structure and the number K of the sequence numbers of the at least one logic gate is greater than M, i.e., Y+K>M.

[0092] Wherein, the at least one fault corresponding to the fault logic gate A in S410 can be combined in the manner of the compact fault set of the CFS, or can be combined in other manners, which is not limited in the embodiments of the present application.

[0093] It can be understood that each fault in the embodiments of the present application can have a corresponding sequence number, so that different faults can be distinguished.

[0094] S420, under the condition that the first logic gate corresponds to the logic value of the first fault, the first simulation device deletes the sequence number of the first logic gate from the first data structure, the first logic gate being one of the at least one logic gate, and the first fault being one of the at least one fault.

[0095] Specifically, under the condition that the first simulation device determines that the first logic gate corresponds to the logic value of the first fault, the first simulation device deletes the serial number of the first logic gate from the first data structure. It can be understood that: the first simulation device takes out the serial number of the first logic gate from the first data structure, and deletes the serial number of the first logic gate while performing fault simulation on the first logic gate; or it can also be understood that: the first simulation device takes out the serial number of the first logic gate from the first data structure, and deletes the serial number of the first logic gate after performing fault simulation on the first logic gate.

[0096] Specifically, under the condition that the first simulation device determines that the first logic gate corresponds to the logic value of the first fault, the first simulation device deletes the serial number of the first logic gate from the first data structure. Thus, this can make the memory space of the first data structure recyclable, and can complete the simulation processing of the logic gates in the fan-out area of the fault logic gate.

[0097] In order to better understand the content shown in S420, the following will be combined with Table 1, Table 2 and Figure 3 Further description is made.

[0098] It is assumed that the fault logic gate A is the logic gate A, and the logic gate B and the logic gate C belong to the at least one logic gate described above. The first logic gate is any one of the logic gate B or the logic gate C. The at least one fault corresponding to the logic gate A includes: f1(a / 1), f2(b / 1), f3(c / 0) and f4(c / 1). The first fault is f4(c / 1). The first simulation device determines that the fault value of the logic gate B is 0 under the condition of the first test vector (a=0\b=0\d=0) and the first fault f4(c / 1) (see Table 2). At the same time, the first simulation device deletes the serial number of the logic gate B from the first data structure.

[0099] By storing the serial numbers of the logic gates connected to the output node of the fault logic gate into the data structure with limited memory and supporting deletion of the stored serial numbers of the logic gates, the first simulation device can complete the simulation processing of all the logic gates in the fan-out area of the fault logic gate in a way of recycling the data structure, which can reduce the order of magnitude of the data required to be stored when the GPU performs fault simulation, thereby increasing the number of test vectors and the number of concurrent threads for fault simulation, and also enhancing the execution speed of fault simulation and improving the efficiency of fault simulation.

[0100] In other words, by reducing the order of magnitude of the data required to be stored when the GPU performs fault simulation, the GPU can increase the number of test vectors and the number of concurrent threads for fault simulation, thereby enhancing the execution speed of fault simulation, so that it can effectively complete fault simulation on a large-scale circuit (for example, a circuit of tens of millions of gates or more).

[0101] In one possible implementation, when the logic value of the first logic gate corresponding to the first fault is the same as the logic value of the first logic gate not corresponding to the first fault, the first simulation device deletes the serial number of the second logic gate from the first data structure under the condition that the second logic gate corresponds to the logic value of the first fault.

[0102] For example, the first logic gate is logic gate B, and the logic value of logic gate B corresponding to the first test vector (a=0\b=0\d=0) and the first fault f4(c / 1) is 0 (see Table 2), which is the same as the logic value of logic gate B corresponding to only the first test vector (a=0\b=0\d=0) (see Table 1). Therefore, the first simulation device can determine that the second logic gate corresponds to the logic value of the first fault and the first test vector, and the second logic gate can be understood as logic gate C. At the same time, the first simulation device deletes the serial number of the second logic gate from the first data structure.

[0103] In one possible implementation, when the logic value of the first logic gate corresponding to the first fault is different from the logic value of the first logic gate not corresponding to the first fault, the first simulation device stores the serial number of at least one logic gate connected to the output node of the first logic gate into the first data structure.

[0104] For example, the first logic gate is logic gate C, and the logic value of logic gate C corresponding to the first test vector (a=0\b=0\d=0) and the first fault f4(c / 1) is 1 (see Table 2), which is different from the logic value of logic gate C corresponding to only the first test vector (a=0\b=0\d=0) (see Table 1). The first simulation device stores the serial number of at least one logic gate connected to the output node of logic gate C into the first data structure, for example, the serial number of logic gate E connected to the output node of logic gate C is stored into the first data structure.

[0105] Specifically, when the logic value of the first logic gate corresponding to the first fault is the same as the logic value of the first logic gate not corresponding to the first fault, the first simulation device starts fault simulation on the second logic gate, and deletes the serial number of the second logic gate from the first data structure; when the logic value of the first logic gate corresponding to the first fault is different from the logic value of the first logic gate not corresponding to the first fault, the first simulation device stores the serial number of the logic gate connected to the output node of the first logic gate into the first data structure.

[0106] By deleting and adding the serial numbers of the logic gates in the data structure, the first simulation device can recycle the data structure, thereby saving the memory for storing the logic gate information, and then improving the overall efficiency of fault simulation.

[0107] In one possible implementation, the first simulation device simulates the fault of the logic gate E, i.e., the first simulation device simulates a third logic gate in at least one logic gate connected to the output node of the first logic gate. Details can be referred to the foregoing description of the first logic gate, which will not be repeated here.

[0108] In one possible implementation, the first simulation device receives the information of at least one fault corresponding to the fault logic gate A from the second simulation device. For example, the second simulation device can send the information of at least one fault corresponding to the fault logic gate A to the first simulation device according to a pre-set fault allocation ratio. Through the cooperative processing of the first simulation device and the second simulation device, the fault simulation efficiency of the first simulation device can be further improved. Each fault can include a serial number, so as to distinguish different faults.

[0109] Specifically, when the FR of the fault logic gate A is small, the memory occupancy of the fault logic gate A in simulation is also small. Therefore, the number of logic gates in the FR of each logic gate in the circuit can be pre-counted and sorted in descending order. Then each fault is sorted according to the serial number of the logic gate in which the fault is located. Assuming that the total number of faults is N, and the fault allocation ratio in the second simulation device is a (0≤a≤1), the fault allocation ratio in the first simulation device is 1-a. According to the sorted faults, the first N*a faults are allocated to the second simulation device, and the remaining faults are allocated to the first simulation device. Subsequently, the second simulation device and the first simulation device simultaneously start fault simulation. The second simulation device can use a multi-level queue or the foregoing data structure, and the first simulation device uses the foregoing data structure.

[0110] In one possible implementation, when the number of at least one logic gate connected to the output node of the first logic gate causes the first data structure to be in an overflow state, the first simulation device sends the serial number of the first fault to the second simulation device.

[0111] Specifically, if the number of logic gates connected to the output node of the first logic gate causes the first data structure to be in an overflow state, the first simulation device can send the serial number of the first fault to the second simulation device, and the second simulation device can complete the simulation of the fault logic gate under the first fault. In this way, through the cooperative simulation of the first simulation device and the second simulation device, the overall efficiency of fault simulation can be improved.

[0112] Optionally, different first simulation devices simulate different faults, i.e. device parallelism. Each bit (32 or 64 bits) in the computer can correspond to a different test vector, i.e. bit parallelism. Each thread in the first simulation device simulates different faults for the same set of test vectors, i.e. fault parallelism, thereby minimizing memory occupation. When the simulation is completed, the first simulation device transmits the faults that have not been simulated to the second simulation device, and the second simulation device re-executes the simulation. In this way, through the cooperation of the first simulation device and the second simulation device in fault simulation, the efficiency of fault simulation of the first simulation device can be further improved.

[0113] Optionally, the embodiments of the present application can use a dynamic allocation manner to allocate faults. The specific allocation scheme of the faults can be different, such as random allocation, average allocation according to the size of the FR, etc. At the beginning of fault simulation, the first simulation device and the second simulation device each allocate a portion of faults, and when the second simulation device completes the fault simulation of the portion, the next portion of faults is immediately allocated. When the first simulation device completes the fault simulation of the portion, a signal is transmitted to the second simulation device, and the second simulation device transmits the next portion of faults to the first simulation device, and the first simulation device immediately starts fault simulation. Repeat the above steps until the simulation of all faults is completed. The above dynamic allocation manner can not depend on the prior allocation proportion of other circuits, i.e. is more relevant to the simulated circuit, and the load balancing is more accurate.

[0114] The simulation method will be further described below in conjunction with Figure 6 and Figure 7 . Figure 4 .

[0115] Figure 6 FIG. 6 is a schematic diagram of the simulation method 600 of the embodiments of the present application. The execution subject of the method 600 is the first simulation device. The method 600 comprises:

[0116] S610, determining the fault simulation order of all logic gates in the fan-out region of the fault logic gate A.

[0117] Before fault simulation, all logic gates in the circuit can be classified, i.e. the level of the logic gate as the main input in the circuit is defined as 0, and the level of the remaining logic gates is defined as the maximum level of the input logic gates plus 1. For example, if the logic gate #A is the main input logic gate of the circuit, the level of the logic gate #A is defined as 0, and the level of the remaining logic gates connected to the output pin of the logic gate #A can be 1, 2, etc. For details, please refer to Figure 7 .

[0118] Figure 7 FIG. 6 is a schematic diagram of the simulation method 600 of the embodiments of the present application. The execution subject of the method 600 is the first simulation device. The method 600 comprises: Figure 7As shown, the logic gate #a is the logic gate of the main input, and the logic gate #i is the logic gate of the main output. According to the foregoing description, the level of the logic gate #a is 0, the level of the logic gate #b is 1, the level of the logic gate #c is 1, the level of the logic gate #d is 2, the level of the logic gate #e is 2, the level of the logic gate #f is 3 (although the logic gate #f is connected with the logic gate #a, the maximum level of the input logic gate is 2, and therefore the level of the logic gate #f is 3), the level of the logic gate #g is 3, the level of the logic gate #h is 4, and the level of the logic gate #i is 5.

[0119] Through the above hierarchical processing, each logic gate in the circuit has a corresponding level number, and the level number is used to represent the level of the logic gate. The level numbers of different logic gates can be the same or different.

[0120] The fault logic gate A in S610 can be any logic gate as shown. Figure 7 As shown, all the logic gates in the fan-out region of the fault logic gate A have corresponding level numbers, and therefore the fault simulation order of all the logic gates in the fan-out region of the fault logic gate A can be determined according to the level numbers of the logic gates. Figure 3 For example, the fault logic gate A is the logic gate #A, and the fault simulation order of all the logic gates in the fan-out region of the logic gate #A is as follows:

[0121] The logic gate #A→the logic gate #B→the logic gate #D→the logic gate #C→the logic gate #E; or,

[0122] The logic gate #A→the logic gate #B→the logic gate #C→the logic gate #D→the logic gate #E.

[0123] In addition, since the level numbers of the logic gate #D and the logic gate #C are the same, the simulation order of the logic gate #D and the logic gate #C is not limited in the embodiments of the present application.

[0124] S620, when the data structure S1 is in the non-overflow state, the serial number of at least one logic gate connected with the output node of the fault logic gate A is stored into the data structure S1.

[0125] Specifically, the data structure S1 can be used to store the serial number of the logic gate in the fault simulation process, in other words, the data structure S1 is used to store the serial number of the logic gate to be accessed in the fault simulation process. The data structure S1 can include a PQ, and the PQ can include a ring PQ or a non-ring PQ.

[0126] S630, under the condition that the first logic gate corresponds to the fault value of the first fault, the serial number of the first logic gate is deleted from the data structure S1.

[0127] Specifically, the first simulation device determines whether the number of logic gates connected to the output node of the faulty logic gate A exceeds the maximum capacity of the data structure S1. If the number of logic gates connected to the output node of the faulty logic gate A exceeds the maximum capacity of the data structure S1, the first simulation device terminates the fault simulation of all logic gates in the fan-out region of the faulty logic gate A, and records the fault serial number corresponding to the faulty logic gate A.

[0128] In addition, if the first simulation device determines that the number of logic gates connected to the output node of the faulty logic gate A does not exceed the maximum capacity of the data structure S1, the first simulation device calculates and determines the fault value of the first logic gate (the logic gate with the first level number) of the faulty logic gate A, and deletes the serial number of the first logic gate from the data structure S1. If the logic value corresponding to the first fault of the first logic gate is the same as the logic value not corresponding to the first fault of the first logic gate, the first simulation device continues to calculate and determine the logic value corresponding to the first fault of the second logic gate of the faulty logic gate A, and deletes the serial number of the second logic gate from the data structure S1. The above steps are repeated until the fault simulation of all logic gates in the fan-out region of the faulty logic gate A is completed.

[0129] If the logic value corresponding to the first fault of the first logic gate of the faulty logic value A is different from the logic value not corresponding to the first fault, the first simulation device stores the serial number of the first logic gate of the faulty logic gate A and the logic value corresponding to the first fault in the data structure S2, and stores the serial number of at least one logic gate connected to the output node of the first logic gate in the data structure S1, and repeats the process according to the method shown in S603.

[0130] For example, the first logic gate of the faulty logic gate A is logic gate #1, and the fault value corresponding to the first fault of the logic gate #1 is different from the real value. The first simulation device stores the serial number of at least one logic gate connected to the output node of the logic gate #1 in the data structure S1.

[0131] In the embodiment of the present application, the data structure S2 can be used to store the fault value different from the real value in the fault simulation process, and the serial number of the logic gate corresponding to the fault value. For details, see Table 3.

[0132] Table 3

[0133] Fault value 1 0 1 0 Gate number Gate #1 Gate #5 Gate #7 Gate #10

[0134] In Table 3, the first row is used to store the fault value, and the second row is used to store the serial number of the logic gate corresponding to the fault value. For example, in the process of fault simulation, if the logic value of Gate#1 corresponding to the first fault is different from the logic value of Gate#1 not corresponding to the first fault, the fault value of Gate#1 is stored in the data structure S2, and the serial number of Gate#1 is stored at the same time. In this way, the embodiments of the present application can reduce the memory overhead for storing the fault value, and can use the two-level storage mode of storing the fault value and the corresponding serial number at the same time to replace the storage of the fault values of all logic gates.

[0135] In the method 600, the fault logic gate which cannot be simulated by the first simulation device is fed back to the second simulation device by the first simulation device, and the second simulation device is responsible for simulating the fault logic gate which cannot be simulated by the first simulation device.

[0136] Through the above technical solutions, the embodiments of the present application can enable the simulation device to not store all logic gates in the fan-out area of the fault logic gate when performing fault simulation, and only need to store the relevant information of part of the logic gates, so as to complete the fault simulation processing of all logic gates in the fan-out area of the fault logic gate. In this way, the first simulation device can reduce the data level required to be stored when performing fault simulation, thereby improving the efficiency of the processing device in performing fault simulation. For example, for the storage of the real values of each logic gate, since only 32 or 64 patterns need to be simulated at a time, the memory occupied is “4*total number of logic gates”. For the storage of the fault values, the memory occupied is “total number of threads*maximum length of the data structure B*memory occupied for storing one fault value”. The storage amount of the fault logic gate corresponding to the fault value is calculated in the same way as the storage of the fault value.

[0137] For a million-gate circuit, through the above scheme, the embodiments of the present application can reduce the memory required to store the logic gate information by more than one order of magnitude.

[0138] Optionally, when the first simulation device determines that the number of logic gates connected to the output node of the fault logic gate is greater than the maximum length of the data structure S1, the first simulation device can send the serial number of the fault logic gate to the second simulation device, and the second simulation device is responsible for simulating all logic gates in the fan-out area of the fault logic gate. In this way, through the cooperative processing of the first simulation device and the second simulation device, the overall fault simulation efficiency can be improved.

[0139] Through the above manner, the embodiments of the present application can dynamically adjust and allocate the number of logic gates and the number of faults which the first simulation device needs to perform fault simulation, so as to balance the load and make the order of the fault simulation processing required by the first simulation device not affect the efficiency of the first simulation device in performing fault simulation.

[0140] Optionally, the number of faults that the first simulation device can handle is statically configured. For example, the number of faults that the first simulation device can handle can be determined based on the size of the memory space of the first simulation device, and this number of faults will not affect the efficiency of the fault simulation of the first simulation device.

[0141] The following will combine Figure 8 and Figure 9 The simulation apparatus and simulation system of the embodiments of this application will be described.

[0142] Figure 8 This is a schematic diagram of the structure of the simulation device 800 according to an embodiment of this application. Figure 8 As shown, Figure 8 The simulation device 800 shown can be either a first simulation device or a second simulation device. Figure 8 The simulation device 800 shown includes a processing module 810 and a storage module 820, which are used to execute the fault simulation method 400 / 600 in the aforementioned method embodiments.

[0143] For example, the processing module 810 is used to store the serial number of at least one logic gate into a data structure; the processing module 810 is also used to determine the fault value of the first logic gate corresponding to the first fault and the first test vector, and delete the serial number of the first logic gate from the data structure, etc. The storage module 820 is used to store the serial number of the aforementioned at least one logic gate.

[0144] Optionally, the storage module 820 is also used to store the logic value corresponding to the first fault of the aforementioned logic gate and the sequence number of the logic gate, etc. For details, please refer to the description of the aforementioned method embodiments.

[0145] Figure 8 The simulation device 800 shown can be a GPU, CPU, or other processors or hardware, such as hardware acceleration cards and FPGAs, etc., and is used to implement or execute the fault simulation method described in the foregoing method embodiments.

[0146] Figure 9 This is a schematic diagram of the simulation system 900 in an embodiment of this application. Figure 9 As shown, the simulation system 900 includes a first simulation device and a second simulation device. In this embodiment, the first simulation device is a GPU and the second simulation device is a CPU, but other types of processors are not limited to this embodiment.

[0147] Exemplarily, the GPU is used to perform the simulation method performed by the first simulation device, and the CPU can also be used to perform the simulation method performed by the second simulation device. The CPU can be used to read the netlist information and obtain the test vector, and according to a preset fault allocation ratio, the faults processed by the GPU simulation are sent to the GPU, and different faults are simulated simultaneously with the GPU. By Figure 9 According to the simulation system shown in the embodiment of the present application, the fault simulation efficiency can be improved.

[0148] In the case of the same hardware resources (single GPU, CPU 32 threads), Table 4 shows the fault simulation acceleration of two industrial circuits, which is based on the CPU single-thread system. Compared with the single CPU system and the single GPU system, the CPU-GPU heterogeneous system can achieve higher execution efficiency. For details, see Table 4.

[0149] Table 4 shows the acceleration of the industrial circuit under different fault allocation ratios. The running environment is CPU 32 threads and GPU single card.

[0150] The comparison benchmark is the CPU single thread.

[0151]

[0152] In Table 4, the fault simulation acceleration of industrial circuit A varies with the fault allocation ratio, for example, when the fault allocation ratio is 0, the acceleration is 25.4, when the fault allocation ratio is 0.4, the acceleration is 33.7, and when the fault allocation ratio is 1, the acceleration is 20.1. Therefore, a suitable fault allocation ratio can be selected, so that the fault simulation acceleration can be improved. In Table 4, the fault simulation acceleration of industrial circuit B varies with the fault allocation ratio, for example, when the fault allocation ratio is 0, the acceleration is 18, when the fault allocation ratio is 0.4, the acceleration is 27.3, and when the fault allocation ratio is 1, the acceleration is 14.8. Therefore, a suitable fault allocation ratio can be selected to enable the CPU and the GPU to cooperate in fault simulation, so that the fault simulation acceleration can be improved.

[0153] By using the simulation system described above, compared with using the first simulation device to perform fault simulation processing, the embodiment of the present application can significantly improve the fault simulation efficiency.

[0154] Optionally, the above method can also be extended to a multi-GPU system, that is, the fault allocation ratio of the CPU and each GPU is preset, and the fault is statically allocated in advance according to the size of the FR area, so that the parallel simulation time of each hardware is as same as possible. Subsequently, the circuit information, fault information and the like are transmitted to each GPU asynchronously. The data structure allocated on different GPUs and the multi-dimensional parallel simulation scheme adopted are consistent with the above single-GPU system. Each GPU starts simulation at the same time, and stores the fault sequence numbers exceeding the accommodation space of the data structure. When any GPU completes simulation, the fault list that fails to be simulated is immediately transmitted to the CPU. Finally, the CPU re-simulates the above faults. In this way, the scalability of the algorithm can be improved, and the simulation efficiency is also improved.

[0155] The application further provides a computer readable storage medium comprising a computer program or instructions, which, when executed on a computer, cause the computer to perform the simulation method.

[0156] The application further provides a computer program product comprising instructions, which, when executed on a computer, cause the computer to perform the simulation method.

[0157] Those skilled in the art can appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the application.

[0158] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0159] In several embodiments provided in the application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms.

[0160] The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0161] In addition, the functional units in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0162] The functions, if realized in the form of software functional units and sold or used as independent products, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application or the part of the present application that essentially contributes to the prior art or the part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program code storage media.

[0163] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A simulation method, characterized by, The method comprises: The first simulation device stores the serial number of at least one logic gate connected to the output node of the faulty logic gate into the first data structure, the first data structure can store M serial numbers, the number of logic gates in the fan-out region of the faulty logic gate is N, M is less than N, and the faulty logic gate corresponds to at least one fault; On the condition that the first logic gate corresponds to the logic value of the first fault, the first simulation device deletes the serial number of the first logic gate from the first data structure; Wherein, the first logic gate is one of the at least one logic gate, and the first fault is one of the at least one fault; The method further comprises: When the logic value of the first logic gate corresponding to the first fault is the same as the logic value of the first logic gate not corresponding to the first fault, on the condition that the second logic gate corresponds to the logic value of the first fault, the first simulation device deletes the serial number of the second logic gate from the first data structure, and the second logic gate is another logic gate different from the first logic gate in the at least one logic gate; Or, When the logic value of the first logic gate corresponding to the first fault is different from the logic value of the first logic gate not corresponding to the first fault, the first simulation device stores the serial number of at least one logic gate connected to the output node of the first logic gate into the first data structure.

2. The simulation method of claim 1, wherein, When the logic value of the first logic gate corresponding to the first fault is different from the logic value of the first logic gate not corresponding to the first fault, the method further comprises: The first simulation device stores the logic value of the first logic gate corresponding to the first fault and the serial number of the first logic gate into the second data structure.

3. The simulation method of claim 1, wherein, After the first simulation device stores the serial number of at least one logic gate connected to the output node of the first logic gate into the first data structure, the method further comprises: On the condition that the third logic gate corresponds to the logic value of the first fault, the first simulation device deletes the serial number of the third logic gate from the first data structure; Wherein, the third logic gate is one of the at least one logic gate connected to the output node of the first logic gate.

4. The simulation method of any one of claims 1 to 3, wherein, Before the first simulation device stores the serial number of at least one logic gate into the first data structure, the method further comprises: The first simulation device acquires the first data structure sent by the second simulation device; Wherein, the first data structure is determined by the second simulation device according to the total number of logic gates and prior information; or, The first data structure is determined by the second simulation device according to the number of logic gates in the fan-out region of the faulty logic gate.

5. The simulation method of any one of claims 1 to 3, wherein, The first data structure comprises at least one of the following: Priority queue, small heap structure; Wherein, the first logic gate is the logic gate with the highest priority in the fault simulation sequence among the at least one logic gate.

6. The simulation method of any one of claims 1 to 3, wherein, Before the first simulation device stores the serial number of at least one logic gate into the first data structure, the method further comprises: The first simulation device acquires the information of the at least one fault sent by the second simulation device.

7. The simulation method of any one of claims 1 to 3, wherein, The method further comprises: When the number of at least one logic gate connected to the output node of the first logic gate makes the first data structure overflow, the first simulation device sends the sequence number of the first fault to a second simulation device.

8. An emulation apparatus, characterized by, Comprise: The processing module is used for storing the sequence number of at least one logic gate connected to the output node of the fault logic gate into a first data structure, the first data structure can store a number of sequence numbers, the number of logic gates in the fan-out area of the fault logic gate is N, M is less than N, the fault logic gate corresponds to at least one fault; The processing module is also used for deleting the sequence number of the first logic gate from the first data structure under the condition that the first logic gate corresponds to the logic value of the first fault, Wherein, the first logic gate is one of the at least one logic gate, and the first fault is one of the at least one fault; The storage module is used for storing the sequence number of the at least one logic gate; When the logic value corresponding to the first fault of the first logic gate is the same as the logic value not corresponding to the first fault of the first logic gate, the processing module is also used for deleting the sequence number of the second logic gate from the first data structure under the condition that the second logic gate corresponds to the logic value of the first fault, Wherein, the second logic gate is another logic gate different from the first logic gate in the at least one logic gate; or, When the logic value corresponding to the first fault of the first logic gate is different from the logic value not corresponding to the first fault of the first logic gate, the processing module is also used for storing the sequence number of at least one logic gate connected to the output node of the first logic gate into the first data structure.

9. The emulation apparatus of claim 8, wherein, When the logic value corresponding to the first fault of the first logic gate is different from the logic value not corresponding to the first fault of the first logic gate, the processing module is also used for storing the logic value corresponding to the first fault of the first logic gate and the sequence number of the first logic gate into a second data structure; The storage module is also used for storing the logic value corresponding to the first fault of the first logic gate and the sequence number of the first logic gate.

10. The emulation apparatus of claim 8, wherein, The processing module is also used for: Deleting the sequence number of the third logic gate from the first data structure under the condition that the third logic gate corresponds to the logic value of the first fault; Wherein, the third logic gate is one of at least one logic gate connected to the output node of the first logic gate.

11. The emulation apparatus according to any one of claims 8 to 10, wherein, The processing module is also used for: Obtaining the first data structure sent by a second simulation device; Wherein, the first data structure is determined by the second simulation device according to the total number of logic gates and prior information; or, The first data structure is determined by the second simulation device according to the number of logic gates in the fan-out area of the fault logic gate.

12. The emulation apparatus according to any one of claims 8 to 10, wherein The first data structure comprises at least one of the following: Priority queue, small heap structure; Wherein, the first logic gate is the logic gate with the highest priority in the fault simulation sequence of the at least one logic gate.

13. The emulation apparatus according to any one of claims 8 to 10, wherein The processing module is also used for: Obtaining the information of the at least one fault sent by a second simulation device.

14. The emulation apparatus according to any one of claims 8 to 10, wherein, The processing module is further configured to: when the number of at least one logic gate connected to the output node of the first logic gate makes the first data structure in an overflow state, send the sequence number of the first fault to a second simulation device.

15. An emulation system, comprising: comprising: a first simulation device configured to perform the simulation method of any one of claims 1 to 7; a second simulation device configured to send the first data structure to the first simulation device; the second simulation device is further configured to send information of the at least one fault to the first simulation device.

16. A computer-readable storage medium, characterized in that, comprising computer programs or instructions, when the computer programs or the instructions are run on a computer, so that the computer performs the simulation method of any one of claims 1 to 7.

17. A computer program product, characterised in that, comprising instructions, when the instructions are run on a computer, so that the computer performs the simulation method of any one of claims 1 to 7.

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